DG211_05 INTERSIL | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 7
Technical content
Features
- Switches ±15V Analog Signals
- TTL Compatibility
- Logic Inputs Accept Negative Voltages
- Pb-Free Plus Anneal Available (RoHS Compliant) Functional Block Diagrams DG211 Part Number Information PART NUMBER PART MARKING TEMP . RANGE (°C) PACKAGE PKG. NO. DG211CJ DG211CJ 0 to 70 16 Ld PDIP E16.3 DG211CJZ (Notes 1, 2) DG211CJZ 0 to 70 16 Ld PDIP* (Pb-free) E16.3 DG211CY (Note 2) DG211CY 0 to 70 16 Ld SOIC M16.15 DG211CYZ (Notes 1, 2) DG211CYZ 0 to 70 16 Ld SOIC (Pb-free) M16.15 *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTES: 1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. Add “T” suffix for Tape and Reel. IN1 GND IN4 IN2 V+ (SUB- VL (+5V) IN3 STRATE)- TRUTH TABLE LOGIC DG211 0O N 1O F F Logic “0” ≤0.8V, Logic “1” ≥ 2.4V IN1 IN2 IN3 IN4 Data Sheet December 21, 2005
2 FN3118.4 December 21, 2005 Schematic Diagram DG211 (1/4 AS SHOWN) TTL IN GND +15V +5V VL -15V -15V -15V +15V OUTIN DG211
3 FN3118.4 December 21, 2005 Absolute Maximum Ratings Thermal Information Operating Conditions Thermal Resistance (Typical, Note 3) θJA (°C/W) (SOIC - Lead Tips Only) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 3. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications V+ = +15V, V- = -15V, VL = +5V, GND, TA = 25°C PARAMETER TEST CONDITIONS (NOTE 4) MIN (NOTE 5) TYP MAX UNITS DYNAMIC CHARACTERISTICS Turn-ON Time, tON See Figure 1 VS = 10V, RL = 1kΩ, CL = 35pF - 460 - ns Turn-OFF Time, tOFF1 - 360 - ns tOFF2 - 450 - ns OFF Isolation, OIRR (Note 7) V IN = 5V, RL = 1kΩ, CL = 15pF, VS = 1VRMS, f = 100kHz -7 0- d B Crosstalk (Channel to Channel), CCRR - -90 - dB Source OFF Capacitance, CS(OFF) VD = VS = 0V, VIN = 5V, f = 1MHz - 5 - pF Drain OFF Capacitance, CD(OFF) -5- p F Channel ON Capacitance, CD(ON) + CS(ON) -1 6- p F DIGITAL INPUT CHARACTERISTICS Input Current with Voltage High, I IH VIN = 2.4V -1.0 -0.0004 - µA VIN = 15V - 0.003 1.0 µA Input Current with Voltage Low, IIL VIN = 0V -1.0 -0.0004 - µA ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG -15 - 15 V Drain-Source ON Resistance, rDS(ON) VD = ±10V, IS = 1mA, VIN = 0.8V - 150 175 Ω Source OFF Leakage Current, IS(OFF) VIN = 2.4V V S = 14V, VD = -14V - 0.01 5.0 nA Drain OFF Leakage Current, ID(OFF) VS = -14V, VD = 14V - 0.01 5.0 nA Drain ON Leakage Current, ID(ON) (Note 6) VIN = 0.8V V S = VD = 14V - 0.1 5.0 nA DG211
spikes at leading and trailing edge of output waveform.
- The algebraic convention whereby the most nega tive value is a minimum, and the most positive is a maximum, is used in this data sheet.
- For design reference only, not 100% tested.
- I D(ON) is leakage from driver into ON switch.
FIGURE 1. SWITCHING TIME MEASUREMENT POINTS FIGURE 2. SWITCHING TIME TEST CIRCUIT
5 FN3118.4 December 21, 2005 Die Characteristics DIE DIMENSIONS: 2159µm x 2235µm METALLIZATION: Type: Al Thickness: 10kÅ ±1kÅ PASSIVATION: Type: PSG/Nitride PSG Thickness: 7kÅ ±1.4kÅ Nitride Thickness: 8kÅ ±1.2kÅ WORST CASE CURRENT DENSITY: 9.1 x 104 A/cm2 Metallization Mask Layout DG211 PIN 2 PIN 3 PIN 4 PIN 5 GND PIN 6 PIN 7 PIN 8 IN 4 PIN 9 IN 3 PIN 10 PIN 11 PIN 12 VL PIN 13 V+ (SUBSTRATE) PIN 14 PIN 15 PIN 16 IN 2 PIN 1 IN 1 DG211
6 FN3118.4 December 21, 2005 DG211 Dual-In-Line Plastic Packages (PDIP) NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JE- DEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and are measured with the leads constrained to be perpendic- ular to datum . 7. e B and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. eA -C- CL E eA C eB eC -B- INDEX 12 3 N / 2 N AREA SEATING BASE PLANE PLANE -C- B e D AA2 L -A- 0.010 (0.25) C AM BS E16.3 (JEDEC MS-001-BB ISSUE D)
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
A- 0.210 - 5.33 4 A1 0.015 - 0.39 -4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.15 1.77 8, 10 C 0.008 0.014 0.204 0.355 - D 0.735 0.775 18.66 19.68 5 D1 0.005 - 0.13 -5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC 6 eB - 0.430 - 10.92 7 L 0.115 0.150 2.93 3.81 4 N1 6 1 6 9 Rev. 0 12/93
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN3118.4 December 21, 2005 DG211 Small Outline Plastic Packages (SOIC) NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. INDEX AREA E D N 123 -B- 0.25(0.010) C AM BS e -A- L B M -C- A SEATING PLANE 0.10(0.004) h x 45° C H 0.25(0.010) BM M α M16.15 (JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.3859 0.3937 9.80 10.00 3 E 0.1497 0.1574 3.80 4.00 4 e 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N1 6 1 6 7 α 0° 8° 0° 8° - Rev. 1 6/05