DG201A

DG201A INTERSIL | Alldatasheet

Document overview

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• PDF pages: 7

Technical content

Features

• TTL, CMOS Compatible
• Latch-Up Proof
• True Second Source
• Logic Inputs Accept Negative Voltages Functional Block Diagrams DG201A DG202

Ordering Information

TEMP. RANGE ( oC) PACKAGE PKG. NO. DG201AAK -55 to 125 16 Ld CERDIP F16.3 DG201ABK -25 to 85 16 Ld CERDIP F16.3 DG201ACJ 0 to 70 16 Ld PDIP E16.3 DG201ACY 0 to 70 16 Ld SOIC M16.3 DG202AK -55 to 125 16 Ld CERDIP F16.3 DG202CJ 0 to 70 16 Ld PDIP E16.3 IN1 D 1 GND IN4 D 4 IN2 V+ (SUB- NC D 3 IN3 D 2 STRATE)- TRUTH TABLE LOGIC DG201A DG202

0 ON OFF

1 OFF ON

Logic “0”≤0.8V, Logic “1”≥ 2.4V IN1 D 1 IN2 D 2 IN3 D 3 IN4 D 4 IN1 D 1 IN2 D 2 IN3 D 3 IN4 D 4 SWITCHES SHOWN FOR LOGIC “1” INPUT Data Sheet June 1999

Absolute Maximum Ratings Thermal Information V Operating Conditions Temperature Range Thermal Resistance (Typical, Note 2)θJA (oC/W) θJC (oC/W) Maximum Junction Temperature oC (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationo ft h e device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Signals on VS , VD , or VIN exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical SpecificationsV+ = 15V, V- = -15V, GND = 0V, TA = 25oC PARAMETER TEST CONDITIONS UNITSMIN (NOTE 3) TYP MAX MIN (NOTE 3) TYP MAX DYNAMIC CHARACTERISTICS Turn-ON Time, t ON See Figure 1 - 480 600 - 480 - ns Turn-OFF Time, tOFF See Figure 1 - 370 450 - 370 - ns Charge Injection, Q C L = 1nF, RS = 0, VS = 0V - 20 - - 20 - pC OFF Isolation, OIRR V IN = 5V, RL = 75Ω , VS = 2.0V, f = 100kHz -7 0- -7 0- d B Crosstalk (Channel to Channel), CCRR - -90 - - -90 - dB Source OFF Capacitance, C S(OFF) f = 140kHz, VIN = 5V, VS = VD = 0V - 5.0 - - 5.0 - pF Drain OFF Capacitance, CD(OFF) - 5.0 - - 5.0 - pF Channel ON Capacitance, C D(ON) +C S(ON) -1 6- -1 6- p F DIGITAL INPUT CHARACTERISTICS VIN = 15V - 0.003 1.0 - 0.003 1.0 µA Input Current with Voltage Low, IIL VIN = 0V -1.0 -0.0004 - -1.0 -0.0004 - µA ANALOG SWITCH CHARACTERISTICS Analog Signal Range, V ANALOG -15 - 15 -15 - 15 V Drain-Source ON Resistance, rDS(ON) VD =±10V, VIN = 0.8V (DG201A) IS = 1mA, VIN = 2.4V (DG202) - 115 175 - 115 200 Ω Source OFF Leakage Current, IS(OFF) VIN = 2.4V (DG201A) V IN = 0.8V (DG202) VS = 14V, VD = -14V - 0.01 1.0 - 0.01 5.0 nA Drain OFF Leakage Current, ID(OFF) VS = -14V, VD = 14V - 0.01 1.0 - 0.01 5.0 nA DG201A, DG202

Drain ON Leakage Current, ID(ON) (Note 5) VIN = 0.8V (DG201A) V IN = 2.4V (DG202) VD = VS = 14V - 0.1 1.0 - 0.1 5.0 µA POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ All Channels ON or OFF - 0.9 2 - 0.9 2 mA Negative Supply Current, I- -1 -0.3 - -1 -0.3 - mA Electrical SpecificationsV+ = 15V, V- = -15V, GND = 0V, TA = 25oC (Continued) PARAMETER TEST CONDITIONS UNITSMIN (NOTE 3) TYP MAX MIN (NOTE 3) TYP MAX Electrical SpecificationsV+ = 15V, V- = -15V, GND = 0V, TA Over Operating Temperature Range PARAMETER TEST CONDITIONS “A” SUFFIX UNITSMIN (NOTE 3) TYP MAX DIGITAL INPUT CHARACTERISTICS Input Current with Voltage High, I IH VIN = 2.4V -10 - - µA VIN = 15V - - 10 µA Input Current with Voltage Low, IIL VIN = 0V -10 - - µA ANALOG SWITCH CHARACTERISTICS Analog Signal Range, V ANALOG -15 - 15 V Drain-Source ON Resistance, rDS(ON) VD =±10V, VIN = 0.8V (DG201A) IS = 1mA, VIN = 2.4V (DG202) - - 250 Ω Source OFF Leakage Current, IS(OFF) VIN = 2.4V (DG201A) VIN = 0.8V (DG202) VS = 14V, VD = -14V - - 100 nA VS = -14V, VD = 14V -100 - - nA Drain OFF Leakage Current, ID(OFF) VS = -14V, VD = 14V - - 100 nA VS = 14V, VD = -14V -100 - - nA Drain ON Leakage Current, ID(ON) (Note 5) V IN = 0.8V (DG201A) VIN = 2.4V (DG202) VD = VS = 14V - - 200 µA VD = VS = -14V -200 - - µA NOTES: 3. Typical values are for design aid only, not guaranteed and not subject to production testing. 4. The algebraic convention whereby the most negative value is a minimum, and the most positive is a maximum, is used in this data sheet. 5. I D(ON) is leakage from driver into ON switch. DG201A, DG202

DG201A, DG202 Dual-In-Line Plastic Packages (PDIP) NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JE- DEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and are measured with the leads constrained to be perpendic- ular to datum . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. eA -C- CL E eA C eB eC -B- INDEX 1 2 3 N/2 N AREA SEATING BASE PLANE PLANE -C- B e D AA2 L -A- 0.010 (0.25) C AM BS E16.3(JEDEC MS-001-BB ISSUE D)

16 LEAD DUAL-IN-LINE PLASTIC PACKAGE

A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.15 1.77 8, 10 C 0.008 0.014 0.204 0.355 - D 0.735 0.775 18.66 19.68 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - e A 0.300 BSC 7.62 BSC 6 eB - 0.430 - 10.92 7 L 0.115 0.150 2.93 3.81 4 N1 6 1 6 9 Rev. 0 12/93

DG201A, DG202 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) NOTES: 1. Index area: A notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N,N/2, and N/2+1) may beconfigured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. bbb C A - BS c Q L A SEATING BASE D PLANE PLANE -D--A- -C- -B- α D E b A e M (c) (b) SECTION A-A BASE LEAD FINISH METAL eA/2 A M S S ccc C A - BM DS S aaa C A - BM DS S eA F16.3MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A)

16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE

A - 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 0.840 - 21.34 5 E 0.220 0.310 5.59 7.87 5 e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC - eA/2 0.150 BSC 3.81 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 6 S1 0.005 - 0.13 - 7 α 90o 105o 90o 105o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2, 3 N1 6 1 6 8 Rev. 0 4/94

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 DG201A, DG202 Small Outline Plastic Packages (SOIC) NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. INDEX AREA E D N 123 -B- 0.25(0.010) C AM BS e -A- L B M -C- A SEATING PLANE 0.10(0.004) h x 45o C H 0.25(0.010) BM M α M16.3 (JEDEC MS-013-AA ISSUE C)

16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

A 0.0926 0.1043 2.35 2.65 - A1 0.0040 0.0118 0.10 0.30 - B 0.013 0.0200 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.3977 0.4133 10.10 10.50 3 E 0.2914 0.2992 7.40 7.60 4 e 0.050 BSC 1.27 BSC - H 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 N1 6 1 6 7 α 0o 8o 0o 8o - Rev. 0 12/93