DG201 INTERSIL | Alldatasheet

Document overview

  • Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
  • PDF pages: 7

Technical content

Features

  • Switches Greater than 28VP-P Signals with±15V Supplies
  • Break-Before-Make Switching
  • TTL, DTL, CMOS, PMOS Compatible
  • Non-Latching with Supply Turn-Off
  • Complete Monolithic Construction
  • Industry Standard (DG201)

Applications

  • Data Acquisition
  • Sample and Hold Circuits
  • Operational Amplifier Gain Switching Networks Pinout DG201 (PDIP) TOP VIEW

Ordering Information

TEMP. RANGE (oC) PACKAGE PKG. NO. DG201CJ 0 to 70 16 Ld PDIP E16.3 TRUTH TABLE LOGIC DG201 0O N

1 OFF

S D DG201 SWITCH CELL IN1 D 1 GND IN4 D 4 IN2 V+(SUBSTRATE) VREF D 3 IN3 D 2 SWITCHES SHOWN FOR LOGIC “1” INPUT Data Sheet January 2000 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143| Copyright © Intersil Corporation 2000

Functional Diagram (1/4 DG201) Q 3 VREF INPUT GATE PROTECTION RESISTOR Q 4 Q 7 Q 8 Q 5 Q 10 Q 12 Q 13 Q 11 D 1S1 Q 14 Q 6 Q 9 Q 15 Q 1 Q 2 Pin Descriptions PIN SYMBOL DESCRIPTION 1I N 1 Logic Control for Switch 1 2D 1 Drain (Output) Terminal for Switch 1 3S 1 Source (Input) Terminal for Switch 1

4 V- Negative Power Supply Terminal

5 GND Ground Terminal (Logic Common)

4 Source (Input) Terminal for Switch 4

7D 4 Drain (Output) Terminal for Switch 4 8I N 4 Logic Control for Switch 4 9I N 3 Logic Control for Switch 3

10 D 3 Drain (Output) Terminal for Switch 3

11 S 3 Source (Input) Terminal for Switch 3

12 V REF Logic Reference Voltage

13 V+ Positive Power Supply Terminal (Substrate)

2 Source (Input) Terminal for Switch 2

15 D 2 Drain (Output) Terminal for Switch 2

16 IN 2 Logic Control for Switch 2

Absolute Maximum Ratings Thermal Information Operating Conditions Temperature Range Thermal Resistance (Typical, Note 1)θJA (oC/W) θJC (oC/W) Maximum Junction Temperature CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical SpecificationsTA = 25oC, V+ = +15V, V- = -15V PARAMETER TEST CONDITIONS “C” SUFFIX UNITS0oC (NOTE 2) 25oC7 0 oC DYNAMIC CHARACTERISTICS Turn-ON Time (Note 3), t ON R L =1 kΩ ,VANALOG = -10V to +10V (Figure 1) - 1.0 - µs Turn-OFF Time (Note 3), tOFF R L =1 kΩ ,VANALOG = -10V to +10V (Figure 1) - 0.5 - µs Charge Injection, Q Figure 2 - 20 (Typ) - mV Off Isolation Rejection Ratio, OIRR f = 1MHz, R L = 100Ω , CL ≤ 5pF, (Figure 3) - 50 (Typ) - dB Crosstalk (Channel-to-Channel), CCRR One Channel Off - -50 (Typ) - dB DIGITAL INPUT CHARACTERISTICS Input Logic Current, I IN(ON) VIN = 0.8V (Note 3) ±1 ±1 ±10 µA Input Logic Current, IN(OFF) VIN = 2.4V (Note 3) ±1 ±1 ±10 µA ANALOG SWITCH CHARACTERISTICS Analog Signal Range, V ANALOG - ±15 (Typ) - V Drain-Source ON Resistance, rDS(ON) IS = 10mA, VANALOG =±10V 100 100 125 Ω Channel-to-Channel rDS(ON) Match, rDS(ON) - 30 (Typ) - Ω Drain OFF Leakage Current, ID(OFF) VANALOG = -14V to +14V - ±5 100 nA Source OFF Leakage Current, IS(OFF) VANALOG = -14V to +14V - ±5 100 nA Channel ON Leakage Current, ID(ON) + IS(ON) VD = VS = -14V to +14V - ±5 200 nA POWER SUPPLY CHARACTERISTICS Supply Current, I+ Positive V IN = 0V or VIN = 5V 2000 1000 2000 µA Supply Current, I- Negative 2000 1000 2000 µA NOTES: 2. Typical values are for design aid only, not guaranteed and not subject to production testing. 3. All channels are turned off by high “1” logic inputs and all channels are turned on by low “0” inputs; however 0.8V to 2.4V describes the minimum range for switching properly. Peak input current required for transition is typically -120µA. DG201

DIE DIMENSIONS: 94 mils x 101 mils x 14 mils METALLIZATION: Type: Al Thickness: 10kÅ PASSIVATION: Type: SiO2/Si3N 4 SiO2 Thickness: 7kÅ Si3N 4 Thickness: 8kÅ WORST CASE CURRENT DENSITY: 1 x 105 A/cm2 Metallization Mask Layout DG201 S1 (3) V- (4) GND (5) S4 (6) IN2 (16) IN1 (1) D 1 (2) (11) S3 (13) V+ (SUBSTRATE)† (14) S2 (15) (7) D 4 (8) IN4 (9) IN3 (10) D 3 D 2 † BACKSIDE OF CHIP IS V+ (12) VREF DG201

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitewww.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 DG201 Dual-In-Line Plastic Packages (PDIP) NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JE- DEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and are measured with the leads constrained to be perpendic- ular to datum . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. eA -C- CL E eA C eB eC -B- INDEX 1 2 3 N/2 N AREA SEATING BASE PLANE PLANE -C- B e D AA2 L -A- 0.010 (0.25) C AM BS E16.3(JEDEC MS-001-BB ISSUE D)

16 LEAD DUAL-IN-LINE PLASTIC PACKAGE

A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.15 1.77 8, 10 C 0.008 0.014 0.204 0.355 - D 0.735 0.775 18.66 19.68 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - e A 0.300 BSC 7.62 BSC 6 eB - 0.430 - 10.92 7 L 0.115 0.150 2.93 3.81 4 N1 6 1 6 9 Rev. 0 12/93