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AN1262 STMICROELECTRONICS | Alldatasheet

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1 FLYBACK BASICS

biased, thus the load is being supplied by the energy stored in the output bulk capacitor. Figure 1. Flyback Topology and associated waveforms. complex tradeoffs are necessary to meet the goal. the same time, allow to build robust and cost-effective low-power systems.

CCM features trapezoidal currents. put voltage are defined, it depends on the input voltage and the output load. ing primary RMS current. However, in CCM operation the system's dynamic behavior is considerably worse. with DCM operation, thus CCM will not be considered. Table 1. Converter specification data and pre-design choices

2 CONVERTER ELECTRICAL SPECIFICATION

setting up the brownout protection on the types where it is available. Table 2. Mains voltage specifications the typical requirement is 1 mains cycle, that is NH = 1. It impacts on the input bulk capacitor selection. choice of the feedback technique (primary or secondary). to-peak amplitude and includes both low frequency (at 2·fL) and high frequency (fsw) component. ■ Converter Efficiency. The efficiency is, by definition, the ratio of the output power to the input power. This figure is strongly dependent on the output voltage, because of the losses on the secondary diode. output voltages (12 V and above).

3 PRE-DESIGN CHOICES

vided some constraints are taken into account.

110V AC and WRM applications, and close to 36% in 220 VAC applications. Figure 2. Drain voltage composition. applications (see fig. 2). This will affect the design of the clamp circuit.

allowance for increasing at heavy load and dropping at zero load. typical forward drop of 0.8 V. pacitor. A typical value can be 3 V.

4 PRELIMINARY CALCULATIONS (STEP 1)

block of the converter. They are summarized in table 3. Table 3. Preliminary calculations (step 1).

5 BRIDGE RECTIFIER SELECTION

ufacturers make integrated bridge rectifiers housed in small packages. See table 4 for some suggested parts. Table 4. 1A standard silicon rectifier and bridge selection

6 INPUT BULK CAPACITOR SELECTION

maximum duty cycle and the maximum peak current allowed by the IC must not be exceeded at this voltage. DCmin @ VACmin) should be considered. Figure 3. Input voltage waveforms: in give origin to the opposite situation. ing, which means that in normal operation the ripple will be much less. taking also the tolerance into account.

Table 5. Cin values for 1W input power initially assumed equal to zero. After few iterations both Vinmin and TC will converge to their respective values. H = 0 to find Vinmin in normal operation (to be used for steady state and thermal calculations). for 220 VAC or WRM applications.

7 PRELIMINARY CALCULATIONS (STEP 2)

imum value defined at 125°C. R not to hurt the primary-to-secondary energy transfer. the converter should be derated.

110 VAC or WRM 220 V AC

2 P in

12 N H⋅+

All of the above mentioned calculation steps are summarized in table 6. Table 6. Preliminary Calculations (step 2)

8 OPERATING CONDITIONS @ V IN = VDCMIN

the converter as well, are usually encountered at minimum input voltage. Table 7. Relationship useful for calculating converter's operating conditions @ Vin = VDCmin

2 IpDC

the primary winding and, in case, some external capacitance. capacitor is added on the drain. tance allowed for safe operation at maximum ambient temperature. Table 8. IC's power losses estimate outing to become a serious issue.

2 IsDC

125 T amb–

2 R DS on() max⋅=

Table 7. (continued)

liminary Calculations - step 2", may be necessary.

9 FLYBACK TRANSFORMER DESIGN

primary-to-secondary turns ratio (n) are still to be defined. Table 9. Ferrite Materials selection required. Table 9 shows some suitable materials. ings. Consider that minimizing leakage inductance is one of the major tasks in the design of a flyback transformer. and economic considerations. Table 10 shows some possible choices with the relevant data useful for the design. this a DCM design, Bmax will also equal the maximum flux density swing ΔBmax.

means that transformer's power losses will be located mostly in the windings. maximize core utilization, or Bmax = 0.25 T can be chosen for a more conservative design. lim = 0.7A, from the datasheet). Now a step-by-step procedure for the design of the transformer will be given. Table 10. Core list and significant design data process and a proper starting point may reduce considerably the number of iterations needed. is possible to define the minimum AP required by a specific application.

(6) In this equation Δ T is the hot-spot temperature rise (located in the core center leg, where heat can be re- moved more difficultly), defined as Δ T = Tmax - Tamb . For reliability reasons Tmax is usually limited at 100°C where, by the way, ferrites usually feature minimum losses. Ku is the window utilization factor, that is the por- tion of the total core window area occupied by the windings, which can be estimated equal to 0.4 for margin wound construction and to 0.7 for triple insulated wire construction. The smallest core with an AP greater then AP min will be chosen from the catalog data (the core list of table 10 can be used as a reference). If there is a core with an AP < APmin but very close to, it might be worthwhile trying to design with this smaller core before trying the larger one. 2) Calculate the required minimum number of primary turns of the primary winding. It will be given by: 3) Define primary and secondary windings' turns number. In the case of single-output under consideration, the secondary winding turns number Ns will be simply: that is, the result of the division will be rounded up to the next larger integer. The actual primary turns will then be calculated, rounding the result to the closest integer. Np = [Ns · n + 0.5]. It can be convenient to round to the next even number when interleaved winding technique is to be used for transformer construction, so as to split the primary in two equal halves. 4) Calculate the air gap length. The gap length (lg) needed to get the desired inductance Lp will be calculated with the following empirical formula: (7) If the calculated value is not available as a standard part, if possible, the primary turns number can be adjust- ed a little bit to get an off-the-shelf part. The air gap should be located on the core center leg only, to minimize radiated fields. In prototyping, center leg grinding to get nonstandard gap values can be avoided by keeping the two half-cores apart by about half the calculated value with spacers. Calculate transformer total losses. The allowed total transformer losses (Ptot) can be calculated by dividing the hot-spot temperature rise Δ T by the thermal resistance of the wound core Rth(core): If the manufacturer does not provide thermal data, Rth(core) can be estimated. It has been shown [1] that there is a good correlation between core's area product and thermal resistance, regardless of its shape: R th(core) ≈ 23 · AP-0.37 [°C/W]; Ap min 103 Lp IpRMS⋅ T 2--- Δ Ku B max⋅⋅ 1.316 cm 4[]⋅= Np min Lp 0.7⋅ N s Np Ig Lp mm[]= P tot TΔ R th core()

this best-fit equation refers to natural convection cooling. 6) Calculate the actual flux swing, the actual core losses and the allowed copper losses. The flux swing will be given by: (8) and the corresponding core losses can be calculated with the formulae in table 9: (9) The allowed copper losses will obviously be: PCu = Ptot - PFe [W] (10) 7) Design windings. The goal is to find the right wire size so that copper losses are within the limit stated by (10). At this moment, losses due to skin and proximity effect will not be accounted for. The construction tech- nique of the transformer will be such that these effects will be minimized. Copper losses will be equally apportioned to the primary and the secondary winding (the power handled by the auxiliary one is negligible). Therefore the maximum primary and secondary winding resistance will be re- spectively: ; (11) The primary and secondary conductor copper cross-section area will be obtained considering the resistivity of copper at 100°C ( ρ100 = 2.303·10-6 Ω ·cm) and the average length-per-turn (4) of the bobbin associated to the selected core: (12) (13) A wire table (like the sample one shown in table 11) will be looked up and a wire with a copper area (ApCu, AsCu) equal or greater than the minimum above calculated will be selected. Anyway, to minimize skin effect, the selected wire diameter should not exceed 2·δ, where δ is the skin depth of copper (about 0.3 mm at 65 kHz and 100°C). In practice, the maximum wire size for minimum skin effect is AWG23 (∅ 0.57 mm, ACu = 0.2573 mm2). If ApCu is larger, a number (Nwp, Nws) of such (or smaller) wires will be paralleled so as to achieve the desired total area: where the results will be rounded up to the next larger integer. BΔ Lp lppk⋅ P Fe V e kB pΔ fsw q [W ]⋅⋅ ⋅= Rp P Cu 2I pRMS P Cu 2I sRMS Ap Cumin ρ100 Np L t⋅⋅ As Cumin ρ100 Ns L t⋅⋅ Nwp Ap Cumin Ap Cu Nws As Cumin As Cu

Table 11. Wire Table (RS-214). Copper wire. Heavy insulation. d) use the next size core and restart from step 2. where 0.7 V is the typical forward drop on the auxiliary (small signal) diode.

rule is to minimize parasitics, basically leakage inductance and winding capacitance. insulation construction is recommended. Figure 4. Interleaved winding technique bled transformer, leakage inductance will be about 1 to 3% of the primary inductance. half of the primary, see fig. 4) may considerably reduce leakage inductance (theoretically almost four times). between windings to a minimum are also effective. Besides, the use of split bobbins is not recommended. ditional damping networks to comply with EMC requirements. and therefore should be done with care.

2 Rs Is RMS

10 CLAMP CIRCUIT DESIGN

but dissipates more power at full load. Figure 5. Suggested clamp circuit topologies tion and prevent overheating due to the high peak currents it experiences.

will then be quite larger than the minimum as well. Table 12. Recommended ST parts for blocking diode. whereas the desired clamp voltage is to be considered at operating junction temperature and Ilim current. desired clamp level. Please refer to [2] and [3] to see how these problems are handled. Table 13 lists some recommended devices available from ST. the breakdown voltage could be derated to VPKmax . Table 13. Recommended ST parts for clamping.

110 VAC 220 VAC or WRM

130 V BZW04-188

11 SECONDARY RECTIFIER SELECTION

Table 14. Recommended ST parts for secondary rectification.

12 OUTPUT CAPACITOR SELECTION AND POST FILTER

15 BYV10-60

18 BYV10-60

24 BAT49

may be achieved by using paralleled capacitors. value definitely meets condition (18). like the one shown in fig. 6, that attenuates the ripple to the desired level. Figure 6. Output post filter for ripple reduction connected upstream the post filter to avoid stability problems (see "Control loop compensation" section).

13 SELF-SUPPLY CIRCUIT DESIGN

since the turns number of the auxiliary winding has been defined already. few mA. A popular 1N4148 (75V rating) or an UF4003 (200V rating) may be suitable choices. used instead of RS, with even better results. Figure 7. Self-supply circuit

14 BROWNOUT PROTECTION DESIGN (L6590A AND L6590D ONLY)

timing diagram of figure 8).

Figure 8. Brownout protection circuit and timing diagram

15 CONTROL LOOP DESIGN

in the complex frequency domain represented by means of a Bode plot. Figure 9. Control loop Block Diagram compensated error amplifier is the "controller".

The transfer function G2(jω ) of the plant is defined by the control method (voltage mode), the topology of the converter (flyback) and its operating mode (DCM in the specific case). The task of the control loop design is then to determine the transfer function G1(j ω ) of the error amplifier and define the relevant frequency compensation network. The objective of the design is to ensure that the resulting closed-loop system will be stable and well performing in terms of dynamic response, line and load regulation. The characteristics of the closed-loop system can be inferred from its open-loop properties. Provided the open- loop gain crosses the 0 dB axis only once at f= f c (crossover frequency), stability will be ensured if the gain phase shift (besides the 180° due to negative feedback) is less than 180° at f = fc. This is the well-known Nyquist's stability criterion. Anyway, adequate margin to this boundary condition must be provided to prevent instability due to parameter variations and to optimize the dynamic response that would be severely underdamped otherwise. Under worst case condition this "phase margin" Φ m should never go below 20 or 30°. Typically, Φ m = 45° in nominal condi- tions is used as a design guideline: this ensures fast transient response with very little ringing. Sometimes a higher margin (up to 60° or 75°) is required to account for very large spreads in line, load and temperature changes as well as manufacturing tolerances. Although Nyquist's criterion allows the phase shift to be over 180° at a frequency below f c, this is not recom- mended because it would result in a conditionally stable system. A reduction of the gain (which may temporarily happen during large load transients) would cause the system to oscillate, therefore the phase shift should not get close to 180° at any frequency below f Optimum dynamic performance requires a large gain bandwidth, that is the crossover frequency fc to be pushed as high as possible (≤ fsw/4). When optimum dynamic performance is not a concern, fc will be typically chosen equal to fsw/10. Good load and line regulation implies a high DC gain, thus the open loop gain should have a pole at the origin. In this way the theoretical DC gain would tend to infinity, whereas the real-world one will be limited by the low- frequency gain of the Error Amplifier. Since voltage mode control has poor open-loop line regulation, the overall gain should be still high also at frequencies around 100-120 Hz to maximize rejection of the input voltage ripple. This is related to phase margin: a higher phase margin leads to a lower low-frequency gain. Once the goal of the design has been established in terms of crossover frequency and phase margin, the next step is to determine the transfer function of the plant G2(j ω ) in order to select an appropriate structure for G1(jω ). The transfer function G2(jω ) of the plant is described in Tab. 15, while its asymptotic Bode plot is illustrated in Fig.10. In G20 definition the ratio Dmax/Vs is the PWM modulator gain, while Dmax = 0.7 is the maximum duty cycle and Vs = (3.5-1.5) = 2 V is the oscillator peak-to-valley swing (see the relevant section). Rout = Vout/Iout is the equiv- alent load resistor. This kind of plant will be stabilized in closed-loop operation by what is commonly known as a Type 2 amplifier. Its transfer function G1(jω ), which comprises a pole at the origin and a zero-pole pair, is defined as: Its asymptotic Bode plot is illustrated in Fig. 11. The main task of this correction is to boost the phase of the overall loop (actually, to reduce the phase lag of G2(jω )) in the neighborhood of the crossover frequency. G1 jω() G1 0 1 jω ω Z 1 jω ω P

The synthesis of G1(jω ) can be done by following the following step-by-step procedure: a) Calculate gain and phase of G2(jω ) at the desired crossover frequency (fc). That is: G2(jω ) will be calculated at maximum input voltage and maximum load, where the gain-bandwidth product is maximum. b) Calculate gain and phase of G1(jω ) at f = fc in order for the overall open-loop gain to cross the 0 dB axis at f = fc with the phase margin Φ m : c) Cancel the pole of G2(jω ) by placing the zero of G1(jω ) in the neighborhood: ( α = 1 to 5) d) Place the pole of G1(jω ) so as to get the desired phase margin: e) Calculate the unity gain frequency G10: The synthesis of G1(jω ) is completed. The following step will concern the practical implementation of such func- tion, that is the realization of a Type 2 amplifier. This will be done considering two cases, the secondary and the primary sensing feedback.

16 SECONDARY FEEDBACK IMPLEMENTATION

This kind of feedback, shown in fig. 12, uses a popular arrangement with a TL431 as secondary reference/error amplifier and an optocoupler to transfer the control signal to the primary side. The error amplifier of the IC is then used as a current source whose characteristic is shown in fig. 12 as well: the voltage V COMP is changed (and the duty cycle is controlled) by modulating the current Ic sunk from the pin. A change of Ic causes a change of V COMP corresponding to a resistance RCOMP = 9 kΩ . The resulting transfer function is: and table 16 shows how its quantities are defined G2 c G2 2 π fc⋅⋅()= Φ 2c 180 G1 c G1 2 π fc⋅⋅() 1 G2 c Φ 1c 180 fZ ω Z ω out fP ω P fC π tan G1 0 2 π G1 c fc fZ⋅ fP G1 jω() VCOMPΔ VCOMPΔ ICΔ IFΔ V KΔ CTR max R COMP⋅ jω----- 1j ω R H R F+() C F⋅⋅+

Figure 12. Secondary feedback: TL431 + optocoupler circuit (I) Table 16. G1(jω ) Implementation: secondary feedback (I) should be selected and the calculations from step a) to step e) redone.

Figure 13. PWM gain reduction by RC (secondary feedback II). B can be used, thus giving some extra gain reduction. An additional resistor, RB1, of some kΩ could be needed to guarantee sufficient bias to the TL431. cycle specified for a given application, this can be acceptable. Table 17. PWM gain reduction for different RC values In this case the design procedure outlined in table 16 should be slightly modified as shown in table 18.

Table 18. G1(jω ) Implementation: secondary feedback (II) the error amplifier on board. and Table 19 shows how its quantities are defined. Figure 14. Secondary feedback: TL431 + optocoupler circuit (III)

Table 19. G1(jω ) Implementation: secondary feedback (III) current regulation (e.g. battery chargers, see fig.40 on L6590’s datasheet). Q . The device will be switched off as it goes into UVLO. into UVLO just like in case of overload or short circuit. C) in series to the capacitor.

Figure 15. Secondary feedback: TL431 + optocoupler circuit (IV) Table 20. G1(jω ) Implementation: secondary feedback (IV)

17 PRIMARY FEEDBACK IMPLEMENTATION

coupler is needed, but provides poor regulation, especially as a result of load changes. Figure 16. Primary feedback: circuits Table 21. G1(jω ) Implementation: Primary Feedback minimum load regulation and its value may range from few units to some hundred ohm.

Figure 17. Leading Edge Blanking (LEB) circuit for leakage inductance spikes filtering transformer's leakage inductance, is the major responsible for the poor load regulation.

18 LAYOUT RECOMMENDATIONS

priate traces widths and compliance with isolation distances are the major issues. Figure 18. Suggested ground routing for converters with secondary feedback.

tocoupler for secondary feedback. direct one) noise will be injected into the signal circuitry. Figure 20. Possible component placement.

19 TEST BOARD: DESIGN AND EVALUATION

calculations needed to go further with the design steps. Table 22. Test board's electrical specification and pre-design choices

An integrated bridge (DF06M, 4x1A/600V, GI) has been selected. Operating conditions @ Vin = VDCmin and thermal check. result is shown in table 23d). Figure 21. L6590 Family Packages Junction-to-Ambient Thermal Resistance

1 Oz 2 Oz

Table 22. (continued)

Table 23. Test Board design calculations results.

Flyback transformer design Eqn. 4 gives the primary inductance (Lp = 1.37 mH, rounded up to 1.4 mH), while eqn. (5) gives the primary-to- secondary turns ratio (n = 21.4). The design will be done considering Philip's E-cores in 3C85 ferrite and as- suming a maximum peak flux of 0.25T, a temperature rise of 40 °C and 40% window utilization factor. Going step-by-step: 1) Eqn. 6 provides a minimum AP of 0.042 cm 4. Table 10 shows that an E20/10/6 core could fit the design. 2) The primary turns number will be Npmin = 122.5. 3) The resulting secondary turn number will be 122.5/21.4=5.7 which will rounded up to 6. The primary turns number will then become 6·21.4=128.4. Finally, the choice will be Np=128 turns and Ns=6 turns, which yields an actual turns ratio of 128/6 = 21.33, very close to the target. 4) From eqn. 7, the air gap needed to get the desired value of Lp will be 0.63 mm. 5) Table 10 shows that the thermal resistance of the finished core is 46 °C/W, thus the maximum power dissi- pation inside the transformer shall not exceed 40/46 = 0.87 W. 6) Equations 8, 9 and 10 will provide the actual flux swing (which will be lower than 0.25 T because Np>Npmin), the actual core losses and the allowed copper losses respectively. The resulting flux swing is ΔB=180 mT: the relevant core losses amount at 66 mW, thus it is possible to dissipate up to 0.8 W in the windings. 7) The required primary and secondary winding resistance will be 8.65 Ω and 30 mΩ respectively (resulting from eqns. 11). The resulting primary resistance is quite high and the drop across it reduces significantly the actual voltage applied at the primary inductance. The target primary resistance is then reduced at 4 Ω and the secondary will be increased at 46mΩ to maintain the same total copper losses. The required primary and secondary copper area will be 2.87·10-4 cm2 and 1.2·10-3 cm2 respectively (eqns. 12, 13). Table 11 shows that this can be done with one AWG32 wire at the primary and four paralleled (twist- ed) AWG32 wires at the secondary. This will both minimize high frequency effects and simplify the BOM. The total occupied area will be 7 mm 2 (eqn. 14), 20% of the total available area, thus the windings will fit. On top of the primary and secondary winding, 14 turns of AWG32 wire will be wound to make the auxiliary winding (eqn. 15). 8) The actual resistance of the primary and secondary windings will be 3.6 Ω and 42 mΩ respectively, for total Zener clamp To optimize losses at light load a zener clamp will be used. The clamp voltage should be around 200 V (eqn. 16), thus a BZW06-154 is first selected. Assuming a leakage inductance of 30 µH (about 2% of the primary inductance), power dissipation will be about 0.6 W in normal operation and about 1.1 W in overcurrent limitation. The relevant clamping voltages would be 196 V and 209 V respectively. The initial choice will then be confirmed. An STTA106 (1A / 600V turboswitch diode) will be used as the blocking diode. Secondary rectifier According to eqn. 17, and considering 25% margin, the blocking voltage of the diode should exceed 28 V, while its current rating should be in excess of 4 A. Although table 14 suggests a bigger device, an 1N5822 (3A/40V) Schottky diode is selected for this test board.

Capacitor's ripple current rating should exceed 3 A. The minimum capacitance value should be 373 µF (eqn. 18) and the maximum ESR should be less than 5 mΩ . For long-time reliability the capacitor(s) should also be able to withstand at least 3.08 A current ripple. Three Rubycon's ZL series 470 µF/16V paralleled capacitors were selected, for a total ripple capability of nearly 3 A and a total ESR of about 20 m Ω . To meet the requirement on the output voltage ripple an LC post filter is needed that attenuates ripple at least four times. Choosing a standard value of L = 4.7 µH, the maximum ESR of the additional capacitor should not exceed 300m Ω . An additional 220 µF/10V ZL capacitor has been added. Self-supply circuit The self supply circuit will include an 1N4148 diode and a 22 µF supply capacitor. A 10 Ω resistor will be added in series to the diode to reduce Vcc voltage variations with the load current. This value is likely to be adjusted after bench verification. Control loop design The crossover frequency will be selected as high as 10 kHz, worst case. The objective will be to get 70° phase margin. The plant transfer function is: with G2o = 11.5, f ESR = 5464 Hz, fout = 90.3 Hz (@ max. load and max. Vin). A type 2 amplifier will be used for G1(jω ). Going step-by-step: a) The gain and phase of G2 at f=10 kHz are 0.281 and -29° respectively; b) In order for the overall open-loop gain to cross the 0 dB axis at f=10 kHz with 70° phase margin, the gain and phase of G1(j ω ) will be 3.56 and -81° respectively; c) the compensating zero will be placed at 360 Hz (α = 4, to maximize 100Hz gain); d) the compensating pole will be placed at 2270 Hz; e) the unity gain factor is 35.4·10 4 s/rad. Since a tight tolerance on the output voltage is required, an optoisolated feedback will be used and G1(jω ) will be realized with the schematic of figure 13. The TL431 and an optocoupler PC817A from Sharp will be used. The CTR is specified between 0.8 and 1.6. Using a 6.8k Ω resistor as RC, the resulting part values are: R L = RH = 2.43 kΩ ; RB = 560 Ω ; RF = 2kΩ ; CF = 100 nF; CCOMP = 22 nF. Electrical Schematic, BOM and evaluation results In fig. 22 the electrical schematic of the test board is illustrated and table 24 lists the relevant BOM. The dia- grams of figure 23 show the evaluation results of the board, figure 24 shows some typical waveforms and figure 25 the effect of the frequency change on the output voltage transient. G2 jω() G2 0 1 jω ω ESR 1 jω ω out

Figure 22. Test board electrical schematic Table 24. Test board Bill Of Material

5 Vdc / 2 A

Figure 23. Test board evaluation results

264 VAC

88 VAC

110 VAC

220 VAC

Table 24. (continued)

Figure 24. Test board main waveforms under different operating conditions Figure 25. Test board load transient response; effect of frequency change (left).

20 REFERENCES

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics  2001 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com AN1262 APPLICATION NOTE