DFPADD DCD | Alldatasheet

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All trademarks mentioned in this document are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved. http://www.DigitalCoreDesign.com Encrypted, or plain text EDIF netlist DDFFPPAADDDD Floating Point Pipelined Adder Unit ver 2.50 Fully synthesizable, static synchronous design with no internal tri-states OVERVIEW The DFPADD uses the pipelined mathemat- ics algorithm to compute sum of two argu- ments. The input numbers format is accord- ing to IEEE-754 standard. DFPADD supports single precision real number. Add operation was pipelined up to 5 levels. Input data are fed every clock cycle. The first result appears after 5 clock periods latency and next results are available each clock cycle. Full IEEE- 754 precision and accuracy were included. DELIVERABLES Source code: VHDL Source Code or/and VERILOG Source Code or/and VHDL & VERILOG test bench environ- ment Active-HDL automatic simulation mac- ros APPLICATION NCSim automatic simulation macros ModelSim automatic simulation macros Math coprocessors Tests with reference responses DSP algorithms Technical documentation Installation notes Embedded arithmetic coprocessor HDL core specification Data processing & control Datasheet Synthesis scripts Example application KEY FEATURES Technical support IP Core implementation support Full IEEE-754 compliance 3 months maintenance Single precision real format support ● Delivery the IP Core updates, minor and major versions changes Simple interface ● Delivery the documentation updates No programming required ● Phone & email support 5 levels pipeline LICENSING Full accuracy and precision Comprehensible and clearly defined licensing methods without royalty fees make using of IP Core easy and simply. Results available at every clock Overflow, underflow and invalid operation flags Single Design license allows using IP Core in single FPGA bitstream and ASIC implemen-Fully configurable

tation. It also permits FPGA prototyping be- fore ASIC production. BLOCK DIAGRAM bdatai(31:0) datao(31:0) en rst clk ofo ufo ifo Arguments Checker Main FP Pipelined Unit Result Composer adatai(31:0) Unlimited Designs license allows using IP Core in unlimited number of FPGA bitstreams and ASIC implementations. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited. There is no time of use limitations. Arguments Checker - performs input data analyze against IEEE-754 number standard compliance. The appropriate numbers and information about the input data classes are given as the results to Main FP Pipelined Unit. Single Design license for VHDL, Verilog source code called HDL Source Encrypted, or plain text EDIF called Netlist All trademarks mentioned in this document are trademarks of their respective owners. Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved. http://www.DigitalCoreDesign.com http://www.dcd.pl Unlimited Designs license for HDL Source Main FP Pipelined Unit - performs floating point add function. Gives the complex infor- mation about the results and makes final flags settings. Netlist Upgrade from Netlist to HDL Source Single Design to Unlimited Designs SYMBOL Result Composer - performs result rounding function, data alignment to IEEE-754 stan- dard, and the final flags setting. adatai(31:0) bdatai(31:0) datao(31:0) en rst clk ofo ufo ifo PERFORMANCE The following table gives a survey about the Core area and performance in the ALTERA® devices after Place & Route : PINS DESCRIPTION PIN TYPE DESCRIPTION clk Input Global system clock rst Input Global system reset en Input Enable computing adatai[31:0] Input A data bus input bdatai[31:0] Input B data bus input datao[31:0] Output Data bus output ofo Output Overflow flag ufo Output Underflow flag ifo Output Invalid result flag Speed Device Logic Cells Fmaxgrade FLEX10KE -1 1110 47 MHz ACEX1K -1 1110 47 MHz APEX20K -1 955 55 MHz APEX20KE -1 955 52 MHz APEX20KC -7 955 68 MHz APEX-II -7 955 88 MHz MERCURY -5 975 117 MHz STRATIX -5 845 107 MHz CYCLONE -6 845 104 MHz STRATIX-II -3 690 153 MHz CYCLONE-II -6 845 105 MHz Core performance in ALTERA® devices

All trademarks mentioned in this document are trademarks of their respective owners. Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved. http://www.DigitalCoreDesign.com http://www.dcd.pl CONTACTS For any modification or special request please contact to Digital Core Design or local distributors. Headquarters: Wroclawska 94 41-902 Bytom, POLAND e-mail: info@dcd.pliinnffoo@@ddccdd..ppll tel. : +48 32 282 82 66 fax : +48 32 282 74 37 Distributors: