DF70854AD80FPV

DF70854AD80FPV RENESAS | Alldatasheet

Document overview

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• PDF pages: 1622

Technical content

Datasheet sections

• 1.1 Features of SH7083, SH7084, SH7085, and SH7086
• 1.2 Block Diagram
• 1.3 Pin Assignments
• 1.4 Pin Functions
• 2.1 Features
• 2.2.1 General Registers (Rn)
• 2.2.2 Control Registers
• 2.2.3 System Registers
• 2.2.4 Initial Values of Registers
• 2.3 Data Formats
• 2.3.1 Register Data Format
• 2.3.2 Memory Data Formats
• 2.3.3 Immediate Data Formats
• 2.4 Features of Instructions
• 2.4.1 RISC Type
• 2.4.2 Addressing Modes
• 2.4.3 Instruction Formats
• 2.5 Instruction Set
• 2.5.1 Instruction Set by Type
• 2.5.2 Data Transfer Instructions
• 2.5.3 Arithmetic Operation Instructions
• 2.5.4 Logic Operation Instructions
• 2.5.5 Shift Instructions
• 2.5.6 Branch Instructions
• 2.5.7 System Control Instructions
• 2.6 Processing States
• 3.1 Selection of Operating Modes
• 3.2 Input/Output Pins
• 3.3.1 Mode 0 (MCU Extension Mode 0)
• 3.3.2 Mode 1 (MCU Extension Mode 1)

User's Manual: Hardware Rev.5.00 Mar 2011 SH7083 R5F7083 R5M7083 R5S7083 SH7084 R5F7084 R5M7084 R5S7084 SH7085 R5F7085 R5M7085 R5S7085 SH7086 R5F7086 Renesas 32-Bit RISC Microcompute r SuperH TM RISC engine Family

Page ii of lviii R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. Notes regarding these materials

R01UH0198EJ0500 Rev. 5.00 Page iii of lviii Mar 18, 2011 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual. ⎯ The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions may occur due to the false recognition of the pin state as an input signal. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. ⎯ The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. ⎯ The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. ⎯ When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different type number, confirm that the change will not lead to problems. ⎯ The characteristics of MPU/MCU in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different type numbers, implement a system-evaluation test for each of the products.

Page iv of lviii R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 Configuration of This Manual This manual comprises the following items: 1. General Precautions in the Handling of MPU/MCU Products 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules

• CPU and System-Control Modules
• On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. List of Registers 8. Electrical Characteristics 9. Appendix 10. Main Revisions for This Edition (only for revised versions) The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 11. Index

R01UH0198EJ0500 Rev. 5.00 Page v of lviii Mar 18, 2011 Preface The SH7083, SH7084, SH7085, and SH7086 Group RISC (Reduced Instruction Set Computer) microcomputers include a Renesas original RISC CPU as its core, and the peripheral functions required to configure a system. Target Users: This manual was written for users who will be using the SH7083, SH7084, SH7085, and SH7086 Group in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of the SH7083, SH7084, SH7085, and SH7086 Group to the target users. Refer to the SH-1/SH-2/SH-DSP Software Manual for a detailed description of the instruction set. Notes on reading this manual:

• In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics.
• In order to understand the details of the CPU's functions Read the SH-1/SH-2/SH-DSP Software Manual.
• In order to understand the details of a register when its name is known Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bits, and initial values of the registers are summarized in section 27, List of Registers. Examples: Register name: The following notatio n is used for cases when the same or a similar function, e.g. serial communication interface, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel number) Bit order: The MSB is on the left and the LSB is on the right. Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx. Signal notation: An overbar is added to a low-active signal: xxxx

Page vi of lviii R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/ SH7083, SH7084, SH7085, and SH7086 Group Manuals: Document Title Document No. SH7080 Group Hardware Manual This manual SH-1/SH-2/SH-DSP Software Manual REJ09B0171 User's Manuals for Development Tools: Document Title Document No. SuperH TM RISC engine C/C++ Compiler, Assembler, Optimizing Linkage Editor Compiler Package V.9.04 User's Manual REJ10J2202 High-performance Embedded Workshop User's Manual REJ10J2169 Application Note: Document Title Document No. SuperH RISC engine C/C++ Compiler Package Application Note REJ05B0463 All trademarks and registered trademarks are the property of their respective owners.

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6.3.4 Interrupt Priority Registers A to F and H to M

6.8.1 Handling Interrupt Request Signals as Sources for DTC Activation and

6.8.2 Handling Interrupt Request Signals as Sources for DMAC Activation,

6.8.3 Handling Interrupt Request Signals as Sources for DTC Activation,

6.8.4 Handling Interrupt Request Signals as Sources for CPU Interrupts,

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8.9.5 Transfer Information Start Address, Source Address, and Destination

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11.3.11 Timer A/D Converter Start Request Cycle Set Registers

11.3.12 Timer A/D Converter Start Request Cycle Set Buffer Registers

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11.7.12 TCNT_2 Write and Overflow/Underflow Contention

11.7.19 Cautions on Transition from Normal Operation or PWM Mode 1 to

11.7.20 Output Level in Complementary PWM Mode and Reset-Synchronized

11.7.23 Notes on Output Waveform Control During Synchronous Counter

11.8.4 Overview of Initialization Procedures and Mode Transitions in Case of

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R01UH0198EJ0500 Rev. 5.00 Page xvii of lviii Mar 18, 2011 15.7.5 Receive Data Sampling Timing and Receive Margin (Asynchronous Mode) .. 789

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17.6.5 Note on Master Transmission and Master Reception Operations

C Bus Interface 2 (I 18.3.1 I 18.3.2 I 18.3.3 I 18.3.4 I 18.3.5 I 18.3.6 I 18.3.7 I 18.3.8 I 18.3.9 I 18.4.1 I

18.4.8 Using the IICRST Bit to Reset I

18.5 I

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18.8.6 Access to ICE and IICRST Bits during I

18.8.8 Operation of I

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21.1.2 Port A Control Registers L1 to L4, H1 to H4

21.1.6 Port C Control Registers L1 to L4, H1 to H3

21.1.8 Port D Control Registers L1 to L4, H1 to H4

21.1.10 Port E Control Registers L1 to L4, H1, H2

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23.9.1 Specifications of the Standard Serial Communications Interface

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R01UH0198EJ0500 Rev. 5.00 Page xlvii of lviii Mar 18, 2011 Tables Section 1 Overview Section 2 CPU Section 3 MCU Operating Modes Section 4 Clock Pulse Generator (CPG) Section 5 Exception Handling

Page xlviii of lviii R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 Section 6 Interrupt Controller (INTC) Section 7 User Break Controller (UBC) Section 8 Data Transfer Controller (DTC) Table 8.5 Transfer Information Writeback Skip Condition and Writeback Section 9 Bus State Controller (BSC) Table 9.2 Address Map: SH7083 (256-Kbyte Flash Memory Version)

R01UH0198EJ0500 Rev. 5.00 Page xlix of lviii Mar 18, 2011 Table 9.3 Address Map: SH7083 (256-Kbyte Flash Memory Version) Table 9.4 Address Map: SH7083 (512-Kbyte Flash Memory Version) Table 9.5 Address Map: SH7083 (512-Kbyte Flash Memory Version) Table 9.6 Address Map: SH7084 (256-Kbyte Flash Memory Version) Table 9.7 Address Map: SH7084 (256-Kbyte Flash Memory Version) Table 9.8 Address Map: SH7084 (512-Kbyte Flash Memory Version) Table 9.9 Address Map: SH7084 (512-Kbyte Flash Memory Version) Table 9.10 Address Map: SH7085 (256-Kbyte Flash Memory Version) Table 9.11 Address Map: SH7085 (256-Kbyte Flash Memory Version) Table 9.12 Address Map: SH7085 (512-Kbyte Flash Memory Version) Table 9.13 Address Map: SH7085 (512-Kbyte Flash Memory Version) Table 9.20 Relationship between BSZ[1:0], A2ROW[1:0]/A3ROW[1:0], Table 9.20 Relationship between BSZ[1:0], A2ROW[1:0]/A3ROW[1:0], Table 9.21 Relationship between BSZ[1:0], A2ROW[1:0]/A3ROW[1:0], Table 9.21 Relationship between BSZ[1:0], A2ROW[1:0]/A3ROW[1:0], Table 9.22 Relationship between BSZ[1:0], A2ROW[1:0]/A3ROW[1:0], Table 9.23 Relationship between BSZ[1:0], A2ROW[1:0]/A3ROW[1:0],

Page l of lviii R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 Table 9.23 Relationship between BSZ[1:0], A2ROW[1:0]/A3ROW[1:0], Table 9.24 Relationship between BSZ[1:0], A2ROW[1:0]/A3ROW[1:0], Table 9.24 Relationship between BSZ[1:0], A2ROW[1:0]/A3ROW[1:0], Table 9.25 Relationship between BSZ[1:0], A2ROW[1:0]/A3ROW[1:0], Table 9.25 Relationship between BSZ[1:0], A2ROW[1:0]/A3ROW[1:0], Table 9.29 Minimum Number of Idle Cycles between CPU Access Cycles Table 9.30 Minimum Number of Idle Cycles between Access Cycles during DMAC Table 9.31 Minimum Number of Idle Cycles during DMAC Single Address Mode Table 9.32 Minimum Number of Idle Cycles between Access Cycles of CPU, Table 9.33 Minimum Number of Idle Cycles between Access Cycles of the DMAC Table 9.34 Minimum Number of Idle Cycles between Access Cycles of the DMAC Section 10 Direct Memory Access Controller (DMAC) Table 10.8 Relationship between Request Modes and Bus Modes by DMA Transfer Category. 413

R01UH0198EJ0500 Rev. 5.00 Page li of lviii Mar 18, 2011 Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)

Page lii of lviii R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 Section 12 Multi-Function Timer Pulse Unit 2S (MTU2S) Section 13 Port Output Enable (POE) Section 14 Watchdog Timer (WDT)

R01UH0198EJ0500 Rev. 5.00 Page liii of lviii Mar 18, 2011 Section 15 Serial Communication Interface (SCI) Table 15.10 Maximum Bit Rates for Various Frequencies with Baud Rate Generator Section 16 Serial Communication Interface with FIFO (SCIF) Table 16.10 Maximum Bit Rates for Various Frequencies with Baud Rate Generator

Page liv of lviii R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 Section 17 Synchronous Serial Communication Unit (SSU) Section 18 I C Bus Interface 2 (I C2) Table 18.1 I Section 19 A/D Converter (ADC) Section 20 Compare Match Timer (CMT) Section 21 Pin Function Controller (PFC)

R01UH0198EJ0500 Rev. 5.00 Page lv of lviii Mar 18, 2011 Section 22 I/O Ports Section 23 Flash Memory Table 23.1 (1) Relationship between FWE and MD Pins and Operating Modes Table 23.1 (2) Relationship between FWE and MD Pins and Operating Modes

Page lvi of lviii R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 Table 23.8 Peripheral Clock (Pφ) Frequency that Can Automatically Adjust Bit Section 26 Power-Down Modes Section 28 Electrical Characteristics

R01UH0198EJ0500 Rev. 5.00 Page lvii of lviii Mar 18, 2011 Table 28.18 I C Bus Interface 2 (I Appendix

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R01UH0198EJ0500 Rev. 5.00 Page 1 of 1560 Mar 18, 2011 SH7080 Group Section 1 Overview

1.1 Features of SH7083, SH7084, SH7085, and SH7086

This LSI is a single-chip RISC (Reduced Instruction Set Computer) microcomputer that integrates a Renesas original RISC CPU core with peripheral functions required for system configuration. The CPU in this LSI has a RISC-type instruction set. Most instructions can be executed in one state (one system clock cycle), which greatly improves instruction execution speed. In addition, the 32-bit internal-bus architecture enhances data processing power. With this CPU, it has become possible to assemble low-cost, high-performance, and high-functioning systems, even for applications that were previously impossible with microcomputers, such as real-time control, which demands high speeds. In addition, this LSI includes on-chip peripheral functions necessary for system configuration, such as large-capacity ROM and RAM, a direct memory access controller (DMAC), a data transfer controller (DTC), timers, a serial communication interface (SCI), a serial communication interface with FIFO (SCIF), a synchronous serial communication unit (SSU), an A/D converter, an interrupt controller (INTC), I/O ports, and an I C bus interface 2 (I C2). This LSI also provides an external memory access support function to enable direct connection to various memory devices or peripheral LSIs. These on-chip functions significantly reduces costs of designing and manufacturing application systems. In terms of on-chip ROM, F-ZTAT TM (Flexible Zero Turn Around Time)* version incorporating flash memory and mask ROM version are available. The flash memory can be programmed with a programmer that supports programming of this LSI, and can also be programmed and erased by software. This enables LSI chip to be re-programmed at a user-site while mounted on a board. The features of this LSI are listed in table 1.1. Note: * F-ZTAT TM is a trademark of Renesas Electronics Corp.

Page 2 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 1.1 Features Items Specification CPU • Central processing unit with an internal 32-bit RISC (Reduced Instruction Set Computer) architecture

• Instruction length: 16-bit fixed length for improved code efficiency
• Load-store architecture (basic operations are executed between registers)
• Sixteen 32-bit general registers
• Five-stage pipeline
• On-chip multiplier: Multiplication operations (32 bits × 32 bits → 64 bits) executed in two to five cycles
• C language-oriented 62 basic instructions Note: Some specifications on slot illegal instruction exception handling in this LSI differ from those of the conventional SH-2. For details, see section 5.8.4, Notes on Slot Illegal Instruction Exception Handling. Operating modes • Operating modes ⎯ Single chip mode ⎯ Extended ROM enabled mode ⎯ Extended ROM disabled mode
• Operating states ⎯ Program execution state ⎯ Exception handling state ⎯ Bus release state
• Power-down modes ⎯ Sleep mode ⎯ Software standby mode ⎯ Deep software standby mode ⎯ Module standby mode User break controller (UBC)
• Addresses, data values, type of access, and data size can all be set as break conditions
• Supports a sequential break function
• Two break channels On-chip ROM • 256 kbytes or 512 kbytes

R01UH0198EJ0500 Rev. 5.00 Page 3 of 1560 Mar 18, 2011 SH7080 Group Items Specification On-chip RAM • 16 kbytes or 32 kbytes Bus state controller (BSC)

• Address space divided into nine areas: Eight areas (CS0 to CS7), each a maximum of 64 Mbytes, and one area (CS8) of a maximum of 1 Gbytes (a total of three areas in SH7083, eight areas in SH7084/SH7085, and nine areas in SH7086)
• 8-bit external bus
• 16-bit external bus
• 32-bit external bus (only in SH7085/SH7086)
• The following features settable for each area independently ⎯ Bus size (8, 16, or 32 bits) ⎯ Number of access wait cycles ⎯ Idle wait cycle insertion ⎯ Specifying the memory to be connected to each area enables direct connection to SRAM, SRAM with byte selection, burst ROM (clock synchronous or asynchronous), MPX-I/O, burst MPX-I/O, SDRAM, and PCMCIA
• Outputs a chip select signal according to the target area Direct memory access controller (DMAC)
• Four channels
• External request available
• Burst mode and cycle steal mode Data transfer controller (DTC)
• Data transfer activated by an on-chip peripheral module interrupt can be done independently of the CPU transfer.
• Transfer mode selectable for each interrupt source (transfer mode is specified in memory)
• Multiple data transfer enabled for one activation source
• Various transfer modes Normal mode, repeat mode, or block transfer mode can be selected.
• Data transfer size can be specified as byte, word, or longword
• The interrupt that activated the DTC can be issued to the CPU. A CPU interrupt can be requested after one data transfer completion.
• A CPU interrupt can be requested after all specified data transfer completion.

Page 4 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Items Specification Interrupt controller (INTC)

• Nine external interrupt pins (NMI and IRQ7 to IRQ0)
• On-chip peripheral interrupts: Priority level set for each module
• Vector addresses: A vector address for each interrupt source User debugging interface (H-UDI) (only in F-ZTAT version)
• E10A emulator support Advanced user debugger (AUD) (only in F-ZTAT version supporting full functions of E10A)
• E10A emulator support Clock pulse generator (CPG)
• Clock mode: Input clock can be selected from external input or crystal resonator
• Five types of clocks generated: ⎯ CPU clock: Maximum 80 MHz ⎯ Bus clock: Maximum 40 MHz ⎯ Peripheral clock: Maximum 40 MHz ⎯ MTU2 clock: Maximum 40 MHz ⎯ MTU2S clock: Maximum 80 MHz Watchdog timer (WDT)
• On-chip one-channel watchdog timer
• Interrupt generation is supported.

R01UH0198EJ0500 Rev. 5.00 Page 5 of 1560 Mar 18, 2011 SH7080 Group Items Specification Multi-function timer pulse unit 2 (MTU2)

• Maximum 16 lines (maximum 13 lines in SH7083) of pulse input/output and three lines of pulse input based on six channels of 16-bit timers
• 21 output compare and input capture registers
• A total of 21 independent comparators
• Selection of eight counter input clocks
• Input capture function
• Pulse output modes Toggle, PWM, complementary PWM, and reset-synchronized PWM modes
• Synchronization of multiple counters
• Complementary PWM output mode ⎯ Six-phase (four-phase in SH7083) non-overlapping waveforms output for inverter control ⎯ Automatic dead time setting ⎯ 0% to 100% PWM duty cycle specifiable ⎯ Output suppression ⎯ A/D conversion delaying function ⎯ Dead time compensation ⎯ Interrupt skipping at crest or trough
• Reset-synchronized PWM mode Three-phase PWM waveforms in positive and negative phases can be output with a required duty cycle
• Phase counting mode Two-phase encoder pulse counting available Multi-function timer pulse unit 2S (MTU2S)
• Subset of MTU2, including channels 3 to 5
• Operating at 80 MHz max. Port output enable (POE)
• High-impedance control of waveform output pins in MTU2 and MTU2S Compare match timer (CMT)
• 16-bit counters
• Compare match interrupts can be generated
• Two channels Serial communication interface (SCI)
• Clock synchronous or asynchronous mode
• Three channels

Page 6 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Items Specification Serial communication interface with FIFO (SCIF)

• Clock synchronous or asynchronous mode
• Separate 16-byte FIFO registers for transmission and reception
• One channel Synchronous serial communication unit (SSU)
• Master mode or slave mode selectable
• Standard mode or bidirectional mode selectable
• Transmit/receive data length can be selected from 8, 16, and 32 bits.
• Full-duplex communication (transmission and reception executed simultaneously)
• Consecutive serial communication
• One channel I C bus interface 2 C2) (SH7084, SH7085, and SH7086 only)
• Conforming to Philips I C bus interface
• Master mode and slave mode supported
• Continuous transfer
• I C bus format or clock synchronous serial format selectable
• One channel A/D converter (ADC) • 10 bits × 8 channels (in SH7083/SH7084/SH7085)
• 10 bits × 16 channels (in SH7086)
• Conversion request by external triggers, MTU2, or MTU2S
• Two sample-and-hold function units (two channels can be sampled simultaneously) (in SH7083/SH7084/SH7085)
• Three sample-and-hold function units (three channels can be sampled simultaneously) (in SH7086) I/O ports • 65 general input/output pins and eight general input pins (SH7083)
• 76 general input/output pins and eight general input pins (SH7084)
• 100 general input/output pins and eight general input pins (SH7085)
• 118 general input/output pins and 16 general input pins (SH7086)
• Input or output can be selected for each bit
• LQFP2020-112 (0.65 pitch) (SH7084)
• LQFP2020-144 (0.5 pitch) (SH7085)
• LQFP2424-176 (0.5 pitch) (SH7086) Power supply voltage • Vcc: 3.0 to 3.6 V or 4.0 to 5.5 V
• AVcc: 4.0 to 5.5 V

R01UH0198EJ0500 Rev. 5.00 Page 7 of 1560 Mar 18, 2011 SH7080 Group

1.2 Block Diagram

The block diagram of this LSI is shown in figure 1.1. SH2 CPU UBC AUD BSC DMAC I/O port (PFC) [Legend] ROM: On-chip ROM RAM: On-chip RAM UBC: User break controller AUD: Advanced user debugger H-UDI: User debugging interface INTC: Interrupt controller CPG: Clock pulse generator WDT: Watchdog timer CPU: Central processing unit BSC: Bus state controller DMAC: Direct memory access controller DTC: Data transfer controller PFC: Pin function controller MTU2: Multi-function timer pulse unit 2 MTU2S: Multi-function timer pulse unit 2 (subset) POE: Port output enable SCI: Serial communication interface SCIF: Serial communication interface with FIFO SSU: Synchronous serial communication unit I 2C2: I2C bus interface 2 CMT: Compare match timer ADC: A/D converter INTC WDT CPG DTC H-UDI Internal bus controller RAMROM Peripheral bus (Pφ) I bus (Bφ) L bus (Iφ) MTU2 MTU2S POESCI SCIF SSU I 2C2 CMT ADCPower- down mode control External bus Peripheral bus controller Notes: 1. Only in F-ZTAT version 2. Only in F-ZTAT version supporting full functions of E10A 3. SH7084, SH7085, and SH7086 only Figure 1.1 Block Diagram

Page 8 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

1.3 Pin Assignments

(Top view) PE0/DREQ0/TIOC0A/TMS*3 PE1/TEND0/TIOC0B/TRST*3 PE2/DREQ1/TIOC0C/TDI*3 PE3/TEND1/TIOC0D/TDO*3 PE4/TIOC1A/RXD3/TCK*3 VSS PF0/AN0 PF1/AN1 PF2/AN2 PF3/AN3 PF4/AN4 PF5/AN5 AVSS PF6/AN6 PF7/AN7 AVref AVCC VSS VCC PE6/CS7/TIOC2A/SCK3 PE7/BS/TIOC2B/UBCTRG/RXD2/SSI PE8/TIOC3A/SCK2/SSCK PE10/TIOC3C/TXD2/SSO PE12/TIOC4A/TXD3/SCS PE13/TIOC4B/MRES/ASEBRKAK*3/ASEBRK*3 100 RES PA15/CK PLLV SS VCL VCC PB4/RASL/IRQ2/POE2 PB5/CASL/IRQ3/POE3 VSS (FWE*1) NMI MD0 EXTAL MD1 XTAL V SS PD0/D0 PD1/D1 PD2/D2/TIC5U PD3/D3/TIC5V PD4/D4/TIC5W PD5/D5/TIC5US V CC PD6/D6/TIC5VS PD7/D7/TIC5WS VSS PD8/D8/TIOC3AS/AUDATA0*4 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PD9/D9/TIOC3BS/AUDATA1*4 PD10/D10/TIOC3CS/AUDATA2*4 PD11/D11/TIOC3DS/AUDATA3*4 PD12/D12/TIOC4AS PD13/D13/TIOC4BS PD14/D14/TIOC4CS/AUDCK* PD15/D15/TIOC4DS/AUDSYNC*4 PB6/A18/BACK/IRQ4/RXD0 PB7/A19/BREQ/IRQ5/TXD0 PB8/A20/WAIT/IRQ6/SCK0 PA3/A24/RXD1 PA4/A23/TXD1 PA5/A22/DREQ1/IRQ1/SCK1 PA7/CS3/TCLKB PA8/RDWR/IRQ2/TCLKC PA9/CKE/IRQ3/TCLKD PA10/CS0/POE4 V SS VCC PA12/WRL/DQMLL/POE6 PA13/WRH/DQMLU/POE7 WDTOVF PA14/RD VCC (ASEMD0*2) PB9/A21/IRQ7/ADTRG/POE8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PE14/DACK0/TIOC4C PE15/CKE/DACK1/TIOC4D/IRQOUT VSS PC0/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 PC6/A6 PC7/A7 PC8/A8 PC9/A9 PC10/A10 PC11/A11 PC12/A12 PC13/A13 PC14/A14 V CC VCL PC15/A15 PB0/A16/TIC5WS PB1/A17/TIC5W VSS PB2/IRQ0/POE0 Notes: 1. This pin is fixed to VSS in the mask ROM and ROM-less versions and is used as the FWE input pin in the F-ZTAT version. 2. This pin is for the E10A emulator. It is fixed to V CC in the mask ROM and ROM-less versions and is used as the ASEMD0 input pin in the F-ZTAT version. 3. These pin functions are only available in the F-ZTAT version (i.e., they are not available in the mask ROM and ROM-less ve rsions). 4. These pin functions are only available in the F-ZTAT version supporting full functions of E10A (not available in normal F- ZTAT version). Figure 1.2 Pin Assignments of SH7083 (TQFP1414-100)

R01UH0198EJ0500 Rev. 5.00 Page 9 of 1560 Mar 18, 2011 SH7080 Group LQFP-112 (Top view) 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 51 61 71 81 92 02 12 22 32 42 52 62 72 8 100 101 102 103 104 105 106 107 108 109 110 111 112 PD12/D12/TIOC4AS Vss PD13/D13/TIOC4BS PD14/D14/TIOC4CS/AUDCK* PD15/D15/TIOC4DS/AUDSYNC*4 PA0/CS4/RXD0 PA1/CS5/TXD0 PA2/A25/DREQ0/IRQ0/SCK0 PA3/A24/RXD1 PA4/A23/TXD1 PA5/A22/DREQ1/IRQ1/SCK1 PA6/CS2/TCLKA PA7/CS3/TCLKB PA8/RDWR/IRQ2/TCLKC PA9/CKE/IRQ3/TCLKD PA10/CS0/POE4 PA11/CS1/POE5 Vss PA12/WRL/DQMLL/POE6 Vcc PA13/WRH/DQMLU/POE7 WDTOVF PA14/RD Vcc (ASEMD0* PB9/A21/IRQ7/ADTRG/POE8 PB8/A20/WAIT/IRQ6/SCK0 PB7/A19/BREQ/IRQ5/TXD0 PB6/A18/BACK/IRQ4/RXD0 PE14/AH/DACK0/TIOC4C PE15/CKE/DACK1/TIOC4D/IRQOUT Vss PC0/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 PC6/A6 PC7/A7 PC8/A8 PC9/A9 PC10/A10 PC11/A11 PC12/A12 PC13/A13 PC14/A14 PC15/A15 PB0/A16/TIC5WS Vcc PB1/A17/TIC5W Vc L PB2/IRQ0/POE0/SCL PB3/IRQ1/POE1/SDA PB4/RASL/IRQ2/POE2 Vss PB5/CASL/IRQ3/POE3 RES PA15/CK PLLVss Vc L Vcc PA17/WAIT PA16/AH/CKE Vss (FWE*1) NMI MD0 EXTAL MD1 XTAL Vss PD0/D0 PD1/D1 PD2/D2/TIC5U PD3/D3/TIC5V PD4/D4/TIC5W Vcc PD5/D5/TIC5US PD6/D6/TIC5VS PD7/D7/TIC5WS Vss PD8/D8/TIOC3AS/AUDATA0* PD9/D9/TIOC3BS/AUDATA1*4 PD10/D10/TIOC3CS/AUDATA2*4 PD11/D11/TIOC3DS/AUDATA3*4 PE0/DREQ0/TIOC0A/TMS*3 PE1/TEND0/TIOC0B/TRST*3 PE2/DREQ1/TIOC0C/TDI*3 PE3/TEND1/TIOC0D/TDO*3 PE4/TIOC1A/RXD3/TCK*3 Vss PF0/AN0 PF1/AN1 PF2/AN2 PF3/AN3 PF4/AN4 PF5/AN5 AVss PF6/AN6 PF7/AN7 AVcc Vss PE5/CS6/TIOC1B/TXD3/ASEBRKAK* 3/ASEBRK*3 Vcc PE6/CS7/TIOC2A/SCK3 PE7/BS/TIOC2B/UBCTRG/RXD2/SSI PE8/TIOC3A/SCK2/SSCK PE9/TIOC3B/SCK3/RTS3 PE10/TIOC3C/TXD2/SSO VcL PE11/TIOC3D/RXD3/CTS3 PE12/TIOC4A/TXD3/SCS PE13/TIOC4B/MRES Notes: 1. This pin is fixed to VSS in the mask ROM and ROM-less versions and is used as the FWE input pin in the F-ZTAT version. 2. This pin is for the E10A emulator. It is fixed to V CC in the mask ROM and ROM-less versions and is used as the ASEMD0 input pin in the F-ZTAT version. 3. These pin functions are only available in the F-ZTAT version (i.e., they are not available in the mask ROM and ROM-less ve rsions). 4. These pin functions are only available in the F-ZTAT version supporting full functions of E10A (not available in normal F- ZTAT version). Figure 1.3 Pin Assignments of SH7084

Page 10 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group LQFP-144 (Top view) PA23/WRHH/ICIOWR/AH/DQMUU/TIC5W PE14/WRHH/ICIOWR/AH/DQMUU/DACK0/TIOC4C PA22/WRHL/ICIORD/DQMUL/TIC5V PA21/CS5/CE1A/CASU/TIC5U PE15/CKE/DACK1/TIOC4D/IRQOUT Vss PC0/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 Vcc PC5/A5 Vss PC6/A6 PC7/A7 PC8/A8 PC9/A9 PC10/A10 PC11/A11 PC12/A12 PC13/A13 PC14/A14 PC15/A15 PB0/A16/TIC5WS Vcc PB1/A17/TIC5W Vss PA20/CS4/RASU PA19/BACK/TEND1 PB2/IRQ0/POE0/SCL PB3/IRQ1/POE1/SDA PA18/BREQ/TEND0 PB4/RASL/IRQ2/POE2 Vss PB5/CASL/IRQ3/POE3 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 RES PA15/CK PLLVss VcL Vcc PA25/CE2B/DACK3/POE8 PA24/CE2A/DREQ3 PA17/WAIT/DACK2 PA16/WRHH/ICIOWR/AH/DQMUU/CKE/DREQ2/AUDSYNC*4 Vss (FWE*1) NMI MD0 EXTAL MD1 XTAL Vss PD0/D0 PD1/D1 PD2/D2/TIC5U PD3/D3/TIC5V PD4/D4/TIC5W Vss PD5/D5/TIC5US Vcc PD6/D6/TIC5VS PD7/D7/TIC5WS PD8/D8/TIOC3AS PD9/D9/TIOC3BS PD10/D10/TIOC3CS Vss PD11/D11/TIOC3DS Vcc PD12/D12/TIOC4AS PD13/D13/TIOC4BS PD14/D14/TIOC4CS PD15/D15/TIOC4DS PE0/DREQ0/TIOC0A/AUDCK*4 PE1/TEND0/TIOC0B PE2/DREQ1/TIOC0C Vcc PE3/TEND1/TIOC0D/AUDATA3*4 PE4/IOIS16/TIOC1A/RXD3/AUDATA2*4 PE5/CS6/CE1B/TIOC1B/TXD3/AUDATA1*4 PE6/CS7/TIOC2A/SCK3/AUDATA0*4 Vss PF0/AN0 PF1/AN1 PF2/AN2 PF3/AN3 PF4/AN4 PF5/AN5 AVss PF6/AN6 PF7/AN7 AVref AVcc Vss PA0/CS4/RXD0 PA1/CS5/CE1A/TXD0 PA2/A25/DREQ0/IRQ0/SCK0 PA3/A24/RXD1 PA4/A23/TXD1 Vcc PA5/A22/DREQ1/IRQ1/SCK1 PE7/BS/TIOC2B/UBCTRG/RXD2/SSI PE8/TIOC3A/SCK2/SSCK/TMS* PE9/TIOC3B/SCK3/RTS3/TRST*3 PE10/TIOC3C/TXD2/SSO/TDI*3 VcL PE11/TIOC3D/RXD3/CTS3/TDO*3 PE12/TIOC4A/TXD3/SCS/TCK*3 PE13/TIOC4B/MRES/ASEBRKAK*3/ASEBRK*3 PD16/D16/IRQ0/POE4/AUDATA0*4 Vss PD17/D17/IRQ1/POE5/AUDATA1*4 PD18/D18/IRQ2/POE6/AUDATA2*4 PD19/D19/IRQ3/POE7/AUDATA3*4 PD20/D20/IRQ4/TIC5WS PD21/D21/IRQ5/TIC5VS PD22/D22/IRQ6/TIC5US/AUDCK* PD23/D23/IRQ7/AUDSYNC*4 Vcc PD24/D24/DREQ0/TIOC4DS VcL PD25/D25/DREQ1/TIOC4CS PD26/D26/DACK0/TIOC4BS PD27/D27/DACK1/TIOC4AS PD28/D28/CS2/TIOC3DS PD29/D29/CS3/TIOC3BS Vss PA6/CS2/TCLKA PA7/CS3/TCLKB PA8/RDWR/IRQ2/TCLKC PA9/FRAME/CKE/IRQ3/TCLKD PA10/CS0/POE4 PA11/CS1/POE5 PA12/WRL/DQMLL/POE6 PA13/WRH/WE/DQMLU/POE7 PD30/D30/TIOC3CS/IRQOUT PD31/D31/TIOC3AS/ADTRG WDTOVF PA14/RD Vcc (ASEMD0*2) PB9/A21/IRQ7/ADTRG/POE8 Vcc PB8/A20/WAIT/IRQ6/SCK0 PB7/A19/BREQ/IRQ5/TXD0 PB6/A18/BACK/IRQ4/RXD0 1 2 3 4 5 6 7 8 9 1 0 1 11 21 31 41 51 61 71 81 92 02 12 22 32 42 52 62 7 2 82 93 03 13 23 33 43 53 6 108 107106 105 104 103102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 Notes: 1. This pin is fixed to VSS in the mask ROM and ROM-less versions and is used as the FWE input pin in the F-ZTAT version. 2. This pin is for the E10A emulator. It is fixed to V CC in the mask ROM and ROM-less versions and is used as the ASEMD0 input pin in the F-ZTAT version. 3. These pin functions are only available in the F-ZTAT version (i.e., they are not available in the mask ROM and ROM-less ve rsions). 4. These pin functions are only available in the F-ZTAT version supporting full functions of E10A (not available in normal F- ZTAT version). Figure 1.4 Pin Assignments of SH7085

R01UH0198EJ0500 Rev. 5.00 Page 11 of 1560 Mar 18, 2011 SH7080 Group LQFP-176 (Top view) PE12/TIOC4A/TXD3/SCS/TCK*3 PE13/TIOC4B/MRES/ASEBRKAK*3/ASEBRK*3 PA23/WRHH/ICIOWR/AH/DQMUU/TIC5W PE14/WRHH/ICIOWR/AH/DQMUU/DACK0/TIOC4C PA22/WRHL/ICIORD/DQMUL/TIC5V PA21/CS5/CE1A/CASU/TIC5U PE15/CKE/DACK1/TIOC4D/IRQOUT Vss PE16/CS8/TIOC3BS PE17/TIOC3DS Vcc PE18/TIOC4AS PE19/TIOC4BS PE20/TIOC4CS PE21/TIOC4DS PC0/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 Vcc PC5/A5 Vss PC6/A6 PC7/A7 PC8/A8 PC9/A9 PC10/A10 PC11/A11 PC12/A12 PC13/A13 PC14/A14 PC15/A15 PB0/A16/TIC5WS Vcc PB1/A17/TIC5W Vc L PA20/CS4/RASU PA19/BACK/TEND1 PB2/IRQ0/POE0/SCL PB3/IRQ1/POE1/SDA PA18/BREQ/TEND0 PB4/RASL/IRQ2/POE2 Vss 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 RES PA15/CK PLLVss Vc L Vcc PA25/CE2B/DACK3/POE8 PA24/CE2A/DREQ3 PA17/WAIT/DACK2 PA16/WRHH/ICIOWR/AH/DQMUU/CKE/DREQ2/AUDSYNC*4 Vss (FWE*1) NMI MD0 EXTAL MD1 XTAL Vss PD0/D0 PD1/D1 PD2/D2/TIC5U PD3/D3/TIC5V PD4/D4/TIC5W PD5/D5/TIC5US PD6/D6/TIC5VS Vcc PD7/D7/TIC5WS PD8/D8/TIOC3AS PD9/D9/TIOC3BS PD10/D10/TIOC3CS Vss PD11/D11/TIOC3DS Vcc PD12/D12/TIOC4AS PD13/D13/TIOC4BS PD14/D14/TIOC4CS PD15/D15/TIOC4DS PD16/D16/IRQ0/POE4/AUDATA0* Vss PD17/D17/IRQ1/POE5/AUDATA1*4 Vcc PD18/D18/IRQ2/POE6/AUDATA2* PD19/D19/IRQ3/POE7/AUDATA3*4 PD20/D20/IRQ4/TIC5WS PD21/D21/IRQ5/TIC5VS PD22/D22/IRQ6/TIC5US/AUDCK* PE0/DREQ0/TIOC0A/AUDCK*4 PE1/TEND0/TIOC0B PE2/DREQ1/TIOC0C Vcc PE3/TEND1/TIOC0D/AUDATA3*4 PE4/IOIS16/TIOC1A/RXD3/AUDATA2*4 PE5/CS6/CE1B/TIOC1B/TXD3/AUDATA1*4 PE6/CS7/TIOC2A/SCK3/AUDATA0*4 Vss AVss PF0/AN0 PF1/AN1 PF8/AN8 PF9/AN9 PF2/AN2 PF3/AN3 PF10/AN10 PF11/AN11 AVcc PF4/AN4 PF5/AN5 PF12/AN12 PF13/AN13 AVss PF6/AN6 PF7/AN7 PF14/AN14 PF15/AN15 AVref AVcc Vss PA0/CS4/RXD0 PA1/CS5/CE1A/TXD0 PA2/A25/DREQ0/IRQ0/SCK0 PA3/A24/RXD1 Vcc PA4/A23/TXD1 PA5/A22/DREQ1/IRQ1/SCK1 PE7/BS/TIOC2B/UBCTRG/RXD2/SSI PE8/TIOC3A/SCK2/SSCK/TMS* VcL PE9/TIOC3B/SCK3/RTS3/TRST*3 PE10/TIOC3C/TXD2/SSO/TDI*3 PE11/TIOC3D/RXD3/CTS3/TDO*3 PD23/D23/IRQ7/AUDSYNC*4 PD24/D24/DREQ0/TIOC4DS Vss PD25/D25/DREQ1/TIOC4CS PD26/D26/DACK0/TIOC4BS PD27/D27/DACK1/TIOC4AS PD28/D28/CS2/TIOC3DS PD29/D29/CS3/TIOC3BS PA6/CS2/TCLKA PA7/CS3/TCLKB PA8/RDWR/IRQ2/TCLKC PA9/FRAME/CKE/IRQ3/TCLKD PA10/CS0/POE4 PA11/CS1/POE5 Vcc PA12/WRL/DQMLL/POE6 PA13/WRH/DQMLU/WE/POE7 Vc L PD30/D30/TIOC3CS/IRQOUT PD31/D31/TIOC3AS/ADTRG PA29/A29/IRQ3 PA28/A28/IRQ2 Vcc PA27/A27/IRQ1 Vss PA26/A26/IRQ0 PC25/A25 PC24/A24 PC23/A23 PC22/A22 PC21/A21 Vss PC20/A20 PC19/A19 PC18/A18 WDTOVF PA14/RD Vcc (ASEMD0* PB9/A21/IRQ7/ADTRG/POE8 PB8/A20/WAIT/IRQ6/SCK0 Vcc PB7/A19/BREQ/IRQ5/TXD0 PB6/A18/BACK/IRQ4/RXD0 PB5/CASL/IRQ3/POE3 12 3456 789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 108109110111112113114115116117118119120121122123124125126127128129130131132 107 106 105 104 103 102 101 10099 98 97 96 95 94 93 92 91 90 89 Notes: 1. This pin is fixed to VSS in the mask ROM and ROM-less versions and is used as the FWE input pin in the F-ZTAT version. 2. This pin is for the E10A emulator. It is fixed to V CC in the mask ROM and ROM-less versions and is used as the ASEMD0 input pin in the F-ZTAT version. 3. These pin functions are only available in the F-ZTAT version (i.e., they are not available in the mask ROM and ROM-less ve rsions). 4. These pin functions are only available in the F-ZTAT version supporting full functions of E10A (not available in normal F- ZTAT version). Figure 1.5 Pin Assignments of SH7086

Page 12 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group NC PE1 PE4 PF1 PF4 PF6 NC Vcc PE8 PE13 NC PA15 PE0 PE3 PF0 PF5 PF7 AVcc PE7 PE12 PE14 PE15 Vcc PLLVss RES Vss PF3 AVss Vss PE10 NC PC0 PC1 Vss (FWE* PB4 VCL PE2 PF2 AVref PE6 Vss NC PC2 PC3 EXTAL MD0 NMI PB5 PC4 PC5 PC7 PC6 XTAL MD1 NC NC PC11 PC8 PC10 PC9 PD0 Vss PD1 PD2 V CL PC14 PC13 PC12 PD3 PD4 PD5 PD7 PD14 PB8 PA10 PA14 PB1 PC15 Vcc Vcc PD6 NC PD11 PB6 PA5 PA9 PA12 PB2 NC PB0 Vss PD8 PD10 PD13 NC PA3 PA7 Vcc WDTOVF PB9 Vss NC PD9 PD12 PD15 PB7 PA4 PA8 Vss PA13 Vss (ASEMD0*2) NC ABCDEFGHJKL P-LFBGA-112*3 (Top view) INDEX Notes: 1. This pin is fixed to Vss in the mask ROM version and is used as the FWE input pin in the F-ZTAT version. 2. This pin is for the E10A emulator. It is fixed to V CC in the mask ROM version and is used as the ASEMD0 input pin in the F-ZTAT version. 3. The multiplexing of pin functions is the same as for the TQFP1414-100. For details on the pin-multiplexed functions, see the manual for the TQFP1414-100. Figure 1.6 Pin Assignments of SH7083 (P-LFBGA-112)

R01UH0198EJ0500 Rev. 5.00 Page 13 of 1560 Mar 18, 2011 SH7080 Group

1.4 Pin Functions

Table 1.2 summarizes the pin functions. Table 1.2 Pin Functions Classification Symbol I/O Name Function Vcc I Power supply Power supply pins. Connect all Vcc pins to the system. There will be no operation if any pins are open. Vss I Ground Ground pin. Connect all Vss pins to the system power supply (0V). There will be no operation if any pins are open. Power supply VCL O Power supply for internal power- down External capacitance pins for internal power-down power supply. Connect these pins to Vss via a 0.47 μF capacitor (placed close to the pins). PLLVss I PLL ground Ground pin for the on-chip PLL oscillator EXTAL I External clock Connected to a crystal resonator. An external clock signal may also be input to the EXTAL pin. Clock XTAL O Crystal Connected to a crystal resonator. CK O System clock Supplies the system clock to external devices. Operating mode control MD1, MD0 I Mode set Sets the operating mode. Do not change values on these pins during operation. FWE I Flash memory write enable Pin for flash memory. Flash memory can be protected against programming or erasure through this pin.

Page 14 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Classification Symbol I/O Name Function RES I Power-on reset When low, this LSI enters the power- on reset state. MRES I Manual reset When low, this LSI enters the manual reset state. WDTOVF O Watchdog timer overflow Output signal for the watchdog timer overflow. If this pin need to be pulled down, use the resistor larger than 1 MΩ to pull this pin down. BREQ I Bus-mastership request Low when an external device requests the release of the bus mastership. System control BACK O Bus-mastership request acknowledge Indicates that the bus mastership has been released to an external device. Reception of the BACK signal informs the device which has output the BREQ signal that it has acquired the bus. NMI I Non-maskable interrupt Non-maskable interrupt request pin. Fix to high or low level when not in use. Interrupts IRQ7 to IRQ0 I Interrupt requests 7 to 0 Maskable interrupt request pin. Selectable as level input or edge input. The rising edge, falling edge, and both edges are selectable as edges. IRQOUT O Interrupt request output Shows that an interrupt cause has occurred. The interrupt cause can be recognized even in the bus release state. Address bus A29 to A0 O A ddress bus Outputs addresses. A24 to A0 are available in the SH7083. A25 to A0 are available in the SH7084/SH7085. Data bus D31 to D0 I/O Data bus 32-bit bidirectional bus. D15 to D0 are available in the SH7083/SH7084.

R01UH0198EJ0500 Rev. 5.00 Page 15 of 1560 Mar 18, 2011 SH7080 Group Classification Symbol I/O Name Function CS8 to CS0 O Chip select 8 to 0 Chip-select signal for external memory or devices. CS7, CS3, and CS0 are available in the SH7083. CS7 to CS0 are available in the SH7084/SH7085. Bus control RD O Read Indicates reading of data from external devices. RDWR O Read/write Read/write signal BS O Bus start Bus-cycle start AH O Address hold Address hold timing signal for the device that uses the address/data- multiplexed bus. Available only in the SH7084/SH7085/SH7086. FRAME O FRAME signal In burst MPX-I/O interface mode, negated before the last bus cycle to indicate that the next bus cycle is the last access. Available only in the SH7085/SH7086. WRHH O Write to HH byte Indicates a write access to bits 31 to 24 of the external data. Available only in the SH7085/SH7086. WRHL O Write to HL byte Indicates a write access to bits 23 to 16 of the external data. Available only in the SH7085/SH7086. WRH O Write to upper byte Indicates a write access to bits 15 to 8 of the external data. WRL O Write to lower byte Indicates a write access to bits 7 to 0 of the external data. WAIT I Wait Input signal for inserting a wait cycle into the bus cycles during access to the external space.

Page 16 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Classification Symbol I/O Name Function Bus control RASL O RAS Connected to the RAS pin of the SDRAM. RASU O RAS Connected to the RAS pin of the SDRAM. Available only in the SH7085/SH7086. CASL O CAS Connected to the CAS pin of the SDRAM. CASU O CAS Connected to the CAS pin of the SDRAM. Available only in the SH7085/SH7086. CKE O Clock enable Connected to the CKE pin of the SDRAM. DQMUU O HH byte selection Selects bits 31 to 24 of the SDRAM data bus. Available only in the SH7085/SH7086. DQMUL O HL byte selection Selects bits 23 to 16 of the SDRAM data bus. Available only in the SH7085/SH7086. DQMLU O Upper byte selection Selects bits 15 to 8 of the SDRAM data bus. DQMLL O Lower byte selection Selects bits 7 to 0 of the SDRAM data bus. CE1A O Lower byte selection for PCMCIA card Chip enable for PCMCIA connected to area 5 Available only in the SH7085/SH7086. CE1B O Lower byte selection for PCMCIA card Chip enable for PCMCIA connected to area 6 Available only in the SH7085/SH7086.

R01UH0198EJ0500 Rev. 5.00 Page 17 of 1560 Mar 18, 2011 SH7080 Group Classification Symbol I/O Name Function Bus control CE2A O Upper byte selection for PCMCIA card Chip enable for PCMCIA connected to area 5 Available only in the SH7085/SH7086. CE2B O Upper byte selection for PCMCIA card Chip enable for PCMCIA connected to area 6 Available only in the SH7085/SH7086. ICIOWR O Write strobe for PCMCIA I/O Connected to the PCMCIA I/O write strobe signal Available only in the SH7085/SH7086. ICIORD O Read strobe for PCMCIA I/O Connected to the PCMCIA I/O read strobe signal Available only in the SH7085/SH7086. WE O Write strobe for PCMCIA memory Connected to the PCMCIA memory write strobe signal Available only in the SH7085/SH7086. IOIS16 I PCMCIA dynamic bus sizing Indicates 16-bit I/O for PCMCIA in little endian mode. This LSI does not support little endian and this pin must be held low. Available only in the SH7085/SH7086. Direct memory access controller (DMAC) DREQ3 to DREQ0 I DMA-transfer request Input pins to receive external requests for DMA transfer. Only DREQ1 and DREQ0 are available in the SH7083/SH7084. DACK3 to DACK0 O DMA-transfer strobe Strobe signal output pins for the external device that has requested DMA transfer. Only DACK1 and DACK0 are available in the SH7083/SH7084. TEND1, TEND0 O DMA-transfer end Output pins for DMA transfer end signals

Page 18 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Classification Symbol I/O Name Function TCLKA, TCLKB, TCLKC, TCLKD I MTU2 timer clock input External clock input pins for the timer. Only TCLKB, TCLKC, and TCLKD are available in the SH7083. TIOC0A, TIOC0B, TIOC0C, TIOC0D I/O MTU2 input capture/output compare (channel 0) The TGRA_0 to TGRD_0 input capture input/output compare output/PWM output pins. TIOC1A, TIOC1B I/O MTU2 input capture/output compare (channel 1) The TGRA_1 to TGRB_1 input capture input/output compare output/PWM output pins. Only TIOC1A is available in the SH7083. TIOC2A, TIOC2B I/O MTU2 input capture/output compare (channel 2) The TGRA_2 to TGRB_2 input capture input/output compare output/PWM output pins. TIOC3A, TIOC3B, TIOC3C, TIOC3D I/O MTU2 input capture/output compare (channel 3) The TGRA_3 to TGRD_3 input capture input/output compare output/PWM output pins. Only TIOC3A and TIOC3C are available in the SH7083. TIOC4A, TIOC4B, TIOC4C, TIOC4D I/O MTU2 input capture/output compare (channel 4) The TGRA_4 to TGRD_4 input capture input/output compare output/PWM output pins. Multi function timer- pulse unit 2 (MTU2) TIC5U, TIC5V, TIC5W I MTU2 input capture (channel 5) The TGRU_5, TGRV_5, and TGRW_5 input capture input pins. Multi function timer- pulse unit 2S (MTU2S) TIOC3AS, TIOC3BS, TIOC3CS, TIOC3DS I/O MTU2S input capture/output compare (channel 3) The TGRA_3S to TGRD_3S input capture input/output compare output/PWM output pins. TIOC4AS, TIOC4BS, TIOC4CS, TIOC4DS I/O MTU2S input capture/output compare (channel 4) The TGRA_4S to TGRD_4S input capture input/output compare output/PWM output pins.

R01UH0198EJ0500 Rev. 5.00 Page 19 of 1560 Mar 18, 2011 SH7080 Group Classification Symbol I/O Name Function Multi function timer- pulse unit 2S (MTU2S) TIC5US, TIC5VS, TIC5WS I MTU2S input capture (channel 5) The TGRU_5S, TGRV_5S, and TGRW_5S input capture input pins. Port output enable (POE) POE8 to POE0 I Port output enable Request signal input to place the MTU2 and MTU2S waveform output pins in high impedance state. POE8 to POE6, POE4 to POE2, and POE0 are available in the SH7083. TXD2 to TXD0 O Transmit data Transmit data output pins RXD2 to RXD0 I Receive data Receive data input pins Serial communication interface (SCI) SCK2 to SCK0 I/O Serial clock Clock input/output pins TXD3 O Transmit data Transmit data output pin RXD3 I Receive data Receive data input pin SCK3 I/O Serial clock Clock input/output pin RTS3 O Request to send Modem control pin. This pin is not available in the SH7083. Serial communication interface with FIFO (SCIF) CTS3 I Clear to send Modem control pin. This pin is not available in the SH7083. SSO I/O Data Data input/output pin. SSI I/O Data Data input/output pin. SSCK I/O Clock Clock input/output pin. Synchronous serial communication unit (SSU) SCS I/O Chip select Chip select input/output pin. I C bus interface 2 C2) SCL I/O I C clock input/output Clock input/output pin for I C bus. Available only in the SH7084/SH7085/SH7086. SDA I/O I C data input/output Data input/output pin for I C bus. Available only in the SH7084/SH7085/SH7086.

Page 20 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Classification Symbol I/O Name Function AN15 to AN0 I Analog input pins Analog input pins. AN7 to AN0 are available in the SH7083/SH7084/SH7085. ADTRG I A/D conversion trigger input External trigger input pin for starting A/D conversion. AVref I Analog reference power supply Reference voltage pin for the A/D converter. Available only in the SH7083/SH7085/SH7086. (In the SH7084, this pin is connected to AVcc inside this LSI.) AVcc I Analog power supply Power supply pin for the A/D converter. Connect all AVcc pins to the system power supply (Vcc) when the A/D converter is not used. The A/D converter does not work if any pin is open. A/D converter (ADC) AVss I Analog ground Ground pin for the A/D converter. Connect it to the system ground (0 V). Connect all AVss pins to the system ground (0 V) correctly. The A/D converter does not work if any pin is open. I/O ports PA29 to PA0 I/O General port 30-bit general input/output port pins. PA15 to PA12, PA10 to PA7, and PA5 to PA3 are available in the SH7083. PA17 to PA0 are available in the SH7084. PA25 to PA0 are available in the SH7085. PB9 to PB0 I/O General port 10-bit general input/output port pins. PB9 to PB4 and PB2 to PB0 are available in the SH7083. PC25 to PC18, PC15 to PC0 I/O General port 24-bit general input/output port pins. PC15 to PC0 are available in the SH7083/SH7084/SH7085.

R01UH0198EJ0500 Rev. 5.00 Page 21 of 1560 Mar 18, 2011 SH7080 Group Classification Symbol I/O Name Function PD31 to PD0 I/O General port 32-bit general input/output port pins. PD15 to PD0 are available in the SH7083/SH7084. PE21 to PE0 I/O General port 22-bit general input/output port pins. PE15 to PE12, PE10, PE8 to PE6, and PE4 to PE0 are available in the SH7083. PE15 to PE0 are available in the SH7084/SH7085. I/O ports PF15 to PF0 I General port 16-bit general input port pins. PF7 to PF0 are available in the SH7083/SH7084/SH7085. User break controller (UBC) UBCTRG O User break trigger output Trigger output pin for UBC condition match. TCK I Test clock Test-clock input pin. TMS I Test mode select Inputs the test-mode select signal. TDI I Test data input Serial input pin for instructions and data. TDO O Test data output Serial output pin for instructions and data. User debugging interface (H-UDI) (only in the F-ZTAT version) TRST I Test reset Initialization-signal input pin. AUDATA3 to AUDATA0 O AUD data Branch destination address output pins. AUDCK O AUD clock Sync-clock output pin. Advanced user debugger (AUD) (only in F-ZTAT version supporting full functions of E10A) AUDSYNC O AUD sync signal Data start-position acknowledge- signal output pin.

Page 22 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Classification Symbol I/O Name Function E10A interface (only in the F-ZTAT version) ASEMD0 I ASE mode Sets the ASE mode. When a low level is input, this LSI enters ASE mode. When a high level is input, this LSI enters the normal mode. The emulator functions are available in ASE mode. When no signal is input, this pin is pulled up inside this LSI. ASEBRK I Break request E10A emulator break input pin. ASEBRKAK O Break mode acknowledge Indicates that the E10A emulator has entered its break mode. Note: The WDTOVF pin should not be pulled down. When absolutely necessary, pull it down through a resistor of 1 MΩ or larger.

R01UH0198EJ0500 Rev. 5.00 Page 23 of 1560 Mar 18, 2011 SH7080 Group Section 2 CPU

2.1 Features

• General registers: 32-bit register × 16
• Basic instructions: 62
• Addressing modes: 11 Register direct (Rn) Register indirect (@Rn) Post-increment register indirect (@Rn+) Pre-decrement register indirect (@-Rn) Register indirect with displacement (@disp:4, Rn) Index register indirect (@R0, Rn) GBR indirect with displacement (@disp:8, GBR) Index GBR indirect (@R0, GBR) PC relative with displacement (@disp:8, PC) PC relative (disp:8/disp:12/Rn) Immediate (#imm:8)

Page 24 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

2.2 Register Configuration

There are three types of registers: general registers (32-bit × 16), control registers (32-bit × 3), and system registers (32-bit × 4). 31 0 R0*1 R10 R11 R12 R13 R14 R15, SP (hardware stack pointer)0* 31 9 8 7 6 5 4 3 2 1 0 M GBR VBR QI 3I 2I 1 I 0 S T 31 0 MACH 31 0 PR 31 0 PC MACL Notes: 1. R0 can be used as an index register in index register indirect or index GBR indirect addressing mode. For some instructions, only R0 is used as the source or destination register. 2. R15 is used as a hardware stack pointer during exception handling. General register (Rn) Status register (SR) Global base register (GBR) Vector base register (VBR) Multiply and accumulate register (MAC) Procedure register (PR) Program counter (PC) Figure 2.1 CPU Internal Register Configuration

R01UH0198EJ0500 Rev. 5.00 Page 25 of 1560 Mar 18, 2011 SH7080 Group

2.2.1 General Registers (Rn)

There are sixteen 32-bit general registers (Rn), designated R0 to R15. The general registers are used for data processing and address calculation. R0 is also used as an index register. With a number of instructions, R0 is the only register that can be used. R15 is used as a hardware stack pointer (SP). In exception handling, R15 is used for accessing the stack to save or restore the status register (SR) and program counter (PC) values.

2.2.2 Control Registers

There are three 32-bit control registers, designated status register (SR), global base register (GBR), and vector base register (VBR). SR indicates a processing state. GBR is used as a base address in GBR indirect addressing mode for data transfer of on-chip peripheral module registers. VBR is used as a base address of the exception handling (including interrupts) vector table.

• Status register (SR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 9876543210Bit: Initial value: R/W: 0000000000000000 RRRRRRRRRRRRRRRR 000000- -111100- - RRRRRR R / W R / W R / W R / W R / W R / W RR R / W R / W Bit Bit name Default Read/ Write

Description

31 to 10 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. 9 M Undefined R/W Used by the DIV0U, DIV0S, and DIV1 instructions. 8 Q Undefined R/W Used by the DIV0U, DIV0S, and DIV1 instructions. 7 to 4 I[3:0] 1111 R/W Interrupt Mask 3, 2 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Page 26 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit name Default Read/ Write

1 S Undefined R/W S Bit

Used by the multiply and accumulate instruction.

0 T Undefined R/W T Bit

Indicates true (1) or false (0) in the following instructions: MOVT, CMP/cond, TAS, TST, BT (BT/S), BF (BF/S), SETT, CLRT Indicates carry, borrow, overflow, or underflow in the following instructions: ADDV, ADDC, SUBV, SUBC, NEGC, DIV0U, DIV0S, DIV1, SHAR, SHAL, SHLR, SHLL, ROTR, ROTL, ROTCR, ROTCL

• Global-base register (GBR) This register indicates a base address in GBR indirect addressing mode. The GBR indirect addressing mode is used for data transfer of the on-chip peripheral module registers and logic operations.
• Vector-base register (VBR) This register indicates the base address of the exception handling vector table.

R01UH0198EJ0500 Rev. 5.00 Page 27 of 1560 Mar 18, 2011 SH7080 Group

2.2.3 System Registers

There are four 32-bit system registers, designated two multiply and accumulate registers (MACH and MACL), a procedure register (PR), and program counter (PC).

• Multiply and accumulate registers (MACH and MACL) This register stores the results of multiplication and multiply-and-accumulate operation.
• Procedure register (PR) This register stores the return-destination address from subroutine procedures.
• Program counter (PC) The PC indicates the point which is four bytes (two instructions) after the current execution instruction.

2.2.4 Initial Values of Registers

Table 2.1 lists the initial values of registers after a reset. Table 2.1 Initial Values of Registers Type of register Register Default General register R0 to R14 Undefined R15 (SP) SP value set in the exception handling vector table Control register SR I3 to I0: 1111 (H'F) Reserved bits: 0 Other bits: Undefined GBR Undefined VBR H'00000000 System register MACH, MACL, PR Undefined PC PC value set in the exception handling vector table

Page 28 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

2.3 Data Formats

2.3.1 Register Data Format

The size of register operands is always longwords (32 bits). When loading byte (8 bits) or word (16 bits) data in memory into a register, the data is sign-extended to longword and stored in the register. Longword 31 0 Figure 2.2 Register Data Format

2.3.2 Memory Data Formats

Memory data formats are classified into bytes, words, and longwords. Byte data can be accessed from any address. Locate, however, word data at an address 2n, longword data at 4n. Otherwise, an address error will occur if an attempt is made to access word data starting from an address other than 2n or longword data starting from an address other than 4n. In such cases, the data accessed cannot be guaranteed. The hardware stack area, pointed by the hardware stack pointer (SP, R15), uses only longword data starting from address 4n because this area holds the program counter and status register. Byte Byte Byte Byte Word Word Longword 31 23 15 7 Address m + 1 Address 2n Address 4n Address m Address m + 3 Address m + 2 Figure 2.3 Memory Data Format

R01UH0198EJ0500 Rev. 5.00 Page 29 of 1560 Mar 18, 2011 SH7080 Group

2.3.3 Immediate Data Formats

Immediate data of eight bits is placed in the instruction code. For the MOV, ADD, and CMP/EQ instructions, the immediate data is sign-extended to longword and then calculated. For the TST, AND, OR, and XOR instructions, the immediate data is zero- extended to longword and then calculated. Thus, if the immediate data is used for the AND instruction, the upper 24 bits in the destination register are always cleared. The immediate data of word or longword is not placed in the instruction code. It is placed in a table in memory. The table in memory is accessed by the MOV immediate data instruction in PC relative addressing mode with displacement.

2.4 Features of Instructions

2.4.1 RISC Type

The instructions are RISC-type instructions with the following features: Fixed 16-Bit Length: All instructions have a fixed length of 16 bits. This improves program code efficiency. One Instruction per Cycle: Since pipelining is used, basic instructions can be executed in one cycle. Data Size: The basic data size for operations is longword. Byte, word, or longword can be selected as the memory access size. Byte or word data in memory is sign-extended to longword and then calculated. Immediate data is sign-extended to longword for arithmetic operations or zero-extended to longword size for logical operations. Table 2.2 Word Data Sign Extension CPU in this LSI Description Example of Other CPUs MOV.W @(disp,PC),R1 ADD R1,R0 .DATA.W H'1234 Sign-extended to 32 bits, R1 becomes H'00001234, and is then operated on by the ADD instruction. ADD.W #H'1234,R0 Note: Immediate data is accessed by @(disp,PC).

Page 30 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Load/Store Architecture: Basic operations are executed between registers. In operations involving memory, data is first loaded into a register (load/store architecture). However, bit manipulation instructions such as AND are executed directly in memory. Delayed Branching: Unconditional branch instructions means the delayed branch instructions. With a delayed branch instruction, the branch is made after execution of the instruction immediately following the delayed branch instruction. This minimizes disruption of the pipeline when a branch is made. The conditional branch instructions have two types of instructions: conditional branch instructions and delayed branch instructions. Table 2.3 Delayed Branch Instructions CPU in this LSI Description Example of Other CPUs BRA TRGET ADD R1,R0 ADD is executed before branch to TRGET. ADD.W R1,R0 BRA TRGET Multiply/Multiply-and-Accumulate Operations: A 16 × 16 → 32 multiply operation is executed in one to two cycles, and a 16 × 16 + 64 → 64 multiply-and-accumulate operation in two to three cycles. A 32 × 32 → 64 multiply operation and a 32 × 32 + 64 → 64 multiply-and- accumulate operation are each executed in two to four cycles. T Bit: The result of a comparison is indicated by the T bit in SR, and a conditional branch is performed according to whether the result is True or False. Processing speed has been improved by keeping the number of instructions that modify the T bit to a minimum. Table 2.4 T Bit CPU in this LSI Description Example of Other CPUs CMP/GE R1,R0 When R0 ≥ R1, the T bit is set. CMP.W R1,R0 BT TRGET0 When R0 ≥ R1, a branch is made to TRGET0. BGE TRGET0 BF TRGET1 When R0 < R1, a branch is made to TRGET1. BLT TRGET1 ADD # −1,R0 The T bit is not changed by ADD. SUB.W #1,R0 CMP/EQ #0,R0 When R0 = 0, the T bit is set. BEQ TRGET BT TRGET A branch is made when R0 = 0. Immediate Data: 8-bit immediate data is placed in the instruction code. Word and longword immediate data is not placed in the instruction code. It is placed in a table in memory. The table in memory is accessed with the MOV immediate data instruction using PC relative addressing mode with displacement.

R01UH0198EJ0500 Rev. 5.00 Page 31 of 1560 Mar 18, 2011 SH7080 Group Table 2.5 Access to Immediate Data Type This LSI's CPU Example of Other CPU 8-bit immediate MOV #H'12,R0 MOV.B #H'12,R0 16-bit immediate MOV.W @(disp,PC),R0 .DATA.W H'1234 MOV.W #H'1234,R0 32-bit immediate MOV.L @(disp,PC),R0 .DATA.L H'12345678 MOV.L #H'12345678,R0 Note: Immediate data is accessed by @(disp,PC). Absolute Addresses: When data is accessed by absolute address, place the absolute address value in a table in memory beforehand. The absolute address value is transferred to a register using the method whereby immediate data is loaded when an instruction is executed, and the data is accessed using the register indirect addressing mode. Table 2.6 Access to Absolute Address Type CPU in this LSI Example of Other CPUs Absolute address MOV.L @(disp,PC),R1 MOV.B @R1,R0 .DATA.L H'12345678 MOV.B @H'12345678,R0 Note: Immediate data is referenced by @(disp,PC). 16-Bit/32-Bit Displacement: When data is accessed using the 16- or 32-bit displacement addressing mode, the displacement value is placed in a table in memory beforehand. Using the method whereby immediate data is loaded when an instruction is executed, this value is transferred to a register and the data is accessed using index register indirect addressing mode.

Page 32 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 2.7 Access with Displacement Type CPU in this LSI Example of Other CPUs 16-bit displacement MOV.W @(disp,PC),R0 MOV.W @(R0,R1),R2 .DATA.W H'1234 MOV.W @(H'1234,R1),R2 Note: Immediate data is referenced by @(disp,PC).

2.4.2 Addressing Modes

Table 2.8 lists addressing modes and effective address calculation methods. Table 2.8 Addressing Modes and Effective Addresses Addressing Mode Instruction Format Effective Address Calculation Method Calculation Formula Register direct Rn Effective address is register Rn. (Operand is register Rn contents.) Register indirect @Rn Effective address is register Rn contents. Rn Rn Rn Register indirect with post-increment @Rn+ Effective address is register Rn contents. A constant is added to Rn after instruction execution: 1 for a byte operand, 2 for a word operand, 4 for a longword operand. Rn Rn 1/2/4 Rn + 1/2/4 Rn After instruction execution Byte: Rn + 1 → Rn Word: Rn + 2 → Rn Longword: Rn + 4 → Rn Register indirect with pre-decrement @–Rn Effective address is register Rn contents, decremented by a constant beforehand: 1 for a byte operand, 2 for a word operand, 4 for a longword operand. Rn Rn - 1/2/4 1/2/4 Rn - 1/2/4 Byte: Rn – 1 → Rn Word: Rn – 2 → Rn Longword: Rn – 4 → Rn (Instruction executed with Rn after calculation)

R01UH0198EJ0500 Rev. 5.00 Page 33 of 1560 Mar 18, 2011 SH7080 Group Addressing Mode Instruction Format Effective Address Calculation Method Calculation Formula Register indirect with displacement @(disp:4, Rn) Effective address is register Rn contents with 4-bit displacement disp added. After disp is zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size. 1/2/4 disp (zero-extended) Rn + disp × 1/2/4+ Rn Byte: Rn + disp Word: Rn + disp × 2 Longword: Rn + disp × 4 Index register indirect @(R0, Rn) Effective address is sum of register Rn and R0 contents. Rn Rn + R0 Rn + R0 GBR indirect with displacement @(disp:8, GBR) Effective address is register GBR contents with 8-bit displacement disp added. After disp is zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size. GBR 1/2/4 disp (zero-extended) GBR + disp × 1/2/4 Byte: GBR + disp Word: GBR + disp × Longword: GBR + disp × 4 Index GBR indirect @(R0, GBR) Effective address is sum of register GBR and R0 contents. GBR GBR + R0 GBR + R0

Page 34 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Addressing Mode Instruction Format Effective Address Calculation Method Calculation Formula PC relative with displacement @(disp:8, PC) Effective address is PC with 8-bit displacement disp added. After disp is zero-extended, it is multiplied by 2 (word) or 4 (longword), according to the operand size. With a longword operand, the lower 2 bits of PC are masked. PC PC + disp × 2 or PC& H'FFFFFFFC + disp × 4 H'FFFFFFFC disp (zero-extended) *With longword operand Word: PC + disp × 2 Longword: PC&H'FFFFFFFC + disp × 4 PC relative disp:8 Effective address is PC with 8-bit displacement disp added after being sign-extended and multiplied by 2. PC disp (sign-extended) PC + disp × 2 PC + disp × 2 disp:12 Effective address is PC with 12-bit displacement disp added after being sign-extended and multiplied by 2. PC disp (sign-extended) PC + disp × 2 PC + disp × 2

R01UH0198EJ0500 Rev. 5.00 Page 35 of 1560 Mar 18, 2011 SH7080 Group Addressing Mode Instruction Format Effective Address Calculation Method Calculation Formula PC relative Rn Effective address is sum of PC and Rn. PC PC + Rn Rn PC + Rn Immediate #imm:8 8-bit immediate data imm of TST, AND, OR, or XOR instruction is zero-extended. #imm:8 8-bit immediate data imm of MOV, ADD, or CMP/EQ instruction is sign-extended. #imm:8 8-bit immediate data imm of TRAPA instruction is zero-extended and multiplied by 4.

2.4.3 Instruction Formats

This section describes the instruction formats, and the meaning of the source and destination operands. The meaning of the operands depends on the instruction code. The following symbols are used in the table. xxxx: Instruction code mmmm: Source register nnnn: Destination register iiii: Immediate data dddd: Displacement

Page 36 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 2.9 Instruction Formats Instruction Format Source Operand Destination Operand Sample Instruction 0 type xxxx xxxx xxxx xxxx 15 0 ⎯ ⎯ NOP ⎯ nnnn: register direct MOVT Rn Control register or system register nnnn: register direct STS MACH,Rn n type xxxx nnnn xxxx xxxx 15 0 Control register or system register nnnn: pre- decrement register indirect STC.L SR,@-Rn mmmm: register direct Control register or system register LDC Rm,SR m type xxxx mmmm xxxx xxxx 15 0 mmmm: post- increment register indirect Control register or system register LDC.L @Rm+,SR mmmm: register indirect ⎯ JMP @Rm PC relative using Rm ⎯ BRAF Rm

R01UH0198EJ0500 Rev. 5.00 Page 37 of 1560 Mar 18, 2011 SH7080 Group Instruction Format Source Operand Destination Operand Sample Instruction mmmm: register direct nnnn: register direct ADD Rm,Rn mmmm: register direct nnnn: register indirect MOV.L Rm,@Rn mmmm: post- increment register indirect (multiply- and-accumulate operation) nnnn: * post- increment register indirect (multiply- and-accumulate operation) MACH, MACL MAC.W @Rm+,@Rn+ mmmm: post- increment register indirect nnnn: register direct MOV.L @Rm+,Rn mmmm: register direct nnnn: pre- decrement register indirect MOV.L Rm,@-Rn nm type xxxx nnnn mmmm xxxx 15 0 mmmm: register direct nnnn: index register indirect MOV.L Rm,@(R0,Rn) md type xxxx xxxx mmmm dddd 15 0 mmmmdddd: register indirect with displacement R0 (register direct) MOV.B @(disp,Rm),R0 nd4 type xxxx xxxx nnnn dddd 15 0 R0 (register direct) nnnndddd: register indirect with displacement MOV.B R0,@(disp,Rn) nmd type xxxx nnnn mmmm dddd 15 0 mmmm: register direct nnnndddd: register indirect with displacement MOV.L Rm,@(disp,Rn) mmmmdddd: register indirect with displacement nnnn: register direct MOV.L @(disp,Rm),Rn

Page 38 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Instruction Format Source Operand Destination Operand Sample Instruction dddddddd: GBR indirect with displacement R0 (register direct) MOV.L @(disp,GBR),R0 R0 (register direct) dddddddd: GBR indirect with displacement MOV.L R0,@(disp,GBR) dddddddd: PC relative with displacement R0 (register direct) MOVA @(disp,PC),R0 d type xxxx xxxx dddd dddd 15 0 ⎯ dddddddd: PC relative BF label d12 type xxxx dddd dddd dddd 15 0 ⎯ dddddddddddd: PC relative BRA label (label=disp+PC) nd8 type xxxx nnnn dddd dddd 15 0 dddddddd: PC relative with displacement nnnn: register direct MOV.L @(disp,PC),Rn iiiiiiii: immediate Index GBR indirect AND.B #imm,@(R0,GBR) iiiiiiii: immediate R0 (register direct) AND #imm,R0 i type xxxx xxxx iiii iiii 15 0 iiiiiiii: immediate ⎯ TRAPA #imm ni type xxxx nnnn iiii iiii 15 0 iiiiiiii: immediate nnnn: register direct ADD #imm,Rn Note: * In multiply and accumulate instructions, nnnn is the source register.

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2.5 Instruction Set

2.5.1 Instruction Set by Type

Table 2.10 lists the instructions classified by type. Table 2.10 Instruction Types Type Kinds of Instruction Op Code Function Number of Instructions MOV Data transfer Immediate data transfer Peripheral module data transfer Structure data transfer MOVA Effective address transfer MOVT T bit transfer SWAP Upper/lower swap Data transfer instructions XTRCT Extraction of middle of linked registers ADD Binary addition ADDC Binary addition with carry ADDV Binary addition with overflow CMP/cond Comparison DIV1 Division DIV0S Signed division initialization DIV0U Unsigned division initialization DMULS Signed double-precision multiplication DMULU Unsigned double-precision multiplication DT Decrement and test EXTS Sign extension EXTU Zero extension Arithmetic operation instructions MAC Multiply-and-accumulate, double- precision multiply-and-accumulate MUL Double-precision multiplication

Page 40 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Type Kinds of Instruction Op Code Function Number of Instructions MULS Signed multiplication MULU Unsigned multiplication NEG Sign inversion NEGC Sign inversion with borrow SUB Binary subtraction SUBC Binary subtraction with carry Arithmetic operation instructions SUBV Binary subtraction with underflow AND Logical AND NOT Bit inversion OR Logical OR TAS Memory test and bit setting TST T bit setting for logical AND Logic operation instructions XOR Exclusive logical OR

14 ROTL 1-bit left shift

ROTCL 1-bit left shift with T bit ROTCR 1-bit right shift with T bit SHAL Arithmetic 1-bit left shift SHAR Arithmetic 1-bit right shift SHLL Logical 1-bit left shift SHLLn Logical n-bit left shift Shift instructions SHLR Logical 1-bit right shift SHLRn Logical n-bit right shift

R01UH0198EJ0500 Rev. 5.00 Page 41 of 1560 Mar 18, 2011 SH7080 Group Type Kinds of Instruction Op Code Function Number of Instructions BF Conditional branch, delayed conditional branch (T = 0) BT Conditional branch, delayed conditional branch (T = 1) BRA Unconditional branch BRAF Unconditional branch BSR Branch to subroutine procedure BSRF Branch to subroutine procedure JMP Unconditional branch JSR Branch to subroutine procedure Branch instructions RTS Return from subroutine procedure CLRT T bit clear CLRMAC MAC register clear LDC Load into control register LDS Load into system register NOP No operation RTE Return from exception handling SETT T bit setting SLEEP Transition to power-down mode STC Store from control register STS Store from system register System control instructions TRAPA Trap exception handling

31 Total: 62 142

Page 42 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group The instruction code, operation, and execution cycles of the instructions are listed in the following tables, classified by type. Instruction Instruction Code Summary of Operation Execution Cycles T Bit Indicated by mnemonic. Explanation of Symbols OP.Sz SRC, DEST OP: Operation code Sz: Size SRC: Source DEST: Destination Rm: Source register Rn: Destination register imm: Immediate data disp: Displacement* Indicated in MSB ↔ LSB order. Explanation of Symbols mmmm: Source register nnnn: Destination register 0000: R0 0001: R1 1111: R15 iiii: Immediate data dddd: Displacement Indicates summary of operation. Explanation of Symbols →, ←: Transfer direction (xx): Memory operand M/Q/T: Flag bits in SR &: Logical AND of each bit |: Logical OR of each bit ^: Exclusive logical OR of each bit ∼: Logical NOT of each bit <<n: n-bit left shift >>n: n-bit right shift Value when no wait cycles are inserted* Value of T bit after instruction is executed Explanation of Symbols ⎯: No change Notes: 1. The table shows the minimum number of execution states. In practice, the number of instruction execution states will be increased in cases such as the following:

• When there is contention between an instruction fetch and a data access
• When the destination register of a load instruction (memory → register) is also used by the following instruction 2. Scaled ( ×1, ×2, or ×4) according to the instruction operand size, etc. For details, see SH-1/SH-2/SH-DSP Software Manual.

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2.5.2 Data Transfer Instructions

Table 2.11 Data Transfer Instructions Instruction Operation Code Execution Cycles T Bit MOV #imm,Rn imm → Sign extension → Rn 1110nnnniiiiiiii 1 ⎯ MOV.W @(disp,PC),Rn (disp × 2 + PC) → Sign extension → Rn 1001nnnndddddddd 1 ⎯ MOV.L @(disp,PC),Rn (disp × 4 + PC) → Rn 1101nnnndddddddd 1 ⎯ MOV Rm,Rn Rm → Rn 0110nnnnmmmm0011 1 ⎯ MOV.B Rm,@Rn Rm → (Rn) 0010nnnnmmmm0000 1 ⎯ MOV.W Rm,@Rn Rm → (Rn) 0010nnnnmmmm0001 1 ⎯ MOV.L Rm,@Rn Rm → (Rn) 0010nnnnmmmm0010 1 ⎯ MOV.B @Rm,Rn (Rm) → Sign extension → Rn 0110nnnnmmmm0000 1 ⎯ MOV.W @Rm,Rn (Rm) → Sign extension → Rn 0110nnnnmmmm0001 1 ⎯ MOV.L @Rm,Rn (Rm) → Rn 0110nnnnmmmm0010 1 ⎯ MOV.B Rm,@–Rn Rn–1 → Rn, Rm → (Rn) 0010nnnnmmmm0100 1 ⎯ MOV.W Rm,@–Rn Rn–2 → Rn, Rm → (Rn) 0010nnnnmmmm0101 1 ⎯ MOV.L Rm,@–Rn Rn–4 → Rn, Rm → (Rn) 0010nnnnmmmm0110 1 ⎯ MOV.B @Rm+,Rn (Rm) → Sign extension → Rn, Rm + 1 → Rm 0110nnnnmmmm0100 1 ⎯ MOV.W @Rm+,Rn (Rm) → Sign extension → Rn, Rm + 2 → Rm 0110nnnnmmmm0101 1 ⎯ MOV.L @Rm+,Rn (Rm) → Rn,Rm + 4 → Rm 0110nnnnmmmm0110 1 ⎯ MOV.B R0,@(disp,Rn) R0 → (disp + Rn) 10000000nnnndddd 1 ⎯ MOV.W R0,@(disp,Rn) R0 → (disp × 2 + Rn) 10000001nnnndddd 1 ⎯ MOV.L Rm,@(disp,Rn) Rm → (disp × 4 + Rn) 0001nnnnmmmmdddd 1 ⎯ MOV.B @(disp,Rm),R0 (disp + Rm) → Sign extension → R0 10000100mmmmdddd 1 ⎯ MOV.W @(disp,Rm),R0 (disp × 2 + Rm) → Sign extension → R0 10000101mmmmdddd 1 ⎯ MOV.L @(disp,Rm),Rn (disp × 4 + Rm) → Rn 0101nnnnmmmmdddd 1 ⎯

Page 44 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Instruction Operation Code Execution Cycles T Bit MOV.B Rm,@(R0,Rn) Rm → (R0 + Rn) 0000nnnnmmmm0100 1 ⎯ MOV.W Rm,@(R0,Rn) Rm → (R0 + Rn) 0000nnnnmmmm0101 1 ⎯ MOV.L Rm,@(R0,Rn) Rm → (R0 + Rn) 0000nnnnmmmm0110 1 ⎯ MOV.B @(R0,Rm),Rn (R0 + Rm) → Sign extension → Rn 0000nnnnmmmm1100 1 ⎯ MOV.W @(R0,Rm),Rn (R0 + Rm) → Sign extension → Rn 0000nnnnmmmm1101 1 ⎯ MOV.L @(R0,Rm),Rn (R0 + Rm) → Rn 0000nnnnmmmm1110 1 ⎯ MOV.B R0,@(disp,GBR) R0 → (disp + GBR) 11000000dddddddd 1 ⎯ MOV.W R0,@(disp,GBR) R0 → (disp × 2 + GBR) 11000001dddddddd 1 ⎯ MOV.L R0,@(disp,GBR) R0 → (disp × 4 + GBR) 11000010dddddddd 1 ⎯ MOV.B @(disp,GBR),R0 (disp + GBR) → Sign extension → R0 11000100dddddddd 1 ⎯ MOV.W @(disp,GBR),R0 (disp × 2 + GBR) → Sign extension → R0 11000101dddddddd 1 ⎯ MOV.L @(disp,GBR),R0 (disp × 4 + GBR) → R0 11000110dddddddd 1 ⎯ MOVA @(disp,PC),R0 disp × 4 + PC → R0 11000111dddddddd 1 ⎯ MOVT Rn T → Rn 0000nnnn00101001 1 ⎯ SWAP.B Rm,Rn Rm → Swap lowest two bytes → Rn 0110nnnnmmmm1000 1 ⎯ SWAP.W Rm,Rn Rm → Swap two consecutive words → Rn 0110nnnnmmmm1001 1 ⎯ XTRCT Rm,Rn Rm: Middle 32 bits of Rn → Rn 0010nnnnmmmm1101 1 ⎯

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2.5.3 Arithmetic Operation Instructions

Table 2.12 Arithmetic Operation Instructions Instruction Operation Code Execution Cycles T Bit ADD Rm,Rn Rn + Rm → Rn 0011nnnnmmmm1100 1 ⎯ ADD #imm,Rn Rn + imm → Rn 0111nnnniiiiiiii 1 ⎯ ADDC Rm,Rn Rn + Rm + T → Rn, Carry → T 0011nnnnmmmm1110 1 Carry ADDV Rm,Rn Rn + Rm → Rn, Overflow → T 0011nnnnmmmm1111 1 Overflow CMP/EQ #imm,R0 If R0 = imm, 1 → T 10001000iiiiiiii 1 Comparison result CMP/EQ Rm,Rn If Rn = Rm, 1 → T 0011nnnnmmmm0000 1 Comparison result CMP/HS Rm,Rn If Rn ≥ Rm with unsigned data, 1 → T 0011nnnnmmmm0010 1 Comparison result CMP/GE Rm,Rn If Rn ≥ Rm with signed data, 1 → T 0011nnnnmmmm0011 1 Comparison result CMP/HI Rm,Rn If Rn > Rm with unsigned data, 1 → T 0011nnnnmmmm0110

1 Comparison

CMP/GT Rm,Rn If Rn > Rm with signed data, 1 → T 0011nnnnmmmm0111 CMP/PZ Rn If Rn ≥ 0, 1 → T 0100nnnn00010001 1 Comparison result CMP/PL Rn If Rn > 0, 1 → T 0100nnnn00010101 1 Comparison result CMP/STR Rm,Rn If Rn and Rm have an equivalent byte, 1 → T 0010nnnnmmmm1100 DIV1 Rm,Rn Single-step division (Rn/Rm) 0011nnnnmmmm0100

1 Calculation

DIV0S Rm,Rn MSB of Rn → Q, MSB of Rm → M, M^ Q → T 0010nnnnmmmm0111 1 Calculation result DIV0U 0 → M/Q/T 0000000000011001 1 0 DMULS.L Rm,Rn Signed operation of Rn × Rm → MACH, MACL 32 × 32 → 64 bits 0011nnnnmmmm1101 2 to 5* ⎯

Page 46 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Instruction Operation Code Execution Cycles T Bit DMULU.L Rm,Rn Unsigned operation of Rn × Rm → MACH, MACL 32 × 32 → 64 bits 0011nnnnmmmm0101 2 to 5* ⎯ DT Rn Rn - 1 → Rn, if Rn = 0, 1 → T, else 0 → T 0100nnnn00010000 1 Comparison result EXTS.B Rm,Rn A byte in Rm is sign- extended → Rn 0110nnnnmmmm1110 1 ⎯ EXTS.W Rm,Rn A word in Rm is sign- extended → Rn 0110nnnnmmmm1111 1 ⎯ EXTU.B Rm,Rn A byte in Rm is zero- extended → Rn 0110nnnnmmmm1100 1 ⎯ EXTU.W Rm,Rn A word in Rm is zero- extended → Rn 0110nnnnmmmm1101 1 ⎯ MAC.L @Rm+,@Rn+ Signed operation of (Rn) × (Rm) + MAC → MAC, 32 × 32 + 64 → 64 bits 0000nnnnmmmm1111 2 to 5* ⎯ MAC.W @Rm+,@Rn+ Signed operation of (Rn) × (Rm) + MAC → MAC, 16 × 16 + 64 → 64 bits 0100nnnnmmmm1111 2 to 4* ⎯ MUL.L Rm,Rn Rn × Rm → MACL 32 × 32 → 32 bits 0000nnnnmmmm0111 2 to 5* ⎯ MULS.W Rm,Rn Signed operation of Rn × Rm → MAC 16 × 16 → 32 bits 0010nnnnmmmm1111 1 to 3* ⎯ MULU.W Rm,Rn Unsigned operation of Rn × Rm → MAC 16 × 16 → 32 bits 0010nnnnmmmm1110 1 to 3* ⎯ NEG Rm,Rn 0-Rm → Rn 0110nnnnmmmm1011 1 ⎯ NEGC Rm,Rn 0-Rm-T → Rn, Borrow → T 0110nnnnmmmm1010 1 Borrow SUB Rm,Rn Rn-Rm → Rn 0011nnnnmmmm1000 1 ⎯ SUBC Rm,Rn Rn-Rm–T → Rn, Borrow → T 0011nnnnmmmm1010 1 Borrow SUBV Rm,Rn Rn-Rm → Rn, Underflow → T 0011nnnnmmmm1011 1 Overflow Note: * Indicates the number of execution cycles for normal operation.

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2.5.4 Logic Operation Instructions

Table 2.13 Logic Opera tion Instructions Instruction Operation Code Execution Cycles T Bit AND Rm,Rn Rn & Rm → Rn 0010nnnnmmmm1001 1 ⎯ AND #imm,R0 R0 & imm → R0 11001001iiiiiiii 1 ⎯ AND.B #imm,@(R0,GBR) (R0 + GBR) & imm → (R0 + GBR) 11001101iiiiiiii 3 ⎯ NOT Rm,Rn ~Rm → Rn 0110nnnnmmmm0111 1 ⎯ OR Rm,Rn Rn | Rm → Rn 0010nnnnmmmm1011 1 ⎯ OR #imm,R0 R0 | imm → R0 11001011iiiiiiii 1 ⎯ OR.B #imm,@(R0,GBR) (R0 + GBR) | imm → (R0 + GBR) 11001111iiiiiiii 3 ⎯ TAS.B @Rn If (Rn) is 0, 1 → T; 1 → MSB of (Rn) 0100nnnn00011011 4 Test result TST Rm,Rn Rn & Rm; if the result is 0, 1 → T 0010nnnnmmmm1000 1 Test result TST #imm,R0 R0 & imm; if the result is 0, 1 → T 11001000iiiiiiii

1 Test result

TST.B #imm,@(R0,GBR) (R0 + GBR) & imm; if the result is 0, 1 → T 11001100iiiiiiii

3 Test result

XOR Rm,Rn Rn ^ Rm → Rn 0010nnnnmmmm1010 1 ⎯ XOR #imm,R0 R0 ^ imm → R0 11001010iiiiiiii 1 ⎯ XOR.B #imm,@(R0,GBR) (R0 + GBR) ^ imm → (R0 + GBR) 11001110iiiiiiii 3 ⎯

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2.5.5 Shift Instructions

Table 2.14 Shift Instructions Instruction Operation Code Execution Cycles T Bit ROTL Rn T ← Rn ← MSB 0100nnnn00000100 1 MSB ROTR Rn LSB → Rn → T 0100nnnn00000101 1 LSB ROTCL Rn T ← Rn ← T 0100nnnn00100100 1 MSB ROTCR Rn T → Rn → T 0100nnnn00100101 1 LSB SHAL Rn T ← Rn ← 0 0100nnnn00100000 1 MSB SHAR Rn MSB → Rn → T 0100nnnn00100001 1 LSB SHLL Rn T ← Rn ← 0 0100nnnn00000000 1 MSB SHLR Rn 0 → Rn → T 0100nnnn00000001 1 LSB SHLL2 Rn Rn << 2 → Rn 0100nnnn00001000 1 ⎯ SHLR2 Rn Rn >> 2 → Rn 0100nnnn00001001 1 ⎯ SHLL8 Rn Rn << 8 → Rn 0100nnnn00011000 1 ⎯ SHLR8 Rn Rn >> 8 → Rn 0100nnnn00011001 1 ⎯ SHLL16 Rn Rn << 16 → Rn 0100nnnn00101000 1 ⎯ SHLR16 Rn Rn >> 16 → Rn 0100nnnn00101001 1 ⎯

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2.5.6 Branch Instructions

Table 2.15 Branch Instructions Instruction Operation Code Execution Cycles T Bit BF label If T = 0, disp × 2 + PC → PC; if T = 1, nop 10001011dddddddd 3/1* ⎯ BF/S label Delayed branch, if T = 0, disp × 2 + PC → PC; if T = 1, nop 10001111dddddddd 2/1* ⎯ BT label If T = 1, disp × 2 + PC → PC; if T = 0, nop 10001001dddddddd 3/1* ⎯ BT/S label Delayed branch, if T = 1, disp × 2 + PC → PC; if T = 0, nop 10001101dddddddd 2/1* ⎯ BRA label Delayed branch, disp × 2 + PC → PC 1010dddddddddddd 2 ⎯ BRAF Rm Delayed branch, Rm + PC → PC 0000mmmm00100011 2 ⎯ BSR label Delayed branch, PC → PR, disp × 2 + PC → PC 1011dddddddddddd 2 ⎯ BSRF Rm Delayed branch, PC → PR, Rm + PC → PC 0000mmmm00000011 2 ⎯ JMP @Rm Delayed branch, Rm → PC 0100mmmm00101011 2 ⎯ JSR @Rm Delayed branch, PC → PR, Rm → PC 0100mmmm00001011 2 ⎯ RTS Delayed branch, PR → PC 0000000000001011 2 ⎯ Note: * One cycle when the branch is not executed.

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2.5.7 System Control Instructions

Table 2.16 System Co ntrol Instructions Instruction Operation Code Execution Cycles T Bit CLRT 0 → T 0000000000001000 1 0 CLRMAC 0 → MACH, MACL 0000000000101000 1 ⎯ LDC Rm,SR Rm → SR 0100mmmm00001110 6 LSB LDC Rm,GBR Rm → GBR 0100mmmm00011110 4 ⎯ LDC Rm,VBR Rm → VBR 0100mmmm00101110 4 ⎯ LDC.L @Rm+,SR (Rm) → SR, Rm + 4 → Rm 0100mmmm00000111 8 LSB LDC.L @Rm+,GBR (Rm) → GBR, Rm + 4 → Rm 0100mmmm00010111 4 ⎯ LDC.L @Rm+,VBR (Rm) → VBR, Rm + 4 → Rm 0100mmmm00100111 4 ⎯ LDS Rm,MACH Rm → MACH 0100mmmm00001010 1 ⎯ LDS Rm,MACL Rm → MACL 0100mmmm00011010 1 ⎯ LDS Rm,PR Rm → PR 0100mmmm00101010 1 ⎯ LDS.L @Rm+,MACH (Rm) → MACH, Rm + 4 → Rm 0100mmmm00000110 1 ⎯ LDS.L @Rm+,MACL (Rm) → MACL, Rm + 4 → Rm 0100mmmm00010110 1 ⎯ LDS.L @Rm+,PR (Rm) → PR, Rm + 4 → Rm 0100mmmm00100110 1 ⎯ NOP No operation 0000000000001001 1 ⎯ RTE Delayed branch, Stack area → PC/SR 0000000000101011 5 ⎯ SETT 1 → T 0000000000011000 1 1 SLEEP Sleep 0000000000011011 4* ⎯ STC SR,Rn SR → Rn 0000nnnn00000010 1 ⎯ STC GBR,Rn GBR → Rn 0000nnnn00010010 1 ⎯ STC VBR,Rn VBR → Rn 0000nnnn00100010 1 ⎯ STC.L SR,@–Rn Rn–4 → Rn, SR → (Rn) 0100nnnn00000011 1 ⎯ STC.L GBR,@–Rn Rn–4 → Rn, GBR → (Rn) 0100nnnn00010011 1 ⎯ STC.L VBR,@–Rn Rn–4 → Rn, VBR → (Rn) 0100nnnn00100011 1 ⎯

R01UH0198EJ0500 Rev. 5.00 Page 51 of 1560 Mar 18, 2011 SH7080 Group Instruction Operation Code Execution Cycles T Bit STS MACH,Rn MACH → Rn 0000nnnn00001010 1 ⎯ STS MACL,Rn MACL → Rn 0000nnnn00011010 1 ⎯ STS PR,Rn PR → Rn 0000nnnn00101010 1 ⎯ STS.L MACH,@–Rn Rn–4 → Rn, MACH → (Rn) 0100nnnn00000010 1 ⎯ STS.L MACL,@–Rn Rn–4 → Rn, MACL → (Rn) 0100nnnn00010010 1 ⎯ STS.L PR,@–Rn Rn–4 → Rn, PR → (Rn) 0100nnnn00100010 1 ⎯ TRAPA #imm PC/SR → Stack area, (imm × 4 + VBR) → PC 11000011iiiiiiii 8 ⎯ Note: * Number of execution cycles until this LSI enters sleep mode. About the number of execution cycles: The table lists the minimum number of execution cycles. In practice, the number of execution cycles will be increased depending on the conditions such as:

• When there is a conflict between instruction fetch and data access
• When the destination register of a load instruction (memory → register) is also used by the instruction immediately after the load instruction.

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2.6 Processing States

The CPU has the five processing states: reset, exception handling, bus release, program execution, and power-down. Figure 2.4 shows the CPU state transition. From any state when RES = 0 RES = 0 From any state except deep software standby mode when RES = 1 and MRES = 0 Power-on reset state Manual reset state RES = 0 Reset stateRES = 1 RES = 1, MRES = 1 Exception handling state Exception processing source occurs Exception processing ends Program execution state NMI interrupt or IRQ interrupt occurs Bus release state Bus request generated Bus request cleared Bus request generated Bus request cleared Bus request generated Bus request cleared Sleep mode SSBY bit = 1 and STBYMD bit = 1 for SLEEP instruction SSBY bit = 1 and STBYMD bit = 0 for SLEEP instruction SSBY bit = 0 for SLEEP instruction Software standby mode Power-down mode Deep software standby mode Internal power-on reset by WDT or internal manual reset by WDT occurs. Figure 2.4 Transitions between Processing States

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• Reset state The CPU is reset. When the RES pin is low, the CPU enters the power-on reset state. When the RES pin is high and MRES pin is low, the CPU enters the manual reset state.
• Exception handling state This state is a transitional state in which the CPU processing state changes due to a request for exception handling such as a reset or an interrupt. When a reset occurs, the execution start address as the initial value of the program counter (PC) and the initial value of the stack pointer (SP) are fetched from the exception handling vector table. Then, a branch is made for the start address to execute a program. When an interrupt occurs, the PC and status register (SR) are saved in the stack area pointed to by SP. The start address of an exception handling routine is fetched from the exception handling vector table and a branch to the address is made to execute a program. Then the processing state enters the program execution state.
• Program execution state The CPU executes programs sequentially.
• Power-down state The CPU stops to reduce power consumption. The SLEEP instruction makes the CPU enter sleep mode, software standby mode, or deep software standby mode.
• Bus release state In the bus release state, the CPU releases access rights to the bus to the device that has requested them.

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Section 3 MCU Operating Modes R01UH0198EJ0500 Rev. 5.00 Page 55 of 1560 Mar 18, 2011 SH7080 Group Section 3 MCU Operating Modes

3.1 Selection of Operating Modes

This LSI has four MCU operating modes and three on-chip flash memory programming modes. The operating mode is determined by the setting of FWE, MD1, and MD0 pins. Table 3.1 shows the allowable combinations of these pin settings; do not set these pins in the other way than the shown combinations. When power is applied to the system, be sure to conduct power-on reset. The MCU operating mode can be selected from MCU extension modes 0 to 2 and single chip mode. For the on-chip flash memory programming mode, boot mode, user boot mode, and user program mode which are on-chip programming modes are available. Table 3.1 Selection of Operating Modes Pin Setting Bus Width of CS0 Space Mode No. FWE MD1 MD0 Mode Name On-Chip ROM SH7083 SH7084 SH7085 SH7086 Mode 0 0 0 0 MCU extension mode 0 Not active 8 8 16 16 Mode 1 0 0 1 MCU extension mode 1 Not active 16 16 32 32 Mode 2 0 1 0 MCU extension mode 2 Active Set by CS0BCR in BSC Mode 3 0 1 1 Single chip mode Active ⎯ Mode 4* 1 0 0 Boot mode Active ⎯ Mode 5* 1 0 1 User boot mode Active Set by CS0BCR in BSC Mode 6* 1 1 0 Set by CS0BCR in BSC Mode 7* 1 1 1 User programming mode Active Note: * Flash memory programming mode.

Section 3 MCU Operating Modes Page 56 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

3.2 Input/Output Pins

Table 3.2 describes the configuration of operating mode related pin. Table 3.2 Pin Configuration Pin Name Input/Output Function MD0 Input Designates operating mode through the level applied to this pin MD1 Input Designates operating mode through the level applied to this pin FWE Input Enables, by hardware, progr amming/erasing of the on-chip flash memory

Section 3 MCU Operating Modes R01UH0198EJ0500 Rev. 5.00 Page 57 of 1560 Mar 18, 2011 SH7080 Group

3.3 Operating Modes

3.3.1 Mode 0 (MCU Extension Mode 0)

CS0 space becomes external memory spaces with 8-bit bus width in SH7083/SH7084 or 16-bit bus width in SH7085/SH7086.

3.3.2 Mode 1 (MCU Extension Mode 1)

CS0 space becomes external memory spaces with 16-bit bus width in SH7083/SH7084 or 32-bit bus width in SH7085/SH7086.

3.3.3 Mode 2 (MCU Extension Mode 2)

The on-chip ROM is active and CS0 space can be used in this mode.

3.3.4 Mode 3 (Single Chip Mode)

All ports can be used in this mode, however the external address cannot be used.

Section 3 MCU Operating Modes Page 58 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

3.4 Address Map

The address map for the operating modes is shown in figures 3.1 to 3.7. H'00000000 H'0003FFFF H'00040000 H'FFFF7FFF H'FFFF8000 H'FFFFBFFF H'FFFFC000 H'FFFFFFFF H'00000000 H'02000000 H'01FFFFFF H'03FFFFFF H'0003FFFF H'04000000 H'00040000 H'0BFFFFFF H'0C000000 H'0DFFFFFF H'0E000000 H'1BFFFFFF H'1C000000 H'1DFFFFFF H'1E000000 H'02000000 H'01FFFFFF H'FFF7FFFF H'FFF80000 H'FFF9FFFF H'FFFA0000H'FFFF7FFF H'FFFF8000H'FFFFBFFF H'FFFFC000 H'FFFFFFFF H'00000000 H'0BFFFFFF H'0C000000 H'0DFFFFFF H'0E000000 H'1BFFFFFF H'1C000000 H'1DFFFFFF H'1E000000 H'FFF7FFFF H'FFF80000 H'FFF9FFFF H'FFFA0000H'FFFF7FFF H'FFFF8000H'FFFFBFFF H'FFFFC000 H'FFFFFFFF CS7 space On-chip ROM (256 kbytes) Modes 0 and 1 On-chip ROM disabled mode Mode 2 On-chip ROM enabled mode Mode 3 Single chip mode On-chip RAM (16 kbytes) Reserved area Reserved area Reserved area Reserved area CS0 space CS3 space Reserved area On-chip peripheral I/O registers SDRAM mode setting space On-chip RAM (16 kbytes) On-chip peripheral I/O registers CS7 space On-chip RAM (16 kbytes) Reserved area Reserved area Reserved area CS0 space CS3 space Reserved area On-chip peripheral I/O registers SDRAM mode setting space On-chip ROM (256 kbytes) Reserved area Figure 3.1 Address Map for Each Operating Mode in SH7083 (256-Kbyte Flash Memory Version)

Section 3 MCU Operating Modes R01UH0198EJ0500 Rev. 5.00 Page 59 of 1560 Mar 18, 2011 SH7080 Group H'00000000 H'0007FFFF H'00080000 H'FFFF3FFF H'FFFF4000 H'FFFFBFFF H'FFFFC000 H'FFFFFFFF H'00000000 H'02000000 H'01FFFFFF H'03FFFFFF H'0007FFFF H'04000000 H'00080000 H'0BFFFFFF H'0C000000 H'0DFFFFFF H'0E000000 H'1BFFFFFF H'1C000000 H'1DFFFFFF H'1E000000 H'02000000 H'01FFFFFF H'FFF7FFFF H'FFF80000 H'FFF9FFFF H'FFFA0000H'FFFF3FFF H'FFFF4000H'FFFFBFFF H'FFFFC000 H'FFFFFFFF H'00000000 H'0BFFFFFF H'0C000000 H'0DFFFFFF H'0E000000 H'1BFFFFFF H'1C000000 H'1DFFFFFF H'1E000000 H'FFF7FFFF H'FFF80000 H'FFF9FFFF H'FFFA0000H'FFFF3FFF H'FFFF4000H'FFFFBFFF H'FFFFC000 H'FFFFFFFF CS7 space On-chip ROM (512 kbytes) Modes 0 and 1 On-chip ROM disabled mode Mode 2 On-chip ROM enabled mode Mode 3 Single chip mode On-chip RAM (32 kbytes) Reserved area Reserved area Reserved area Reserved area CS0 space CS3 space Reserved area On-chip peripheral I/O registers SDRAM mode setting space On-chip RAM (32 kbytes) On-chip peripheral I/O registers CS7 space On-chip RAM (32 kbytes) Reserved area Reserved area Reserved area CS0 space CS3 space Reserved area On-chip peripheral I/O registers SDRAM mode setting space On-chip ROM (512 kbytes) Reserved area Figure 3.2 Address Map for Each Operating Mode in SH7083 (512-Kbyte Flash Memory Version)

Section 3 MCU Operating Modes Page 60 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group H'00000000 H'0003FFFF H'00040000 H'FFFF7FFF H'FFFF8000 H'FFFFBFFF H'FFFFC000 H'FFFFFFFF H'00000000 H'02000000 H'01FFFFFF H'03FFFFFF H'0003FFFF H'07FFFFFF H'04000000 H'00040000 H'08000000 H'0BFFFFFF H'0C000000 H'0FFFFFFF H'10000000 H'13FFFFFF H'14000000 H'17FFFFFF H'18000000 H'1BFFFFFF H'1C000000 H'1FFFFFFF H'20000000 H'FFF7FFFF H'FFF80000 H'FFF9FFFF H'FFFA0000H'FFFF7FFF H'FFFF8000H'FFFFBFFF H'FFFFC000 H'FFFFFFFF H'00000000 H'03FFFFFF H'07FFFFFF H'04000000 H'08000000 H'0BFFFFFF H'0C000000 H'0FFFFFFF H'10000000 H'13FFFFFF H'14000000 H'17FFFFFF H'18000000 H'1BFFFFFF H'1C000000 H'1FFFFFFF H'20000000 H'FFF7FFFF H'FFF80000 H'FFF9FFFF H'FFFA0000H'FFFF7FFF H'FFFF8000H'FFFFBFFF H'FFFFC000 H'FFFFFFFF CS4 space CS5 space CS6 space CS7 space On-chip ROM (256 kbytes) Modes 0 and 1 On-chip ROM disabled mode Mode 2 On-chip ROM enabled mode Mode 3 Single chip mode On-chip RAM (16 kbytes) Reserved area Reserved area CS0 space CS1 space CS2 space CS3 space Reserved area On-chip peripheral I/O registers SDRAM mode setting space On-chip ROM (256 kbytes) On-chip RAM (16 kbytes) Reserved area On-chip peripheral I/O registers CS4 space CS5 space CS6 space CS7 space On-chip RAM (16 kbytes) CS0 space CS1 space CS2 space CS3 space Reserved area Reserved area On-chip peripheral I/O registers SDRAM mode setting space Figure 3.3 Address Map for Each Operating Mode in SH7084 (256-Kbyte Flash Memory Version)

Section 3 MCU Operating Modes R01UH0198EJ0500 Rev. 5.00 Page 61 of 1560 Mar 18, 2011 SH7080 Group H'00000000 H'0007FFFF H'00080000 H'FFFF3FFF H'FFFF4000 H'FFFFBFFF H'FFFFC000 H'FFFFFFFF H'00000000 H'02000000 H'01FFFFFF H'03FFFFFF H'0007FFFF H'07FFFFFF H'04000000 H'00080000 H'08000000 H'0BFFFFFF H'0C000000 H'0FFFFFFF H'10000000 H'13FFFFFF H'14000000 H'17FFFFFF H'18000000 H'1BFFFFFF H'1C000000 H'1FFFFFFF H'20000000 H'FFF7FFFF H'FFF80000 H'FFF9FFFF H'FFFA0000H'FFFF3FFF H'FFFF4000H'FFFFBFFF H'FFFFC000 H'FFFFFFFF H'00000000 H'03FFFFFF H'07FFFFFF H'04000000 H'08000000 H'0BFFFFFF H'0C000000 H'0FFFFFFF H'10000000 H'13FFFFFF H'14000000 H'17FFFFFF H'18000000 H'1BFFFFFF H'1C000000 H'1FFFFFFF H'20000000 H'FFF7FFFF H'FFF80000 H'FFF9FFFF H'FFFA0000H'FFFF3FFF H'FFFF4000H'FFFFBFFF H'FFFFC000 H'FFFFFFFF CS4 space CS5 space CS6 space CS7 space On-chip ROM (512 kbytes) Modes 0 and 1 On-chip ROM disabled mode Mode 2 On-chip ROM enabled mode Mode 3 Single chip mode On-chip RAM (32 kbytes) Reserved area Reserved area CS0 space CS1 space CS2 space CS3 space Reserved area On-chip peripheral I/O registers SDRAM mode setting space On-chip ROM (512 kbytes) On-chip RAM (32 kbytes) Reserved area On-chip peripheral I/O registers CS4 space CS5 space CS6 space CS7 space On-chip RAM (32 kbytes) CS0 space CS1 space CS2 space CS3 space Reserved area Reserved area On-chip peripheral I/O registers SDRAM mode setting space Figure 3.4 Address Map for Each Operating Mode in SH7084 (512-Kbyte Flash Memory Version)

Section 3 MCU Operating Modes Page 62 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group H'00000000 H'0003FFFF H'00040000 H'FFFF7FFF H'FFFF8000 H'FFFFBFFF H'FFFFC000 H'FFFFFFFF H'00000000 H'02000000 H'01FFFFFF H'03FFFFFF H'0003FFFF H'07FFFFFF H'04000000 H'00040000 H'08000000 H'0BFFFFFF H'0C000000 H'0FFFFFFF H'10000000 H'13FFFFFF H'14000000 H'17FFFFFF H'18000000 H'1BFFFFFF H'1C000000 H1FFFFFFF H'20000000 H'FFF7FFFF H'FFF80000 H'FFF9FFFF H'FFFA0000H'FFFF7FFF H'FFFF8000H'FFFFBFFF H'FFFFC000 H'FFFFFFFF H'00000000 H'03FFFFFF H'07FFFFFF H'04000000 H'08000000 H'0BFFFFFF H'0C000000 H'0FFFFFFF H'10000000 H'13FFFFFF H'14000000 H'17FFFFFF H'18000000 H'1BFFFFFF H'1C000000 H1FFFFFFF H'20000000 H'FFF7FFFF H'FFF80000 H'FFF9FFFF H'FFFA0000H'FFFF7FFF H'FFFF8000H'FFFFBFFF H'FFFFC000 H'FFFFFFFF CS4 space CS5 space CS6 space CS7 space On-chip ROM (256 kbytes) Modes 0 and 1 On-chip ROM disabled mode Mode 2 On-chip ROM enabled mode Mode 3 Single chip mode On-chip RAM (16 kbytes) Reserved area CS0 space CS1 space CS2 space CS3 space Reserved area Reserved area On-chip peripheral I/O registers SDRAM mode setting space On-chip ROM (256 kbytes) On-chip RAM (16 kbytes) Reserved area On-chip peripheral I/O registers CS4 space CS5 space CS6 space CS7 space On-chip RAM (16 kbytes) CS0 space CS1 space CS2 space CS3 space Reserved area Reserved area On-chip peripheral I/O registers SDRAM mode setting space Figure 3.5 Address Map for Each Operating Mode in SH7085 (256-Kbyte Flash Memory Version)

Section 3 MCU Operating Modes R01UH0198EJ0500 Rev. 5.00 Page 63 of 1560 Mar 18, 2011 SH7080 Group H'00000000 H'0007FFFF H'00080000 H'FFFF3FFF H'FFFF4000 H'FFFFBFFF H'FFFFC000 H'FFFFFFFF H'00000000 H'02000000 H'01FFFFFF H'03FFFFFF H'0007FFFF H'07FFFFFF H'04000000 H'00080000 H'08000000 H'0BFFFFFF H'0C000000 H'0FFFFFFF H'10000000 H'13FFFFFF H'14000000 H'17FFFFFF H'18000000 H'1BFFFFFF H'1C000000 H'1FFFFFFF H'20000000 H'FFF7FFFF H'FFF80000 H'FFF9FFFF H'FFFA0000 H'FFFF3FFF H'FFFF4000 H'FFFFBFFF H'FFFFC000 H'FFFFFFFF H'00000000 H'03FFFFFF H'07FFFFFF H'04000000 H'08000000 H'0BFFFFFF H'0C000000 H'0FFFFFFF H'10000000 H'13FFFFFF H'14000000 H'17FFFFFF H'18000000 H'1BFFFFFF H'1C000000 H'1FFFFFFF H'20000000 H'FFF7FFFF H'FFF80000 H'FFF9FFFF H'FFFA0000 H'FFFF3FFF H'FFFF4000 H'FFFFBFFF H'FFFFC000 H'FFFFFFFF CS4 space CS5 space CS6 spaceCS7 space On-chip ROM (512 kbytes) Modes 0 and 1 On-chip ROM disabled mode Mode 2 On-chip ROM enabled mode Mode 3 Single chip mode On-chip RAM (32 kbytes) Reserved area CS0 space CS1 space CS2 space CS3 space Reserved area Reserved area On-chip peripheral I/O registers SDRAM mode setting space On-chip ROM (512 kbytes) On-chip RAM (32 kbytes) Reserved area On-chip peripheral I/O registers CS4 space CS5 space CS6 space CS7 space On-chip RAM (32 kbytes) CS0 space CS1 space CS2 space CS3 space Reserved area Reserved area On-chip peripheral I/O registers SDRAM mode setting space Figure 3.6 Address Map for Each Operating Mode in SH7085 (512-Kbyte Flash Memory Version)

Section 3 MCU Operating Modes Page 64 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group H'00000000 H'0007FFFF H'00080000 H'FFFF3FFF H'FFFF4000 H'FFFFBFFF H'FFFFC000 H'FFFFFFFF H'00000000 H'02000000 H'01FFFFFF H'03FFFFFF H'0007FFFF H'07FFFFFF H'04000000 H'00080000 H'08000000 H'0BFFFFFF H'0C000000 H'0FFFFFFF H'10000000 H'13FFFFFF H'14000000 H'17FFFFFF H'18000000 H'1BFFFFFF H'1C000000 H'1FFFFFFF H'20000000 H'3FFFFFFF H'40000000 H'7FFFFFFF H'80000000 H'FFF7FFFF H'FFF80000 H'FFF9FFFF H'FFFA0000 H'FFFF3FFF H'FFFF4000 H'FFFFBFFF H'FFFFC000 H'FFFFFFFF H'3FFFFFFF H'40000000 H'7FFFFFFF H'80000000 H'00000000 H'03FFFFFF H'07FFFFFF H'04000000 H'08000000 H'0BFFFFFF H'0C000000 H'0FFFFFFF H'10000000 H'13FFFFFF H'14000000 H'17FFFFFF H'18000000 H'1BFFFFFF H'1C000000 H'1FFFFFFF H'20000000 H'FFF7FFFF H'FFF80000 H'FFF9FFFF H'FFFA0000 H'FFFF3FFF H'FFFF4000 H'FFFFBFFF H'FFFFC000 H'FFFFFFFF CS4 space CS5 space CS6 spaceCS7 space On-chip ROM (512 kbytes) Modes 0 and 1 On-chip ROM disabled mode Mode 2 On-chip ROM enabled mode Mode 3 Single chip mode On-chip RAM (32 kbytes) Reserved area Reserved area CS0 space CS1 space CS2 space CS3 space CS8 space Reserved area Reserved area On-chip peripheral I/O registers SDRAM mode setting space On-chip ROM (512 kbytes) On-chip RAM (32 kbytes) Reserved area On-chip peripheral I/O registers CS4 space CS5 space CS6 space CS7 space On-chip RAM (32 kbytes) CS0 space CS1 space CS2 space CS3 space CS8 space Reserved area Reserved area Reserved area On-chip peripheral I/O registers SDRAM mode setting space Figure 3.7 Address Map for Each Operating Mode in SH7086

Section 3 MCU Operating Modes R01UH0198EJ0500 Rev. 5.00 Page 65 of 1560 Mar 18, 2011 SH7080 Group

3.5 Initial State in This LSI

In the initial state of this LSI, some of on-chip modules are set in module standby state for saving power. When operating these modules, clear module standby state according to the procedure in section 26, Power-Down Modes.

3.6 Note on Changing Operating Mode

When changing operating mode while power is applied to this LSI, make sure to do it in the power-on reset state (that is, the low level is applied to the RES pin). Note: * See section 28.3.2, Control Signal Timing. tMDS* CK MD1, MD0 RES Figure 3.8 Reset Input Timing when Changing Operating Mode

Section 3 MCU Operating Modes Page 66 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

Section 4 Clock Pulse Generator (CPG) R01UH0198EJ0500 Rev. 5.00 Page 67 of 1560 Mar 18, 2011 SH7080 Group Section 4 Clock Pulse Generator (CPG) This LSI has a clock pulse generator (CPG) that generates an internal clock (I φ), a bus clock (Bφ), a peripheral clock (Pφ), and clocks (MIφ and MPφ) for the MTU2S and MTU2 modules. The CPG also controls power-down modes.

4.1 Features

• Five clocks generated independently An internal clock (Iφ) for the CPU; a peripheral clock (Pφ) for the on-chip peripheral modules; a bus clock (Bφ = CK) for the external bus interface; a MTU2S clock (MIφ) for the on-chip MTU2S module; and a MTU2 clock (MPφ) for the on-chip MTU2 module.
• Frequency change function Frequencies of the internal clock (Iφ), bus clock (Bφ), peripheral clock (Pφ), MTU2S clock (MIφ), and MTU2 clock (MPφ) can be changed independently using the divider circuit within the CPG. Frequencies are changed by software using the frequency control register (FRQCR) setting.
• Power-down mode control The clock can be stopped in sleep mode and standby mode and specific modules can be stopped using the module standby function.
• Oscillation stop detection If the clock supplied through the clock input pin stops for any reason, the timer pins can be automatically placed in the high-impedance state.

Section 4 Clock Pulse Generator (CPG) R01UH0198EJ0500 Rev. 5.00 Page 69 of 1560 Mar 18, 2011 SH7080 Group The clock pulse generator blocks function as follows: PLL Circuit: The PLL circuit multiples the clock frequency input from the crystal oscillator or the EXTAL pin by 8. The multiplication ratio is fixed at ×8. Crystal Oscillator: The crystal oscillator is an oscillator circuit when a crystal resonator is connected to the XTAL and EXTAL pins. Divider: The divider generates clocks with the frequencies to be used by the internal clock (I φ), bus clock (Bφ), peripheral clock (Pφ), MTU2S clock (MIφ), and MTU2 clock (MPφ). The frequencies can be selected from 1, 1/2, 1/3, 1/4, and 1/8 times the frequency output from the PLL circuit. The division ratio should be specified in the frequency control register (FRQCR). Oscillation Stop Detection Circuit: This circuit detects an abnormal condition in the crystal oscillator. Clock Frequency Control Circuit: The clock frequency control circuit controls the clock frequency according to the setting in the frequency control register (FRQCR). Standby Control Circuit: The standby control circuit controls the state of the on-chip oscillator circuit and other modules in sleep or standby mode. Frequency Control Register (FRQCR): The frequency control register (FRQCR) has control bits for the frequency division ratios of the internal clock (Iφ), bus clock (Bφ), peripheral clock (Pφ), MTU2S clock (MIφ), and MTU2 clock (MPφ). Oscillation Stop Detection Control Register (OSCCR): The oscillation stop detection control register (OSCCR) has an oscillation stop detection flag and a bit for selecting flag status output through an external pin. Standby Control Registers 1 to 6 (STBCR1 to STBCR6): The standby control register (STBCR) has bits for controlling the power-down modes. For details, see section 26, Power-Down Modes.

Section 4 Clock Pulse Generator (CPG) Page 70 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 4.1 shows the operating clock for each module. Table 4.1 Operating Clock for Each Module Operating Clock Operating Module Operating Clock Operating Module Internal clock (Iφ) CPU Peripheral clock (P φ) POE UBC SCI ROM SCIF RAM SSU I A/D CMT WDT Bus clock (Bφ) BSC MTU2 clock (MP φ) MTU2 DMAC MTU2S clock (MI φ) MTU2S DTC

Section 4 Clock Pulse Generator (CPG) R01UH0198EJ0500 Rev. 5.00 Page 71 of 1560 Mar 18, 2011 SH7080 Group

4.2 Input/Output Pins

Table 4.2 shows the CPG pin configuration. Table 4.2 Pin Configuration Pin Name Abbr. I/O Description XTAL Output Connects a crystal resonator. Crystal input/output pins (clock input pins) EXTAL Input Connects a crystal resonator or an external clock. Clock output pin CK Output Outputs an external clock. Note: To use the clock output (CK) pin, appropriate settings may be needed for the pin in the pin function controller (PFC) in some cases. For details, refer to section 21, Pin Function Controller (PFC).

Section 4 Clock Pulse Generator (CPG) Page 72 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

4.3 Clock Operating Mode

Table 4.3 shows the clock operating mode of this LSI. Table 4.3 Clock Operating Mode Clock I/O Clock Operating Mode Source Output PLL Circuit Input to Divider

1 EXTAL input or

CK* ON ( ×8) ×8 Note: * To output the clock through the clock output (CK) pin, appropriate settings should be made in the pin function controller (PFC). For details, refer to section 21, Pin Function Controller (PFC). Mode 1: The frequency of the external clock input from the EXTAL pin is multiplied by 8 in the PLL circuit before being supplied to the on-chip modules in this LSI, which eliminates the need to generate a high-frequency clock outside the LSI. Since the input clock frequency ranging from 5 MHz to 12.5 MHz can be used, the internal clock (Iφ) frequency ranges from 10 MHz to 80 MHz. Maximum operating frequencies: Iφ = 80 MHz, Bφ = 40 MHz, Pφ = 40 MHz, MIφ = 80 MHz, and MPφ = 40 MHz Table 4.4 shows the frequency division ratios that can be specified with FRQCR.

Section 4 Clock Pulse Generator (CPG) R01UH0198EJ0500 Rev. 5.00 Page 73 of 1560 Mar 18, 2011 SH7080 Group Table 4.4 Frequency Division Ratios Specifiable with FRQCR FRQCR Division Ratio Setting Clock Ratio Clock Frequency (MHz) * PLL Multipli- cation Ratio Iφ B φ P φ MI φ MP φ I φ B φ P φ MI φ MP φ Input Clock Iφ B φ P φ MI φ MP φ ×8 1/8 1/8 1/8 1/8 1/8 1 1 1 1 1 10 10 10 10 10 10 1/4 1/8 1/8 1/8 1/8 2 1 1 1 1 20 10 10 10 10 1/4 1/8 1/8 1/4 1/8 2 1 1 2 1 20 10 10 20 10 1/4 1/4 1/8 1/8 1/8 2 2 1 1 1 20 20 10 10 10 1/4 1/4 1/8 1/4 1/8 2 2 1 2 1 20 20 10 20 10 1/4 1/4 1/8 1/4 1/4 2 2 1 2 2 20 20 10 20 20 1/4 1/4 1/4 1/4 1/4 2 2 2 2 2 20 20 20 20 20 1/3 1/3 1/3 1/3 1/3 8/3 8/3 8/3 8/3 8/3 26 26 26 26 26 1/2 1/8 1/8 1/8 1/8 4 1 1 1 1 40 10 10 10 10 1/2 1/8 1/8 1/4 1/8 4 1 1 2 1 40 10 10 20 10 1/2 1/8 1/8 1/2 1/8 4 1 1 4 1 40 10 10 40 10 1/2 1/4 1/8 1/8 1/8 4 2 1 1 1 40 20 10 10 10 1/2 1/4 1/8 1/4 1/8 4 2 1 2 1 40 20 10 20 10 1/2 1/4 1/8 1/4 1/4 4 2 1 2 2 40 20 10 20 20 1/2 1/4 1/8 1/2 1/8 4 2 1 4 1 40 20 10 40 10 1/2 1/4 1/8 1/2 1/4 4 2 1 4 2 40 20 10 40 20 1/2 1/4 1/4 1/4 1/4 4 2 2 2 2 40 20 20 20 20 1/2 1/4 1/4 1/2 1/4 4 2 2 4 2 40 20 20 40 20 1/2 1/2 1/8 1/8 1/8 4 4 1 1 1 40 40 10 10 10 1/2 1/2 1/8 1/4 1/8 4 4 1 2 1 40 40 10 20 10 1/2 1/2 1/8 1/4 1/4 4 4 1 2 2 40 40 10 20 20 1/2 1/2 1/8 1/2 1/8 4 4 1 4 1 40 40 10 40 10 1/2 1/2 1/8 1/2 1/4 4 4 1 4 2 40 40 10 40 20 1/2 1/2 1/8 1/2 1/2 4 4 1 4 4 40 40 10 40 40 1/2 1/2 1/4 1/4 1/4 4 4 2 2 2 40 40 20 20 20 1/2 1/2 1/4 1/2 1/4 4 4 2 4 2 40 40 20 40 20 1/2 1/2 1/4 1/2 1/2 4 4 2 4 4 40 40 20 40 40

Section 4 Clock Pulse Generator (CPG) Page 74 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group FRQCR Division Ratio Setting Clock Ratio Clock Frequency (MHz) * PLL Multipli- cation Ratio Iφ B φ P φ MI φ MP φ I φ B φ P φ MI φ MP φ Input Clock Iφ B φ P φ MI φ MP φ ×8 1/2 1/2 1/2 1/2 1/2 4 4 4 4 4 10 40 40 40 40 40 1/1 1/8 1/8 1/8 1/8 8 1 1 1 1 80 10 10 10 10 1/1 1/8 1/8 1/4 1/8 8 1 1 2 1 80 10 10 20 10 1/1 1/8 1/8 1/2 1/8 8 1 1 4 1 80 10 10 40 10 1/1 1/8 1/8 1/1 1/8 8 1 1 8 1 80 10 10 80 10 1/1 1/4 1/8 1/8 1/8 8 2 1 1 1 80 20 10 10 10 1/1 1/4 1/8 1/4 1/8 8 2 1 2 1 80 20 10 20 10 1/1 1/4 1/8 1/4 1/4 8 2 1 2 2 80 20 10 20 20 1/1 1/4 1/8 1/2 1/8 8 2 1 4 1 80 20 10 40 10 1/1 1/4 1/8 1/2 1/4 8 2 1 4 2 80 20 10 40 20 1/1 1/4 1/8 1/1 1/8 8 2 1 8 1 80 20 10 80 10 1/1 1/4 1/8 1/1 1/4 8 2 1 8 2 80 20 10 80 20 1/1 1/4 1/4 1/4 1/4 8 2 2 2 2 80 20 20 20 20 1/1 1/4 1/4 1/2 1/4 8 2 2 4 2 80 20 20 40 20 1/1 1/4 1/4 1/1 1/4 8 2 2 8 2 80 20 20 80 20 1/1 1/3 1/3 1/3 1/3 8 8/3 8/3 8/3 8/3 80 26 26 26 26 1/1 1/3 1/3 1/1 1/3 8 8/3 8/3 8 8/3 80 26 26 80 26 1/1 1/2 1/8 1/8 1/8 8 4 1 1 1 80 40 10 10 10 1/1 1/2 1/8 1/4 1/8 8 4 1 2 1 80 40 10 20 10 1/1 1/2 1/8 1/4 1/4 8 4 1 2 2 80 40 10 20 20 1/1 1/2 1/8 1/2 1/8 8 4 1 4 1 80 40 10 40 10 1/1 1/2 1/8 1/2 1/4 8 4 1 4 2 80 40 10 40 20 1/1 1/2 1/8 1/2 1/2 8 4 1 4 4 80 40 10 40 40 1/1 1/2 1/8 1/1 1/8 8 4 1 8 1 80 40 10 80 10 1/1 1/2 1/8 1/1 1/4 8 4 1 8 2 80 40 10 80 20 1/1 1/2 1/8 1/1 1/2 8 4 1 8 4 80 40 10 80 40 1/1 1/2 1/4 1/4 1/4 8 4 2 2 2 80 40 20 20 20 1/1 1/2 1/4 1/2 1/4 8 4 2 4 2 80 40 20 40 20

Section 4 Clock Pulse Generator (CPG) R01UH0198EJ0500 Rev. 5.00 Page 75 of 1560 Mar 18, 2011 SH7080 Group FRQCR Division Ratio Setting Clock Ratio Clock Frequency (MHz) * PLL Multipli- cation Ratio Iφ B φ P φ MI φ MP φ I φ B φ P φ MI φ MP φ Input Clock Iφ B φ P φ MI φ MP φ ×8 1/1 1/2 1/4 1/2 1/2 8 4 2 4 4 10 80 40 20 40 40 1/1 1/2 1/4 1/1 1/4 8 4 2 8 2 80 40 20 80 20 1/1 1/2 1/4 1/1 1/2 8 4 2 8 4 80 40 20 80 40 1/1 1/2 1/2 1/2 1/2 8 4 4 4 4 80 40 40 40 40 1/1 1/2 1/2 1/1 1/2 8 4 4 8 4 80 40 40 80 40 1/1 1/1 1/4 1/4 1/4 8 8 2 2 2 5 40 40 10 10 10 1/1 1/1 1/4 1/2 1/4 8 8 2 4 2 40 40 10 20 10 1/1 1/1 1/4 1/2 1/2 8 8 2 4 4 40 40 10 20 20 1/1 1/1 1/4 1/1 1/4 8 8 2 8 2 40 40 10 40 10 1/1 1/1 1/4 1/1 1/2 8 8 2 8 4 40 40 10 40 20 1/1 1/1 1/4 1/1 1/1 8 8 2 8 8 40 40 10 40 40 1/1 1/1 1/3 1/3 1/3 8 8 8/3 8/3 8/3 40 40 13 13 13 1/1 1/1 1/3 1/1 1/3 8 8 8/3 8 8/3 40 40 13 40 13 1/1 1/1 1/3 1/1 1/1 8 8 8/3 8 8 40 40 13 40 40 1/1 1/1 1/2 1/2 1/2 8 8 4 4 4 40 40 20 20 20 1/1 1/1 1/2 1/1 1/2 8 8 4 8 4 40 40 20 40 20 1/1 1/1 1/2 1/1 1/1 8 8 4 8 8 40 40 20 40 40 1/1 1/1 1/1 1/1 1/1 8 8 8 8 8 40 40 40 40 40

Section 4 Clock Pulse Generator (CPG) Page 76 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Notes: * Clock frequencies when the input clock frequency is assumed to be the shown value. 1. The PLL multiplication ratio is fixed at ×8. The division ratio can be selected from ×1, ×1/2, ×1/3, ×1/4, and ×1/8 for each clock by the setting in the frequency control register. 2. The output frequency of the PLL circuit is the product of the frequency of the input from the crystal resonator or EXTAL pin and the multiplication ratio (×8) of the PLL circuit. 3. The input to the divider is always the output from the PLL circuit. 4. The internal clock (I φ) frequency is the product of the frequency of the input from the crystal resonator or EXTAL pin, the multiplication ratio (×8) of the PLL circuit, and the division ratio of the divider. The resultant frequency must be a maximum of 80 MHz (maximum operating frequency). 5. The bus clock (B φ) frequency is the product of the frequency of the input from the crystal resonator or EXTAL pin, the multiplication ratio (×8) of the PLL circuit, and the division ratio of the divider. The resultant frequency must be a maximum of 40 MHz and equal to or lower than the internal clock (Iφ) frequency. 6. The peripheral clock (P φ) frequency is the product of the frequency of the input from the crystal resonator or EXTAL pin, the multiplication ratio (×8) of the PLL circuit, and the division ratio of the divider. The resultant frequency must be a maximum of 40 MHz and equal to or lower than the bus clock (Bφ) frequency. 7. When using the MTU2S and MTU2, the MTU2S clock (MI φ) frequency must be equal to or lower than the internal clock (Iφ) frequency and equal to or higher than the MTU2 clock (MPφ) frequency. The MTU2 clock (MPφ) frequency must be equal to or lower than the MTU2S clock (MIφ) frequency and the bus clock (Bφ) frequency and equal to or higher than the peripheral clock frequency (Pφ). The MTU2S clock (MIφ) frequency and MTU2 clock (MPφ) frequency are the product of the frequency of the input from the crystal resonator or EXTAL pin, the multiplication ratio (×8) of the PLL circuit, and the division ratio of the divider. 8. The frequency of the CK pin is always be equal to the bus clock (B φ) frequency.

Section 4 Clock Pulse Generator (CPG) R01UH0198EJ0500 Rev. 5.00 Page 77 of 1560 Mar 18, 2011 SH7080 Group

4.4 Register Descriptions

The CPG has the following registers. For details on the addresses of these registers and the states of these registers in each processing state, see section 27, List of Registers. Table 4.5 Register Configuration Register Name Abbrevia- tion R/W Initial Value Address Access Size Frequency control register FRQCR R/W H'36DB H'FFFFE800 16 Oscillation stop detection control register OSCCR R/W H'00 H'FFFFE814 8

4.4.1 Frequency Control Register (FRQCR)

FRQCR is a 16-bit readable/writable register that specifies the frequency division ratios for the internal clock (Iφ), bus clock (Bφ), peripheral clock (Pφ), MTU2S clock (MIφ), and MTU2 clock (MPφ). FRQCR can be accessed only in words. FRQCR is initialized to H'36DB only by a power-on reset (except a power-on reset due to a WDT overflow). 1 5 1 4 1 3 1 2 1 1 1 0 9876543210Bit: Initial value: R/W: 0011011011011011 R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W - IFC[2:0] BFC[2:0] PFC[2:0] MIFC[2:0] MPFC[2:0]

Section 4 Clock Pulse Generator (CPG) Page 78 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description 15 ⎯ 0 R Reserved This bit is always read as 0. The write value should always be 0. 14 to 12 IFC[2:0] 011 R/W Internal Clock (I φ) Frequency Division Ratio Specify the division ratio of the internal clock (Iφ) frequency with respect to the output frequency of PLL circuit. If a prohibited value is specified, subsequent operation is not guaranteed. 000: ×1 001: ×1/2 010: ×1/3 011: ×1/4 100: ×1/8 Other than above: Setting prohibited 11 to 9 BFC[2:0] 011 R/W Bus Clock (B φ) Frequency Division Ratio Specify the division ratio of the bus clock (Bφ) frequency with respect to the output frequency of PLL circuit. If a prohibited value is specified, subsequent operation is not guaranteed. 000: ×1 001: ×1/2 010: ×1/3 011: ×1/4 100: ×1/8 Other than above: Setting prohibited

Section 4 Clock Pulse Generator (CPG) R01UH0198EJ0500 Rev. 5.00 Page 79 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description 8 to 6 PFC[2:0] 011 R/W Peripheral Clock (P φ) Frequency Division Ratio Specify the division ratio of the peripheral clock (Pφ) frequency with respect to the output frequency of PLL circuit. If a prohibited value is specified, subsequent operation is not guaranteed. 000: ×1 001: ×1/2 010: ×1/3 011: ×1/4 100: ×1/8 Other than above: Setting prohibited 5 to 3 MIFC[2:0] 011 R/W MTU2S Clock (MI φ) Frequency Division Ratio Specify the division ratio of the MTU2S clock (MIφ) frequency with respect to the output frequency of PLL circuit. If a prohibited value is specified, subsequent operation is not guaranteed. 000: ×1 001: ×1/2 010: ×1/3 011: ×1/4 100: ×1/8 Other than above: Setting prohibited 2 to 0 MPFC[2:0] 011 R/W MTU2 Clock (MP φ) Frequency Division Ratio Specify the division ratio of the MTU2 clock (MPφ) frequency with respect to the output frequency of PLL circuit. If a prohibited value is specified, subsequent operation is not guaranteed. 000: ×1 001: ×1/2 010: ×1/3 011: ×1/4 100: ×1/8 Other than above: Setting prohibited

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4.4.2 Oscillation Stop Detection Control Register (OSCCR)

OSCCR is an 8-bit readable/writable register that has an oscillation stop detection flag and selects flag status output to an external pin. OSCCR can be accessed only in bytes. 76543210Bit: Initial value: R/W: 00000000 RRRRRRR R / W ----- OSC STOP - OSC ERS Bit Bit Name Initial Value R/W Description 7 to 3 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0.

2 OSCSTOP 0 R Oscillation Stop Detection Flag

[Setting conditions]

• When a stop in the clock input is detected during normal operation
• When software standby mode is entered [Clearing conditions]
• By a power-on reset input through the RES pin
• When software standby mode is canceled 1 ⎯ 0 R Reserved This bit is always read as 0. The write value should always be 0.

0 OSCERS 0 R/W Oscillation Stop Detection Flag Output Select

Selects whether to output the oscillation stop detection flag signal through the WDTOVF pin. 0: Outputs only the WDT overflow signal through the WDTOVF pin 1: Outputs the WDT overflow signal and the oscillation stop detection flag signal through the WDTOVF pin

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4.5 Changing Frequency

Selecting division ratios for the frequency divider can change the frequencies of the internal clock (Iφ), bus clock (Bφ), peripheral clock (Pφ), MTU2S clock (MIφ), and MTU2 clock (MPφ). This is controlled by software through the frequency control register (FRQCR). The following describes how to specify the frequencies. 1. In the initial state, IFC2 to IFC0 = H'011 ( ×1/4), BFC2 to BFC0 = H'011 (×1/4), PFC2 to PFC0 = H'011 (×1/4), MIFC2 to MIFC0 = H'011 (×1/4), and MPFC2 to MPFC0 = H'011 (×1/4). 2. Stop all modules except the CPU, on-chip ROM, and on-chip RAM. 3. Set the desired values in bits IFC2 to IFC0, BFC2 to BFC0, PFC2 to PFC0, MIFC2 to MIFC0, and MPFC2 to MPFC0 bits. Since the frequency multiplication ratio in the PLL circuit is fixed at ×8, the frequencies are determined only be selecting division ratios. When specifying the frequencies, satisfy the following condition: internal clock (Iφ) ≥ bus clock (Bφ) ≥ peripheral clock (Pφ). When using the MTU2S clock and MTU2 clock, specify the frequencies to satisfy the following condition: internal clock (Iφ) ≥ MTU2S clock (MIφ) ≥ MTU2 clock (MPφ) ≥ peripheral clock (Pφ) and bus clock (Bφ) ≥ MTU2 clock (MPφ). Code to rewrite values of FRQCR should be executed in the on-chip ROM or on-chip RAM. 4. After an instruction to rewrite FRQCR has been issued, the actual clock frequencies will change after (1 to 24n) cyc + 11Bφ + 7Pφ. n: Division ratio specified by the BFC bit in FRQCR (1, 1/2, 1/3, 1/4, or 1/8) cyc: Clock obtained by dividing EXTAL by 8 with the PLL. Note: (1 to 24n) depends on the internal state.

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4.6 Oscillator

Clock pulses can be supplied from a connected crystal resonator or an external clock.

4.6.1 Connecting Crystal Resonator

A crystal resonator can be connected as shown in figure 4.2. Use the damping resistance (Rd) listed in table 4.6. Use a crystal resonator that has a resonance frequency of 5 to 12.5 MHz. It is recommended to consult the crystal resonator manufacturer concerning the compatibility of the crystal resonator and the LSI. EXTAL XTAL Rd CL2 CL1 CL1 = CL2 = 18 to 22 pF (Reference values) Figure 4.2 Connection of Crystal Resonator (Example) Table 4.6 Damping Resistan ce Values (Reference Values) Frequency (MHz) 5 8 10 12.5 Rd (Ω)(Reference values) 500 200 0 0 Figure 4.3 shows an equivalent circuit of the crystal resonator. Use a crystal resonator with the characteristics listed in table 4.7. XTAL CL EXTAL L Rs Figure 4.3 Crystal Resonator Equivalent Circuit Table 4.7 Crystal Resonator Characteristics Frequency (MHz) 5 8 10 12.5 Rs Max. (Ω) (Reference values) 120 80 60 50 C0 Max. (pF) (Reference values) 7 7 7 7

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4.6.2 External Clock Input Method

Figure 4.4 shows an example of an external clock input connection. In this case, make the external clock high level to stop it when in software standby mode. During operation, make the external input clock frequency 5 to 12.5 MHz. When leaving the XTAL pin open, make sure the parasitic capacitance is less than 10 pF. Even when inputting an external clock, be sure to wait at least the oscillation stabilization time in power-on sequence or in releasing software standby mode, in order to ensure the PLL stabilization time. EXTAL XTAL External clock input Open state Figure 4.4 Example of External Clock Connection

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4.7 Function for Detecting Oscillator Stop

This CPG detects a stop in the clock input if any system abnormality halts the clock supply. When no change has been detected in the EXTAL input for a certain period, the OSCSTOP bit in OSCCR is set to 1 and this state is retained until a power-on reset is input through the RES pin or software standby mode is canceled. If the OSCERS bit is set to 1 at this time, an oscillation stop detection flag signal is output through the WDTOVF pin. In addition, the high-current ports (pins to which the TIOC3B, TIOC3D, and TIOC4A to TIOC4D signals in the MTU2 and the TIOC3BS, TIOC3DS, and TIOC4AS to TIOC4DS signals in the MTU2S are assigned) can be placed in high- impedance state regardless of the PFC setting. For details, refer to section 21.1.11, High-Current Port Control Register (HCPCR), and appendix A, Pin States. Even in software standby mode, these pins can be placed in high-impedance state. For details, refer to section 21.1.11, High-Current Port Control Register (HCPCR), and appendix A, Pin States. These pins enter the normal state after software standby mode is canceled. Under an abnormal condition where oscillation stops while the LSI is not in software standby mode, LSI operations other than the oscillation stop detection function become unpredictable. In this case, even after oscillation is restarted, LSI operations including the above high-current pins become unpredictable. Even while no change is detected in the EXTAL input, the PLL circuit in this LSI continues oscillating at a frequency range from 100 kHz to 10 MHz (depending on the temperature and operating voltage).

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4.8 Usage Notes

4.8.1 Note on Crystal Resonator

A sufficient evaluation at the user’s site is necessary to use the LSI, by referring the resonator connection examples shown in this section, because various characteristics related to the crystal resonator are closely linked to the user’s board design. As the oscillator circuit's circuit constant will depend on the resonator and the floating capacitance of the mounting circuit, the value of each external circuit’s component should be determined in consultation with the resonator manufacturer. The design must ensure that a voltage exceeding the maximum rating is not applied to the oscillator pin.

4.8.2 Notes on Board Design

Measures against radiation noise are taken in this LSI. If further reduction in radiation noise is needed, it is recommended to use a multiple layer board and provide a layer exclusive to the system ground. When using a crystal resonator, place the crystal resonator and its load capacitors as close as possible to the XTAL and EXTAL pins. Do not route any signal lines near the oscillator circuitry as shown in figure 4.5. Otherwise, correct oscillation can be interfered by induction. CL2 Signal A Signal B This LSI CL1 XTAL EXTAL Avoid Figure 4.5 Cautions for Oscillator Circuit Board Design

Section 4 Clock Pulse Generator (CPG) Page 86 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group A circuitry shown in figure 4.6 is recommended as an external circuitry around the PLL. Separate the PLL power lines (PLLVss) and the system power lines (Vcc, Vss) at the board power supply source, and be sure to insert bypass capacitors CB and CPB close to the pins. PLLVSS VCL VCC VSS CPB = 0.47 µF* CB = 0.1 µF* (Recommended values are shown.) Note: * CB and CPB are laminated ceramic type. Figure 4.6 Recommended External Circuitry around PLL

Section 5 Exception Handling R01UH0198EJ0500 Rev. 5.00 Page 87 of 1560 Mar 18, 2011 SH7080 Group Section 5 Exception Handling

5.1 Overview

5.1.1 Types of Exception Handling and Priority

Exception handling is started by four sources: resets, address errors, interrupts and instructions and have the priority, as shown in table 5.1. When several exceptions are detected at once, they are processed according to the priority. Table 5.1 Types of Exceptions and Priority Exception Exception Source Priority Reset Power-on reset High Manual reset Interrupt User break (break before instruction execution) Address error CPU address error (instruction fetch) Instruction General illegal instructions (undefined code) Illegal slot instruction (undefined code placed immediately after a delayed branch instruction* or instruction that changes the PC value* Trap instruction (TRAPA instruction) Address error CPU address error (data access) Interrupt User break (break after instruction execution or operand break) Address error DMAC/DTC address error (data access) Interrupt NMI IRQ On-chip peripheral modules Low Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, and BRAF. 2. Instructions that change the PC value: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA, BF/S, BT/S, BSRF, BRAF, LDC Rm,SR, LDC.L @Rm+,SR.

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5.1.2 Exception Handling Operations

The exceptions are detected and the exception handling starts according to the timing shown in table 5.2. Table 5.2 Timing for Exception Detection and Start of Exception Handling Exception Timing of Source Detection and Start of Exception Handling Reset Power-on reset Started when the RES pin changes from low to high or when the WDT overflows. Manual reset Started when the MRES pin changes from low to high or when the WDT overflows. Address error Interrupt Detected during the instruction decode stage and started after the execution of the current instruction is completed. Instruction Trap instruction Started by the execution of the TRAPA instruction. General illegal instructions Started when an undefined code placed at other than a delay slot (immediately after a delayed branch instruction) is decoded. Illegal slot instructions Started when an undefined code placed at a delay slot (immediately after a delayed branch instruction) or an instruction that changes the PC value is detected. When exception handling starts, the CPU operates Exception Handling Triggered by Reset: The initial values of the program counter (PC) and stack pointer (SP) are fetched from the exception handling vector table (PC from the address H'00000000 and SP from the address H'00000004 when a power-on reset. PC from the address H'00000008 and SP from the address H'0000000C when a manual reset.). For details, see section 5.1.3, Exception Handling Vector Table. H'00000000 is then written to the vector base register (VBR), and H'F (B'1111) is written to the interrupt mask bits (I3 to I0) in the status register (SR). The program starts from the PC address fetched from the exception handling vector table. Exception Handling Triggered by Address Error, Interrupt, and Instruction: SR and PC are saved to the stack indicated by R15. For interrupt exception handling, the interrupt priority level is written to the interrupt mask bits (I3 to I0) in SR. For address error and instruction exception handling, bits I3 to I0 are not affected. The start address is then fetched from the exception handling vector table and the program starts from that address.

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5.1.3 Exception Handling Vector Table

Before exception handling starts, the exception handling vector table must be set in memory. The exception handling vector table stores the start addresses of exception handling routines. (The reset exception handling table holds the initial values of PC and SP.) All exception sources are given different vector numbers and vector table address offsets. The vector table addresses are calculated from these vector numbers and vector table address offsets. During exception handling, the start addresses of the exception handling routines are fetched from the exception handling vector table that is indicated by this vector table address. Table 5.3 shows the vector numbers and vector table address offsets. Table 5.4 shows how vector table addresses are calculated. Table 5.3 Vector Numbers and Vector Table Address Offsets Exception Handling Source Vector Number Vector Table Address Offset Power-on reset PC 0 H'00000000 to H'00000003 SP 1 H'00000004 to H'00000007 Manual reset PC 2 H'00000008 to H'0000000B SP 3 H'0000000C to H'0000000F General illegal instruction 4 H'00000010 to H'00000013 (Reserved for system use) 5 H'00000014 to H'00000017 Illegal slot instruction 6 H'00000018 to H'0000001B (Reserved for system use) 7 H'0000001C to H'0000001F

8 H'00000020 to H'00000023

CPU address error 9 H'00000024 to H'00000027 DMAC/DTC address error 10 H'00000028 to H'0000002B Interrupt NMI 11 H'0000002C to H'0000002F User break 12 H'00000030 to H'00000033 (Reserved for system use) 13 H'00000034 to H'00000037 : :

31 H'0000007C to H'0000007F

Trap instruction (user vector) 32 H'00000080 to H'00000083 : :

63 H'000000FC to H'000000FF

Section 5 Exception Handling Page 90 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Exception Handling Source Vector Number Vector Table Address Offset Interrupt IRQ0 64 H'00000100 to H'00000103 IRQ1 65 H'00000104 to H'00000107 IRQ2 66 H'00000108 to H'0000010B IRQ3 67 H'0000010C to H'0000010F IRQ4 68 H'00000110 to H'00000113 IRQ5 69 H'00000114 to H'00000117 IRQ6 70 H'00000118 to H'0000011B IRQ7 71 H'0000011C to H'0000011F On-chip peripheral module* 72 H'00000120 to H'00000123 : :

255 H'000003FC to H'000003FF

Note: * For details on the vector numbers and vector table address offsets of on-chip peripheral module interrupts, see table 6.3 in section 6, Interrupt Controller (INTC). Table 5.4 Calculating Exception Handling Vector Table Addresses Exception Source Vector Table Address Calculation Resets Vector table address = (vector table address offset) = (vector number) × 4 Address errors, interrupts, instructions Vector table address = VBR + (vector table address offset) = VBR + (vector number) × 4 Notes: 1. VBR: Vector base register 2. Vector table address offset: See table 5.3. 3. Vector number: See table 5.3.

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5.2 Resets

5.2.1 Types of Resets

Resets have priority over any exception source. There are two types of resets: power-on resets and manual resets. As table 5.5 shows, both types of resets initialize the internal status of the CPU. In power-on resets, all registers of the on-chip peripheral modules are initialized; in manual resets, they are not. Table 5.5 Reset Status Conditions for Transition to Reset State Internal State Type RES WDT Overflow MRES CPU, INTC On-Chip Peripheral Module POE, PFC, I/O Port Low ⎯ ⎯ Initialized Initialized Initialized Power-on reset High Overflow High Initialized Initialized Initialized Manual reset High Not overflowed Low Initialized Not initialized Not initialized

5.2.2 Power-On Reset

Power-On Reset by RES Pin: When the RES pin is driven low, this LSI enters the power-on reset state. To reliably reset this LSI, the RES pin should be kept low for at least the oscillation settling time when applying the power or when in standby mode (when the clock is halted) or at least 20 tcyc when the clock is operating. During the power-on reset state, CPU internal states and all registers of on-chip peripheral modules are initialized. See appendix A, Pin States, for the status of individual pins during power-on reset mode. In the power-on reset state, power-on reset exception handling starts when driving the RES pin high after driving the pin low for the given time. The CPU operates as follows: 1. The initial value (execution start address) of the program counter (PC) is fetched from the exception handling vector table. 2. The initial value of the stack pointer (SP) is fetched from the exception handling vector table. 3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3 to I0) of the status register (SR) are set to H'F (B'1111). 4. The values fetched from the exception handling vector table are set in PC and SP, then the program starts.

Section 5 Exception Handling Page 92 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Be certain to always perform power-on reset exception handling when turning the system power on. Power-On Reset by WDT: When WTCNT of the WDT overflows while a setting is made so that a power-on reset can be generated in watchdog timer mode of the WDT, this LSI enters the power-on reset state. The frequency control register (FRQCR) in the clock pulse generator (CPG) and the watchdog timer (WDT) registers are not initialized by the reset signal generated by the WDT (these registers are only initialized by a power-on reset from the RES pin). If a reset caused by the signal input on the RES pin and a reset caused by a WDT overflow occur simultaneously, the RES pin reset has priority, and the WOVF bit in WTCSR is cleared to 0. When the power-on reset exception handling caused by the WDT is started, the CPU operates as follows: 1. The initial value (execution start address) of the program counter (PC) is fetched from the exception handling vector table. 2. The initial value of the stack pointer (SP) is fetched from the exception handling vector table. 3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3 to I0) of the status register (SR) are set to H'F (B'1111). 4. The values fetched from the exception handling vector table are set in the PC and SP, then the program starts.

5.2.3 Manual Reset

When the RES pin is high and the MRES pin is driven low, the LSI becomes to be a manual reset state. To reliably reset the LSI, the MRES pin should be kept at low for at least the duration of the oscillation settling time that is set in WDT when in software standby mode (when the clock is halted) or at least 20 tcyc when the clock is operating. During manual reset, the CPU internal status is initialized. Registers of on-chip peripheral modules are not initialized. When the LSI enters manual reset status in the middle of a bus cycle, manual reset exception processing does not start until the bus cycle has ended. Thus, manual resets do not abort bus cycles. However, once MRES is driven low, hold the low level until the CPU becomes to be a manual reset mode after the bus cycle ends. (Keep at low level for at least the longest bus cycle). See appendix A, Pin States, for the status of individual pins during manual reset mode. In the manual reset status, manual reset exception processing starts when the MRES pin is first kept low for a set period of time and then returned to high. The CPU will then operate in the same procedures as described for power-on resets.

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5.3 Address Errors

5.3.1 Address Error Sources

Address errors occur when instructions are fetched or data is read from or written to, as shown in table 5.6. Table 5.6 Bus Cycles and Address Errors Bus Cycle Type Bus Master Bus Cycle Description Address Errors CPU Instruction fetched from even address None (normal) Instruction fetch Instruction fetched from odd address Address error occurs Instruction fetched from a space other than on-chip peripheral module space None (normal) Instruction fetched from on-chip peripheral module space Address error occurs Instruction fetched from external memory space in single chip mode Address error occurs Word data accessed from even address None (normal) Data read/write CPU, DMAC, or DTC Word data accessed from odd address Address error occurs Longword data accessed from a longword boundary None (normal) Longword data accessed from other than a long-word boundary Address error occurs Byte or word data accessed in on-chip peripheral module space None (normal) Longword data accessed in 16-bit on-chip peripheral module space None (normal) Longword data accessed in 8-bit on-chip peripheral module space None (normal) External memory space accessed when in single chip mode Address error occurs

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5.3.2 Address Error Exception Source

When an address error exception is generated, the bus cycle which caused the address error ends, the current instruction finishes, and then the address error exception handling starts. The CPU operates as follows: 1. The status register (SR) is saved to the stack. 2. The program counter (PC) is saved to the stack. The PC value to be saved is the start address of the instruction which caused an address error exception. When the instruction that caused the exception is placed in the delay slot, the address of the delayed branch instruction which is placed immediately before the delay slot. 3. The start address of the exception handling routine is fetched from the exception handling vector table that corresponds to the generated address error, and the program starts executing from that address. This branch is not a delayed branch.

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5.4 Interrupts

5.4.1 Interrupt Sources

Table 5.7 shows the sources that start the interrupt exception handling. They are NMI, user break, IRQ, and on-chip peripheral modules. Table 5.7 Interrupt Sources Type Request Source Number of Sources NMI NMI pin (external input) 1 User break User break controller (UBC) 1 IRQ IRQ0 to IRQ7 pins (external input) 8 On-chip peripheral module Direct memory access controller (DMAC) 8 Multi-function timer pulse unit 2 (MTU2) 28 Multi-function timer pulse unit 2S (MTU2S) 13 Data transfer controller (DTC) 1 Bus state controller (BSC) 1 Watchdog timer (WDT) 1 A/D converter (A/D_0, A/D_1, and A/D_2) 3 Compare match timer (CMT_0 and CMT_1) 2 Serial communication interface (SCI_0, SCI_1, and SCI_2) Serial communication interface with FIFO (SCIF_3) Synchronous serial communication unit (SSU) 3 Port output enable (POE) 3 I C bus interface 2 (I C2) 5 All interrupt sources are given different vector numbers and vector table address offsets. For details on vector numbers and vector table address offsets, see table 6.3 in section 6, Interrupt Controller (INTC).

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5.4.2 Interrupt Priority

The interrupt priority is predetermined. When multiple interrupts occur simultaneously (overlapped interruptions), the interrupt controller (INTC) determines their relative priorities and starts the exception handling according to the results. The priority of interrupts is expressed as priority levels 0 to 16, with priority 0 the lowest and priority 16 the highest. The NMI interrupt has priority 16 and cannot be masked, so it is always accepted. The priority level of the user break interrupt is 15. IRQ interrupt and on-chip peripheral module interrupt priority levels can be set freely using the interrupt priority registers A to F and H to M (IPRA to IPRF and IPRH to IPRM) of the INTC as shown in table 5.8. The priority levels that can be set are 0 to 15. Level 16 cannot be set. For details on IPRA to IPRF, see section 6.3.4, Interrupt Priority Registers A to F and H to M (IPRA to IPRF and IPRH to IPRM). Table 5.8 Interrupt Priority Type Priority Level Comment NMI 16 Fixed priority level. Cannot be masked. User break 15 Fixed priority level. Can be masked. IRQ 0 to 15 On-chip peripheral module Set with interrupt priority registers A to F and H to M (IPRA to IPRF and IPRH to IPRM).

5.4.3 Interrupt Exception Handling

When an interrupt occurs, the interrupt controller (INTC) ascertains its priority level. NMI is always accepted, but other interrupts are only accepted if they have a priority level higher than the priority level set in the interrupt mask bits (I3 to I0) of the status register (SR). When an interrupt is accepted, exception handling begins. In interrupt exception handling, the CPU saves SR and the program counter (PC) to the stack. The priority level of the accepted interrupt is written to bits I3 to I0 in SR. Although the priority level of the NMI is 16, the value set in bits I3 to I0 is H'F (level 15). Next, the start address of the exception handling routine is fetched from the exception handling vector table for the accepted interrupt, and program execution branches to that address and the program starts. For details on the interrupt exception handling, see section 6.6, Interrupt Operation.

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5.5 Exceptions Triggered by Instructions

5.5.1 Types of Exceptions Triggered by Instructions

Exception handling can be triggered by the trap instruction, illegal slot instructions, and general illegal instructions, as shown in table 5.9. Table 5.9 Types of Exceptions Triggered by Instructions Type Source Instruction Comment Trap instruction TRAPA ⎯ Illegal slot instructions* Undefined code placed immediately after a delayed branch instruction (delay slot) or instructions that changes the PC value Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF Instructions that changes the PC value: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA, BF/S, BT/S, BSRF, BRAF, LDC Rm,SR, LDC.L @Rm+,SR General illegal instructions* Undefined code anywhere besides in a delay slot Note: * The operation is not guaranteed when und efined instructions other than H'F000 to H'FFFF are decoded.

5.5.2 Trap Instructions

When a TRAPA instruction is executed, the trap instruction exception handling starts. The CPU operates as follows: 1. The status register (SR) is saved to the stack. 2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the TRAPA instruction. 3. The CPU reads the start addr ess of the exception handling routine from the exception handling vector table that corresponds to the vector number specified in the TRAPA instruction, program execution branches to that address, and then the program starts. This branch is not a delayed branch.

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5.5.3 Illegal Slot Instructions

An instruction placed immediately after a delayed branch instruction is called "instruction placed in a delay slot". When the instruction placed in the delay slot is an undefined code, illegal slot exception handling starts after the undefined code is decoded. Illegal slot exception handling also starts when an instruction that changes the program counter (PC) value is placed in a delay slot and the instruction is decoded. The CPU handles an illegal slot instruction as follows: 1. The status register (SR) is saved to the stack. 2. The program counter (PC) is saved to the stack. The PC value saved is the target address of the delayed branch instruction immediately before the undefined code or the instruction that rewrites the PC. 3. The start address of the exception handling routine is fetched from the exception handling vector table that corresponds to the exception that occurred. Program execution branches to that address and the program starts. This branch is not a delayed branch.

5.5.4 General Illegal Instructions

When an undefined code placed anywhere other than immediately after a delayed branch instruction (i.e., in a delay slot) is decoded, general illegal instruction exception handling starts. The CPU handles the general illegal instructions in the same procedures as in the illegal slot instructions. Unlike processing of illegal slot instructions, however, the program counter value that is stacked is the start address of the undefined code.

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5.6 Cases when Exceptions Are Accepted

When an exception other than resets occurs during decoding the instruction placed in a delay slot or immediately after an interrupt disabled instruction, it may not be accepted and be held shown in table 5.10. In this case, when an instruction which accepts an interrupt request is decoded, the exception is accepted. Table 5.10 Delay Slot Instructions, Interrupt Disabled Instructions, and Exceptions Exception Occurrence Timing Address Error General Illegal Instruction Slot Illegal Instruction Trap Instruction Interrupt Instruction in delay slot ×* ⎯ ×* ⎯ ×* Immediately after interrupt disabled instruction* [Legend] √: Accepted ×: Not accepted ⎯: Does not occur 2. An exception is accepted before the execution of a delayed branch instruction. However, when an address error or a slot illegal instruction exception occurs in the delay slot of the RTE instruction, correct operation is not guaranteed. 3. An exception is accepted after a delayed branch (between instructions in the delay slot and the branch destination). 4. An exception is accepted after the execution of the next instruction of an interrupt disabled instruction (before the execution two instructions after an interrupt disabled instruction).

Section 5 Exception Handling Page 100 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

5.7 Stack States after Exception Handling Ends

The stack states after exception handling ends are shown in table 5.11. Table 5.11 Stack Status after Exception Handling Ends Types Stack State Address error (when the instruction that caused an exception is placed in the delay slot) SP Address of delayed branch instruction SR → 32 bits 32 bits Address error (other than above) SP SR → 32 bits 32 bits Address of instruction that caused exception Interrupt SP SR → 32 bits 32 bits Address of instruction after executed instruction Trap instruction SP SR → 32 bits 32 bits Address of instruction after TRAPA instruction

Section 5 Exception Handling R01UH0198EJ0500 Rev. 5.00 Page 101 of 1560 Mar 18, 2011 SH7080 Group Types Stack State Illegal slot instruction SP Address of delayed branch instruction SR → 32 bits 32 bits General illegal instruction SP SR → 32 bits 32 bits Start address of general illegal instruction

Section 5 Exception Handling Page 102 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

5.8 Usage Notes

5.8.1 Value of Stack Pointer (SP)

The SP value must always be a multiple of 4. If it is not, an address error will occur when the stack is accessed during exception handling.

5.8.2 Value of Vector Base Register (VBR)

The VBR value must always be a multiple of 4. If it is not, an address error will occur when the stack is accessed during exception handling.

5.8.3 Address Errors Caused by Stacking for Address Error Exception Handling

When the SP value is not a multiple of 4, an address error will occur when stacking for exception handling (interrupts, etc.) and address error exception handling will start after the first exception handling is ended. Address errors will also occur in the stacking for this address error exception handling. To ensure that address error exception handling does not go into an endless loop, no address errors are accepted at that point. This allows program control to be passed to the handling routine for address error exception and enables error processing. When an address error occurs during exception handling stacking, the stacking bus cycle (write) is executed. When stacking the SR and PC values, the SP values for both are subtracted by 4, therefore, the SP value is still not a multiple of 4 after the stacking. The address value output during stacking is the SP value whose lower two bits are cleared to 0. So the write data stacked is undefined.

Section 5 Exception Handling R01UH0198EJ0500 Rev. 5.00 Page 103 of 1560 Mar 18, 2011 SH7080 Group

5.8.4 Notes on Slot Illegal Instruction Exception Handling

Some specifications on slot illegal instruction exception handling in this LSI differ from those of the conventional SH-2.

• Conventional SH-2: Instructions LDC Rm,SR and LDC.L @Rm+,SR are not subject to the slot illegal instructions.
• This LSI: Instructions LDC Rm,SR and LDC.L @Rm+,SR are subject to the slot illegal instructions. The supporting status on our software products regarding this note is as follows: Compiler This instruction is not allocated in the delay slot in the compiler V.4 and its subsequent versions. Real-time OS for μITRON specifications 1. HI7000/4, HI-SH7 This instruction does not exist in the delay slot within the OS. 2. HI7000 This instruction is in part allocated to the delay slot within the OS, which may cause the slot illegal instruction exception handling in this LSI. 3. Others The slot illegal instruction exception handling may be generated in this LSI in a case where the instruction is described in assembler or when the middleware of the object is introduced. Note that a check-up program (checker) to pick up this instruction is available on our website. Download and utilize this checker as needed.

Section 5 Exception Handling Page 104 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

Section 6 Interrupt Controller (INTC) R01UH0198EJ0500 Rev. 5.00 Page 105 of 1560 Mar 18, 2011 SH7080 Group Section 6 Interrupt Controller (INTC) The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU.

6.1 Features

• 16 levels of interrupt priority
• NMI noise canceller function
• Occurrence of interrupt can be reported externally (IRQOUT pin)

Section 6 Interrupt Controller (INTC) R01UH0198EJ0500 Rev. 5.00 Page 107 of 1560 Mar 18, 2011 SH7080 Group

6.2 Input/Output Pins

Table 6.1 shows the INTC pin configuration. Table 6.1 Pin Configuration Pin Name Symbol I/O Function Non-maskable interrupt input pin NMI Input Input of non-maskable interrupt request signal Interrupt request input pins IRQ0 to IRQ7 Input Input of maskable interrupt request signals Interrupt request output pin IRQOUT Output Output of notification signal when an interrupt has occurred

Section 6 Interrupt Controller (INTC) Page 108 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

6.3 Register Descriptions

The interrupt controller has the following registers. For details on the addresses of these registers and the states of these registers in each processing state, see section 27, List of Registers. Table 6.2 Register Configuration Register Name Abbrevia- tion R/W Initial Value Address Access Size Interrupt control register 0 ICR0 R/W H'x000 H'FFFFE900 8, 16 IRQ control register IRQCR R/W H'0000 H'FFFFE902 8, 16 IRQ status register IRQSR R/W H'xx00 H'FFFFE904 8, 16 Interrupt priority register A IPRA R/W H'0000 H'FFFFE906 8, 16 Interrupt priority register B IPRB R/W H'0000 H'FFFFE908 8, 16 Interrupt priority register C IPRC R/W H'0000 H'FFFFE980 16 Interrupt priority register D IPRD R/W H'0000 H'FFFFE982 16 Interrupt priority register E IPRE R/W H'0000 H'FFFFE984 16 Interrupt priority register F IPRF R/W H'0000 H'FFFFE986 16 Interrupt priority register H IPRH R/W H'0000 H'FFFFE98A 16 Interrupt priority register I IPRI R/W H'0000 H'FFFFE98C 16 Interrupt priority register J IPRJ R/W H'0000 H'FFFFE98E 16 Interrupt priority register K IPRK R/W H'0000 H'FFFFE990 16 Interrupt priority register L IPRL R/W H'0000 H'FFFFE992 16 Interrupt priority register M IPRM R/W H'0000 H'FFFFE994 16

Section 6 Interrupt Controller (INTC) R01UH0198EJ0500 Rev. 5.00 Page 109 of 1560 Mar 18, 2011 SH7080 Group

6.3.1 Interrupt Control Register 0 (ICR0)

ICR0 is a 16-bit register that sets the input signal detection mode of the external interrupt input pin NMI and indicates the input signal level on the NMI pin. Bit: Initial value: R/W: 15 14 13 12 11 10 9 87654321 0 Note: The initial value is 1 when the level on the NMI pin is high, and 0 when the level on the pin is low.* * 000000000000000 RRRRRRR R / W RRRRRRRR Bit Bit Name Initial Value R/W Description

15 NMIL * R NMI Input Level

Indicates the state of the signal input to the NMI pin. This bit can be read to determine the NMI pin level. This bit cannot be modified. 0: State of the NMI input is low 1: State of the NMI input is high 14 to 9 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0.

8 NMIE 0 R/W NMI Edge Select

0: Interrupt request is detected on the falling edge of the NMI input 1: Interrupt request is detected on the rising edge of the NMI input 7 to 0 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 6 Interrupt Controller (INTC) Page 110 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

6.3.2 IRQ Control Register (IRQCR)

IRQCR is a 16-bit register that sets the input signal detection mode of the external interrupt input pins IRQ0 to IRQ7. Bit: Initial value: R/W: 15 14 13 12 11 10 9 87654321 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W IRQ71S IRQ70S IRQ61S IRQ60S IRQ51S IRQ50S IRQ41S IRQ40S IRQ31S IRQ30S IRQ21S IRQ20S IRQ11S IRQ10S IRQ01S IRQ00S Bit Bit Name Initial Value R/W Description IRQ71S IRQ70S R/W R/W IRQ7 Sense Select Set the interrupt request detection mode for pin IRQ7. 00: Interrupt request is detected at the low level of pin IRQ7 01: Interrupt request is detected at the falling edge of pin IRQ7 10: Interrupt request is detected at the rising edge of pin IRQ7 11: Interrupt request is detected at both the falling and rising edges of pin IRQ7 IRQ61S IRQ60S R/W R/W IRQ6 Sense Select Set the interrupt request detection mode for pin IRQ6. 00: Interrupt request is detected at the low level of pin IRQ6 01: Interrupt request is detected at the falling edge of pin IRQ6 10: Interrupt request is detected at the rising edge of pin IRQ6 11: Interrupt request is detected at both the falling and rising edges of pin IRQ6

Section 6 Interrupt Controller (INTC) R01UH0198EJ0500 Rev. 5.00 Page 111 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description IRQ51S IRQ50S R/W R/W IRQ5 Sense Select Set the interrupt request detection mode for pin IRQ5. 00: Interrupt request is detected at the low level of pin IRQ5 01: Interrupt request is detected at the falling edge of pin IRQ5 10: Interrupt request is detected at the rising edge of pin IRQ5 11: Interrupt request is detected at both the falling and rising edges of pin IRQ5 IRQ41S IRQ40S R/W R/W IRQ4 Sense Select Set the interrupt request detection mode for pin IRQ4. 00: Interrupt request is detected at the low level of pin IRQ4 01: Interrupt request is detected at the falling edge of pin IRQ4 10: Interrupt request is detected at the rising edge of pin IRQ4 11: Interrupt request is detected at both the falling and rising edges of pin IRQ4 IRQ31S IRQ30S R/W R/W IRQ3 Sense Select Set the interrupt request detection mode for pin IRQ3. 00: Interrupt request is detected at the low level of pin IRQ3 01: Interrupt request is detected at the falling edge of pin IRQ3 10: Interrupt request is detected at the rising edge of pin IRQ3 11: Interrupt request is detected at both the falling and rising edges of pin IRQ3

Section 6 Interrupt Controller (INTC) Page 112 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description IRQ21S IRQ20S R/W R/W IRQ2 Sense Select Set the interrupt request detection mode for pin IRQ2. 00: Interrupt request is detected at the low level of pin IRQ2 01: Interrupt request is detected at the falling edge of pin IRQ2 10: Interrupt request is detected at the rising edge of pin IRQ2 11: Interrupt request is detected at both the falling and rising edges of pin IRQ2 IRQ11S IRQ10S R/W R/W IRQ1 Sense Select Set the interrupt request detection mode for pin IRQ1. 00: Interrupt request is detected at the low level of pin IRQ1 01: Interrupt request is detected at the falling edge of pin IRQ1 10: Interrupt request is detected at the rising edge of pin IRQ1 11: Interrupt request is detected at both the falling and rising edges of pin IRQ1 IRQ01S IRQ00S R/W R/W IRQ0 Sense Select Set the interrupt request detection mode for pin IRQ0. 00: Interrupt request is detected at the low level of pin IRQ0 01: Interrupt request is detected at the falling edge of pin IRQ0 10: Interrupt request is detected at the rising edge of pin IRQ0 11: Interrupt request is detected at both the falling and rising edges of pin IRQ0

Section 6 Interrupt Controller (INTC) R01UH0198EJ0500 Rev. 5.00 Page 113 of 1560 Mar 18, 2011 SH7080 Group

6.3.3 IRQ Status register (IRQSR)

IRQSR is a 16-bit register that indicates the states of the external interrupt input pins IRQ0 to IRQ7 and the status of interrupt request. Bit: Initial value: R/W: 15 14 13 12 11 10 9 87654321 0 RRRRRRRR R / W R / W R / W R / W R / W R / W R / W R / W Note: The initial value is 1 when the level on the corresponding IRQ pin is high, and 0 when the level on the pin is low.* IRQ7L IRQ6L IRQ5L IRQ4L IRQ3L IRQ2L IRQ1L IRQ0L IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Bit Bit Name Initial Value R/W Description 15 IRQ7L * R Indicates the state of pin IRQ7. 0: State of pin IRQ7 is low 1: State of pin IRQ7 is high 14 IRQ6L * R Indicates the state of pin IRQ6. 0: State of pin IRQ6 is low 1: State of pin IRQ6 is high 13 IRQ5L * R Indicates the state of pin IRQ5. 0: State of pin IRQ5 is low 1: State of pin IRQ5 is high 12 IRQ4L * R Indicates the state of pin IRQ4. 0: State of pin IRQ4 is low 1: State of pin IRQ4 is high 11 IRQ3L * R Indicates the state of pin IRQ3. 0: State of pin IRQ3 is low 1: State of pin IRQ3 is high 10 IRQ2L * R Indicates the state of pin IRQ2. 0: State of pin IRQ2 is low 1: State of pin IRQ2 is high 9 IRQ1L * R Indicates the state of pin IRQ1. 0: State of pin IRQ1 is low 1: State of pin IRQ1 is high

Section 6 Interrupt Controller (INTC) Page 114 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description 8 IRQ0L * R Indicates the state of pin IRQ0. 0: State of pin IRQ0 is low 1: State of pin IRQ0 is high 7 IRQ7F 0 R/W Indicates the status of an IRQ7 interrupt request.

• When level detection mode is selected 0: An IRQ7 interrupt has not been detected [Clearing condition] Driving pin IRQ7 high 1: An IRQ7 interrupt has been detected [Setting condition] Driving pin IRQ7 low
• When edge detection mode is selected 0: An IRQ7 interrupt has not been detected [Clearing conditions] ⎯ Writing 0 after reading IRQ7F = 1 ⎯ Accepting an IRQ7 interrupt 1: An IRQ7 interrupt request has been detected [Setting condition] Detecting the specified edge of pin IRQ7

Section 6 Interrupt Controller (INTC) R01UH0198EJ0500 Rev. 5.00 Page 115 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description 6 IRQ6F 0 R/W Indicates the status of an IRQ6 interrupt request.

• When level detection mode is selected 0: An IRQ6 interrupt has not been detected [Clearing condition] Driving pin IRQ6 high 1: An IRQ6 interrupt has been detected [Setting condition] Driving pin IRQ6 low
• When edge detection mode is selected 0: An IRQ6 interrupt has not been detected [Clearing conditions] ⎯ Writing 0 after reading IRQ6F = 1 ⎯ Accepting an IRQ6 interrupt 1: An IRQ6 interrupt request has been detected [Setting condition] Detecting the specified edge of pin IRQ6 5 IRQ5F 0 R/W Indicates the status of an IRQ5 interrupt request.
• When level detection mode is selected 0: An IRQ5 interrupt has not been detected [Clearing condition] Driving pin IRQ5 high 1: An IRQ5 interrupt has been detected [Setting condition] Driving pin IRQ5 low
• When edge detection mode is selected 0: An IRQ5 interrupt has not been detected [Clearing conditions] ⎯ Writing 0 after reading IRQ5F = 1 ⎯ Accepting an IRQ5 interrupt 1: An IRQ5 interrupt request has been detected [Setting condition] Detecting the specified edge of pin IRQ5

Section 6 Interrupt Controller (INTC) Page 116 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description 4 IRQ4F 0 R/W Indicates the status of an IRQ4 interrupt request.

• When level detection mode is selected 0: An IRQ4 interrupt has not been detected [Clearing condition] Driving pin IRQ4 high 1: An IRQ4 interrupt has been detected [Setting condition] Driving pin IRQ4 low
• When edge detection mode is selected 0: An IRQ4 interrupt has not been detected [Clearing conditions] ⎯ Writing 0 after reading IRQ4F = 1 ⎯ Accepting an IRQ4 interrupt 1: An IRQ4 interrupt request has been detected [Setting condition] Detecting the specified edge of pin IRQ4 3 IRQ3F 0 R/W Indicates the status of an IRQ3 interrupt request.
• When level detection mode is selected 0: An IRQ3 interrupt has not been detected [Clearing condition] Driving pin IRQ3 high 1: An IRQ3 interrupt has been detected [Setting condition] Driving pin IRQ3 low
• When edge detection mode is selected 0: An IRQ3 interrupt has not been detected [Clearing conditions] ⎯ Writing 0 after reading IRQ3F = 1 ⎯ Accepting an IRQ3 interrupt 1: An IRQ3 interrupt request has been detected [Setting condition] Detecting the specified edge of pin IRQ3

Section 6 Interrupt Controller (INTC) R01UH0198EJ0500 Rev. 5.00 Page 117 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description 2 IRQ2F 0 R/W Indicates the status of an IRQ2 interrupt request.

• When level detection mode is selected 0: An IRQ2 interrupt has not been detected [Clearing condition] Driving pin IRQ2 high 1: An IRQ2 interrupt has been detected [Setting condition] Driving pin IRQ2 low
• When edge detection mode is selected 0: An IRQ2 interrupt has not been detected [Clearing conditions] ⎯ Writing 0 after reading IRQ2F = 1 ⎯ Accepting an IRQ2 interrupt 1: An IRQ2 interrupt request has been detected [Setting condition] Detecting the specified edge of pin IRQ2 1 IRQ1F 0 R/W Indicates the status of an IRQ1 interrupt request.
• When level detection mode is selected 0: An IRQ1 interrupt has not been detected [Clearing condition] Driving pin IRQ1 high 1: An IRQ1 interrupt has been detected [Setting condition] Driving pin IRQ1 low
• When edge detection mode is selected 0: An IRQ1 interrupt has not been detected [Clearing conditions] ⎯ Writing 0 after reading IRQ1F = 1 ⎯ Accepting an IRQ1 interrupt 1: An IRQ1 interrupt request has been detected [Setting condition] Detecting the specified edge of pin IRQ1

Section 6 Interrupt Controller (INTC) Page 118 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description 0 IRQ0F 0 R/W Indicates the status of an IRQ0 interrupt request.

• When level detection mode is selected 0: An IRQ0 interrupt has not been detected [Clearing condition] Driving pin IRQ0 high 1: An IRQ0 interrupt has been detected [Setting condition] Driving pin IRQ0 low
• When edge detection mode is selected 0: An IRQ0 interrupt has not been detected [Clearing conditions] ⎯ Writing 0 after reading IRQ0F = 1 ⎯ Accepting an IRQ0 interrupt 1: An IRQ0 interrupt request has been detected [Setting condition] Detecting the specified edge of pin IRQ0 Note: * The initial value is 1 when the level on the corresponding IRQ pin is high, and 0 when the level on the pin is low.

6.3.4 Interrupt Priority Registers A to F and H to M (IPRA to IPRF and IPRH to

IPRM) Interrupt priority registers are thirteen 16-bit readable/writable registers that set priority levels from 0 to 15 for interrupts except NMI. For the correspondence between interrupt request sources and IPR, refer to table 6.3. Each of the corresponding interrupt priority ranks are established by setting a value from H'0 to H'F in each of the four-bit groups 15 to 12, 11 to 8, 7 to 4 and 3 to 0. Reserved bits that are not assigned should be set H'0 (B'0000). Bit: Initial value: R/W: 15 14 13 12 11 10 9 87654321 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W IPR[15:12] IPR[11:8] IPR[7:4] IPR[3:0]

Section 6 Interrupt Controller (INTC) R01UH0198EJ0500 Rev. 5.00 Page 119 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description 15 to 12 IPR[15:12] 0000 R/W Set priority levels for the corresponding interrupt source. 0000: Priority level 0 (lowest) 0001: Priority level 1 0010: Priority level 2 0011: Priority level 3 0100: Priority level 4 0101: Priority level 5 0110: Priority level 6 0111: Priority level 7 1000: Priority level 8 1001: Priority level 9 1010: Priority level 10 1011: Priority level 11 1100: Priority level 12 1101: Priority level 13 1110: Priority level 14 1111: Priority level 15 (highest) 11 to 8 IPR[11:8] 0000 R/W Set priority levels for the corresponding interrupt source. 0000: Priority level 0 (lowest) 0001: Priority level 1 0010: Priority level 2 0011: Priority level 3 0100: Priority level 4 0101: Priority level 5 0110: Priority level 6 0111: Priority level 7 1000: Priority level 8 1001: Priority level 9 1010: Priority level 10 1011: Priority level 11 1100: Priority level 12 1101: Priority level 13 1110: Priority level 14 1111: Priority level 15 (highest)

Section 6 Interrupt Controller (INTC) Page 120 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description 7 to 4 IPR[7:4] 0000 R/W Set priority levels for the corresponding interrupt source. 0000: Priority level 0 (lowest) 0001: Priority level 1 0010: Priority level 2 0011: Priority level 3 0100: Priority level 4 0101: Priority level 5 0110: Priority level 6 0111: Priority level 7 1000: Priority level 8 1001: Priority level 9 1010: Priority level 10 1011: Priority level 11 1100: Priority level 12 1101: Priority level 13 1110: Priority level 14 1111: Priority level 15 (highest) 3 to 0 IPR[3:0] 0000 R/W Set priority levels for the corresponding interrupt source. 0000: Priority level 0 (lowest) 0001: Priority level 1 0010: Priority level 2 0011: Priority level 3 0100: Priority level 4 0101: Priority level 5 0110: Priority level 6 0111: Priority level 7 1000: Priority level 8 1001: Priority level 9 1010: Priority level 10 1011: Priority level 11 1100: Priority level 12 1101: Priority level 13 1110: Priority level 14 1111: Priority level 15 (highest) Note: Name in the tables above is represented by a general name. Name in the list of register is, on the other hand, represented by a module name.

Section 6 Interrupt Controller (INTC) R01UH0198EJ0500 Rev. 5.00 Page 121 of 1560 Mar 18, 2011 SH7080 Group

6.4 Interrupt Sources

6.4.1 External Interrupts

There are four types of interrupt sources: User break, NMI, IRQ, and on-chip peripheral modules. Individual interrupts are given priority levels (0 to 16, with 0 the lowest and 16 the highest). Giving an interrupt a priority level of 0 masks it. NMI Interrupt: The NMI interrupt is given a priority level of 16 and is always accepted. An NMI interrupt is detected at the edge of the pins. Use the NMI edge select bit (NMIE) in interrupt control register 0 (ICR0) to select either the rising or falling edge. In the NMI interrupt exception handler, the interrupt mask level bits (I3 to I0) in the status register (SR) are set to level 15. IRQ7 to IRQ0 Interrupts: IRQ interrupts are requested by input from pins IRQ0 to IRQ7. Use the IRQ sense select bits (IRQ71S to IRQ 01S and IRQ70S to IRQ00S) in the IRQ control register (IRQCR) to select the detection mode from low level detection, falling edge detection, rising edge detection, and both edge detection for each pin. The priority level can be set from 0 to 15 for each pin using the interrupt priority registers A and B (IPRA and IPRB). In the case that the low level detection is selected, an interrupt request signal is sent to the INTC while the IRQ pin is driven low. The interrupt request signal stops to be sent to the INTC when the IRQ pin becomes high. It is possible to confirm that an interrupt is requested by reading the IRQ flags (IRQ7F to IRQ0F) in the IRQ status register (IRQSR). In the case that the edge detection is selected, an interrupt request signal is sent to the INTC when the following change on the IRQ pin is detected: from high to low in falling edge detection mode, from low to high in rising edge detection mode, and from low to high or from high to low in both edge detection mode. The IRQ interrupt request by detecting the change on the pin is held until the interrupt request is accepted. It is possible to confirm that an IRQ interrupt request has been detected by reading the IRQ flags (IRQ7F to IRQ0F) in the IRQ status register (IRQSR). An IRQ interrupt request by detecting the change on the pin can be withdrawn by writing 0 to an IRQ flag after reading 1. In the IRQ interrupt exception handling, the interrupt mask bits (I3 to I0) in the status register (SR) are set to the priority level value of the accepted IRQ interrupt. Figure 6.2 shows the block diagram of the IRQ7 to IRQ0 interrupts.

Section 6 Interrupt Controller (INTC) Page 122 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group IRQCR.IRQn1S IRQCR.IRQn0S IRQSR.IRQnF IRQSR.IRQnL IRQn pins RESIRQn Level detection Edge detection SQ R Selection DTC activation request CPU interrupt request (Acceptance of IRQn interrupt/ writing 0 after reading IRQnF = 1) n = 7 to 0 Distribution Figure 6.2 Block Diagram of IRQ7 to IRQ0 Interrupts Control

6.4.2 On-Chip Peripheral Module Interrupts

On-chip peripheral module interrupts are interrupts generated by the following on-chip peripheral modules. Since a different interrupt vector is allocated to each interrupt source, the exception handling routine does not have to decide which interrupt has occurred. Priority levels between 0 and 15 can be allocated to individual on-chip peripheral modules in interrupt priority registers C to F and H to M (IPRC to IPRF and IPRH to IPRM). On-chip peripheral module interrupt exception handling sets the interrupt mask level bits (I3 to I0) in the status register (SR) to the priority level value of the on-chip peripheral module interrupt that was accepted.

6.4.3 User Break Interrupt

A user break interrupt has a priority level of 15, and occurs when the break condition set in the user break controller (UBC) is satisfied. User break interrupt requests are detected by edge and are held until accepted. User break interrupt exception handling sets the interrupt mask level bits (I3 to I0) in the status register (SR) to level 15. For more details on the user break interrupt, see section 7, User Break Controller (UBC).

Section 6 Interrupt Controller (INTC) R01UH0198EJ0500 Rev. 5.00 Page 123 of 1560 Mar 18, 2011 SH7080 Group

6.5 Interrupt Exception Handling Vector Table

Table 6.3 lists interrupt sources, their vector numbers, vector table address offsets, and interrupt priorities. Individual interrupt sources are allocated to different vector numbers and vector table address offsets. Vector table addresses are calculated from the vector numbers and vector table address offsets. For interrupt exception handling, the start address of the exception handling routine is fetched from the vector table address in the vector table. For the details on calculation of vector table addresses, see table 5.4 in section 5, Exception Handling. IRQ interrupts and on-chip peripheral module interrupt priorities can be set freely between 0 and 15 for each pin or module by setting interrupt priority registers A to F and H to M (IPRA to IPRF and IPRH to IPRM). However, when interrupt sources whose priority levels are allocated with the same IPR are requested, the interrupt of the smaller vector number has priority. This priority cannot be changed. Priority levels of IRQ interrupts and on-chip peripheral module interrupts are initialized to level 0 at a power-on reset. If the same priority level is allocated to two or more interrupt sources and interrupts from those sources occur simultaneously, they are processed by the default priority order shown in table 6.3.

Section 6 Interrupt Controller (INTC) Page 124 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 6.3 Interrupt Exception Ha ndling Vectors and Priorities Interrupt Source Name Vector No. Vector Table Starting Address IPR Default Priority User break 12 H'00000030 ⎯ High External pin NMI 11 H'0000002C ⎯ IRQ0 64 H'00000100 IPRA15 to IPRA12 IRQ1 65 H'00000104 IPRA11 to IPRA8 IRQ2 66 H'00000108 IPRA7 to IPRA4 IRQ3 67 H'0000010C IPRA3 to IPRA0 IRQ4 68 H'00000110 IPRB15 to IPRB12 IRQ5 69 H'00000114 IPRB11 to IPRB8 IRQ6 70 H'00000118 IPRB7 to IPRB4 IRQ7 71 H'0000011C IPRB3 to IPRB0 DMAC_0 DEI0 72 H'00000120 IPRC15 to IPRC12 DMAC_1 DEI1 76 H'00000130 IPRC11 to IPRC8 DMAC_2 DEI2 80 H'00000140 IPRC7 to IPRC4 DMAC_3 DEI3 84 H'00000150 IPRC3 to IPRC0 TGIA_0 88 H'00000160 IPRD15 to IPRD12 TGIB_0 89 H'00000164 TGIC_0 90 H'00000168 TGID_0 91 H'0000016C TCIV_0 92 H'00000170 IPRD11 to IPRD8 TGIE_0 93 H'00000174 MTU2_0 TGIF_0 94 H'00000178 TGIA_1 96 H'00000180 IPRD7 to IPRD4 TGIB_1 97 H'00000184 TCIV_1 100 H'00000190 IPRD3 to IPRD0 MTU2_1 TCIU_1 101 H'00000194 MTU2_2 TGIA_2 104 H'000001A0 IPRE15 to IPRE12 TGIB_2 105 H'000001A4 TCIV_2 108 H'000001B0 IPRE11 to IPRE8 TCIU_2 109 H'000001B4 Low

Section 6 Interrupt Controller (INTC) R01UH0198EJ0500 Rev. 5.00 Page 125 of 1560 Mar 18, 2011 SH7080 Group Interrupt Source Name Vector No. Vector Table Starting Address IPR Default Priority MTU2_3 TGIA_3 112 H'000001C0 IPRE7 to IPRE4 High TGIB_3 113 H'000001C4 TGIC_3 114 H'000001C8 TGID_3 115 H'000001CC TCIV_3 116 H'000001D0 IPRE3 to IPRE0 MTU2_4 TGIA_4 120 H'000001E0 IPRF15 to IPRF12 TGIB_4 121 H'000001E4 TGIC_4 122 H'000001E8 TGID_4 123 H'000001EC TCIV_4 124 H'000001F0 IPRF11 to IPRF8 MTU2_5 TGIU_5 128 H'00000200 IPRF7 to IPRF4 TGIV_5 129 H'00000204 TGIW_5 130 H'00000208 POE (MTU2) OEI1 132 H'00000210 IPRF3 to IPRF0 OEI3 133 H'00000214 I C2* IINAKI 156 H'00000270 IPRH11 to IPRH8 TGIA_3S 160 H'00000280 IPRH7 to IPRH4 TGIB_3S 161 H'00000284 TGIC_3S 162 H'00000288 TGID_3S 163 H'0000028C MTU2S_3 TCIV_3S 164 H'00000290 IPRH3 to IPRH0 TGIA_4S 168 H'000002A0 IPRI15 to IPRI12 TGIB_4S 169 H'000002A4 TGIC_4S 170 H'000002A8 TGID_4S 171 H'000002AC MTU2S_4 TCIV_4S 172 H'000002B0 IPRI11 to IPRI8 MTU2S_5 TGIU_5S 176 H'000002C0 IPRI7 to IPRI4 TGIV_5S 177 H'000002C4 TGIW_5S 178 H'000002C8 POE (MTU2S) OEI2 180 H'000002D0 IPRI3 to IPRI0 CMT_0 CMI_0 184 H'000002E0 IPRJ15 to IPRJ12 Low

Section 6 Interrupt Controller (INTC) Page 126 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Interrupt Source Name Vector No. Vector Table Starting Address IPR Default Priority CMT_1 CMI_1 188 H'000002F0 IPRJ11 to IPRJ8 High BSC CMI 192 H'00000300 IPRJ7 to IPRJ4 WDT ITI 196 H'00000310 IPRJ3 to IPRJ0 ADI_0 200 H'00000320 IPRK15 to IPRK12 A/D_0 and A/D_1 ADI_1 201 H'00000324 A/D_2 ADI_2 204 H'00000330 IPRK11 to IPRK8 SCI_0 ERI_0 216 H'00000360 IPRL15 to IPRL12 RXI_0 217 H'00000364 TXI_0 218 H'00000368 TEI_0 219 H'0000036C SCI_1 ERI_1 220 H'00000370 IPRL11 to IPRL8 RXI_1 221 H'00000374 TXI_1 222 H'00000378 TEI_1 223 H'0000037C SCI_2 ERI_2 224 H'00000380 IPRL7 to IPRL4 RXI_2 225 H'00000384 TXI_2 226 H'00000388 TEI_2 227 H'0000038C ERIF 228 H'00000390 IPRL3 to IPRL0 RXIF 229 H'00000394 BRIF 230 H'00000398 SCIF TXIF 231 H'0000039C SSERI 232 H'000003A0 IPRM15 to IPRM12 SSRXI 233 H'000003A4 SSU SSTXI 234 H'000003A8 I C2* IITEI 236 H'000003B0 IPRM11 to IPRM8 IISTPI 237 H'000003B4 IITXI 238 H'000003B8 IIRXI 239 H'000003BC Low Note: * The I C2 has an interrupt whose vector address is separated from those for the other I C2 interrupt sources.

Section 6 Interrupt Controller (INTC) R01UH0198EJ0500 Rev. 5.00 Page 127 of 1560 Mar 18, 2011 SH7080 Group

6.6 Interrupt Operation

6.6.1 Interrupt Sequence

The sequence of interrupt operations is explained below. Figure 6.3 is a flowchart of the operations. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects the highest priority interrupt from interrupt requests sent, according to the priority levels set in interrupt priority registers A to F and H to M (IPRA to IPRF and IPRH to IPRM). Interrupts that have lower-priority than that of the selected interrupt are ignored*. If interrupts that have the same priority level or interrupts within a same module occur simultaneously, the interrupt with the highest priority is selected according to the default priority shown in table 6.3. 3. The interrupt controller compares the priority level of the selected interrupt request with the interrupt mask bits (I3 to I0) in the status register (SR) of the CPU. If the priority level of the selected request is equal to or less than the level set in bits I3 to I0, the request is ignored. If the priority level of the selected request is higher than the level in bits I3 to I0, the interrupt controller accepts the request and sends an interrupt request signal to the CPU. 4. When the interrupt controller accepts an interrupt, a low level is output from the IRQOUT pin. 5. The CPU detects the interrupt request sent from the interrupt controller in the decode stage of an instruction to be executed. Instead of executing the decoded instruction, the CPU starts interrupt exception handling. 6. SR and PC are saved onto the stack. 7. The priority level of the accepted interrupt is copied to bits (I3 to I0) in SR. 8. When the accepted interrupt is sensed by level or is from an on-chip peripheral module, a high level is output from the IRQOUT pin. When the accepted interrupt is sensed by edge, a high level is output from the IRQOUT pin at the moment when the CPU starts interrupt exception processing instead of instruction execution as noted in 5. above. However, if the interrupt controller accepts an interrupt with a higher priority than the interrupt just to be accepted, the IRQOUT pin holds low level. 9. The CPU reads the start addr ess of the exception handling routine from the exception vector table for the accepted interrupt, branches to that address, and starts executing the program. This branch is not a delayed branch.

Section 6 Interrupt Controller (INTC) Page 128 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Notes: The interrupt source flag should be cleared in the interrupt handler. To ensure that an interrupt source that should have been cleared is not inadvertently accepted again, read the interrupt source flag after it has been cleared, confirm that it has been cleared, and then execute an RTE instruction. * Interrupt requests that are designated as edge-detect type are held pending until the interrupt requests are accepted. IRQ interrupts, however, can be cancelled by accessing the IRQ status register (IRQSR). Interrupts held pending due to edge detection are cleared by a power-on reset or a manual reset.

Section 6 Interrupt Controller (INTC) R01UH0198EJ0500 Rev. 5.00 Page 129 of 1560 Mar 18, 2011 SH7080 Group Program execution state Interrupt? User break? I3 to I0 ≤ level 14? Level 14 interrupt? Level 1 interrupt?I3 to I0 ≤ level 13? I3 to I0 = level 0? No Yes No No No No No No No Yes Yes Yes Yes Yes Yes Yes Save SR to stack IRQOUT = low Save PC to stack Copy interrupt level to I3 to I0 Read exception vector table Branch to exception handling routine No Yes Level 15 interrupt? Notes: I3 to I0 are interrupt mask bits in the status register (SR) of the CPU 1. IRQOUT is the same signal as the interrupt request signal to the CPU (see figure 6.1). Therefore, IRQOUT is output when the request priority level is higher than the level in bits I3–I0 of SR. 2. When the accepted interrupt is sensed by edge, a high level is output from the IRQOUT pin at the moment when the CPU starts interrupt exception processing instead of instruction execution (namely, before saving SR to stack). However, if the interrupt controller accepts an interrupt with a higher priority than the interrupt just to be accepted and has output an interrupt request to the CPU, the IRQOUT pin holds low level. 3. The IRQOUT pin change timing depends on a frequency dividing ratio between the internal (Iφ) and bus (Bφ) clocks. This flowchart shows that the frequency dividing ratios of the internal (Iφ) and bus (Bφ) clocks are the same. NMI? I3 to I0 ≤ level 14? No Yes IRQOUT = high *1*3 *2*3 Figure 6.3 Interrupt Sequence Flowchart

Section 6 Interrupt Controller (INTC) Page 130 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

6.6.2 Stack after Interrupt Exception Handling

Figure 6.4 shows the stack after interrupt exception handling. 32 bits 32 bits PC*1 SR Address 4n – 8 4n – 4 SP*2 Notes: 1. PC is the start address of the next instruction (instruction at the return address) after the executed instruction. 2. Always make sure that SP is a multiple of 4 Figure 6.4 Stack after Interrupt Exception Handling

6.7 Interrupt Response Time

Table 6.4 lists the interrupt response time, which is the time from the occurrence of an interrupt request until the interrupt exception handling starts and fetching of the first instruction of the interrupt handling routine begins.

Section 6 Interrupt Controller (INTC) R01UH0198EJ0500 Rev. 5.00 Page 131 of 1560 Mar 18, 2011 SH7080 Group Table 6.4 Interrupt Response Time Number of Cycles Item NMI IRQ Peripheral Modules Remarks DMAC/DTC active judgement ⎯ 2 × Bcyc 1 × Pcyc Interrupt priority decision and comparison with mask bits in SR 1 × Icyc + 2 × Pcyc 1 × Icyc + 1 × Pcyc 1 × Icyc + 2 × Pcyc Wait for completion of sequence currently being executed by CPU X ( ≥ 0) X ( ≥ 0) X ( ≥ 0) The longest sequence is for interrupt or address- error exception handling (X = 7 × Icyc + m1 + m2 + m3 + m4). If an interrupt-masking instruction follows, however, the time may be even longer. Time from start of interrupt exception handling until fetch of first instruction of exception handling routine starts 8 × Icyc + m1 + m2 + m3 8 × Icyc + m1 + m2 + m3 8 × Icyc + m1 + m2 + m3 Performs the saving PC and SR, and vector address fetch. Interrupt response time Total: 9 × Icyc + 2 × Pcyc + m1 + m2 + m3 + X 9 × Icyc + 1 × Pcyc +2 × Bcyc + m1 + m2 + m3 + X 9 × Icyc + 3 × Pcyc + m1 + m2 + m3 + X Minimum *: 12 × Icyc + 2 × Pcyc 12 × Icyc + 1 × Pcyc + 2 × Bcyc 12 × Icyc + 3 × Pcyc SR, PC, and vector table are all in on-chip RAM. Maximum: 16 × Icyc + 2 × Pcyc + 2 × (m1 + m2 + m3) + m4 16 × Icyc + 1 × Pcyc + 2 × Bcyc + 2 × (m1 + m2 + m3) + m4 16 × Icyc + 3 × Pcyc + 2 × (m1 + m2 + m3) + m4 Notes: * In the case that m1 = m2 = m3 = m4 = 1 × Icyc. m1 to m4 are the number of cycles needed for the following memory accesses. m1: SR save (longword write) m2: PC save (longword write) m3: Vector address read (longword read) m4: Fetch first instruction of interrupt service routine

Section 6 Interrupt Controller (INTC) Page 132 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

6.8 Data Transfer with Interrupt Request Signals

The following data transfers can be done using interrupt request signals:

• Activate DMAC only; CPU interrupts do not occur
• Activate DTC only; CPU interrupts depend on DTC settings Interrupt sources that are assigned for DMAC activation sources are masked without being input to the INTC. The mask condition is as follows: Mask condition = Interrupt source select (CH0) + interrupt source select (CH1) + interrupt source select (CH2) + interrupt source select (CH3) The INTC masks a CPU interrupt when the corresponding DTCE bit is 1. The conditions for clearing DTCE and interrupt source flag are shown below. DTCE clear condition = DTC transfer end • DTCECLR Interrupt source flag clear condition = DTC transfer end • DTCECLR + DMAC transfer end where DTCECLR = DISEL + counter 0 Figures 6.5 and 6.6 show control block diagrams. IRQ flag clear by DTC Interrupt request to CPU DTC activation request DTCECLR Transfer end DTCER DTCE clear Interrupt priority determination Interrupt controller IRQ detection IRQ edge detector (in standby mode) IRQ pin DTC Standby cancel determination Standby control Figure 6.5 IRQ Interrupt Control Block Diagram

Section 6 Interrupt Controller (INTC) R01UH0198EJ0500 Rev. 5.00 Page 133 of 1560 Mar 18, 2011 SH7080 Group Interrupt source flag clear Interrupt source flag clear by DMAC Interrupt source Interrupt source flag clear by DTC Interrupt request to CPU DTC activation request DMAC activation request DTCECLR Transfer end DTCER DTCE clear Interrupt priority determination Interrupt controller DTC Decode DMAC CHCR RS bits 3 to 0 Figure 6.6 On-Chip Module Interrupt Control Block Diagram

6.8.1 Handling Interrupt Request Signals as Sources for DTC Activation and CPU

Interrupts, but Not DMAC Activation 1. Do not select DMAC activation sources. 2. For DTC, set the corresponding DTCE bits and DISEL bits to 1. 3. When an interrupt occurs, an activation request is sent to the DTC. 4. When completing a data transfer, the DTC cl ears the DTCE bit to 0 and sends an interrupt request to the CPU. The activation source is not cleared. 5. The CPU clears the interrupt s ource in the interrupt handling routine then checks the transfer counter value. When the transfer counter value is not 0, the CPU sets the DTCE bit to 1 and allows the next data transfer. If the transfer counter value = 0, the CPU performs the necessary end processing in the interrupt processing routine.

Section 6 Interrupt Controller (INTC) Page 134 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

6.8.2 Handling Interrupt Request Signals as Sources for DMAC Activation, but Not

CPU Interrupts and DTC Activation 1. Select DMAC activation sources. Then, CP U interrupts and DTC activation sources are masked regardless of the settings in the interrupt priority registers and the DTC registers. 2. When an interrupt occurs, an activation request is sent to the DMAC. 3. The DMAC clears the interrup t source when starting transfer.

6.8.3 Handling Interrupt Request Signals as Sources for DTC Activation, but Not CPU

Interrupts and DMAC Activation 1. Do not select DMAC activation sources. 2. For DTC, set the corresponding DTCE bits to 1 and clear the DISEL bits to 0. 3. When an interrupt occurs, an activation request is sent to the DTC. 4. When completing a data transf er, the DTC clears the activation source. No interrupt request is sent to the CPU because the DTCE bit is held at 1. 5. However, when the transfer counter value = 0, the DTCE bit is cleared to 0 and an interrupt request is sent to the CPU. 6. The CPU performs the necessary end processing in the interrupt handling routine.

6.8.4 Handling Interrupt Request Signals as Sources for CPU Interrupts, but Not DTC

1 Do not select DMAC activation sources. 2. For DTC, clear the corresponding DTCE bits to 0. 3. When an interrupt occurs, an interrupt request is sent to the CPU. 4. The CPU clears the interrupt source and performs the necessary processing in the interrupt handling routine.

6.9 Usage Note

The interrupt source flag should be cleared in the interrupt handler. To ensure that an interrupt source that should have been cleared is not inadvertently accepted again, read the interrupt source flag after it has been cleared, confirm that it has been cleared, and then execute an RTE instruction.

Section 7 User Break Controller (UBC) R01UH0198EJ0500 Rev. 5.00 Page 135 of 1560 Mar 18, 2011 SH7080 Group Section 7 User Break Controller (UBC) The user break controller (UBC) provides functions that simplify program debugging. These functions make it easy to design an effective self-monitoring debugger, enabling the chip to debug programs without using an in-circuit emulator. Break conditions that can be set in the UBC are instruction fetch or data read/write access, data size, data contents, address value, and stop timing in the case of instruction fetch. For the mask ROM version, only the L-bus instruction-fetch address break (2 channels) is available.

7.1 Features

The UBC has the following features: 1. The following break comparison conditions can be set. Number of break channels: two channels (channels A and B) User break can be requested as either the independent or sequential condition on channels A and B (sequential break setting: channel A and then channel B match with break conditions, but not in the same bus cycle). ⎯ Address Comparison bits are maskable in 1-bit units. One of the two address buses (L-bus address (LAB) and I-bus address (IAB)) can be selected. ⎯ Data 32-bit maskable. One of the two data buses (L-bus data (LDB) and I-bus data (IDB)) can be selected. ⎯ Bus cycle Instruction fetch or data access ⎯ Read/write ⎯ Operand size Byte, word, and longword 2. A user-designed user-break interrupt exception processing routine can be run. 3. In an instruction fetch cycle, it can be select ed that a user break is set before or after an instruction is executed. 4. Maximum repeat times for the break condition (only for channel B): 2 – 1 times.

Section 7 User Break Controller (UBC) Page 136 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group 5. Four pairs of branch source/destination buffers (eight pairs for F-ZTAT version supporting full functions of E10A). Figure 7.1 shows a block diagram of the UBC.

Section 7 User Break Controller (UBC) R01UH0198EJ0500 Rev. 5.00 Page 137 of 1560 Mar 18, 2011 SH7080 Group BBRA BARA BAMRA CPU state signals LDB IABIDB LAB Internal bus Access comparator Address comparator Channel A Access comparator Address comparator Data comparator PC trace Control Channel B BBRB BETR BDRA BDMRA BARB BAMRB BDRB BDMRB BRSR BRDR BRCR User break interrupt request [Legend] BBRA: Break bus cycle register A BARA: Break address register A BAMRA: Break address mask register A BDRA: Break data register A BDMRA: Break data mask register A BBRB: Break bus cycle register B BARB: Break address register B BAMRB: Break address mask register B BDRB: Break data register B BDMRB: Break data mask register B BETR: Execution times break register BRSR: Branch source register BRDR: Branch destination register BRCR: Break control register Access control Data comparator Figure 7.1 Block Diagram of UBC

Section 7 User Break Controller (UBC) Page 138 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

7.2 Input/Output Pins

Table 7.1 shows the UBC pin configuration. Table 7.1 Pin Configuration Pin Name Symbol I/O Function User break trigger output UBCTRG Output UBC condition match trigger output pin.

Section 7 User Break Controller (UBC) R01UH0198EJ0500 Rev. 5.00 Page 139 of 1560 Mar 18, 2011 SH7080 Group

7.3 Register Descriptions

The user break controller has the following registers. For details on register addresses and register states during each processing, refer to section 27, List of Registers. Table 7.2 Register Configuration Register Name Abbrevia- tion R/W Initial Value Address Access Size Break address register A BARA R/W H'00000000 H'FFFFF300 32 Break address mask register A BAMRA R/W H'00000000 H'FFFFF304 32 Break bus cycle register A BBRA R/W H'0000 H'FFFFF308 16 Break data register A BDRA * R/W H'00000000 H'FFFFF310 32 Break data mask register A BDMRA * R/W H'00000000 H'FFFFF314 32 Break address register B BARB R/W H'00000000 H'FFFFF320 32 Break address mask register B BAMRB R/W H'00000000 H'FFFFF324 32 Break bus cycle register B BBRB R/W H'0000 H'FFFFF328 16 Break data register B BDRB * R/W H'00000000 H'FFFFF330 32 Break data mask register B BDMRB * R/W H'00000000 H'FFFFF334 32 Break control register BRCR R/W H'00000000 H'FFFFF3C0 32 Branch source register BRSR * R H'0xxxxxxx H'FFFFF3D0 32 Branch destination register BRDR * R H'0xxxxxxx H'FFFFF3D4 32 Execution times break register BETR * R/W H'0000 H'FFFFF3DC 16 Note: * Only in F-ZTAT version

Section 7 User Break Controller (UBC) Page 140 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

7.3.1 Break Address Register A (BARA)

BARA is a 32-bit readable/writable register. BARA specifies the address used as a break condition in channel A. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W BAA31 BAA30 BAA29 BAA28 BAA27 BAA26 BAA25 BAA24 BAA23 BAA22 BAA21 BAA20 BAA19 BAA18 BAA17 BAA16 BAA15 BAA14 BAA13 BAA12 BAA11 BAA10 BAA9 BAA8 BAA7 BAA6 BAA5 BAA4 BAA3 BAA2 BAA1 BAA0 Bit Bit Name Initial Value R/W Description 31 to 0 BAA31 to BAA 0 All 0 R/W Break Address A Store the address on the LAB or IAB specifying break conditions of channel A.

7.3.2 Break Address Mask Register A (BAMRA)

BAMRA is a 32-bit readable/writable register. BAMRA specifies bits masked in the break address specified by BARA. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W BAMA31 BAMA30 BAMA29 BAMA28 BAMA27 BAMA26 BAMA25 BAMA24 BAMA23 BAMA22 BAMA21 BAMA20 BAMA19 BAMA18 BAMA17 BAMA16 BAMA15 BAMA14 BAMA13 BAMA12 BAMA11 BAMA10 BAMA9 BAMA8 BAMA7 BAMA6 BAMA5 BAMA4 BAMA3 BAMA2 BAMA1 BAMA0

Section 7 User Break Controller (UBC) R01UH0198EJ0500 Rev. 5.00 Page 141 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description 31 to 0 BAMA31 to BAMA 0 All 0 R/W Break Address Mask A Specify bits masked in the channel A break address bits specified by BARA (BAA31 to BAA0). 0: Break address bit BAAn of channel A is included in the break condition 1: Break address bit BAAn of channel A is masked and is not included in the break condition Note: n = 31 to 0

7.3.3 Break Bus Cycle Register A (BBRA)

BBRA is a 16-bit readable/writable register, which specifies (1) bus master for I bus cycle, (2) L bus cycle or I bus cycle, (3) instruction fetch or data access, (4) read or write, and (5) operand size in the break conditions of channel A. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRRR R / W R / W R / W R / W R / W R / W R / W R / W R / W R / W R / W Note: These bits are reserved in the mask ROM and ROM-less versions. These bits are always read as 0. The write value should always be 0. ----- C P A 2 * CPA1* CPA0* CDA1* CDA0 IDA1 * IDA0 RWA1 * RWA0 SZA1 * SZA0* Bit Bit Name Initial Value R/W Description 15 to 11 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. CPA2* CPA1* CPA0* R/W R/W R/W Bus Master Select A for I Bus Select the bus master when the I bus is selected as the bus cycle of the channel A break condition. However, when the L bus is selected as the bus cycle, the setting of the CPA2 to CPA0 bits is disabled. 000: Condition comparison is not performed xx1: The CPU cycle is included in the break condition x1x: The DMAC cycle is included in the break condition 1xx: The DTC cycle is included in the break condition

Section 7 User Break Controller (UBC) Page 142 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description CDA1* CDA0 R/W R/W L Bus Cycle/I Bus Cycle Select A Select the L bus cycle or I bus cycle as the bus cycle of the channel A break condition. 00: Condition comparison is not performed 01: The break condition is the L bus cycle 10: The break condition is the I bus cycle 11: The break condition is the L bus cycle IDA1* IDA0 R/W R/W Instruction Fetch/Data Access Select A Select the instruction fetch cycle or data access cycle as the bus cycle of the channel A break condition. 00: Condition comparison is not performed 01: The break condition is the instruction fetch cycle 10: The break condition is the data access cycle 11: The break condition is the instruction fetch cycle or data access cycle RWA1* RWA0 R/W R/W Read/Write Select A Select the read cycle or write cycle as the bus cycle of the channel A break condition. 00: Condition comparison is not performed 01: The break condition is the read cycle 10: The break condition is the write cycle 11: The break condition is the read cycle or write cycle SZA1* SZA0* R/W R/W Operand Size Select A Select the operand size of the bus cycle for the channel A break condition. 00: The break condition does not include operand size 01: The break condition is byte access 10: The break condition is word access 11: The break condition is longword access Note: When specifying the operand size, specify the size which matches the address boundary. [Legend] x: Don't care. Note: * These bits are reserved in the mask ROM and ROM-less versions. These bits are always read as 0. The write value should always be 0.

Section 7 User Break Controller (UBC) R01UH0198EJ0500 Rev. 5.00 Page 143 of 1560 Mar 18, 2011 SH7080 Group

7.3.4 Break Data Register A (BDRA) (Only in F-ZTAT Version)

BDRA is a 32-bit readable/writable register. The control bits CDA1 and CDA0 in BBRA select one of two data buses for break condition A. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W BDA31 BDA30 BDA29 BDA28 BDA27 BDA26 BDA25 BDA24 BDA23 BDA22 BDA21 BDA20 BDA19 BDA18 BDA17 BDA16 BDA15 BDA14 BDA13 BDA12 BDA11 BDA10 BDA9 BDA8 BDA7 BDA6 BDA5 BDA4 BDA3 BDA2 BDA1 BDA0 Bit Bit Name Initial Value R/W Description 31 to 0 BDA31 to BDA0 All 0 R/W Break Data Bit A Stores data which specifies a break condition in channel If the I bus is selected in BBRA, the break data on IDB is set in BDA31 to BDA0. If the L bus is selected in BBRA, the break data on LDB is set in BDA31 to BDA0. Notes: 1. Specify an operand size when including the value of the data bus in the break condition. 2. When the byte size is selected as a break condition, the same byte data must be set in bits 15 to 8 and 7 to 0 in BDRA as the break data.

Section 7 User Break Controller (UBC) Page 144 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

7.3.5 Break Data Mask Register A (BDMRA) (Only in F-ZTAT Version)

BDMRA is a 32-bit readable/writable register. BDMRA specifies bits masked in the break data specified by BDRA. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W BDMA31 BDMA30 BDMA29 BDMA28 BDMA27 BDMA26 BDMA25 BDMA24 BDMA23 BDMA22 BDMA21 BDMA20 BDMA19 BDMA18 BDMA17 BDMA16 BDMA15 BDMA14 BDMA13 BDMA12 BDMA11 BDMA10 BDMA9 BDMA8 BDMA7 BDMA6 BDMA5 BDMA4 BDMA3 BDMA2 BDMA1 BDMA0 Bit Bit Name Initial Value R/W Description 31 to 0 BDMA31 to BDMA 0 All 0 R/W Break Data Mask A Specifies bits masked in the break data of channel A specified by BDRA (BDA31 to BDA0). 0: Break data BDAn of channel A is included in the break condition 1: Break data BDAn of channel A is masked and is not included in the break condition Note: n = 31 to 0 Notes: 1. Specify an operand size when including the value of the data bus in the break condition. 2. When the byte size is selected as a break condition, the same byte data must be set in bits 15 to 8 and 7 to 0 in BDMRA as the break mask data in BDRA.

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7.3.6 Break Address Register B (BARB)

BARB is a 32-bit readable/writable register. BARB specifies the address used as a break condition in channel B. Control bits CDB1 and CDB0 in BBRB select one of the two address buses for break condition B. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W BAB31 BAB30 BAB29 BAB28 BAB27 BAB26 BAB25 BAB24 BAB23 BAB22 BAB21 BAB20 BAB19 BAB18 BAB17 BAB16 BAB15 BAB14 BAB13 BAB12 BAB11 BAB10 BAB9 BAB8 BAB7 BAB6 BAB5 BAB4 BAB3 BAB2 BAB1 BAB0 Bit Bit Name Initial Value R/W Description 31 to 0 BAB31 to BAB 0 All 0 R/W Break Address B Stores an address which specifies a break condition in channel B. If the I bus or L bus is selected in BBRB, an IAB or LAB address is set in BAB31 to BAB0.

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7.3.7 Break Address Mask Register B (BAMRB)

BAMRB is a 32-bit readable/writable register. BAMRB specifies bits masked in the break address specified by BARB. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W BAMB31 BAMB30 BAMB29 BAMB28 BAMB27 BAMB26 BAMB25 BAMB24 BAMB23 BAMB22 BAMB21 BAMB20 BAMB19 BAMB18 BAMB17 BAMB16 BAMB15 BAMB14 BAMB13 BAMB12 BAMB11 BAMB10 BAMB9 BAMB8 BAMB7 BAMB6 BAMB5 BAMB4 BAMB3 BAMB2 BAMB1 BAMB0 Bit Bit Name Initial Value R/W Description 31 to 0 BAMB31 to BAMB 0 All 0 R/W Break Address Mask B Specifies bits masked in the break address of channel B specified by BARB (BAB31 to BAB0). 0: Break address BABn of channel B is included in the break condition 1: Break address BABn of channel B is masked and is not included in the break condition Note: n = 31 to 0

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7.3.8 Break Data Register B (BDRB) (Only in F-ZTAT Version)

BDRB is a 32-bit readable/writable register. The control bits CDB1 and CDB0 in BBRB select one of the two data buses for break condition B. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W BDB31 BDB30 BDB29 BDB28 BDB27 BDB26 BDB25 BDB24 BDB23 BDB22 BDB21 BDB20 BDB19 BDB18 BDB17 BDB16 BDB15 BDB14 BDB13 BDB12 BDB11 BDB10 BDB9 BDB8 BDB7 BDB6 BDB5 BDB4 BDB3 BDB2 BDB1 BDB0 Bit Bit Name Initial Value R/W Description 31 to 0 BDB31 to BDB0 All 0 R/W Break Data Bit B Stores data which specifies a break condition in channel If the I bus is selected in BBRB, the break data on IDB is set in BDB31 to BDB0. If the L bus is selected in BBRB, the break data on LDB is set in BDB31 to BDB0. Notes: 1. Specify an operand size when including the value of the data bus in the break condition. 2. When the byte size is selected as a break condition, the same byte data must be set in bits 15 to 8 and 7 to 0 in BDRB as the break data.

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7.3.9 Break Data Mask Register B (BDMRB) (Only in F-ZTAT Version)

BDMRB is a 32-bit readable/writable register. BDMRB specifies bits masked in the break data specified by BDRB. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W BDMB31 BDMB30 BDMB29 BDMB28 BDMB27 BDMB26 BDMB25 BDMB24 BDMB23 BDMB22 BDMB21 BDMB20 BDMB19 BDMB18 BDMB17 BDMB16 BDMB15 BDMB14 BDMB13 BDMB12 BDMB11 BDMB10 BDMB9 BDMB8 BDMB7 BDMB6 BDMB5 BDMB4 BDMB3 BDMB2 BDMB1 BDMB0 Bit Bit Name Initial Value R/W Description 31 to 0 BDMB31 to BDMB 0 All 0 R/W Break Data Mask B Specifies bits masked in the break data of channel B specified by BDRB (BDB31 to BDB0). 0: Break data BDBn of channel B is included in the break condition 1: Break data BDBn of channel B is masked and is not included in the break condition Note: n = 31 to 0 Notes: 1. Specify an operand size when including the value of the data bus in the break condition. 2. When the byte size is selected as a break condition, the same byte data must be set in bits 15 to 8 and 7 to 0 in BDMRB as the break mask data in BDRB.

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7.3.10 Break Bus Cycle Register B (BBRB)

BBRB is a 16-bit readable/writable register, which specifies (1) bus master for I bus cycle, (2) L bus cycle or I bus cycle, (3) instruction fetch or data access, (4) read or write, and (5) operand size in the break conditions of channel B. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRRR R / W R / W R / W R / W R / W R / W R / W R / W R / W R / W R / W Note: These bits are reserved in the mask ROM and ROM-less versions. These bits are always read as 0. The write value should always be 0. - - - - - CPB2 * CPB1* CPB0* CDB1* CDB0 IDB1 * IDB0 RWB1 * RWB0 SZB1 * SZB0* Bit Bit Name Initial Value R/W Description 15 to 11 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. CPB2* CPB1* CPB0* R/W R/W R/W Bus Master Select B for I Bus Select the bus master when the I bus is selected as the bus cycle of the channel B break condition. However, when the L bus is selected as the bus cycle, the setting of the CPB2 to CPB0 bits is disabled. 000: Condition comparison is not performed xx1: The CPU cycle is included in the break condition x1x: The DMAC cycle is included in the break condition 1xx: The DTC cycle is included in the break condition CDB1* CDB0 R/W R/W L Bus Cycle/I Bus Cycle Select B Select the L bus cycle or I bus cycle as the bus cycle of the channel B break condition. 00: Condition comparison is not performed 01: The break condition is the L bus cycle 10: The break condition is the I bus cycle 11: The break condition is the L bus cycle

Section 7 User Break Controller (UBC) Page 150 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description IDB1* IDB0 R/W R/W Instruction Fetch/Data Access Select B Select the instruction fetch cycle or data access cycle as the bus cycle of the channel B break condition. 00: Condition comparison is not performed 01: The break condition is the instruction fetch cycle 10: The break condition is the data access cycle 11: The break condition is the instruction fetch cycle or data access cycle RWB1* RWB0 R/W R/W Read/Write Select B Select the read cycle or write cycle as the bus cycle of the channel B break condition. 00: Condition comparison is not performed 01: The break condition is the read cycle 10: The break condition is the write cycle 11: The break condition is the read cycle or write cycle SZB1* SZB0* R/W R/W Operand Size Select B Select the operand size of the bus cycle for the channel B break condition. 00: The break condition does not include operand size 01: The break condition is byte access 10: The break condition is word access 11: The break condition is longword access Note: When specifying the operand size, specify the size which matches the address boundary. [Legend] x: Don't care. Note: * These bits are reserved in the mask ROM and ROM-less versions. These bits are always read as 0. The write value should always be 0.

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7.3.11 Break Control Register (BRCR)

BRCR sets the following conditions: 1. Channels A and B are used in two independent channel conditions or under the sequential condition. 2. A user break is set before or after instruction execution. 3. Specify whether to include the number of execution times on channel B in comparison conditions. 4. Determine whether to include data bus on channels A and B in comparison conditions. 5. Enable PC trace. 6. Select the UBCTRG output pulse width. 7. Specify whether to request the user break interrupt when channels A and B match with comparison conditions. BRCR is a 32-bit readable/writable register that has break conditions match flags and bits for setting a variety of break conditions. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRRRRRRRR R / W R / W R / W R R / W R 0000000000000000 R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R R/W R R R/W SCM FCA SCM FCB SCM FDA SCM FDB PCTE PCBA - - DBEA PCBB DBEB - SEQ - - ETBE

Section 7 User Break Controller (UBC) Page 152 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description 31 to 22 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. 21, 20 UTRGW[1:0] 00 R/W UBCTRG Output Pulse Width Select Select the UBCTRG output pulse width when the break condition matches. 00: Setting prohibited. 01: UBCTRG output pulse width is 3 to 4 tBcyc 10: UBCTRG output pulse width is 7 to 8 tBcyc 11: UBCTRG output pulse width is 15 to 16 tBcyc Note: t Bcyc indicates the period of one cycle of the external bus clock (Bφ = CK).

19 UBIDB 0 R/W User Break Disable B

Enables or disables the user break interrupt request when the channel B break conditions are satisfied. 0: User break interrupt request is enabled when break conditions are satisfied 1: User break interrupt request is disabled when break conditions are satisfied 18 ⎯ 0 R Reserved This bit is always read as 0. The write value should always be 0.

17 UBIDA 0 R/W User Break Disable A

Enables or disables the user break interrupt request when the channel A break conditions are satisfied. 0: User break interrupt request is enabled when break conditions are satisfied 1: User break interrupt request is disabled when break conditions are satisfied 16 ⎯ 0 R Reserved This bit is always read as 0. The write value should always be 0.

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15 SCMFCA 0 R/W L Bus Cycle Condition Match Flag A

When the L bus cycle condition in the break conditions set for channel A is satisfied, this flag is set to 1. In order to clear this flag, write 0 into this bit. 0: The L bus cycle condition for channel A does not match 1: The L bus cycle condition for channel A matches

14 SCMFCB 0 R/W L Bus Cycle Condition Match Flag B

When the L bus cycle condition in the break conditions set for channel B is satisfied, this flag is set to 1. In order to clear this flag, write 0 into this bit. 0: The L bus cycle condition for channel B does not match 1: The L bus cycle condition for channel B matches

13 SCMFDA 0 R/W I Bus Cycle Condition Match Flag A

When the I bus cycle condition in the break conditions set for channel A is satisfied, this flag is set to 1. In order to clear this flag, write 0 into this bit. 0: The I bus cycle condition for channel A does not match 1: The I bus cycle condition for channel A matches

12 SCMFDB 0 R/W I Bus Cycle Condition Match Flag B

When the I bus cycle condition in the break conditions set for channel B is satisfied, this flag is set to 1. In order to clear this flag, write 0 into this bit. 0: The I bus cycle condition for channel B does not match 1: The I bus cycle condition for channel B matches

11 PCTE 0 R/W PC Trace Enable

0: Disables PC trace 1: Enables PC trace

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10 PCBA 0 R/W PC Break Select A

Selects the break timing of the instruction fetch cycle for channel A as before or after instruction execution. 0: PC break of channel A is set before instruction execution 1: PC break of channel A is set after instruction execution 9, 8 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0.

7 DBEA 0 R/W Data Break Enable A

Selects whether or not the data bus condition is included in the break condition of channel A. 0: No data bus condition is included in the condition of channel A 1: The data bus condition is included in the condition of channel A

6 PCBB 0 R/W PC Break Select B

Selects the break timing of the instruction fetch cycle for channel B as before or after instruction execution. 0: PC break of channel B is set before instruction execution 1: PC break of channel B is set after instruction execution

5 DBEB 0 R/W Data Break Enable B

Selects whether or not the data bus condition is included in the break condition of channel B. 0: No data bus condition is included in the condition of channel B 1: The data bus condition is included in the condition of channel B 4 ⎯ 0 R Reserved This bit is always read as 0. The write value should always be 0.

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3 SEQ 0 R/W Sequence Condition Select

Selects two conditions of channels A and B as independent or sequential conditions. 0: Channels A and B are compared under independent conditions 1: Channels A and B are compared under sequential conditions (channel A, then channel B) 2, 1 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0.

0 ETBE 0 R/W Number of Execution Times Break Enable

Enables the execution-times break condition only on channel B. If this bit is 1 (break enable), a user break interrupt is requested when the number of break conditions matches with the number of execution times that is specified by BETR. 0: The execution-times break condition is disabled on channel B 1: The execution-times break condition is enabled on channel B

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7.3.12 Execution Times Break Register (BETR) (Only in F-ZTAT Version)

BETR is a 16-bit readable/writable register. When the execution-times break condition of channel B is enabled, this register specifies the number of execution times to make the break. The maximum number is 2 – 1 times. When a break condition is satisfied, it decreases BETR. A user break interrupt is requested when the break condition is satisfied after BETR becomes H'0001. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRR R / W R / W R / W R / W R / W R / W R / W R / W R / W R / W R / W R / W - - - - BET[11:0] Bit Bit Name Initial Value R/W Description 15 to 12 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. 11 to 0 BET[11:0] All 0 R/W Number of Execution Times

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7.3.13 Branch Source Register (BRSR) (Only in F-ZTAT Version)

BRSR is a 32-bit read-only register. BRSR stores bits 27 to 0 in the address of the branch source instruction. BRSR has the flag bit that is set to 1 when a branch occurs. This flag bit is cleared to 0 when BRSR is read, the setting to enable PC trace is made, or BRSR is initialized by a power-on reset or a manual reset. Other bits are not initialized by a power-on reset. The four BRSR registers (eight pairs for the F-ZTAT version supporting full functions of E10A) have a queue structure and a stored register is shifted at every branch. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 RRRRRRRRRRRRRRRR RRRRRRRRRRRRRRRR SVF - - - BSA27 BSA26 BSA25 BSA24 BSA23 BSA22 BSA21 BSA20 BSA19 BSA18 BSA17 BSA16 BSA15 BSA14 BSA13 BSA12 BSA11 BSA10 BSA9 BSA8 BSA7 BSA6 BSA5 BSA4 BSA3 BSA2 BSA1 BSA0 Bit Bit Name Initial Value R/W Description

31 SVF 0 R BRSR Valid Flag

Indicates whether the branch source address is stored. This flag bit is set to 1 when a branch occurs. This flag is cleared to 0 when BRSR is read, the setting to enable PC trace is made, or BRSR is initialized by a power-on reset. 0: The value of BRSR register is invalid 1: The value of BRSR register is valid 30 to 28 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. 27 to 0 BSA27 to BSA0 Undefined R Branch Source Address Store bits 27 to 0 of the branch source address.

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7.3.14 Branch Destination Register (BRDR) (Only in F-ZTAT Version)

BRDR is a 32-bit read-only register. BRDR stores bits 27 to 0 in the address of the branch destination instruction. BRDR has the flag bit that is set to 1 when a branch occurs. This flag bit is cleared to 0 when BRDR is read, the setting to enable PC trace is made, or BRDR is initialized by a power-on reset or a manual reset. Other bits are not initialized by a power-on reset. The four BRSR registers (eight pairs for the F-ZTAT version supporting full functions of E10A) have a queue structure and a stored register is shifted at every branch. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 RRRRRRRRRRRRRRRR RRRRRRRRRRRRRRRR DVF - - - BDA27 BDA26 BDA25 BDA24 BDA23 BDA22 BDA21 BDA20 BDA19 BDA18 BDA17 BDA16 BDA15 BDA14 BDA13 BDA12 BDA11 BDA10 BDA9 BDA8 BDA7 BDA6 BDA5 BDA4 BDA3 BDA2 BDA1 BDA0 Bit Bit Name Initial Value R/W Description

31 DVF 0 R BRDR Valid Flag

Indicates whether a branch destination address is stored. This flag bit is set to 1 when a branch occurs. This flag is cleared to 0 when BRDR is read, the setting to enable PC trace is made, or BRDR is initialized by a power-on reset. 0: The value of BRDR register is invalid 1: The value of BRDR register is valid 30 to 28 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. 27 to 0 BDA27 to BDA0 Undefined R Branch Destination Address Store bits 27 to 0 of the branch destination address.

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7.4 Operation

7.4.1 Flow of the User Break Operation

The flow from setting of break conditions to user break exception processing is described below: 1. The break addresses are set in the break a ddress registers (BARA or BARB). The masked addresses are set in the break address mask registers (BAMRA or BAMRB). The break data is set in the break data register (BDRA or BDRB). The masked data is set in the break data mask register (BDMRA or BDMRB). The bus break conditions are set in the break bus cycle registers (BBRA or BBRB). Three groups of BBRA or BBRB (L bus cycle/I bus cycle select, instruction fetch/data access select, and read/write select) are each set. No user break will be generated if even one of these groups is set with B'00. The respective conditions are set in the bits of the break control register (BRCR). Make sure to set all registers related to breaks before setting BBRA or BBRB. 2. When the break conditions are satisfied, the UBC sends a user break interrupt request to the CPU and sets the L bus condition match flag (SCMFCA or SCMFCB) and the I bus condition match flag (SCMFDA or SCMFDB) for the appropriate channel. 3. The appropriate condition match flags (S CMFCA, SCMFDA, SCMFCB, and SCMFDB) can be used to check if the set conditions match or not. The matching of the conditions sets flags, but they are not reset. Before using them again, 0 must first be written to them and then reset flags. 4. There is a chance that matches of the break conditions set in channels A and B occur almost at the same time. In this case, there will be only one user break request to the CPU, but these two conditions match flags could be both set. 5. When selecting the I bus as the break condition, note the following: ⎯ The CPU, DMAC, and DTC are connected to the I bus. The UBC monitors bus cycles generated by all bus masters that are selected by the CPA2 to CPA0 bits in BBRA or the CPB2 to CPB0 bits in BBRB, and compares the conditions for a match. ⎯ I bus cycles (including read fill cycles) resulting from instruction fetches on the L bus by the CPU are defined as instruction fetch cycles on the I bus, while other bus cycles are defined as data access cycles. ⎯ The DMAC and DTC only issue data access cycles for I bus cycles. ⎯ If a break condition is specified for the I bus, even when the condition matches in an I bus cycle resulting from an instruction executed by the CPU, at which instruction the user break is to be accepted cannot be clearly defined.

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7.4.2 User Break on Instruction Fetch Cycle

1. When L bus/instruction fetch/read/word, longword, or not including the operand size is set in the break bus cycle register (BBRA or BBRB), the break condition becomes the L bus instruction fetch cycle. Whether it breaks before or after the execution of the instruction can then be selected with the PCBA or PCBB bit in the break control register (BRCR) for the appropriate channel. If an instruction fetch cycle is set as a break condition, clear LSB in the break address register (BARA or BARB) to 0. A user break cannot be generated as long as this bit is set to 1. 2. If the break condition matches when a user break on instruction fetch is specified so that the a break is generated before the execution of the instruction, the user break is generated at the point when it has become deterministic that the instruction will be executed after it is fetched. This means this feature cannot be used on instructions fetched by overrun (instructions fetched at a branch or during an interrupt transition, but not to be executed). When this kind of break condition is set for the delay slot of a delayed branch instruction, the user break is generated prior to execution of the delayed branch instruction. Note: If a branch does not occur at a delay condition branch instruction, the subsequent instruction is not recognized as a delay slot. 3. When the break condition is specified so that a user break is generated after execution of the instruction, the instruction that has met the break condition is executed and then the user break is generated before the next instruction is executed. As with pre-execution user breaks, this cannot be used with overrun fetch instructions. When this kind of break condition is set for a delayed branch instruction and its delay slot, a user break is not generated until the first instruction at the branch destination. 4. When an instruction fetch cycle is set, the break data register (BDRA or BDRB) is ignored. Therefore, break data cannot be set for the user break of the instruction fetch cycle. 5. If the I bus is set for a user break of an instruction fetch cycle, the condition is determined for the instruction fetch cycles on the I bus. For details, see 5 in section 7.4.1, Flow of the User Break Operation.

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7.4.3 User Break on Data Access Cycle

1. If the L bus is specified as a break cond ition for data access break, condition comparison is performed for the address (and data) accessed by the executed instructions, and a user break occurs if the condition is satisfied. If the I bus is specified as a break condition, condition comparison is performed for the addresses (and data) of the data access cycles that are issued on the I bus by all bus masters including the CPU, and a user break occurs if the condition is satisfied. For details on the CPU bus cycles issued on the I bus, see 5 in section 7.4.1, Flow of the User Break Operation. 2. The relationship between the data access cycle address and the comparison condition for each operand size is listed in table 7.3. Table 7.3 Data Access Cycle Addresses and Operand Size Comparison Conditions Access Size Address Compared Longword Compares break address register bits 31 to 2 to address bus bits 31 to 2 Word Compares break address register bits 31 to 1 to address bus bits 31 to 1 Byte Compares break address register bits 31 to 0 to address bus bits 31 to 0 This means that when address H'00001003 is set in the break address register (BARA or BARB), for example, the bus cycle in which the break condition is satisfied is as follows (where other conditions are met). Longword access at H'00001000 Word access at H'00001002 Byte access at H'00001003 3. When the data value is included in the break conditions: When the data value is included in the break conditions, either longword, word, or byte is specified as the operand size of the break bus cycle register (BBRA or BBRB). When data values are included in break conditions, a user break is generated when the address conditions and data conditions both match. To specify byte data for this case, set the same data in two bytes at bits 15 to 8 and bits 7 to 0 of the break data register (BDRA or BDRB) and break data mask register (BDMRA or BDMRB). When word or byte is set, bits 31 to 16 of BDRA or BDRB and BDMRA or BDMRB are ignored. 4. If the L bus is selected, a user break occurs on ending execution of the instruction that matches the break condition, and immediately before the next instruction is executed. However, when data is also specified as the break condition, the break may occur on ending execution of the instruction following the instruction that matches the break condition. If the I bus is selected, the instruction at which the user break will occur cannot be determined. When this kind of user

Section 7 User Break Controller (UBC) Page 162 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group break occurs at a delayed branch instruction or its delay slot, the user break may not actually take place until the first instruction at the branch destination.

7.4.4 Sequential Break

1. By setting the SEQ bit in BRCR to 1, the sequential break is issued when a channel B break condition matches after a channel A break condition matches. A user break is not generated even if a channel B break condition matches before a channel A break condition matches. When channels A and B conditions match at the same time, the sequential break is not issued. To clear the channel A condition match when a channel A condition match has occurred but a channel B condition match has not yet occurred in a sequential break specification, clear the SEQ bit in BRCR to 0 and clear the condition match flag to 0 in channel A. 2. In sequential break specification, the L or I bus can be selected and the execution times break condition can be also specified. For example, when the execution times break condition is specified, the break condition is satisfied when a channel B condition matches with BETR = H'0001 after a channel A condition has matched.

7.4.5 Value of Saved Program Counter

When a user break occurs, the address of the instruction from where execution is to be resumed is saved in the stack, and the exception handling state is entered. If the L bus is specified as a break condition, the instruction at which the user break should occur can be clearly determined (except for when data is included in the break condition). If the I bus is specified as a break condition, the instruction at which the user break should occur cannot be clearly determined. 1. When instruction fetch (before instruction execution) is specified as a break condition: The address of the instruction that matched the break condition is saved in the stack. The instruction that matched the condition is not executed, and the user break occurs before it. However when a delay slot instruction matches the condition, the address of the delayed branch instruction is saved in the stack. 2. When instruction fetch (after instruction execution) is specified as a break condition: The address of the instruction following the instruction that matched the break condition is saved in the stack. The instruction that matches the condition is executed, and the user break occurs before the next instruction is executed. However when a delayed branch instruction or delay slot matches the condition, these instructions are executed, and the branch destination address is saved in the stack.

Section 7 User Break Controller (UBC) R01UH0198EJ0500 Rev. 5.00 Page 163 of 1560 Mar 18, 2011 SH7080 Group 3. When data access (address only) is specified as a break condition: The address of the instruction immediately after the instruction that matched the break condition is saved in the stack. The instruction that matches the condition is executed, and the user break occurs before the next instruction is executed. However when a delay slot instruction matches the condition, the branch destination address is saved in the stack. 4. When data access (address + data) is specified as a break condition: When a data value is added to the break conditions, the address of an instruction that is within two instructions of the instruction that matched the break condition is saved in the stack. At which instruction the user break occurs cannot be determined accurately. When a delay slot instruction matches the condition, the branch destination address is saved in the stack. If the instruction following the instruction that matches the break condition is a branch instruction, the user break may occur after the branch instruction or delay slot has finished. In this case, the branch destination address is saved in the stack.

7.4.6 PC Trace

1. Setting PCTE in BRCR to 1 enables PC traces. Wh en branch (branch instruction, and interrupt exception) is generated, the branch source address and branch destination address are stored in BRSR and BRDR, respectively. 2. The values stored in BRSR and BRDR are as given below due to the kind of branch. ⎯ If a branch occurs due to a branch instruction, the address of the branch instruction is saved in BRSR and the address of the branch destination instruction is saved in BRDR. ⎯ If a branch occurs due to an interrupt or exception, the value saved in stack due to exception occurrence is saved in BRSR and the start address of the exception handling routine is saved in BRDR. 3. BRSR and BRDR have four pairs of queue structures (eight pairs for the F-ZTAT version supporting full functions of E10A). The top of queues is read first when the address stored in the PC trace register is read. BRSR and BRDR share the read pointer. Read BRSR and BRDR in order, the queue only shifts after BRDR is read. After switching the PCTE bit (in BRCR) off and on, the values in the queues are invalid. 4. Since four pairs (eight pairs for the F-ZTAT version supporting full functions of E10A) of queue are shared with the AUD, set the PCTE bit in BRCR to 1 after setting the MSTP25 bit in STBCR5 to 0 and the AUDSRST bit in STBCR6 to 1. Although the AUD is only available in the F-ZTAT version supporting full functions of the E10A, this setting should also be made in the normal F-ZTAT version.

Section 7 User Break Controller (UBC) Page 164 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

7.4.7 Usage Examples

Break Condition Specified for L Bus Instruction Fetch Cycle: (Example 1-1)

• Register specifications BARA = H'00000404, BAMRA = H'00000000, BBRA = H'0054, BDRA = H'00000000, BDMRA = H'00000000, BARB = H'00008010, BAMRB = H'00000006, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000400 Specified conditions: Channel A/channel B independent mode <Channel A> Address: H'00000404, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (after in struction execution)/read (operand size is not included in the condition) <Channel B> Address: H'00008010, Address mask: H'00000006 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before in struction execution)/read (operand size is not included in the condition) A user break occurs after an instruction of address H'00000404 is executed or before instructions of addresses H'00008010 to H'00008016 are executed. (Example 1-2)
• Register specifications BARA = H'00037226, BAMRA = H'00000000, BBRA = H'0056, BDRA = H'00000000, BDMRA = H'00000000, BARB = H'0003722E, BAMRB = H'00000000, BBRB = H'0056, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000008 Specified conditions: Channel A/channel B sequential mode <Channel A> Address: H'00037226, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (b efore instruction execution)/read/word

Section 7 User Break Controller (UBC) R01UH0198EJ0500 Rev. 5.00 Page 165 of 1560 Mar 18, 2011 SH7080 Group <Channel B> Address: H'0003722E, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (b efore instruction execution)/read/word After an instruction with address H'00037226 is executed, a user break occurs before an instruction with address H'0003722E is executed. (Example 1-3)

• Register specifications BARA = H'00027128, BAMRA = H'00000000, BBRA = H'005A, BDRA = H'00000000, BDMRA = H'00000000, BARB = H'00031415, BAMRB = H'00000000, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000000 Specified conditions: Channel A/channel B independent mode <Channel A> Address: H'00027128, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/write/word <Channel B> Address: H'00031415, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before in struction execution)/read (operand size is not included in the condition) On channel A, no user break occurs since instruction fetch is not a write cycle. On channel B, no user break occurs since instruction fetch is performed for an even address. (Example 1-4)
• Register specifications BARA = H'00037226, BAMRA = H'00000000, BBRA = H'005A, BDRA = H'00000000, BDMRA = H'00000000, BARB = H'0003722E, BAMRB = H'00000000, BBRB = H'0056, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000008 Specified conditions: Channel A/channel B sequential mode <Channel A> Address: H'00037226, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/write/word

Section 7 User Break Controller (UBC) Page 166 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group <Channel B> Address: H'0003722E, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (b efore instruction execution)/read/word Since instruction fetch is not a write cycle on channel A, a sequential condition does not match. Therefore, no user break occurs. (Example 1-5)

• Register specifications BARA = H'00000500, BAMRA = H'00000000, BBRA = H'0057, BDRA = H'00000000, BDMRA = H'00000000, BARB = H'00001000, BAMRB = H'00000000, BBRB = H'0057, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000001, BETR = H'0005 Specified conditions: Channel A/channel B independent mode <Channel A> Address: H'00000500, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read/longword The number of execution-times break enable (5 times) <Channel B> Address: H'00001000, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read/longword On channel A, a user break occurs after the instruction of address H'00000500 is executed four times and before the fifth time. On channel B, a user break occurs before an instruction of address H'00001000 is executed. (Example 1-6)
• Register specifications BARA = H'00008404, BAMRA = H'00000FFF, BBRA = H'0054, BDRA = H'00000000, BDMRA = H'00000000, BARB = H'00008010, BAMRB = H'00000006, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000400 Specified conditions: Channel A/channel B independent mode <Channel A> Address: H'00008404, Address mask: H'00000FFF Data: H'00000000, Data mask: H'00000000

Section 7 User Break Controller (UBC) R01UH0198EJ0500 Rev. 5.00 Page 167 of 1560 Mar 18, 2011 SH7080 Group Bus cycle: L bus/instruction fetch (after in struction execution)/read (operand size is not included in the condition) <Channel B> Address: H'00008010, Address mask: H'00000006 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before in struction execution)/read (operand size is not included in the condition) A user break occurs after an instruction with addresses H'00008000 to H'00008FFE is executed or before an instruction with addresses H'00008010 to H'00008016 are executed. Break Condition Specified for L Bus Data Access Cycle: (Example 2-1)

• Register specifications BARA = H'00123456, BAMRA = H'00000000, BBRA = H'0064, BDRA = H'12345678, BDMRA = H'FFFFFFFF, BARB = H'000ABCDE, BAMRB = H'000000FF, BBRB = H'006A, BDRB = H'0000A512, BDMRB = H'00000000, BRCR = H'00000080 Specified conditions: Channel A/channel B independent mode <Channel A> Address: H'00123456, Address mask: H'00000000 Data: H'12345678, Da ta mask: H'FFFFFFFF Bus cycle: L bus/data access/read (operand size is not included in the condition) <Channel B> Address: H'000ABCDE, Address mask: H'000000FF Data: H'0000A512, Data mask: H'00000000 Bus cycle: L bus/data access/write/word On channel A, a user break occurs with longword read from address H'00123454, word read from address H'00123456, or byte read from address H'00123456. On channel B, a user break occurs when word H'A512 is written in addresses H'000ABC00 to H'000ABCFE.

Section 7 User Break Controller (UBC) Page 168 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Break Condition Specified for I Bus Data Access Cycle: (Example 3-1)

• Register specifications BARA = H'00314154, BAMRA = H'00000000, BBRA = H'0194, BDRA = H'12345678, BDMRA = H'FFFFFFFF, BARB = H'00055555, BAMRB = H'00000000, B BRB = H'01A9, BDRB = H'00007878, BDMRB = H'00000F0F, BRCR = H'00000080 Specified conditions: Channel A/channel B independent mode <Channel A> Address: H'00314154, Address mask: H'00000000 Data: H'12345678, Da ta mask: H'FFFFFFFF Bus cycle: I bus (CPU cycle)/instruction fetc h/read (operand size is not included in the condition) <Channel B> Address: H'00055555, Address mask: H'00000000 Data: H'00000078, Data mask: H'0000000F Bus cycle: I bus (CPU cycle)/data access/write/byte On channel A, a user break occurs when instruction fetch is performed for address H'00314156 in the external memory space. On channel B, a user break occurs when byte data H'7x is written in address H'00055555 in the external memory space by the CPU.

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7.5 Usage Notes

1. The CPU can read from or write to the UBC registers via the I bus. Accordingly, during the period from executing an instruction to rewrite the UBC register till the new value is actually rewritten, the desired user break may not occur. In order to know the timing when the UBC register is changed, read from the last written register. Instructions after then are valid for the newly written register value. 2. UBC cannot monitor access to the L bus and I bus in the same channel. 3. Note on specification of sequential break: A condition match occurs when a B-channel match occurs in a bus cycle after an A-channel match occurs in another bus cycle in sequential break setting. Therefore, no user break occurs even if a bus cycle, in which an A-channel match and a channel B match occur simultaneously, is set. 4. When a user break and another exception occur at the same instruction, which has higher priority is determined according to the priority levels defined in table 5.1 in section 5, Exception Handling. If an exception with higher priority occurs, the user break is not generated. ⎯ Pre-execution break has the highest priority. ⎯ When a post-execution break or data access break occurs simultaneously with a re- execution-type exception (including pre-execution break) that has higher priority, the re- execution-type exception is accepted, and the condition match flag is not set (see the exception in the following note). The user break will occur and the condition match flag will be set only after the exception source of the re-execution-type exception has been cleared by the exception handling routine and re-execution of the same instruction has ended. ⎯ When a post-execution break or data access break occurs simultaneously with a completion-type exception (TRAPA) that has higher priority, though a user break does not occur, the condition match flag is set. 5. Note the following ex ception for the above note. If a post-execution break or data access break is satisfied by an instruction that generates a CPU address error by data access, the CPU address error is given priority to the user break interrupt. Note that the UBC condition match flag is set in this case. 6. Note the following when a user break occurs in a delay slot. If a pre-execution break is set at the delay slot instruction of the RTE instruction, the user break does not occur until the branch destination of the RTE instruction.

Section 7 User Break Controller (UBC) Page 170 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group 7. User breaks are disabled during UBC module standby mode. Do not read from or write to the UBC registers during UBC module standby mode; the values are not guaranteed. 8. Do not set a post-execution break at a SLEEP instruction or a branch instruction for which a SLEEP instruction is placed in the delay slot. In addition, do not set a data access break at a SLEEP instruction or one or two instructions before a SLEEP instruction. 9. When the DTC or DMAC is in operation, the UBC cannot correctly determine access to the external space by the CPU via the I bus. To determine access to the external space via the I bus in the above situation, select all bus masters. This makes it impossible to determine conditions of access with specified bus masters. However, when a bus master can be inferred from data values, the relevant data values can be included as a condition that indicates a particular bus master.

Section 8 Data Transfer Controller (DTC) R01UH0198EJ0500 Rev. 5.00 Page 171 of 1560 Mar 18, 2011 SH7080 Group Section 8 Data Transfer Controller (DTC) This LSI includes a data transfer controller (DTC). The DTC can be activated to transfer data by an interrupt request.

8.1 Features

• Transfer possible over any number of channels:
• Chain transfer Multiple rounds of data transfer is executed in response to a single activation source Chain transfer is only possible after data transfer has been done for the specified number of times (i.e. when the transfer counter is 0)
• Three transfer modes Normal/repeat/block transfer modes selectable Transfer source and destination addresses can be selected from increment/decrement/fixed
• The transfer source and destination addresses can be specified by 32 bits to select a 4-Gbyte address space directly
• Size of data for data transfer can be specified as byte, word, or longword
• A CPU interrupt can be requested for the interrupt that activated the DTC A CPU interrupt can be requested after one data transfer completion A CPU interrupt can be requested after the specified data transfer completion
• Read skip of the transfer information specifiable
• Writeback skip executed for the fixed transfer source and destination addresses
• Module stop mode specifiable
• Short address mode specifiable
• Bus release timing selectable from five types
• Priority of the DTC activation selectable from two types Figure 8.1 shows a block diagram of the DTC. The DTC transfer information can be allocated to the data area*. Note: * When the transfer information is stored in the on-chip RAM, the RAME bit in RAMCR must be set to 1.

Section 8 Data Transfer Controller (DTC) Page 172 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bus interface Interrupt source clear request DTC DTC internal bus Peripheral bus Internal bus (32 bits) External bus CPU interrupt request Register control CPU/DTC /DMAC request determination Interrupt control Interrupt request On-chip memory MRA CHCR[11:8] MRB SAR DAR CRA CRB On-chip peripheral module External memory External device (memory mapped) Bus state controller MRA, MRB: SAR: DAR: CRA, CRB: DTCERA to DTCERE: DTCCR: DTCVBR: CHCR: DTC mode registers A, B DTC source address register DTC destination address register DTC transfer count registers A, B DTC enable registers A to E DTC control register DTC vector base register DMA channel control register [Legend] DTCERA to DTCERE DTCCR DTCVBR Activation control INTC DMAC DMAC activation source clear signal Figure 8.1 Block Diagram of DTC

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8.2 Register Descriptions

DTC has the following registers. For details on the addresses of these registers and the states of these registers in each processing state, see section 27, List of Registers. These six registers MRA, MRB, SAR, DAR, CRA, and CRB cannot be directly accessed by the CPU. The contents of these registers are stored in the data area as transfer information. When a DTC activation request occurs, the DTC reads a start address of transfer information that is stored in the data area according to the vector address, reads the transfer information, and transfers data. After the data transfer, it writes a set of updated transfer information back to the data area. On the other hand, DTCERA to DTCERE, DTCCR, and DTCVBR can be directly accessed by the CPU. Table 8.1 Register Configuration Register Name Abbrevia- tion R/W Initial Value Address Access Size DTC enable register A DTCERA R/W H'0000 H'FFFFCC80 8, 16 DTC enable register B DTCERB R/W H'0000 H'FFFFCC82 8, 16 DTC enable register C DTCERC R/W H'0000 H'FFFFCC84 8, 16 DTC enable register D DTCERD R/W H'0000 H'FFFFCC86 8, 16 DTC enable register E DTCERE R/W H'0000 H'FFFFCC88 8, 16 DTC control register DTCCR R/W H'00 H'FFFFCC90 8 DTC vector base register DTCVBR R/W H'00000000 H'FFFFCC94 8, 16, 32 Bus function extending register BSCEHR R/W H'0000 H'FFFFE89A 8, 16

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8.2.1 DTC Mode Register A (MRA)

MRA selects DTC operating mode. MRA cannot be accessed directly by the CPU. Bit: Initial value: R/W: 7654321 0 Bit Bit Name Initial Value R/W Description 7, 6 MD[1:0] Undefined ⎯ DTC Mode 1 and 0 Specify DTC transfer mode. 00: Normal transfer mode 01: Repeat transfer mode 10: Block transfer mode 11: Setting prohibited 5, 4 Sz[1:0] Undefined ⎯ DTC Data Transfer Size 1 and 0 Specify the size of data to be transferred. 00: Byte-size transfer 01: Word-size transfer 10: Longword-size transfer 11: Setting prohibited 3, 2 SM[1:0] Undefined ⎯ Source Address Mode 1 and 0 Specify an SAR operation after a data transfer. 0x: SAR is fixed (SAR writeback is skipped) 10: SAR is incremented after a transfer (by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10) 11: SAR is decremented after a transfer (by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10)

Section 8 Data Transfer Controller (DTC) R01UH0198EJ0500 Rev. 5.00 Page 175 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description 1, 0 ⎯ Undefined ⎯ Reserved The write value should always be 0. [Legend] x: Don't care

8.2.2 DTC Mode Register B (MRB)

MRB selects DTC operating mode. MRB cannot be accessed directly by the CPU. Bit: Initial value: R/W: 7654321 0 CHNE CHNS DISEL DTS DM[1:0] - - Bit Bit Name Initial Value R/W Description

7 CHNE Undefined ⎯ DTC Chain Transfer Enable

Specifies the chain transfer. For details, see section 8.5.6, Chain Transfer. The chain transfer condition is selected by the CHNS bit. 0: Disables the chain transfer 1: Enables the chain transfer

6 CHNS Undefined ⎯ DTC Chain Transfer Select

Specifies the chain transfer condition. If the following transfer is a chain transfer, the completion check of the specified transfer count is not performed and activation source flag or DTCER is not cleared. 0: Chain transfer every time 1: Chain transfer only when transfer counter = 0

Section 8 Data Transfer Controller (DTC) Page 176 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description

5 DISEL Undefined ⎯ DTC Interrupt Select

When this bit is set to 1, an interrupt request is generated to the CPU every time a data transfer or a block transfer ends. When this bit is set to 0, a CPU interrupt request is only generated when the specified number of data transfers end. Note: This bit should be cleared to 0 when the I C2 is selected as an activation source.

4 DTS Undefined ⎯ DTC Transfer Mode Select

Specifies either the source or destination as repeat or block area during repeat or block transfer mode. 0: Specifies the destination as repeat or block area 1: Specifies the source as repeat or block area 3, 2 DM[1:0] Undefined ⎯ Destination Address Mode 1 and 0 Specify a DAR operation after a data transfer. 0x: DAR is fixed (DAR writeback is skipped) 10: DAR is incremented after a transfer (by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10) 11: SAR is decremented after a transfer (by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10) 1, 0 ⎯ Undefined ⎯ Reserved The write value should always be 0. [Legend] x: Don't care

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8.2.3 DTC Source Address Register (SAR)

SAR is a 32-bit register that designates the source address of data to be transferred by the DTC. SAR cannot be accessed directly from the CPU. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 : Undefined*

8.2.4 DTC Destination Address Register (DAR)

DAR is a 32-bit register that designates the destination address of data to be transferred by the DTC. DAR cannot be accessed directly from the CPU. Bit: Initial value: R/W: Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 : Undefined*

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8.2.5 DTC Transfer Count Register A (CRA)

CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC. In normal transfer mode, CRA functions as a 16-bit transfer counter (1 to 65,536). It is decremented by 1 every time data is transferred, and bit DTCEn (n = 15 to 0) corresponding to the activation source is cleared and then an interrupt is requested to the CPU when the count reaches H'0000. The transfer count is 1 when CRA = H'0001, 65,535 when CRA = H'FFFF, and 65,536 when CRA = H'0000. In repeat transfer mode, CRA is divided into two parts: the upper eight bits (CRAH) and the lower eight bits (CRAL). CRAH holds the number of transfers while CRAL functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the contents of CRAH are sent to CRAL when the count reaches H'00. The transfer count is 1 when CRAH = CRAL = H'01, 255 when CRAH = CRAL = H'FF, and 256 when CRAH = CRAL = H'00. In block transfer mode, CRA is divided into two parts: the upper eight bits (CRAH) and the lower eight bits (CRAL). CRAH holds the block size while CRAL functions as an 8-bit block-size counter (1 to 256 for byte, word, or longword). CRAL is decremented by 1 every time a byte (word or longword) data is transferred, and the contents of CRAH are sent to CRAL when the count reaches H'00. The block size is 1 byte (word or longword) when CRAH = CRAL =H'01, 255 bytes (words or longwords) when CRAH = CRAL = H'FF, and 256 bytes (words or longwords) when CRAH = CRAL =H'00. CRA cannot be accessed directly from the CPU. Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 : Undefined*

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8.2.6 DTC Transfer Count Register B (CRB)

CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1 every time a block of data is transferred, and bit DTCEn (n = 15 to 0) corresponding to the activation source is cleared and then an interrupt is requested to the CPU when the count reaches H'0000. The transfer count is 1 when CRB = H'0001, 65,535 when CRB = H'FFFF, and 65,536 when CRB = H'0000. CRB is not available in normal and repeat modes and cannot be accessed directly by the CPU. Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 : Undefined*

Section 8 Data Transfer Controller (DTC) Page 180 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

8.2.7 DTC Enable Registers A to E (DTCERA to DTCERE)

DTCER which is comprised of eight registers, DTCERA to DTCERE, is a register that specifies DTC activation interrupt sources. The correspondence between interrupt sources and DTCE bits is shown in table 8.2. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W DTCE15 DTCE14 DTCE13 DTCE12 DTCE11 DTCE10 DTCE9 DTCE8 DTCE7 DTCE6 DTCE5 DTCE4 DTCE3 DTCE2 DTCE1 DTCE0 Bit Bit Name Initial Value R/W Description DTCE15 DTCE14 DTCE13 DTCE12 DTCE11 DTCE10 DTCE9 DTCE8 DTCE7 DTCE6 DTCE5 DTCE4 DTCE3 DTCE2 DTCE1 DTCE0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W DTC Activation Enable 15 to 0 If set to 1, the corresponding interrupt source is specified as a DTC activation source. [Clearing conditions]

• Writing 0 to the bit after reading 1 from it
• When the DISEL bit is 1 and the data transfer has ended
• When the specified number of transfers have ended These bits are not cleared when the DISEL bit is 0 and the specified number of transfers have not ended [Setting condition]
• Writing 1 to the bit after reading 0 from it

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8.2.8 DTC Control Register (DTCCR)

DTCCR specifies transfer information read skip. Bit: Initial value: R/W: 7654321 0 00000000 R R R R/W R/W R R R/(W) * Note: Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.* - - - RRS RCHNE - - ERR Bit Bit Name Initial Value R/W Description 7 to 5 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0.

4 RRS 0 R/W DTC Transfer Information Read Skip Enable

Controls the vector address read and transfer information read. A DTC vector number is always compared with the vector number for the previous activation. If the vector numbers match and this bit is set to 1, the DTC data transfer is started without reading a vector address and transfer information. If the previous DTC activation is a chain transfer, the vector address read and transfer information read are always performed. However, when the DTPR bit in the bus function extending register (BSCEHR) is set to 1, transfer information read skip is not performed regardless of the setting of this bit. 0: Transfer read skip is not performed. 1: Transfer read skip is performed when the vector numbers match.

3 RCHNE 0 R/W Chain Transfer Enable After DTC Repeat Transfer

Enables/disables the chain transfer while transfer counter (CRAL) is 0 in repeat transfer mode. In repeat transfer mode, the CRAH value is written to CRAL when CRAL is 0. Accordingly, chain transfer may not occur when CRAL is 0. If this bit is set to 1, the chain transfer is enabled when CRAH is written to CRAL. 0: Disables the chain transfer after repeat transfer 1: Enables the chain transfer after repeat transfer

Section 8 Data Transfer Controller (DTC) Page 182 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description 2, 1 ⎯ All 0 R Reserved These are read-only bits and cannot be modified.

0 ERR 0 R/(W) * Transfer Stop Flag

Indicates that the DTC address error or NMI interrupt request has occurred. If a DTC address error or NMI interrupt occurs while the DTC is active, address error handling or NMI interrupt handling processing is executed after the DTC has released the bus mastership. The DTC stops in the transfer information writing state after transferring data. 0: No interrupt occurs 1: An interrupt occurs [Clearing condition]

• When writing 0 after reading 1 Note: * Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.

Section 8 Data Transfer Controller (DTC) R01UH0198EJ0500 Rev. 5.00 Page 183 of 1560 Mar 18, 2011 SH7080 Group

8.2.9 DTC Vector Base Register (DTCVBR)

DTCVBR is a 32-bit register that specifies the base address for vector table address calculation. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000000000000000 R/W R/W R/W R/W R R R R R R R R R R R R Bit Bit Name Initial Value R/W Description 31 to 12 All 0 R/W 11 to 0 ⎯ All 0 R Bits 11 to 0 are always read as 0. The write value should always be 0.

8.2.10 Bus Function Extending Register (BSCEHR)

BSCEHR is a 16-bit register that specifies the timing of bus release by the DTC and other functions. This register can be used to give higher priority to the transfer by the DTC and configure the functions that can reduce the number of cycles over which the DTC is active. For more details, see section 9.4.8, Bus Function Extending Register (BSCEHR).

Section 8 Data Transfer Controller (DTC) Page 184 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

8.3 Activation Sources

The DTC is activated by an interrupt request. The interrupt source is selected by DTCER. A DTC activation source can be selected by setting the corresponding bit in DTCER; the CPU interrupt source can be selected by clearing the corresponding bit in DTCER. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the activation source interrupt flag or corresponding DTCER bit is cleared.

8.4 Location of Transfer Information and DTC Vector Table

Locate the transfer information in the data area. The start address of transfer information should be located at the address that is a multiple of four (4n). Otherwise, the lower two bits are ignored during access ([1:0] = B'00.) Transfer information located in the data area is shown in figure 8.2. Only in the case where all transfer sources/transfer destinations are in on-chip RAM and on-chip peripheral modules, short address mode can be selected by setting the DTSA bit in the bus function extending register (BSCEHR) to 1 (see section 9.4.8, Bus Function Extending Register (BSCEHR)). Normally, four longwords of transfer information has to be read. But if short address mode is selected, the size of transfer information is reduced to three longwords, which can shorten the period over which the DTC is active. The DTC reads the start address of the transfer information from the vector table for every activation source and reads the transfer information from this start address. Figure 8.3 shows correspondences between the DTC vector table and transfer information.

Section 8 Data Transfer Controller (DTC) Page 186 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 8.2 shows correspondence between the DTC activation source and vector address. Table 8.2 Interrupt Sources, DTC Vect or Addresses, and Corresponding DTCEs Origin of Activation Source Activation Source Vector Number DTC Vector Address Offset DTCE* Transfer Source Transfer Destination Priority External pin IRQ0 64 H'500 DTCERA15 Arbitrary * Arbitrary * High IRQ1 65 H'504 DTCERA14 Arbitrary * Arbitrary * IRQ2 66 H'508 DTCERA13 Arbitrary * Arbitrary * IRQ3 67 H'50C DTCERA12 Arbitrary * Arbitrary * IRQ4 68 H'510 DTCERA11 Arbitrary * Arbitrary * IRQ5 69 H'514 DTCERA10 Arbitrary * Arbitrary * IRQ6 70 H'518 DTCERA9 Arbitrary * Arbitrary * IRQ7 71 H'51C DTCERA8 Arbitrary * Arbitrary * MTU2_0 TGIA_0 88 H'560 DTCERB15 Arbitrary * Arbitrary * TGIB_0 89 H'564 DTCERB14 Arbitrary * Arbitrary * TGIC_0 90 H'568 DTCERB13 Arbitrary * Arbitrary * TGID_0 91 H'56C DTCERB12 Arbitrary * Arbitrary * MTU2_1 TGIA_1 96 H'580 DTCERB11 Arbitrary * Arbitrary * TGIB_1 97 H'584 DTCERB10 Arbitrary * Arbitrary * MTU2_2 TGIA_2 104 H'5A0 DTCERB9 Arbitrary * Arbitrary * TGIB_2 105 H'5A4 DTCERB8 Arbitrary * Arbitrary * MTU2_3 TGIA_3 112 H'5C0 DTCERB7 Arbitrary * Arbitrary * TGIB_3 113 H'5C4 DTCERB6 Arbitrary * Arbitrary * TGIC_3 114 H'5C8 DTCERB5 Arbitrary * Arbitrary * TGID_3 115 H'5CC DTCERB4 Arbitrary * Arbitrary * MTU2_4 TGIA_4 120 H'5E0 DTCERB3 Arbitrary * Arbitrary * TGIB_4 121 H'5E4 DTCERB2 Arbitrary * Arbitrary * TGIC_4 122 H'5E8 DTCERB1 Arbitrary * Arbitrary * TGID_4 123 H'5EC DTCERB0 Arbitrary * Arbitrary * TCIV_4 124 H'5F0 DTCERC15 Arbitrary * Arbitrary * Low

Section 8 Data Transfer Controller (DTC) R01UH0198EJ0500 Rev. 5.00 Page 187 of 1560 Mar 18, 2011 SH7080 Group Origin of Activation Source Activation Source Vector Number DTC Vector Address Offset DTCE * Transfer Source Transfer Destination Priority MTU2_5 TGIU_5 128 H'600 DTCERC14 Arbitrary * Arbitrary * High TGIV_5 129 H'604 DTCERC13 Arbitrary * Arbitrary * TGIW_5 130 H'608 DTCERC12 Arbitrary * Arbitrary * MTU2S_3 TGIA_3S 160 H'680 DTCERC3 Arbitrary * Arbitrary * TGIB_3S 161 H'684 DTCERC2 Arbitrary * Arbitrary * TGIC_3S 162 H'688 DTCERC1 Arbitrary * Arbitrary * TGID_3S 163 H'68C DTCERC0 Arbitrary * Arbitrary * MTU2S_4 TGIA_4S 168 H'6A0 DTCERD15 Arbitrary * Arbitrary * TGIB_4S 169 H'6A4 DTCERD14 Arbitrary * Arbitrary * TGIC_4S 170 H'6A8 DTCERD13 Arbitrary * Arbitrary * TGID_4S 171 H'6AC DTCERD12 Arbitrary * Arbitrary * TCIV_4S 172 H'6B0 DTCERD11 Arbitrary * Arbitrary * MTU2S_5 TGIU_5S 176 H'6C0 DTCERD10 Arbitrary * Arbitrary * TGIV_5S 177 H'6C4 DTCERD9 Arbitrary * Arbitrary * TGIW_5S 178 H'6C8 DTCERD8 Arbitrary * Arbitrary * CMT_0 CMI_0 184 H'6E0 DTCERD7 Arbitrary * Arbitrary * CMT_1 CMI_1 188 H'6F0 DTCERD6 Arbitrary * Arbitrary * A/D_0, A/D_1 ADI_0 200 H'720 DTCERD5 ADDR0 to ADDR3 Arbitrary* ADI_1 201 H'724 DTCERD4 ADDR4 to ADDR7 Arbitrary* A/D_2 ADI_2 204 H'730 DTCERD3 ADDR8 to ADDR15 Arbitrary* SCI_0 RXI_0 217 H'764 DTCERE15 SCRDR_0 Arbitrary * TXI_0 218 H'768 DTCERE14 Arbitrary * SCTDR_0 SCI_1 RXI_1 221 H'774 DTCERE13 SCRDR_1 Arbitrary * TXI_1 222 H'778 DTCERE12 Arbitrary * SCTDR_1 SCI_2 RXI_2 225 H'784 DTCERE11 SCRDR_2 Arbitrary * TXI_2 226 H'788 DTCERE10 Arbitrary * SCTDR_2 SCIF RXIF 229 H'794 DTCERE9 SCFRDR_3 Arbitrary * TXIF 231 H'79C DTCERE8 Arbitrary * SCFTDR_3 Low

Section 8 Data Transfer Controller (DTC) Page 188 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Origin of Activation Source Activation Source Vector Number DTC Vector Address Offset DTCE * Transfer Source Transfer Destination Priority SSU SSRXI 233 H'7A4 DTCERE7 SSRDR0 to SSRDR3 Arbitrary* High SSTXI 234 H'7A8 DTCERE6 Arbitrary * SSTDR0 to SSTDR3 I C2 IITXI 238 H'7B8 DTCERE5 Arbitrary * ICDRT IIRXI 239 H'7BC DTCERE4 ICDRR Arbitrary * Low Notes: 1. The DTCE bits with no corresponding interrupt are reserved, and the write value should always be 0. To leave software standby mode with an interrupt, write 0 to the corresponding DTCE bit. 2. An external memory, a memory-mapped external device, an on-chip memory, or an on- chip peripheral module (except DMAC, DTC, BSC, UBC, and FLASH) can be selected as the source or destination. Note that at least either the source or destination must be an on-chip peripheral module; transfer cannot be done among an external memory, a memory-mapped external device, and an on-chip memory.

Section 8 Data Transfer Controller (DTC) R01UH0198EJ0500 Rev. 5.00 Page 189 of 1560 Mar 18, 2011 SH7080 Group

8.5 Operation

There are three transfer modes: normal, repeat, and block transfer modes. Since transfer information is in the data area, it is possible to transfer data over any required number of channels. When activated, the DTC reads transfer information stored in the data are and transfers data according to the transfer information. After the data transfer is complete, it writes updated transfer information back to the data area. The DTC specifies the source address and destination address in SAR and DAR, respectively. After a transfer, SAR and DAR are incremented, decremented, or fixed independently. Table 8.3 shows the DTC transfer modes. Table 8.3 DTC Transfer Modes Transfer Mode Size of Data Transferred at One Transfer Request Memory Address Increment or Decrement Transfer Count Normal 1 byte/word/longword Incremented/decremented by 1, 2, or 4, or fixed 1 to 65536 Repeat* 1 byte/word/longword Incremented/decremented by 1, 2, or 4, or fixed 1 to 256* Block* Block size specified by CRAH (1 to 256 bytes/words/longwords) Incremented/decremented by 1, 2, or 4, or fixed 1 to 65536* Notes: 1. Either source or desti nation is specified to repeat area. 2. Either source or destination is specified to block area. 3. After transfer of the specified transfer c ount, initial state is recovered to continue the operation. 4. Number of transfers of the specified block size of data. Setting the CHNE bit in MRB to 1 makes it possible to perform a number of transfers with a single activation (chain transfer). Setting the CHNS bit in MRB to 1 can also be made to have chain transfer performed only when the transfer counter value is 0. Figure 8.4 shows a flowchart of DTC operation, and table 8.4 summarizes the conditions for DTC transfers including chain transfer (combinations for performing the second and third transfers are omitted).

Section 8 Data Transfer Controller (DTC) Page 190 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Start Match & RRS = 1 Not match | RRS = 0 Next transfer Read transfer information Transfer data Update transfer information Update the start address of transfer information Write transfer information CHNE = 1 Transfer counter = 0 or DISEL = 1 Clear activation source flag End CHNS = 0 Transfer counter = 0 DISEL = 1 Clear DTCER/request an interrupt to the CPU No No No No No Yes Yes Yes Yes Yes Vector number comparison Read DTC vector Figure 8.4 Flowchart of DTC Operation

Section 8 Data Transfer Controller (DTC) R01UH0198EJ0500 Rev. 5.00 Page 191 of 1560 Mar 18, 2011 SH7080 Group Table 8.4 DTC Transfer Conditions (Chain Transfer Conditions Included) 1st Transfer 2nd Transfer Transfer Mode CHNE CHNS RCHNE DISEL Transfer Counter* CHNE CHNS RCHNE DISEL Transfer Counter* DTC Transfer 0 ⎯ ⎯ 0 Not 0 ⎯ ⎯ ⎯ ⎯ ⎯ Ends at 1st transfer Ends at 1st transfer Interrupt request to CPU 1 0 ⎯ ⎯ ⎯ 0 ⎯ ⎯ 0 Not 0 Ends at 2nd transfer 0 ⎯ ⎯ 0 0 0 ⎯ ⎯ 1 ⎯ Ends at 2nd transfer Interrupt request to CPU 1 1 ⎯ 0 Not 0 ⎯ ⎯ ⎯ ⎯ ⎯ Ends at 1st transfer 1 1 ⎯ 1 Not 0 ⎯ ⎯ ⎯ ⎯ ⎯ Ends at 1st transfer Interrupt request to CPU 1 1 ⎯ ⎯ 0 0 ⎯ ⎯ 0 Not 0 Ends at 2nd transfer Normal 0 ⎯ ⎯ 0 0 0 ⎯ ⎯ 1 ⎯ Ends at 2nd transfer Interrupt request to CPU

Section 8 Data Transfer Controller (DTC) Page 192 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group 1st Transfer 2nd Transfer Transfer Mode CHNE CHNS RCHNE DISEL Transfer Counter* CHNE CHNS RCHNE DISEL Transfer Counter* DTC Transfer transfer transfer Interrupt request to CPU 1 0 ⎯ ⎯ ⎯ 0 ⎯ ⎯ 0 ⎯ Ends at 2nd transfer 0 ⎯ ⎯ 1 ⎯ Ends at 2nd transfer Interrupt request to CPU 1 1 ⎯ 0 Not 0 ⎯ ⎯ ⎯ ⎯ ⎯ Ends at 1st transfer 1 1 ⎯ 1 Not 0 ⎯ ⎯ ⎯ ⎯ ⎯ Ends at 1st transfer Interrupt request to CPU 1 1 0 0 0 * transfer 1 1 0 1 0 * transfer Interrupt request to CPU Repeat 1 1 1 ⎯ 0 * 0 ⎯ ⎯ 0 ⎯ Ends at 2nd transfer 0 ⎯ ⎯ 1 ⎯ Ends at 2nd transfer Interrupt request to CPU

Section 8 Data Transfer Controller (DTC) R01UH0198EJ0500 Rev. 5.00 Page 193 of 1560 Mar 18, 2011 SH7080 Group 1st Transfer 2nd Transfer Transfer Mode CHNE CHNS RCHNE DISEL Transfer Counter* CHNE CHNS RCHNE DISEL Transfer Counter* DTC Transfer 0 ⎯ ⎯ 0 Not 0 ⎯ ⎯ ⎯ ⎯ ⎯ Ends at 1st transfer Ends at 1st transfer Interrupt request to CPU 1 0 ⎯ ⎯ ⎯ 0 ⎯ ⎯ 0 Not 0 Ends at 2nd transfer 0 ⎯ ⎯ 0 0 0 ⎯ ⎯ 1 ⎯ Ends at 2nd transfer Interrupt request to CPU transfer 1 1 ⎯ 1 Not 0 ⎯ ⎯ ⎯ ⎯ ⎯ Ends at 1st transfer Interrupt request to CPU 1 1 ⎯ 1 0 0 ⎯ ⎯ 0 Not 0 Ends at 2nd transfer Block 0 ⎯ ⎯ 0 0 0 ⎯ ⎯ 1 ⎯ Ends at 2nd transfer Interrupt request to CPU Notes: 1. CRA in normal mode transfer, CRAL in re peat transfer mode, or CRB in block transfer mode 2. When the contents of the CRAH is written to the CRAL in repeat transfer mode

Section 8 Data Transfer Controller (DTC) Page 194 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

8.5.1 Transfer Information Read Skip Function

By setting the RRS bit of DTCCR, the vector address read and transfer information read can be skipped. The current DTC vector number is always compared with the vector number of previous activation. If the vector numbers match when RRS = 1, a DTC data transfer is performed without reading the vector address and transfer information. If the previous activation is a chain transfer, the vector address read and transfer information read are always performed. Figure 8.5 shows the transfer information read skip timing. To modify the vector table and transfer information, temporarily clear the RRS bit to 0, modify the vector table and transfer information, and then set the RRS bit to 1 again. When the RRS bit is cleared to 0, the stored vector number is deleted, and the updated vector table and transfer information are read at the next activation. If the DTPR bit in the bus function extending register (BSCEHR) is set to 1, this function is always disabled. Vector read Transfer information read Data transfer Transfer information write Data transfer Transfer information write Note: The DTC request signal indicates the state of internal bus request after the DTC activation source has been determined. Internal address DTC activation request DTC request Skip transfer information read Clock (Bφ) RW RW Figure 8.5 Transfer Information Read Skip Timing (Activated by On-Chip Peripheral Module; Iφ: Bφ: Pφ =1: 1/2: 1/2; Data Transferred from On-Chip Peripheral Module to On-Chip RAM; Transfer Information Is Written in 3 States)

Section 8 Data Transfer Controller (DTC) R01UH0198EJ0500 Rev. 5.00 Page 195 of 1560 Mar 18, 2011 SH7080 Group

8.5.2 Transfer Information Writeback Skip Function

By specifying bit SM1 in MRA and bit DM1 in MRB to the fixed address mode, a part of transfer information will not be written back. Table 8.5 shows the transfer information writeback skip condition and writeback skipped registers. Note that the CRA and CRB are always written back. The writeback of the MRA and MRB are always skipped. Table 8.5 Transfer Information Writeback Skip Condition and Writeback Skipped Registers SM1 DM1 SAR DAR 0 0 Skipped Skipped 0 1 Skipped Written back 1 0 Written back Skipped 1 1 Written back Written back

8.5.3 Normal Transfer Mode

In normal transfer mode, data are transferred in one byte, one word, or one longword units in response to a single activation request. From 1 to 65,536 transfers can be specified. The transfer source and destination addresses can be specified as incremented, decremented, or fixed. When the specified number of transfers ends, an interrupt can be requested to the CPU. Table 8.6 lists the register function in normal transfer mode. Figure 8.6 shows the memory map in normal transfer mode. Table 8.6 Register Function in Normal Transfer Mode Register Function Written Back Value SAR Source address Incremented/decremented/fixed * DAR Destination address Incremented/decremented/fixed * CRA Transfer count A CRA − 1 CRB Transfer count B Not updated Note: * Transfer information writeback is skipped.

Section 8 Data Transfer Controller (DTC) Page 196 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group SAR Transfer source data area DAR Transfer Transfer destination data area Figure 8.6 Memory Map in Normal Transfer Mode

8.5.4 Repeat Transfer Mode

In repeat transfer mode, data are transferred in one byte, one word, or one longword units in response to a single activation request. By the DTS bit in MRB, either the source or destination can be specified as a repeat area. From 1 to 256 transfers can be specified. When the specified number of transfers ends, the transfer counter and address register specified as the repeat area is restored to the initial state, and transfer is repeated. The other address register is then incremented, decremented, or left fixed. In repeat transfer mode, the transfer counter (CRAL) is updated to the value specified in CRAH when CRAL becomes H'00. Thus the transfer counter value does not reach H'00, and therefore a CPU interrupt cannot be requested when DISEL = 0. Table 8.7 lists the register function in repeat transfer mode. Figure 8.7 shows the memory map in repeat transfer mode.

Section 8 Data Transfer Controller (DTC) R01UH0198EJ0500 Rev. 5.00 Page 197 of 1560 Mar 18, 2011 SH7080 Group Table 8.7 Register Function in Repeat Transfer Mode Written Back Value Register Function CRAL is not 1 CRAL is 1 SAR Source address Incremented/decremented/fixed * DTS = 0: Incremented/ decremented/fixed* DTS = 1: SAR initial value DAR Destination address Incremented/decremented/fixed * DTS = 0: DAR initial value DTS = 1: Incremented/ decremented/fixed* CRAH Transfer count storage CRAH CRAH CRAL Transfer count A CRAL − 1 CRAH CRB Transfer count B Not updated Not updated Note: * Transfer information writeback is skipped. SAR Transfer source data area (specified as repeat area) DAR Transfer Transfer destination data area Figure 8.7 Memory Map in Repeat Transfer Mode (When Transfer Source Is Specified as Repeat Area)

Section 8 Data Transfer Controller (DTC) Page 198 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

8.5.5 Block Transfer Mode

In block transfer mode, data are transferred in block units in response to a single activation request. Either the transfer source or the transfer destination is designated as a block area by the DTS bit in MRB. The block size is 1 to 256 bytes (1 to 256 words, or 1 to 256 longwords). When the block data transfer of one block ends, the block size counter (CRAL) and address register (SAR when DTS = 1 or DAR when DTS = 0) specified as the block area is restored to the initial state. The other address register is then incremented, decremented, or left fixed. From 1 to 65,536 transfers can be specified. When the specified number of transfers ends, an interrupt is requested to the CPU. Table 8.8 lists the register function in block transfer mode. Figure 8.8 shows the memory map in block transfer mode. Table 8.8 Register Function in Block Transfer Mode Register Function Written Back Value SAR Source address DTS = 0: Incremented/decremented/fixed * DTS = 1: SAR initial value DAR Destination address DTS = 0: DAR initial value DTS = 1: Incremented/decremented/fixed* CRAH Block size storage CRAH CRAL Block size counter CRAH CRB Block transfer counter CRB − 1 Note: * Transfer information writeback is skipped.

Section 8 Data Transfer Controller (DTC) R01UH0198EJ0500 Rev. 5.00 Page 199 of 1560 Mar 18, 2011 SH7080 Group Transfer source data area Transfer destination data area (specified as block area) Block area DAR SAR Transfer1st block Nth block Figure 8.8 Memory Map in Block Transfer Mode (When Transfer Destination Is Specified as Block Area)

8.5.6 Chain Transfer

Setting the CHNE bit in MRB to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. Setting the CHNE and CHNS bits in MRB set to 1 enables a chain transfer only when the transfer counter reaches 0. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 8.9 shows the chain transfer operation. In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the end of the specified number of transfers or by setting the DISEL bit to 1, and the interrupt source flag for the activation source and DTCER are not affected. In repeat transfer mode, setting the RCHNE bit in DTCCR and the CHNE and CHNS bits in MRB to 1 enables a chain transfer after transfer with transfer counter = 1 has been completed.

Section 8 Data Transfer Controller (DTC) Page 200 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Transfer information CHNE = 1 Transfer information CHNE = 0 Transfer information stored in user area Data area Transfer source data (1) Transfer destination data (1) Transfer source data (2) Transfer destination data (2) Transfer information start address Vector table DTC vector address Figure 8.9 Operation of Chain Transfer

Section 8 Data Transfer Controller (DTC) R01UH0198EJ0500 Rev. 5.00 Page 201 of 1560 Mar 18, 2011 SH7080 Group

8.5.7 Operation Timing

Figures 8.10 to 8.15 show the DTC operation timings. Internal address Vector read Transfer information read Data transfer Transfer information write Note: The DTC request signal indicates the state of internal bus request after the DTC activation source has been determined. DTC activation request DTC request Clock (Bφ) RW Figure 8.10 Example of DTC Operation Timing: Normal Transfer Mode or Repeat Transfer Mode (Activated by On-Chip Peripheral Module; Iφ: Bφ: Pφ =1: 1/2: 1/2; Data Transferred from On-Chip Peripheral Module to On-Chip RAM; Transfer Information Is Written in 3 Cycles) Internal address Vector read Transfer information read Data transfer Transfer information write Note: The DTC request signal indicates the state of internal bus request after the DTC activation source has been determined. DTC activation request DTC request Clock (Bφ) RW RW Figure 8.11 Example of DTC Operation Timing: Block Transfer Mode with Block Size = 2 (Activated by On-Chip Peripheral Module; Iφ: Bφ: Pφ =1: 1/2: 1/2; Data Transferred from On-Chip Peripheral Module to On-Chip RAM; Transfer Information Is Written in 3 Cycles)

Section 8 Data Transfer Controller (DTC) Page 204 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

8.5.8 Number of DTC Execution Cycles

Table 8.9 shows the execution status for a single DTC data transfer, and table 8.10 shows the number of cycles required for each execution. Table 8.9 DTC Execution Status Mode Vector Read I Transfer Information Read J Transfer Information Write K Data Read L Data Write M Internal Operation N Normal 1 0 * 4 3 * 0 * 3 2 * 1 * 1 1 1 0 * Repeat 1 0 * 4 3 * 0 * 3 2 * 1 * 1 1 1 0 * Block transfer 1 0 * 4 3 * 0 * 3 2 * 1 * 1•P 1P 1 0 * [Legend] P: Block size (initial setting of CRAH and CRAL) Notes: 1. When transfer information read is skipped 2. When the SAR or DAR is in fixed mode 3. When the SAR and DAR are in fixed mode 4. When short address mode

Section 8 Data Transfer Controller (DTC) R01UH0198EJ0500 Rev. 5.00 Page 205 of 1560 Mar 18, 2011 SH7080 Group Table 8.10 Number of Cycles Requ ired for Each Execution State Object to be Accessed On-Chip RAM* /ROM* On-Chip I/O Registers External Devices * Bus width 32 bits 8 bits * 16 bits 8 bits 16 bits 32 bits Access cycles 1B φ to 3Bφ* 2P φ 2P φ 2B φ 2B φ 2B φ Vector read SI 1B φ to 3Bφ* ⎯ ⎯ 9B φ 5B φ 3B φ Transfer information read SJ 1B φ to 3Bφ* ⎯ ⎯ 9B φ 5B φ 3B φ Execu- tion status Transfer information write Sk 1B φ to 3Bφ* ⎯ ⎯ 2B φ* 2B φ* 2B φ* Byte data read S L 1B φ to 3Bφ* 1B φ + 2Pφ* 1B φ + 2Pφ* 3B φ 3B φ 3B φ Word data read S L 1B φ to 3Bφ* ⎯ 1B φ + 2Pφ* 5B φ 3B φ 3B φ Longword data read S L 1B φ to 3Bφ* ⎯ 1B φ + 4Pφ* 9B φ 5B φ 3B φ Byte data write S M 1B φ to 3Bφ* 1B φ + 2Pφ* 1B φ + 2Pφ* 2B φ* 2B φ* 2B φ* Word data write S M 1B φ to 3Bφ* ⎯ 1B φ + 2Pφ* 2B φ* 2B φ* 2B φ* Longword data write S M 1B φ to 3Bφ* ⎯ 1B φ + 4Pφ* 2B φ* 2B φ* 2B φ* Internal operation S N 1 Notes: 1. Values for on-chip RAM. Number of cycles varies depending on the ratio of I φ:Bφ. Read Write I φ:Bφ = 1:1 3B φ 3B φ I φ:Bφ = 1:1/2 2B φ 1B φ I φ:Bφ = 1:1/3 2B φ 1B φ I φ:Bφ = 1:1/4 or less 1B φ 1B φ 2. Values for on-chip ROM. Number of cycles varies depending on the ratio of I φ:Bφ.and are the same as on-chip RAM. Only vector read is possible. 3. The values in the table are those for the fastest case. Depending on the state of the internal bus, replace 1Bφ by 1Pφ in a slow case. 4. This applies to the I C2. 5. Values are different depending on the BSC register setting. The values in the table are the sample for the case with no wait cycles and the WM bit in CSnWCR = 1. 6. Values are different depending on the bus state. The number of cycles increases when many external wait cycles are inserted in the case where writing is frequently executed, such as block transfer, and when the external bus is in use because the write buffer cannot be used efficiently in such cases. For details on the write buffer, see section 9.5.14 (2), Access in View of LSI Internal Bus Master.

Section 8 Data Transfer Controller (DTC) Page 206 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group The number of execution cycles is calculated from the formula below. Note that Σ means the sum of cycles for all transfers initiated by one activation event (the number of 1-valued CHNE bits in transfer information plus 1). Number of execution cycles = I • SI + Σ (J • SJ + K • SK + L • SL + M • SM) + N • SN

8.5.9 DTC Bus Release Timing

The DTC requests the bus mastership to the bus arbiter when an activation request occurs. The DTC releases the bus after a vector read, NOP cycle generation after a vector read, transfer information read, a single data transfer, or transfer information writeback. The DTC does not release the bus mastership during transfer information read, single data transfer, or transfer information writeback. The bus release timing can be specified through the bus function extending register (BSCEHR). For details see section 9.4.8, Bus Function Extending Register (BSCEHR). The difference in bus release timing according to the register setting is summarized in table 8.11. Settings other than settings 1 to 5 are not allowed. The setting must not be changed while the DTC is active. Figure 8.16 is a timing chart showing an example of bus release timing.

Section 8 Data Transfer Controller (DTC) R01UH0198EJ0500 Rev. 5.00 Page 207 of 1560 Mar 18, 2011 SH7080 Group Table 8.11 DTC Bus Release Timing Bus Function Extending Register (BSCEHR) Setting Bus Release Timing (O: Bus is released; x: Bus is not released) After write-back of transfer information Setting DTLOCK CSSTP1 CSSTP2 CSSTP3 DTBST After vector read NOP cycle generation* After transfer information read After a single data transfer Normal transfer Continuous transfer Setting 1 1 0 * 1 0 O O O O O O Setting 2 0 0 0 * 0 x O x x O O Setting 3 0 1 * 0 x x x x O O Setting 4* 0 1 * 1 x x x x O x Setting 5 1 1 * 1 0 O x O O O O Notes: 1. The bus mastership is only released for the external space access request from the CPU after a vector read. 2. There are following restrictions in setting 4.

• Clock setting by the frequency control register (FRQCR) must be Iφ:Bφ:Pφ:MIφ:MPφ = 8:4:4:4:4, 4:2:2:2:2, or 2:1:1:1:1.
• Locate vector information in on-chip ROM or on-chip RAM.
• Locate transfer information in on-chip RAM.
• Transfer is allowed between on-chip RAM and on-chip peripheral module or between external memory and on-chip peripheral module. 3. Don't care.

Section 8 Data Transfer Controller (DTC) Page 208 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Vector read Transfer information read Data transfer Transfer information write Vector read Transfer information read Data transfer Transfer information write Note: DTC request signal indicates the state of internal bus request after the DTC activation source is determined. [Legend] Clock (Bφ) Internal address : Indicates bus release timing. : Bus mastership is only released for the external access request from the CPU. DTC activation request 2 DTC request Bus release timing [setting 1] Bus release timing [setting 2] Bus release timing [setting 3] Bus release timing [setting 5] Bus release timing [setting 4] DTC activation request 1 R W R W Figure 8.16 Example of DTC Operation Timing: Conflict of Two Activation Requests in Normal Transfer Mode (Activated by On-Chip Peripheral Module; Iφ: Bφ: Pφ = 1: 1/2: 1/2; Data Transferred from On-Chip Peripheral Module to On-Chip RAM; Transfer Information Is Written in 3 Cycles)

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8.5.10 DTC Activation Priority Order

In the case where multiple DTC activation requests are generated while the DTC is inactive, it is selectable whether the DTC starts transfer in the order of activation request generation or in the order of priority for DTC activation. This selection is made by the setting of the DTPR bit in the bus function extending register (BSCEHR). On the other hand, if multiple activation requests are generated while the DTC is active, transfer is performed according to the priority order for DTC activation. Figure 8.17 shows an example of DTC activation according to the priority. Transfer is started for the request that is generated first Transfer is performed according to the priority Internal bus Priority determination Priority determination Priority determination Other than DTC DTC is inactive DTC is active DTC (request 3) DTC (request 1) DTC (request 2) Other than DTC DTC (request 1) DTC (request 2) DTC (request 3) DTC activation request 1 (High priority) DTC activation request 1 (High priority) (1) DTPR = 0 DTC activation request 2 (Medium priority) DTC activation request 2 (Medium priority) DTC activation request 3 (Low priority) DTC activation request 3 (Low priority) Transfer is performed according to the priority Transfer is performed according to the priority Internal bus DTC is inactive DTC is active(2) DTPR =1 Figure 8.17 Example of DTC Activation in Accordance with Priority

Section 8 Data Transfer Controller (DTC) Page 210 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

8.6 DTC Activation by Interrupt

The procedure for using the DTC with interrupt activation is shown in figure 8.18. Clearing the RRS bit in DTCCR to 0 clears the read skip flag of transfer information. Read skip is not performed when the DTC is activated after clearing the RRS bit. When updating transfer information, the RRS bit must be cleared. Set the MRA, MRB, SAR, DAR, CRA, and CRB transfer information in the data area. For details on setting transfer information, see section 8.2, Register Descriptions. For details on location of transfer information, see section 8.4, Location of Transfer Information and DTC Vector Table. Set the start address of the transfer information in the DTC vector table. For details on setting DTC vector table, see section 8.4, Location of Transfer Information and DTC Vector Table. Setting the RRS bit to 1 performs a read skip of second time or later transfer information when the DTC is activated consecu- tively by the same interrupt source. Setting the RRS bit to 1 is always allowed. However, the value set during transfer will be valid from the next transfer. Set the bit in DTCER corresponding to the DTC activation interrupt source to 1. For the correspondence of interrupts and DTCER, refer to table 8.2. The bit in DTCER may be set to 1 on the second or later transfer. In this case, setting the bit is not needed. Set the enable bits for the interrupt sources to be used as the activation sources to 1. The DTC is activated when an interrupt used as an activation source is generated. For details on the settings of the interrupt enable bits, see the corresponding descriptions of the corresponding module. After the end of one data transfer, the DTC clears the activation source flag or clears the corresponding bit in DTCER and requests an interrupt to the CPU. The operation after transfer depends on the transfer information. For details, see section 8.2, Register Descriptions and figure 8.4. DTC activation by interrupt Clear RRS bit in DTCCR to 0 Set transfer information (MRA, MRB, SAR, DAR, CRA, CRB) Set starts address of transfer information in DTC vector table Set RRS bit in DTCCR to 1 Set corresponding bit in DTCER to 1 Set enable bit of interrupt request for activation source to 1 Interrupt request generated DTC activated Corresponding bit in DTCER cleared or CPU interrupt requested Transfer end [1] [2] [3] [4] [5] [6] [7] [1] [2] [3] [4] [5] [6] [7] Determine clearing method of activation source Clear activation source Clear corresponding bit in DTCER Figure 8.18 Activation of DTC by Interrupt

Section 8 Data Transfer Controller (DTC) R01UH0198EJ0500 Rev. 5.00 Page 211 of 1560 Mar 18, 2011 SH7080 Group

8.7 Examples of Use of the DTC

8.7.1 Normal Transfer Mode

An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. 1. Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal transfer mode (MD1 = MD0 = 0), and byte size (Sz1 = Sz0 = 0). The DTS bit can have any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set the RDR address of the SCI in SAR, the start address of the RAM area where the data will be received in DAR, and 128 (H'0080) in CRA. CRB can be set to any value. 2. Set the start address of the transfer information for an RXI interrupt at the DTC vector address. 3. Set the corresponding bit in DTCER to 1. 4. Set the SCI to the appropriate receive mode. Se t the RIE bit in SCR to 1 to enable the receive end (RXI) interrupt. Since the generation of a receive error during the SCI reception operation will disable subsequent reception, the CPU should be enabled to accept receive error interrupts. 5. Each time reception of one byte of data ends on the SCI, the RDRF flag in SSR is set to 1, an RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR to RAM by the DTC. DAR is incremented and CRA is decremented. The RDRF flag is automatically cleared to 0. 6. When CRA becomes 0 after the 128 data transfers have ended, the RDRF flag is held at 1, the DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. Termination processing should be performed in the interrupt handling routine.

8.7.2 Chain Transfer when Counter = 0

By executing a second data transfer and performing re-setting of the first data transfer only when the counter value is 0, it is possible to perform 256 or more repeat transfers. An example is shown in which a 128-kbyte input buffer is configured. The input buffer is assumed to have been set to start at lower address H'0000. Figure 8.19 shows the chain transfer when the counter value is 0. 1. For the first transfer, set the normal transfer mode for input data. Set the fixed transfer source address, CRA = H'0000 (65,536 times), CHNE = 1, CHNS = 1, and DISEL = 0. 2. Prepare the upper 8-bit addresses of the start addresses for 65,536-transfer units for the first data transfer in a separate area (in ROM, etc.). For example, if the input buffer is configured at addresses H'200000 to H'21FFFF, prepare H'21 and H'20.

Section 8 Data Transfer Controller (DTC) Page 212 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group 3. For the second transfer, set repeat transfer mode (with the source side as the repeat area) for re- setting the transfer destination address for the first data transfer. Use the upper eight bits of DAR in the first transfer information area as the transfer destination. Set CHNE = DISEL = 0. If the above input buffer is specified as H'200000 to H'21FFFF, set the transfer counter to 2. 4. Execute the first data transfer 65536 times by means of interrupts. When the transfer counter for the first data transfer reaches 0, the second data transfer is started. Set the upper eight bits of the transfer destination address for the first data transfer to H'21. The lower 16 bits of the transfer destination address of the first data transfer and the transfer counter are H'0000. 5. Next, execute the first data transfer the 6553 6 times specified for the first data transfer by means of interrupts. When the transfer counter for the first data transfer reaches 0, the second data transfer is started. Set the upper eight bits of the transfer destination address for the first data transfer to H'20. The lower 16 bits of the transfer destination address of the first data transfer and the transfer counter are H'0000. 6. Steps 4 and 5 are repeated endlessly. As repeat mode is specified for the second data transfer, no interrupt request is sent to the CPU. 1st data transfer information 2nd data transfer information Transfer information located on the on-chip memory Chain transfer (counter = 0) Input circuit Input buffer Upper 8 bits of DAR Figure 8.19 Chain Transfer when Counter = 0

Section 8 Data Transfer Controller (DTC) R01UH0198EJ0500 Rev. 5.00 Page 213 of 1560 Mar 18, 2011 SH7080 Group

8.8 Interrupt Sources

An interrupt request is issued to the CPU when the DTC finishes the specified number of data transfers, or on completion of a single data transfer or a single block data transfer with the DISEL bit set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and priority level control in the interrupt controller. For details, refer to section 6.8, Data Transfer with Interrupt Request Signals.

8.9 Usage Notes

8.9.1 Module Standby Mode Setting

Operation of the DTC can be disabled or enabled using the standby control register. The initial setting is for operation of the DTC to be disabled. DTC operation is disabled in module standby mode but register access is available. Module standby mode cannot be set while the DTC is activated. Before entering software standby mode or module standby mode, all DTCER registers must be cleared. For details, refer to section 26, Power-Down Modes.

8.9.2 On-Chip RAM

Transfer information can be located in on-chip RAM. In this case, the RAME bit in RAMCR must not be cleared to 0.

8.9.3 DTCE Bit Setting

To set a DTCE bit, disable the corresponding interrupt, read 0 from the bit, and then write 1 to it. While DTC transfer is in progress, do not modify the DTCE bits.

8.9.4 Chain Transfer

When chain transfer is used, clearing of the activation source or DTCER is performed when the last of the chain of data transfers is executed. SCI, SCIF, SSU, I C2, and A/D converter interrupt/activation sources, on the other hand, are cleared when the DTC reads or writes to the relevant register.

Section 8 Data Transfer Controller (DTC) Page 214 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

8.9.5 Transfer Information Start Address, Source Address, and Destination Address

The transfer information start address to be specified in the vector table should be address 4n. Transfer information should be placed in on-chip RAM or external memory space.

8.9.6 Access to DMAC or DTC Registers through DTC

Do not access the DMAC or DTC registers by using DTC operation. Do not access the DTC registers by using DMAC operation.

8.9.7 Notes on IRQ Interrupt as DTC Activation Source

• The IRQ interrupt specified as a DTC activation source must not be used to cancel software standby mode.
• The IRQ edge input in software standby mode must not be specified as a DTC activation source.
• When a low level on the IRQ pin is to be detected, if the end of DTC transfer is used to request an interrupt to the CPU (transfer counter = 0 or DISEL = 1), the IRQ signal must be kept low until the CPU accepts the interrupt.

8.9.8 Notes on SCI and SCIF as DTC Activation Sources

• When the TXI interrupt from the SCI is specified as a DTC activation source, the TEND flag in the SCI must not be used as the transfer end flag.
• When the TXIF interrupt from the SCIF is specified as a DTC activation source, the TEND flag in the SCIF must not be used as the transfer end flag.

8.9.9 Clearing Interrupt Source Flag

The interrupt source flag set when the DTC transfer is completed should be cleared in the interrupt handler in the same way as for general interrupt source flags. For details, refer to section 6.9, Usage Note.

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8.9.10 Conflict between NMI Interrupt and DTC Activation

When a conflict occurs between the generation of the NMI interrupt and the DTC activation, the NMI interrupt has priority. Thus the ERR bit is set to 1 and the DTC is not activated. It takes 1 × Bcyc + 3 × Pcyc for determining DTC stop by NMI, 2 × Bcyc for determining DTC activation by IRQ, and 1 × Pcyc for determining DTC activation by peripheral modules.

8.9.11 Operation when a DTC Activation Request Is Cancelled While in Progress

Once the DTC has accepted an activation request, the DTC does not accept the next activation request until the sequence of DTC processing that ends with writeback has been completed.

Section 8 Data Transfer Controller (DTC) Page 216 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 217 of 1560 Mar 18, 2011 SH7080 Group Section 9 Bus State Controller (BSC) The bus state controller (BSC) outputs control signals for various types of memory that is connected to the external address space and external devices. BSC functions enable this LSI to connect directly with SRAM, SDRAM, and other memory storage devices, and external devices.

9.1 Features

1. External address space ⎯ A maximum 64 Mbytes for each of eight areas, CS0 to CS7, and a maximum 1 Gbyte for the CS8 area ⎯ Can specify the normal space interface, SRAM interface with byte selection, burst ROM (clock synchronous or asynchronous), MPX-I/O, burst MPX-I/O, SDRAM, or PCMCIA for each address space ⎯ Can select the data bus width (8, 16, or 32 bits) for each address space ⎯ Controls the insertion of the wait state for each address space. ⎯ Controls the insertion of the wait state for each read access and write access ⎯ Can set the independent idling cycle in the continuous access for five cases: read-write (in same space/different space), read-read (in same space/different space), the first cycle is a write access. 2. Normal space interface ⎯ Supports the interface that can directly connect to the SRAM 3. Burst ROM interface (clock asynchronous) ⎯ High-speed access to the ROM that has the page mode function 4. MPX-I/O interface ⎯ Directly connects peripheral LSIs with address/data multiplexing 5. SDRAM interface ⎯ Can set the SDRAM up to 2 areas ⎯ Multiplex output for row address/column address ⎯ Efficient access by single read/single write ⎯ High-speed access by bank-active mode ⎯ Supports an auto-refresh and self-refresh 6. SRAM interface with byte selection ⎯ Supports interfaces that can be connected directly to SRAM with byte selection

Section 9 Bus State Controller (BSC) Page 218 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group 7. PCMCIA direct interface ⎯ Supports the IC memory card and I/O card interface defined in JEIDA specifications Ver. 4.2 (PCMCIA2.1 Rev. 2.1) ⎯ Wait-cycle insertion controllable by program 8. Burst MPX-I/O interface ⎯ Directly connects peripheral LSIs with address/data multiplexing ⎯ Supports burst transfer 9. Burst ROM (clock synchronous) interface ⎯ Directly connects clock-synchronous burst ROM 10. Refresh function ⎯ Supports the auto-refresh and self-refresh functions ⎯ Specifies the refresh interval using the refresh counter and clock selection ⎯ Can execute concentrated refresh by specifying the refresh counts (1, 2, 4, 6, or 8) 11. Usage as interval timer for refresh counter ⎯ Generates an interrupt request at compare match

Section 9 Bus State Controller (BSC) Page 220 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

9.2 Input/Output Pins

The pin configuration of the BSC is listed in table 9.1. Table 9.1 Pin Configuration Name I/O Function A29 to A0 Output Address bus D31 to D0 I/O Data bus BS Output Bus cycle start Asserted when a normal space, burst ROM (clock synchronous or asynchronous), MPX-I/O, burst MPX-I/O, or PCMCIA is accessed. When SDRAM is accessed, this signal is asserted at the same timing as CAS. CS0 to CS8 Output Chip select CE1A Output Chip enable for PCMCIA connected to area 5 CE2A Output Chip enable for PCMCIA connected to area 5 CE1B Output Chip enable for PCMCIA connected to area 6 CE2B Output Chip enable for PCMCIA connected to area 6 RDWR Output Read/write Connected to WE pin when SDRAM or SRAM with byte selection is used. RD Output Read pulse signal (read data output enable signal) Strobe signal for indicating memory read cycles when PCMCIA is used. WRHH Output Indicates byte write through D31 to D24. Connected to the byte select pin when SRAM with byte selection is used. WRHL Output Indicates byte write through D23 to D16. Connected to the byte select pin when SRAM with byte selection is used. WRH Output Indicates byte write through D15 to D8. Connected to the byte select pin when SRAM with byte selection is used. WRL Output Indicates byte write through D7 to D0. Connected to the byte select pin when SRAM with byte selection is used.

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 221 of 1560 Mar 18, 2011 SH7080 Group Name I/O Function RASU, RASL Output Connected to RAS pin when SDRAM is used. CASU, CASL Output Connected to CAS pin when SDRAM is used. CKE Output Connected to CKE pin when SDRAM is used. IOIS16 Input Indicates 16-bit I/O for PCMCIA. This LSI does not support little endian and this pin must be held low. DQMUU DQMUL DQMLU DQMLL Output Connected to the DQMxx pins when SDRAM is used. DQMUU: D31 to D24 select signal DQMUL: D23 to D16 select signal DQMLU: D15 to D8 select signal DQMLL: D7 to D0 select signal AH Output Address hold signal when MPX-I/O is used FRAME Output FRAME signal when burst MPX-I/O is used WAIT Input External wait input BREQ Input Bus request input BACK Output Bus acknowledge output ICIOWR Output I/O write strobe signal when PCMCIA is used ICIORD Output I/O read strobe signal when PCMCIA is used WE Output Strobe signal for indicating memory write cycles when PCMCIA is used

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9.3 Area Overview

9.3.1 Area Division

In the architecture, this LSI has 32-bit address spaces. As listed in tables 9.2 to 9.15, this LSI can connect nine areas to each type of memory, and it outputs chip select signals (CS0 to CS8) for each of them. CS0 is asserted during area 0 access. In access to SDRAM connected to areas 2 and 3, signals such as RASx, CASx, RD/WR, and DQMxx will be asserted. Furthermore, when the PCMCIA interface is selected in areas 5 and 6, CE1A, CE1B, CE2A, and CE2B as well as CS5 and CS6 are asserted, according to the bytes to be accessed.

9.3.2 Address Map

The external address space has a capacity of 1.5 Gbytes and is used by dividing into 9 spaces. The memory to be connected and the data bus width are specified in each space. The address map for the entire address space is listed in tables 9.2 to 9.15. Table 9.2 Address Map: SH7083 (256-Kbyte Flash Memory Version) in On-Chip ROM- Enabled Mode Address Area Memory Type Capacity Bus Width H'00000000 to H'0003FFFF On-chip ROM 256 Kbytes 32 bits H'00040000 to H'01FFFFFF Reserved H'02000000 to H'03FFFFFF CS0 space Normal space SRAM with byte selection Burst ROM (asynchronous) Burst ROM (synchronous)

32 Mbytes 8 or 16

bits* H'04000000 to H'0BFFFFFF Reserved H'0C000000 to H'0DFFFFFF CS3 space Normal space SRAM with byte selection SDRAM bits*

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 223 of 1560 Mar 18, 2011 SH7080 Group Address Area Memory Type Capacity Bus Width H'0E000000 to H'1BFFFFFF Reserved H'1C000000 to H'1DFFFFFF CS7 space Normal space SRAM with byte selection bits* H'1E000000 to H'FFF7FFFF Reserved H'FFF80000 to H'FFF9FFFF SDRAM mode setting space H'FFFA0000 to H'FFFF7FFF Reserved H'FFFF8000 to H'FFFFBFFF On-chip RAM 16 Kbytes 32 bits H'FFFFC000 to H'FFFFFFFF On-chip peripheral modules

16 Kbytes 8 or 16

Notes: Do not access the reserved area. If the reserved area is accessed, the correct operation cannot be guaranteed. In single-chip mode, only the on-chip ROM, on-chip RAM, and on- chip peripheral modules can be accessed; the other areas cannot be accessed. * The bus width is selected by the register setting. Table 9.3 Address Map: SH7083 (256-Kbyte Flash Memory Version) in On-Chip ROM- Disabled Mode Address Area Memory Type Capacity Bus Width H'00000000 to H'01FFFFFF CS0 space Normal space SRAM with byte selection Burst ROM (asynchronous) Burst ROM (synchronous) bits* H'02000000 to H'0BFFFFFF Reserved H'0C000000 to H'0DFFFFFF CS3 space Normal space SRAM with byte selection SDRAM bits* H'0E000000 to H'1BFFFFFF Reserved

Section 9 Bus State Controller (BSC) Page 224 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Address Area Memory Type Capacity Bus Width H'1C000000 to H'1DFFFFFF CS7 space Normal space SRAM with byte selection bits* H'1E000000 to H'FFF7FFFF Reserved H'FFF80000 to H'FFF9FFFF SDRAM mode setting space H'FFFA0000 to H'FFFF7FFF Reserved H'FFFF8000 to H'FFFFBFFF On-chip RAM 16 Kbytes 32 bits H'FFFFC000 to H'FFFFFFFF On-chip peripheral modules Notes: Do not access the reserved area. If the reserved area is accessed, the correct operation cannot be guaranteed. 1. The bus width is selected by the mode pins. 2. The bus width is selected by the register setting. Table 9.4 Address Map: SH7083 (512-Kbyte Flash Memory Version) in On-Chip ROM- Enabled Mode Address Area Memory Type Capacity Bus Width H'00000000 to H'0007FFFF On-chip ROM 512 Kbytes 32 bits H'00080000 to H'01FFFFFF Reserved H'02000000 to H'03FFFFFF CS0 space Normal space SRAM with byte selection Burst ROM (asynchronous) Burst ROM (synchronous) bits* H'04000000 to H'0BFFFFFF Reserved H'0C000000 to H'0DFFFFFF CS3 space Normal space SRAM with byte selection SDRAM bits*

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 225 of 1560 Mar 18, 2011 SH7080 Group Address Area Memory Type Capacity Bus Width H'0E000000 to H'1BFFFFFF Reserved H'1C000000 to H'1DFFFFFF CS7 space Normal space SRAM with byte selection bits* H'1E000000 to H'FFF7FFFF Reserved H'FFF80000 to H'FFF9FFFF SDRAM mode setting space H'FFFA0000 to H'FFFF3FFF Reserved H'FFFF4000 to H'FFFFBFFF On-chip RAM 32 Kbytes 32 bits H'FFFFC000 to H'FFFFFFFF On-chip peripheral modules Notes: Do not access the reserved area. If the reserved area is accessed, the correct operation cannot be guaranteed. In single-chip mode, only the on-chip ROM, on-chip RAM, and on- chip peripheral modules can be accessed; the other areas cannot be accessed. * The bus width is selected by the register setting. Table 9.5 Address Map: SH7083 (512-Kbyte Flash Memory Version) in On-Chip ROM- Disabled Mode Address Area Memory Type Capacity Bus Width H'00000000 to H'01FFFFFF CS0 space Normal space SRAM with byte selection Burst ROM (asynchronous) Burst ROM (synchronous) bits* H'02000000 to H'0BFFFFFF Reserved H'0C000000 to H'0DFFFFFF CS3 space Normal space SRAM with byte selection SDRAM bits* H'0E000000 to H'1BFFFFFF Reserved

Section 9 Bus State Controller (BSC) Page 226 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Address Area Memory Type Capacity Bus Width H'1C000000 to H'1DFFFFFF CS7 space Normal space SRAM with byte selection bits* H'1E000000 to H'FFF7FFFF Reserved H'FFF80000 to H'FFF9FFFF SDRAM mode setting space H'FFFA0000 to H'FFFF3FFF Reserved H'FFFF4000 to H'FFFFBFFF On-chip RAM 32 Kbytes 32 bits H'FFFFC000 to H'FFFFFFFF On-chip peripheral modules Notes: Do not access the reserved area. If the reserved area is accessed, the correct operation cannot be guaranteed. 1. The bus width is selected by the mode pins. 2. The bus width is selected by the register setting. Table 9.6 Address Map: SH7084 (256-Kbyte Flash Memory Version) in On-Chip ROM- Enabled Mode Address Area Memory Type Capacity Bus Width H'00000000 to H'0003FFFF On-chip ROM 256 Kbytes 32 bits H'00040000 to H'01FFFFFF Reserved H'02000000 to H'03FFFFFF CS0 space Normal space SRAM with byte selection Burst ROM (asynchronous) Burst ROM (synchronous) bits* H'04000000 to H'07FFFFFF CS1 space Normal space SRAM with byte selection

64 Mbytes 8 or 16

bits* H'08000000 to H'0BFFFFFF CS2 space Normal space SRAM with byte selection SDRAM bits*

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 227 of 1560 Mar 18, 2011 SH7080 Group Address Area Memory Type Capacity Bus Width H'0C000000 to H'0FFFFFFF CS3 space Normal space SRAM with byte selection SDRAM bits* H'10000000 to H'13FFFFFF CS4 space Normal space SRAM with byte selection Burst ROM (asynchronous) bits* H'14000000 to H'17FFFFFF CS5 space Normal space SRAM with byte selection MPX-I/O bits* H'18000000 to H'1BFFFFFF CS6 space Normal space SRAM with byte selection bits* H'1C000000 to H'1FFFFFFF CS7 space Normal space SRAM with byte selection bits* H'20000000 to H'FFF7FFFF Reserved H'FFF80000 to H'FFF9FFFF SDRAM mode setting space H'FFFA0000 to H'FFFF7FFF Reserved H'FFFF8000 to H'FFFFBFFF On-chip RAM 16 Kbytes 32 bits H'FFFFC000 to H'FFFFFFFF On-chip peripheral modules Notes: Do not access the reserved area. If the reserved area is accessed, the correct operation cannot be guaranteed. In single-chip mode, only the on-chip ROM, on-chip RAM, and on- chip peripheral modules can be accessed; the other areas cannot be accessed. * The bus width is selected by the register setting.

Section 9 Bus State Controller (BSC) Page 228 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 9.7 Address Map: SH7084 (256-Kbyte Flash Memory Version) in On-Chip ROM- Disabled Mode Address Area Memory Type Capacity Bus Width H'00000000 to H'03FFFFFF CS0 space Normal space SRAM with byte selection Burst ROM (asynchronous) Burst ROM (synchronous) bits* H'04000000 to H'07FFFFFF CS1 space Normal space SRAM with byte selection bits* H'08000000 to H'0BFFFFFF CS2 space Normal space SRAM with byte selection SDRAM bits* H'0C000000 to H'0FFFFFFF CS3 space Normal space SRAM with byte selection SDRAM bits* H'10000000 to H'13FFFFFF CS4 space Normal space SRAM with byte selection Burst ROM (asynchronous) bits* H'14000000 to H'17FFFFFF CS5 space Normal space SRAM with byte selection MPX-I/O bits* H'18000000 to H'1BFFFFFF CS6 space Normal space SRAM with byte selection bits* H'1C000000 to H'1FFFFFFF CS7 space Normal space SRAM with byte selection bits* H'20000000 to H'FFF7FFFF Reserved H'FFF80000 to H'FFF9FFFF SDRAM mode setting space H'FFFA0000 to H'FFFF7FFF Reserved

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 229 of 1560 Mar 18, 2011 SH7080 Group Address Area Memory Type Capacity Bus Width H'FFFF8000 to H'FFFFBFFF On-chip RAM 16 Kbytes 32 bits H'FFFFC000 to H'FFFFFFFF On-chip peripheral modules Notes: Do not access the reserved area. If the reserved area is accessed, the correct operation cannot be guaranteed. 1. The bus width is selected by the mode pins. 2. The bus width is selected by the register setting. Table 9.8 Address Map: SH7084 (512-Kbyte Flash Memory Version) in On-Chip ROM- Enabled Mode Address Area Memory Type Capacity Bus Width H'00000000 to H'0007FFFF On-chip ROM 512 Kbytes 32 bits H'00080000 to H'01FFFFFF Reserved H'02000000 to H'03FFFFFF CS0 space Normal space SRAM with byte selection Burst ROM (asynchronous) Burst ROM (synchronous) bits* H'04000000 to H'07FFFFFF CS1 space Normal space SRAM with byte selection bits* H'08000000 to H'0BFFFFFF CS2 space Normal space SRAM with byte selection SDRAM bits* H'0C000000 to H'0FFFFFFF CS3 space Normal space SRAM with byte selection SDRAM bits* H'10000000 to H'13FFFFFF CS4 space Normal space SRAM with byte selection Burst ROM (asynchronous) bits*

Section 9 Bus State Controller (BSC) Page 230 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Address Area Memory Type Capacity Bus Width H'14000000 to H'17FFFFFF CS5 space Normal space SRAM with byte selection MPX-I/O bits* H'18000000 to H'1BFFFFFF CS6 space Normal space SRAM with byte selection bits* H'1C000000 to H'1FFFFFFF CS7 space Normal space SRAM with byte selection bits* H'20000000 to H'FFF7FFFF Reserved H'FFF80000 to H'FFF9FFFF SDRAM mode setting space H'FFFA0000 to H'FFFF3FFF Reserved H'FFFF4000 to H'FFFFBFFF On-chip RAM 32 Kbytes 32 bits H'FFFFC000 to H'FFFFFFFF On-chip peripheral modules Notes: Do not access the reserved area. If the reserved area is accessed, the correct operation cannot be guaranteed. In single-chip mode, only the on-chip ROM, on-chip RAM, and on- chip peripheral modules can be accessed; the other areas cannot be accessed. * The bus width is selected by the register setting. Table 9.9 Address Map: SH7084 (512-Kbyte Flash Memory Version) in On-Chip ROM- Disabled Mode Address Area Memory Type Capacity Bus Width H'00000000 to H'03FFFFFF CS0 space Normal space SRAM with byte selection Burst ROM (asynchronous) Burst ROM (synchronous) bits* H'04000000 to H'07FFFFFF CS1 space Normal space SRAM with byte selection bits*

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 231 of 1560 Mar 18, 2011 SH7080 Group Address Area Memory Type Capacity Bus Width H'08000000 to H'0BFFFFFF CS2 space Normal space SRAM with byte selection SDRAM bits* H'0C000000 to H'0FFFFFFF CS3 space Normal space SRAM with byte selection SDRAM bits* H'10000000 to H'13FFFFFF CS4 space Normal space SRAM with byte selection Burst ROM (asynchronous) bits* H'14000000 to H'17FFFFFF CS5 space Normal space SRAM with byte selection MPX-I/O bits* H'18000000 to H'1BFFFFFF CS6 space Normal space SRAM with byte selection bits* H'1C000000 to H'1FFFFFFF CS7 space Normal space SRAM with byte selection bits* H'20000000 to H'FFF7FFFF Reserved H'FFF80000 to H'FFF9FFFF SDRAM mode setting space H'FFFA0000 to H'FFFF3FFF Reserved H'FFFF4000 to H'FFFFBFFF On-chip RAM 32 Kbytes 32 bits H'FFFFC000 to H'FFFFFFFF On-chip peripheral modules Notes: Do not access the reserved area. If the reserved area is accessed, the correct operation cannot be guaranteed. 1. The bus width is selected by the mode pins. 2. The bus width is selected by the register setting.

Section 9 Bus State Controller (BSC) Page 232 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 9.10 Address Map: SH7085 (256-Kbyte Flash Memory Version) in On-Chip ROM- Enabled Mode Address Area Memory Type Capacity Bus Width H'00000000 to H'0003FFFF On-chip ROM 256 Kbytes 32 bits H'00040000 to H'01FFFFFF Reserved H'02000000 to H'03FFFFFF CS0 space Normal space SRAM with byte selection Burst ROM (asynchronous) Burst ROM (synchronous)

32 Mbytes 8, 16, or

32 bits* H'04000000 to H'07FFFFFF CS1 space Normal space SRAM with byte selection

64 Mbytes 8, 16, or

32 bits* H'08000000 to H'0BFFFFFF CS2 space Normal space SRAM with byte selection SDRAM 32 bits* H'0C000000 to H'0FFFFFFF CS3 space Normal space SRAM with byte selection SDRAM 32 bits* H'10000000 to H'13FFFFFF CS4 space Normal space SRAM with byte selection Burst ROM (asynchronous) 32 bits* H'14000000 to H'17FFFFFF CS5 space Normal space SRAM with byte selection PCMCIA MPX-I/O 32 bits* H'18000000 to H'1BFFFFFF CS6 space Normal space SRAM with byte selection PCMCIA Burst MPX-I/O 32 bits* H'1C000000 to H'1FFFFFFF CS7 space Normal space SRAM with byte selection 32 bits* H'20000000 to H'FFF7FFFF Reserved

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 233 of 1560 Mar 18, 2011 SH7080 Group Address Area Memory Type Capacity Bus Width H'FFF80000 to H'FFF9FFFF SDRAM mode setting space H'FFFA0000 to H'FFFF7FFF Reserved H'FFFF8000 to H'FFFFBFFF On-chip RAM 16 Kbytes 32 bits H'FFFFC000 to H'FFFFFFFF On-chip peripheral modules Notes: Do not access the reserved area. If the reserved area is accessed, the correct operation cannot be guaranteed. In single-chip mode, only the on-chip ROM, on-chip RAM, and on- chip peripheral modules can be accessed; the other areas cannot be accessed. * The bus width is selected by the register setting. Table 9.11 Address Map: SH7085 (256-Kbyte Flash Memory Version) in On-Chip ROM- Disabled Mode Address Area Memory Type Capacity Bus Width H'00000000 to H'03FFFFFF CS0 space Normal space SRAM with byte selection Burst ROM (asynchronous) Burst ROM (synchronous)

64 Mbytes 16 or 32

bits* H'04000000 to H'07FFFFFF CS1 space Normal space SRAM with byte selection 32 bits* H'08000000 to H'0BFFFFFF CS2 space Normal space SRAM with byte selection SDRAM 32 bits* H'0C000000 to H'0FFFFFFF CS3 space Normal space SRAM with byte selection SDRAM 32 bits* H'10000000 to H'13FFFFFF CS4 space Normal space SRAM with byte selection Burst ROM (asynchronous) 32 bits*

Section 9 Bus State Controller (BSC) Page 234 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Address Area Memory Type Capacity Bus Width H'14000000 to H'17FFFFFF CS5 space Normal space SRAM with byte selection PCMCIA MPX-I/O 32 bits* H'18000000 to H'1BFFFFFF CS6 space Normal space SRAM with byte selection PCMCIA Burst MPX-I/O 32 bits* H'1C000000 to H'1FFFFFFF CS7 space Normal space SRAM with byte selection 32 bits* H'20000000 to H'FFF7FFFF Reserved H'FFF80000 to H'FFF9FFFF SDRAM mode setting space H'FFFA0000 to H'FFFF7FFF Reserved H'FFFF8000 to H'FFFFBFFF On-chip RAM 16 Kbytes 32 bits H'FFFFC000 to H'FFFFFFFF On-chip peripheral modules Notes: Do not access the reserved area. If the reserved area is accessed, the correct operation cannot be guaranteed. 1. The bus width is selected by the mode pins. 2. The bus width is selected by the register setting. Table 9.12 Address Map: SH7085 (512-Kbyte Flash Memory Version) in On-Chip ROM- Enabled Mode Address Area Memory Type Capacity Bus Width H'00000000 to H'0007FFFF On-chip ROM 512 Kbytes 32 bits H'00080000 to H'01FFFFFF Reserved

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 235 of 1560 Mar 18, 2011 SH7080 Group Address Area Memory Type Capacity Bus Width H'02000000 to H'03FFFFFF CS0 space Normal space SRAM with byte selection Burst ROM (asynchronous) Burst ROM (synchronous) 32 bits* H'04000000 to H'07FFFFFF CS1 space Normal space SRAM with byte selection 32 bits* H'08000000 to H'0BFFFFFF CS2 space Normal space SRAM with byte selection SDRAM 32 bits* H'0C000000 to H'0FFFFFFF CS3 space Normal space SRAM with byte selection SDRAM 32 bits* H'10000000 to H'13FFFFFF CS4 space Normal space SRAM with byte selection Burst ROM (asynchronous) 32 bits* H'14000000 to H'17FFFFFF CS5 space Normal space SRAM with byte selection PCMCIA MPX-I/O 32 bits* H'18000000 to H'1BFFFFFF CS6 space Normal space SRAM with byte selection PCMCIA Burst MPX-I/O 32 bits* H'1C000000 to H'1FFFFFFF CS7 space Normal space SRAM with byte selection 32 bits* H'20000000 to H'FFF7FFFF Reserved H'FFF80000 to H'FFF9FFFF SDRAM mode setting space H'FFFA0000 to H'FFFF3FFF Reserved

Section 9 Bus State Controller (BSC) Page 236 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Address Area Memory Type Capacity Bus Width H'FFFF4000 to H'FFFFBFFF On-chip RAM 32 Kbytes 32 bits H'FFFFC000 to H'FFFFFFFF On-chip peripheral modules Notes: Do not access the reserved area. If the reserved area is accessed, the correct operation cannot be guaranteed. In single-chip mode, only the on-chip ROM, on-chip RAM, and on- chip peripheral modules can be accessed; the other areas cannot be accessed. * The bus width is selected by the register setting. Table 9.13 Address Map: SH7085 (512-Kbyte Flash Memory Version) in On-Chip ROM- Disabled Mode Address Area Memory Type Capacity Bus Width H'00000000 to H'03FFFFFF CS0 space Normal space SRAM with byte selection Burst ROM (asynchronous) Burst ROM (synchronous) bits* H'04000000 to H'07FFFFFF CS1 space Normal space SRAM with byte selection 32 bits* H'08000000 to H'0BFFFFFF CS2 space Normal space SRAM with byte selection SDRAM 32 bits* H'0C000000 to H'0FFFFFFF CS3 space Normal space SRAM with byte selection SDRAM 32 bits* H'10000000 to H'13FFFFFF CS4 space Normal space SRAM with byte selection Burst ROM (asynchronous) 32 bits* H'14000000 to H'17FFFFFF CS5 space Normal space SRAM with byte selection PCMCIA MPX-I/O 32 bits*

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 237 of 1560 Mar 18, 2011 SH7080 Group Address Area Memory Type Capacity Bus Width H'18000000 to H'1BFFFFFF CS6 space Normal space SRAM with byte selection PCMCIA Burst MPX-I/O 32 bits* H'1C000000 to H'1FFFFFFF CS7 space Normal space SRAM with byte selection 32 bits* H'20000000 to H'FFF7FFFF Reserved H'FFF80000 to H'FFF9FFFF SDRAM mode setting space H'FFFA0000 to H'FFFF3FFF Reserved H'FFFF4000 to H'FFFFBFFF On-chip RAM 32 Kbytes 32 bits H'FFFFC000 to H'FFFFFFFF On-chip peripheral modules Notes: Do not access the reserved area. If the reserved area is accessed, the correct operation cannot be guaranteed. 1. The bus width is selected by the mode pins. 2. The bus width is selected by the register setting. Table 9.14 Address Map: SH7086 in On-Chip ROM-Enabled Mode Address Area Memory Type Capacity Bus Width H'00000000 to H'0007FFFF On-chip ROM 512 Kbytes 32 bits H'00080000 to H'01FFFFFF Reserved H'02000000 to H'03FFFFFF CS0 space Normal space SRAM with byte selection Burst ROM (asynchronous) Burst ROM (synchronous) 32 bits* H'04000000 to H'07FFFFFF CS1 space Normal space SRAM with byte selection 32 bits*

Section 9 Bus State Controller (BSC) Page 238 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Address Area Memory Type Capacity Bus Width H'08000000 to H'0BFFFFFF CS2 space Normal space SRAM with byte selection SDRAM 32 bits* H'0C000000 to H'0FFFFFFF CS3 space Normal space SRAM with byte selection SDRAM 32 bits* H'10000000 to H'13FFFFFF CS4 space Normal space SRAM with byte selection Burst ROM (asynchronous) 32 bits* H'14000000 to H'17FFFFFF CS5 space Normal space SRAM with byte selection PCMCIA MPX-I/O 32 bits* H'18000000 to H'1BFFFFFF CS6 space Normal space SRAM with byte selection PCMCIA Burst MPX-I/O 32 bits* H'1C000000 to H'1FFFFFFF CS7 space Normal space SRAM with byte selection 32 bits* H'20000000 to H'3FFFFFFF Reserved H'40000000 to H'7FFFFFFF CS8 space Normal space SRAM with byte selection

1 Gbyte 8, 16, or

32 bits* H'80000000 to H'FFF7FFFF Reserved H'FFF80000 to H'FFF9FFFF SDRAM mode setting space H'FFFA0000 to H'FFFF3FFF Reserved

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 239 of 1560 Mar 18, 2011 SH7080 Group Address Area Memory Type Capacity Bus Width H'FFFF4000 to H'FFFFBFFF On-chip RAM 32 Kbytes 32 bits H'FFFFC000 to H'FFFFFFFF On-chip peripheral modules Notes: Do not access the reserved area. If the reserved area is accessed, the correct operation cannot be guaranteed. In single-chip mode, only the on-chip ROM, on-chip RAM, and on- chip peripheral modules can be accessed; the other areas cannot be accessed. * The bus width is selected by the register setting. Table 9.15 Address Map: SH7086 in On-Chip ROM-Disabled Mode Address Area Memory Type Capacity Bus Width H'00000000 to H'03FFFFFF CS0 space Normal space SRAM with byte selection Burst ROM (asynchronous) Burst ROM (synchronous) bits* H'04000000 to H'07FFFFFF CS1 space Normal space SRAM with byte selection 32 bits* H'08000000 to H'0BFFFFFF CS2 space Normal space SRAM with byte selection SDRAM 32 bits* H'0C000000 to H'0FFFFFFF CS3 space Normal space SRAM with byte selection SDRAM 32 bits* H'10000000 to H'13FFFFFF CS4 space Normal space SRAM with byte selection Burst ROM (asynchronous) 32 bits* H'14000000 to H'17FFFFFF CS5 space Normal space SRAM with byte selection PCMCIA MPX-I/O 32 bits*

Section 9 Bus State Controller (BSC) Page 240 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Address Area Memory Type Capacity Bus Width H'18000000 to H'1BFFFFFF CS6 space Normal space SRAM with byte selection PCMCIA Burst MPX-I/O 32 bits* H'1C000000 to H'1FFFFFFF CS7 space Normal space SRAM with byte selection 32 bits* H'20000000 to H'3FFFFFFF Reserved H'40000000 to H'7FFFFFFF CS8 space Normal space SRAM with byte selection 32 bits* H'80000000 to H'FFF7FFFF Reserved H'FFF80000 to H'FFF9FFFF SDRAM mode setting space H'FFFA0000 to H'FFFF3FFF Reserved H'FFFF4000 to H'FFFFBFFF On-chip RAM 32 Kbytes 32 bits H'FFFFC000 to H'FFFFFFFF On-chip peripheral modules Notes: Do not access the reserved area. If the reserved area is accessed, the correct operation cannot be guaranteed. 1. The bus width is selected by the mode pins. 2. The bus width is selected by the register setting.

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 241 of 1560 Mar 18, 2011 SH7080 Group

9.4 Register Descriptions

The BSC has the following registers. Refer to section 27, List of Registers, for details on the register addresses and register states in each operating mode. Do not access spaces other than CS0 until the termination of the memory interface setting. Table 9.16 Register Configuration Register Name Abbrevia- tion R/W Initial Value Address Access Size Common control register CMNCR R/W H'00001010 H'FFFFF000 32 CS0 space bus control register CS0BCR R/W H'36DB0600 H'FFFFF004 32 CS1 space bus control register CS1BCR R/W H'36DB0600 H'FFFFF008 32 CS2 space bus control register CS2BCR R/W H'36DB0600 H'FFFFF00C 32 CS3 space bus control register CS3BCR R/W H'36DB0600 H'FFFFF010 32 CS4 space bus control register CS4BCR R/W H'36DB0600 H'FFFFF014 32 CS5 space bus control register CS5BCR R/W H'36DB0600 H'FFFFF018 32 CS6 space bus control register CS6BCR R/W H'36DB0600 H'FFFFF01C 32 CS7 space bus control register CS7BCR R/W H'36DB0600 H'FFFFF020 32 CS8 space bus control register CS8BCR R/W H'36DB0600 H'FFFFF024 32 CS0 space wait control register CS0WCR R/W H'00000500 H'FFFFF028 32 CS1 space wait control register CS1WCR R/W H'00000500 H'FFFFF02C 32 CS2 space wait control register CS2WCR R/W H'00000500 H'FFFFF030 32 CS3 space wait control register CS3WCR R/W H'00000500 H'FFFFF034 32 CS4 space wait control register CS4WCR R/W H'00000500 H'FFFFF038 32 CS5 space wait control register CS5WCR R/W H'00000500 H'FFFFF03C 32 CS6 space wait control register CS6WCR R/W H'00000500 H'FFFFF040 32 CS7 space wait control register CS7WCR R/W H'00000500 H'FFFFF044 32 CS8 space wait control register CS8WCR R/W H'00000500 H'FFFFF048 32 SDRAM control register SDCR R/W H'00000000 H'FFFFF04C 32 Refresh timer control/status register RTCSR R/W H'00000000 H'FFFFF050 32 Refresh timer counter RTCNT R/W H'00000000 H'FFFFF054 32 Refresh time constant register RTCOR R/W H'00000000 H'FFFFF058 32 Bus function extending register BSCEHR R/W H'0000 H'FFFFE89A 8,16

Section 9 Bus State Controller (BSC) Page 242 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

9.4.1 Common Control Register (CMNCR)

CMNCR is a 32-bit register that controls the common items for each area. Do not access external memory other than area 0 until the register initialization is complete. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRRRRRRRRRRRRRR 0001000000010000 RRRRRRRR R / W R / W R / W RRR R / W R / W - - - - - - - - DMAIW[1:0] DMAIWA --- HIZMEM HIZCNT Bit Bit Name Initial Value R/W Description 31 to 13 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12 ⎯ 1 R Reserved This bit is always read as 1. The write value should always be 1. 11 to 8 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. 7, 6 DMAIW[1:0] 00 R/W Wait Specification between Access Cycles during DMA Single Address Transfer Specify the number of idle cycles to be inserted after data is output from an external device with DACK when DMA single address transfer is performed. The method of inserting idle cycles depends on the setting in the DMAIWA bit described later. 00: No idle cycle inserted 01: 1 idle cycle inserted 10: 2 idle cycles inserted 11: 4 idle cycled inserted

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 243 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description

5 DMAIWA 0 R/W Specification for Method of Inserting Wait States

between Access Cycles during DMA Single Address Transfer Specifies the method of inserting the idle cycles specified by the DMAIW1 and DMAIW0 bits. Clearing this bit will make this LSI insert the idle cycles when another device, which includes this LSI, drives the data bus after an external device with DACK drove it. When the external device with DACK drives the data bus continuously, idle cycles are not inserted. Setting this bit will make this LSI insert the idle cycles after one access is completed even when the continuous accesses to an external device with DACK are performed. 0: Idle cycles are inserted when another device drives data bus after external device with DACK drives data bus 1: Idle cycles are always inserted after external device with DACK is accessed. 4 ⎯ 1 R Reserved This bit is always read as 1. The write value should always be 1. 3, 2 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0.

1 HIZMEM 0 R/W Hi-Z Memory Control

Specifies the pin state in software standby mode for A29 to A0, BS, CSn, RDWR, WRxx, RD, AH, FRAME, ICIORD, ICIOWR, WE, CE1A, CE1B, CE2A, and CE2B. While the bus is released, these pins are in high- impedance state regardless of this bit setting. 0: High impedance in software standby mode 1: Driven in software standby mode

Section 9 Bus State Controller (BSC) Page 244 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description

0 HIZCNT 0 R/W Hi-Z Control

Specifies the state in software standby mode and when bus mastership is released for CKE, RASU, RASL, CASU, and CASL. 0: High impedance in software standby mode and when bus mastership is released for CKE, RASU, RASL, CASU, and CASL. 1: Driven in software standby mode and when bus mastership is released for CKE, RASU, RASL, CASU, and CASL.

9.4.2 CSn Space Bus Control Register (CSnBCR) (n = 0 to 8)

CSnBCR is a 32-bit readable/writable register that specifies the type of memory connected to the respective space, the data bus width of the space, and the number of wait cycles between access cycles. Do not access external memory other than area 0 until the register initialization is complete. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 000 R/W R/W R/W 0011011011011011 R R R/W R/W R R/W R/W R R/W R/W R R/W R/W R R/W R/W 00 1 * 1* 000000000 R R R / W R / W RRRRRRRRR Note: When the on-chip ROM is disabled, CS0BCR samples the value input through the MD0 and MD1 external pins that specify the bus width when a power-on reset is performed. TYPE[2:0] - - IWW[1:0] - IWRWD[1:0] - IWRWS[1:0] - IWRRD[1:0] - IWRRS[1:0] Bit Bit Name Initial Value R/W Description 31, 30 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 245 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description 29, 28 IWW[1:0] 11 R/W Specification for Idle Cycles between Write-Read/Write- Write Cycles Specify the number of idle cycles to be inserted after access to memory that is connected to the space. The target cycles are write-read cycles and write-write cycles. 00: No idle cycle inserted 01: 1 idle cycle inserted 10: 2 idle cycles inserted 11: 4 idle cycles inserted 27 ⎯ 0 R Reserved This bit is always read as 0. The write value should always be 0. 26, 25 IWRWD[1:0] 11 R/W Specification for Idle Cycles between Read-Write Cycles in Different Spaces Specify the number of idle cycles to be inserted after access to memory that is connected to the space. The target cycles are continuous read-write cycles in different spaces. 00: No idle cycle inserted 01: 1 idle cycle inserted 10: 2 idle cycles inserted 11: 4 idle cycles inserted 24 ⎯ 0 R Reserved This bit is always read as 0. The write value should always be 0. 23, 22 IWRWS[1:0] 11 R/W Specification for Idle Cycles between Read-Write Cycles in the Same Space Specify the number of idle cycles to be inserted after access to memory that is connected to the space. The target cycles are continuous read-write cycles in the same space. 00: No idle cycle inserted 01: 1 idle cycle inserted 10: 2 idle cycles inserted 11: 4 idle cycles inserted

Section 9 Bus State Controller (BSC) Page 246 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description 21 ⎯ 0 R Reserved This bit is always read as 0. The write value should always be 0. 20, 19 IWRRD[1:0] 11 R/W Specification for Idle Cycles between Read-Read Cycles in Different Spaces Specify the number of idle cycles to be inserted after access to memory that is connected to the space. The target cycles are continuous read-read cycles in different spaces. 00: No idle cycle inserted 01: 1 idle cycle inserted 10: 2 idle cycles inserted 11: 4 idle cycles inserted 18 ⎯ 0 R Reserved This bit is always read as 0. The write value should always be 0. 17, 16 IWRRS[1:0] 11 R/W Specification for Idle Cycles between Read-Read Cycles in the Same Space Specify the number of idle cycles to be inserted after access to memory that is connected to the space. The target cycles are continuous read-read cycles in the same space. 00: No idle cycle inserted 01: 1 idle cycle inserted 10: 2 idle cycles inserted 11: 4 idle cycles inserted 15 ⎯ 0 R Reserved This bit is always read as 0. The write value should always be 0.

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 247 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description 14 to 12 TYPE[2:0] 000 R/W Memory Type Specification Specify the type of memory connected to the space. 000: Normal space 001: Burst ROM (clock asynchronous) 010: MPX-I/O 011: SRAM with byte selection 100: SDRAM 101: PCMCIA 110: Burst MPX-I/O 111: Burst ROM (clock synchronous) For the memory type for each area, see tables 9.2 to 9.15. Notes: 1. When burst MPX-I/O is selected for area 6, do not set areas 2 and 3 for SDRAM space. 2. SDRAM can be selected only for areas 2 and 3. If the SDRAM is only to be connected in one area, select area 3 as the SDRAM space. In this case, specify area 2 as normal space or SRAM with byte selection. 11 ⎯ 0 R Reserved This bit is always read as 0. The write value should always be 0.

Section 9 Bus State Controller (BSC) Page 248 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description 10, 9 BSZ[1:0] 11 * R/W Data Bus Size Specification Specify the data bus sizes of spaces. 00: Setting prohibited 01: 8-bit size 10: 16-bit size 11: 32-bit size Bus width determined by the address when MPX-I/O is used Notes: 1. When MPX-I/O is selected for area 5, setting these bits to 11 enables the bus width (8 bits or 16 bits) to be determined by the address according to the SZSEL bit setting in CS5WCR. 2. When the on-chip ROM is disabled, the data bus width in area 0 is specified through external input pins. The BSZ1 and BSZ0 bit setting in CS0BCR is ignored. 3. When burst MPX-I/O is selected for area 6, only 32-bit size can be selected for the bus width. 4. When PCMCIA is selected for area 5 or 6, 8- bit or 16-bit size can be selected for the bus width. 5. When SDRAM is selected for area 2 or 3, 16-bit or 32-bit size can be selected for the bus width. 8 to 0 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. Note: * When the on-chip ROM is disabled, CS0BCR samples the value input through the MD0 and MD1 external pins that specify the bus width when a power-on reset is performed.

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 249 of 1560 Mar 18, 2011 SH7080 Group

9.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0 to 8)

CSnWCR specifies various wait cycles for memory accesses. The bit configuration of this register varies as shown below according to the memory type (TYPE 2, TYPE 1, or TYPE 0) specified by the CSn space bus control register (CSnBCR). Specify CSnWCR before accessing the target area. CSnWCR should be modified only after CSnBCR setting is completed. (1) Normal Space, SRAM with Byte Selection

• CS0WCR, CS1WCR, CS2WCR, CS3WCR, CS4WCR, CS5WCR, CS6WCR, CS7WCR, CS8WCR Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRRRRRRRRR R / W R R / W R / W R / W 0000010100000000 R R R R/W R/W R/W R/W R/W R/W R/W R R R R R/W R/W Bit Bit Name Initial Value R/W Description 31 to 21 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0.

20 BAS 0 R/W Byte Access Selection when SRAM with Byte Selection

Specifies the WRxx and RDWR signal timing when SRAM interface with byte selection is used. 0: Asserts the WRxx signal at the read/write timing and asserts the RDWR signal during the write access cycle. 1: Asserts the WRxx signal during the read/write access cycle and asserts the RDWR signal at the write timing. 19 ⎯ 0 R Reserved This bit is always read as 0. The write value should always be 0.

Section 9 Bus State Controller (BSC) Page 250 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description 18 to 16 WW[2:0] 000 R/W Number of Wait Cycles in Write Access Specify the number of cycles required for write access. 000: The same cycles as WR3 to WR0 settings (read access wait) 001: 0 cycles 010: 1 cycle 011: 2 cycles 100: 3 cycles 101: 4 cycles 110: 5 cycles 111: 6 cycles 15 to 13 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12, 11 SW[1:0] 00 R/W Number of Delay Cycles from Address and CSn Assertion to RD and WRxx Assertion Specify the number of delay cycles from address and CSn assertion to RD and WRxx assertion. 00: 0.5 cycle 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 251 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description 10 to 7 WR[3:0] 1010 R/W Number of Read Access Wait Cycles Specify the number of wait cycles required for read access. 0000: 0 cycles 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited)

6 WM 0 R/W External Wait Mask Specification

Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycles is 0. 0: External wait input is valid 1: External wait input is ignored 5 to 2 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 9 Bus State Controller (BSC) Page 252 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description 1, 0 HW[1:0] 00 R/W Delay Cycles from RD and WRxx Negation to Address and CSn Negation Specify the number of delay cycles from RD and WRxx negation to address and CSn negation. 00: 0.5 cycle 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles (2) MPX-I/O

• CS5WCR Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRRRRRRRR R / W R / W R R / W R / W R / W 0000010100000000 R R R R/W R/W R/W R/W R/W R/W R/W R R R R R/W R/W Bit Bit Name Initial Value R/W Description 31 to 22 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 253 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description MPX-I/O Interface Bus Width Specification Specifies the address bit to select the bus width when the BSZ1 and BSZ0 bits in CS5BCR are set to 11. This setting is valid only when MPX-I/O is selected for area 0: Address A14 selects the bus width 1: Address A21 selects the bus width The following shows bus width selection through the SZSEL bit and A14 or A21. SZSEL A14 A21 Bus Width 0 0 No effect 8 bits 0 1 No effect 16 bits

1 No effect 0 8 bits

1 No effect 1 16 bits

21 SZSEL 0 R/W

20 MPXW 0 R/W MPX-I/O Interface Address Wait

This setting is valid only when MPX-I/O is selected for area 5. This bit specifies insertion of a wait cycle into the address cycle in MPX-I/O interface. 0: No wait 1: Inserts one wait cycle 19 ⎯ 0 R Reserved This bit is always read as 0. The write value should always be 0.

Section 9 Bus State Controller (BSC) Page 254 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description 18 to 16 WW[2:0] 000 R/W Number of Wait Cycles in Write Access Specify the number of cycles required for write access. 000: The same cycles as WR3 to WR0 settings (read access wait) 001: 0 cycles 010: 1 cycle 011: 2 cycles 100: 3 cycles 101: 4 cycles 110: 5 cycles 111: 6 cycles 15 to 13 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12, 11 SW[1:0] 00 R/W Number of Delay Cycles from Address and CSn Assertion to RD and WRxx Assertion Specify the number of delay cycles from address and CSn assertion to RD and WRxx assertion. 00: 0.5 cycle 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 255 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description 10 to 7 WR[3:0] 1010 R/W Number of Wait Cycles in Read Access Specify the number of wait cycles required for read access. 0000: 0 cycles 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycles is 0. 0: External wait is valid 1: External wait is ignored 5 to 2 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 9 Bus State Controller (BSC) Page 256 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description 1, 0 HW[1:0] 00 R/W Delay Cycles from RD and WRxx Negation to Address and CSn Negation Specify the number of delay cycles from RD and WRxx negation to address and CSn negation. 00: 0.5 cycle 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles (3) Burst ROM (Asynchronous)

• CS0WCR, CS4WCR Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRRRRRRRRR R / W RR R / W R / W 0000010100000000 R R R R/W R/W R/W R/W R/W R/W R/W R R R R R/W R/W Bit Bit Name Initial Value R/W Description 31 to 21 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 257 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description

20 BEN 0 R/W Burst Enable Specification

Enables or disables 8-burst access to the 16-bit bus and 16-burst access to the 8-bit bus when 16-byte access is required. When this bit is cleared to 0, 2-burst access is performed four times for the 16-bit bus or 4- burst access is performed four times for the 8-bit bus. When using a device that does not support 8-burst and 16-burst access, set this bit to 1. 0: Enables 8-burst access to the 16-bit bus and 16- burst access to the 8-bit bus 1: Disables 8-burst access to the 16-bit bus and 16- burst access to the 8-bit bus 19, 18 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. 17, 16 BW[1:0] 00 R/W Number of Burst Wait Cycles Specify the number of wait cycles to be inserted between the second or subsequent access cycles in burst access. 00: 0 cycles 01: 1 cycle 10: 2 cycles 11: 3 cycles 15 to 13 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12, 11 SW[1:0] 00 R/W Number of Delay Cycles from Address and CSn Assertion to RD and WRxx Assertion Specify the number of delay cycles from address and CSn assertion to RD and WRxx assertion. 00: 0.5 cycle 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles

Section 9 Bus State Controller (BSC) Page 258 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description 10 to 7 W[3:0] 1010 R/W Number of Access Wait Cycles Specify the number of wait cycles to be inserted in the first access cycles. 0000: 0 cycles 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycles is 0. 0: External wait input is valid 1: External wait input is ignored 5 to 2 ⎯ All 0 R Reserved These bit are always read as 0. The write value should always be 0.

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 259 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description 1, 0 HW[1:0] 00 R/W Delay Cycles from RD and WRxx Negation to Address and CSn Negation Specify the number of delay cycles from RD and WRxx negation to address and CSn negation. 00: 0.5 cycle 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles (4) SDRAM When SDRAM is selected in areas 2 and 3, the WTRP1/0, WTRCD0/1, TRWL1/0, and WTRC1/0 bit settings are effective in both areas in common. When SDRAM should be connected to only one area, select area 3 for SDRAM connection. In this case, the normal space or SRAM with byte selection must be selected for area 2.

• CS2WCR Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRRRRRRRRRRRRRR 0000010100000000 RRRRRRR R / W R / W RRRRRRR Bit Bit Name Initial Value R/W Description 31 to 11 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 ⎯ 1 R Reserved This bit is always read as 1. The write value should always be 1.

Section 9 Bus State Controller (BSC) Page 260 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description 9 ⎯ 0 R Reserved This bit is always read as 0. The write value should always be 0. 8, 7 A2CL[1:0] 10 R/W CAS Latency for Area 2 Specify the CAS latency for area 2. 00: 1 cycle 01: 2 cycles 10: 3 cycles 11: 4 cycles 6 to 0 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0.

• CS3WCR Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRRRRRRRRRRRRRR 0000010100000000 R R/W R/W R R/W R/W R R/W R/W R R R/W R/W R R/W R/W - WTRP[1:0] - WTRCD[1:0] - A3CL[1:0] - - TRWL[1:0] - WTRC[1:0] Bit Bit Name Initial Value R/W Description 31 to 15 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 261 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description 14, 13 WTRP[1:0] 00 R/W Number of Wait Cycles for Precharge Completion Specify the number of minimum wait cycles to be inserted for completion of precharge.

• From activation of auto precharge to ACTV command issuance for the same bank.
• From issuance of PRE/PALL command to ACTV command issuance for the same bank.
• From PALL command issuance to REF command issuance in auto refresh.
• From PALL command issuance to SELF command issuance in self-refresh. The setting for areas 2 and 3 is common. 00: 0 cycle (No wait cycles) 01: 1 cycle 10: 2 cycles 11: 3 cycles 12 ⎯ 0 R Reserved This bit is always read as 0. The write value should always be 0. 11, 10 WTRCD [1:0]

01 R/W Number of Wait Cycles from ACTV Command to

READ(A)/WRIT(A) Command Specify the number of minimum wait cycles from issuing ACTV command to issuing READ(A)/WRIT(A) command. The setting for areas 2 and 3 is common. 00: 0 cycle (No wait cycles) 01: 1 cycle 10: 2 cycles 11: 3 cycles 9 ⎯ 0 R Reserved This bit is always read as 0. The write value should always be 0.

Section 9 Bus State Controller (BSC) Page 262 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description 8, 7 A3CL[1:0] 10 R/W CAS Latency for Area 3 Specify the CAS latency for area 3. 00: 1 cycle 01: 2 cycles 10: 3 cycles 11: 4 cycles 6, 5 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4, 3 TRWL[1:0] 00 R/W Number of Wait Cycles for Precharge Activation Specify the minimum number of wait cycles to be inserted for activation of precharge.

• From issuance of WRITA command by this LSI until auto precharge is activated in SDRAM: ACTV command is issued for the same bank in non- bank active mode. See the datasheet of the SDRAM to find the number of cycles taken from the acceptance of WRITA command by SDRAM until auto-precharge is activated. These bits should be set so that the above number of cycles will not exceed the number of cycles specified by these bits.
• From issuance of WRIT command by this LSI until issuance of PRE command: Different row addresses in the same bank are accessed in bank active mode. The setting for areas 2 and 3 is common. 00: 0 cycle (No wait cycles) 01: 1 cycle 10: 2 cycles 11: 3 cycles 2 ⎯ 0 R Reserved This bit is always read as 0. The write value should always be 0.

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 263 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description 1, 0 WTRC[1:0] 00 R/W Number of Idle Cycles from REF Command Issuance/Exit from Self-Refresh Mode until ACTV/REF/MRS Command Issuance Specify the minimum number of idle cycles between commands in the following cases.

• From issuance of REF command to issuance of ACTV/REF/MRS command.
• From exit from self-refresh mode to issuance of ACTV/REF/MRS command. The setting for areas 2 and 3 is common. 00: 2 cycles 01: 3 cycles 10: 5 cycles 11: 8 cycles (5) PCMCIA
• CS5WCR, CS6WCR Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRRRRRRRR R / W R / W RRRR 0000010100000000 R R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W - TED[3:0] PCW[3:0] WM - - TEH[3:0] Bit Bit Name Initial Value R/W Description 31 to 22 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 9 Bus State Controller (BSC) Page 264 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description 21, 20 SA[1:0] 00 R/W Space Attribute Specification Selects memory card interface or I/O card interface when PCMCIA interface is selected. SA1: 0: Selects memory card interface for the space for A25 = 1. 1: Selects I/O card interface for the space for A25 = 1. SA0: 0: Selects memory card interface for the space for A25 = 0. 1: Selects I/O card interface for the space for A25 = 0. 19 to 15 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. 14 to 11 TED[3:0] 0000 R/W Number of De lay Cycles from Address Output to RD and WE Assertion Specify the number of delay cycles from address output to RD and WE assertion in PCMCIA interface. 0000: 0.5 cycle 0001: 1.5 cycles 0010: 2.5 cycles 0011: 3.5 cycles 0100: 4.5 cycles 0101: 5.5 cycles 0110: 6.5 cycles 0111: 7.5 cycles 1000: 8.5 cycles 1001: 9.5 cycles 1010: 10.5 cycles 1011: 11.5 cycles 1100: 12.5 cycles 1101: 13.5 cycles 1110: 14.5 cycles 1111: 15.5 cycles

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 265 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description 10 to 7 PCW[3:0] 1010 R/W Number of Access Wait Cycles Specify the number of wait cycles to be inserted. 0000: 3 cycles 0001: 6 cycles 0010: 9 cycles 0011: 12 cycles 0100: 15 cycles 0101: 18 cycles 0110: 22 cycles 0111: 26 cycles 1000: 30 cycles 1001: 33 cycles 1010: 36 cycles 1011: 38 cycles 1100: 52 cycles 1101: 60 cycles 1110: 64 cycles 1111: 80 cycles Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycles is 0. 0: External wait input is valid 1: External wait input is ignored 5, 4 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 9 Bus State Controller (BSC) Page 266 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description 3 to 0 TEH[3:0] 0000 R/W Delay Cycles from RD and WE Negation to Address Specify the number of address hold cycles from RD and WEn negation in PCMCIA interface. 0000: 0.5 cycle 0001: 1.5 cycles 0010: 2.5 cycles 0011: 3.5 cycles 0100: 4.5 cycles 0101: 5.5 cycles 0110: 6.5 cycles 0111: 7.5 cycles 1000: 8.5 cycles 1001: 9.5 cycles 1010: 10.5 cycles 1011: 11.5 cycles 1100: 12.5 cycles 1101: 13.5 cycles 1110: 14.5 cycles 1111: 15.5 cycles

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 267 of 1560 Mar 18, 2011 SH7080 Group (6) Burst MPX-I/O

• CS6WCR Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRRRRRRRR R / W R / W R / W R R / W R / W 0000010100000000 RRRRR R / W R / W R / W R / W R / W RRRRRR Bit Bit Name Initial Value R/W Description 31 to 22 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. 21, 20 MPXAW[1:0] 00 R/W Number of Wait Cycles in Address Cycle Specifies the number of wait cycles to be inserted into the address cycle. 00: 0 cycles 01: 1 cycle 10: 2 cycles 11: 3 cycles

Section 9 Bus State Controller (BSC) Page 268 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description Burst MPX-I/O Interface Mode Specification This bit specifies the number of bursts per access. This setting has effect only when the DMAC is set to the 16- byte transfer unit size. When other transfer unit size is selected, the setting of the MPXMD bit is ignored and there is always one burst per access. 0: Four bursts per access Four consecutive data cycles occur after the address cycle. 1: Two bursts per access Two consecutive data cycles occur after the address cycle. The correspondence between the data (D31 to D29) output in the address cycle and the transfer size is shown below. D31 D30 D29 Transfer Size 0 0 0 Byte (one byte) 0 0 1 Word (two bytes) 0 1 0 Longword (four bytes) 0 1 1 Quadword (eight bytes) (only when MPXMD = 1) 1 0 0 16 bytes (only when MPXMD = 0) 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved

19 MPXMD 0 R/W

18 ⎯ 0 R Reserved This bit is always read as 0. The write value should always be 0.

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 269 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description 17, 16 BW[1:0] 00 R/W Number of Burst Wait Cycles Specifies the number of wait cycles to be inserted into the second or subsequent access cycles in burst access. 00: 0 cycles 01: 1 cycle 10: 2 cycles 11: 3 cycles 15 to 11 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 to 7 W[3:0] 1010 R/W Number of Access Wait Cycles Specify the number of wait cycles to be inserted into the first burst access cycle or single access cycle. 0000: 0 cycles 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited)

Section 9 Bus State Controller (BSC) Page 270 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description Specifies whether or not the external wait input is valid. The specification by this bit is valid even when the number of access wait cycles is 0. 0: External wait is valid 1: External wait is ignored 5 to 0 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. (7) Burst ROM (Clock Synchronous)

• CS0WCR Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRRRRRRRRRRRR R / W R / W 0000010100000000 RRRRR R / W R / W R / W R / W R / W RRRRRR Bit Bit Name Initial Value R/W Description 31 to 18 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. 17, 16 BW[1:0] 00 R/W Number of Burst Wait Cycles Specify the number of wait cycles to be inserted in the second or subsequent access cycles in burst access. 00: 0 cycles 01: 1 cycle 10: 2 cycles 11: 3 cycles

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 271 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description 15 to 11 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 to 7 W[3:0] 1010 R/W Number of Access Wait Cycles Specify the number of wait cycles to be inserted in the first access cycle. 0000: 0 cycles 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: Reserved (setting prohibited) 1110: Reserved (setting prohibited) 1111: Reserved (setting prohibited) Specifies whether or nor the external wait input is valid. The specification by this bit is valid even when the number of access wait cycles is 0. 0: External wait input is valid. 1: External wait input is ignored. 5 to 0 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 9 Bus State Controller (BSC) Page 272 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

9.4.4 SDRAM Control Register (SDCR)

SDCR specifies the method to refresh and access SDRAM, and the types of SDRAMs to be connected. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRRRRRRRRR R / W R / W R R / W R / W 0000000000000000 RRRR R / W R / W R R / W RRR R / W R / W R R / W R / W - - - - RFSH RMODE - BACTV - - - A3ROW[1:0] - A3COL[1:0] Bit Bit Name Initial Value R/W Description 31 to 21 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. 20, 19 A2ROW[1:0] 00 R/W Number of Bits of Row Address for Area 2 Specify the number of bits of row address for area 2. 00: 11 bits 01: 12 bits 10: 13 bits 11: Reserved (setting prohibited) 18 ⎯ 0 R Reserved This bit is always read as 0. The write value should always be 0. 17, 16 A2COL[1:0] 00 R/W Number of Bits of Column Address for Area 2 Specify the number of bits of column address for area 00: 8 bits 01: 9 bits 10: 10 bits 11: Reserved (setting prohibited)

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 273 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description 15 to 12 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0.

11 RFSH 0 R/W Refresh Control

Specifies whether or not the refresh operation of SDRAM is performed. 0: No refresh 1: Refresh

10 RMODE 0 R/W Refresh Control

Specifies whether to perform auto-refresh or self- refresh when the RFSH bit is 1. When the RFSH bit is 1 and this bit is 1, self-refresh starts immediately. When the RFSH bit is 1 and this bit is 0, auto-refresh starts according to the contents that are set in RTCSR, RTCNT, and RTCOR. 0: Auto-refresh is performed 1: Self-refresh is performed 9 ⎯ 0 R Reserved This bit is always read as 0. The write value should always be 0.

8 BACTV 0 R/W Bank Active Mode

Specifies to access whether in auto-precharge mode (using READA and WRITA commands) or in bank active mode (using READ and WRIT commands). 0: Auto-precharge mode (using READA and WRITA commands) 1: Bank active mode (using READ and WRIT commands) Note: Bank active mode can be used only for the area 3. The bus width can be set as 16 or 32 bits. When both the area 2 and area 3 are set to SDRAM, specify auto-precharge mode. 7 to 5 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 9 Bus State Controller (BSC) Page 274 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description 4, 3 A3ROW[1:0] 00 R/W Number of Bits of Row Address for Area 3 Specify the number of bits of the row address for area 00: 11 bits 01: 12 bits 10: 13 bits 11: Reserved (setting prohibited) 2 ⎯ 0 R/W Reserved This bit is always read as 0. The write value should always be 0. 1, 0 A3COL[1:0] 00 R/W Number of Bits of Column Address for Area 3 Specify the number of bits of the column address for area 3. 00: 8 bits 01: 9 bits 10: 10 bits 11: Reserved (setting prohibited)

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 275 of 1560 Mar 18, 2011 SH7080 Group

9.4.5 Refresh Timer Control/Status Register (RTCSR)

RTCSR specifies various items about refresh for SDRAM. When writing to RTCSR, write data with setting the upper 16 bits to H'A55A to cancel write protection. Phase matching of the clock input to the refresh timer counter (RTCNT) is only performed on power-on reset. Accordingly, if the timer is started with CKS[2:0] set to other than B'000, there will be an error contained in the period until the first setting of the compare match flag. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000000000000000 RRRRRRRR R / W R / W R / W R / W R / W R / W R / W R / W - - - - - - - - CMF CMIE CKS[2:0] RRC[2:0] Bit Bit Name Initial Value R/W Description 31 to ⎯ All 0 R/W Write Protect Cancellation When writing to RTCSR, write H'A55A to these bits to cancel write protection. These bits are always read as 0. 15 to 8 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0.

7 CMF 0 R/W Compare Match Flag

This is a status flag which indicates that a compare match occurs between the refresh timer counter (RTCNT) and refresh time constant register (RTCOR). This bit is set or cleared in the following conditions. 0: Clearing condition: When 0 is written in CMF after reading out RTCSR during CMF = 1. 1: Setting condition: When the condition RTCNT = RTCOR is satisfied.

Section 9 Bus State Controller (BSC) Page 276 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description

6 CMIE 0 R/W Compare Match Interrupt Enable

Enables or disables CMF interrupt requests when the CMF bit in RTCSR is set to 1. 0: Disables CMF interrupt requests. 1: Enables CMF interrupt requests. 5 to 3 CKS[2:0] 000 R/W Clock Select Select the clock input to count-up the refresh timer counter (RTCNT). 000: Stop the counting-up 001: Bφ/4 010: Bφ/16 011: Bφ/64 100: Bφ/256 101: Bφ/1024 110: Bφ/2048 111: Bφ/4096 2 to 0 RRC[2:0] 000 R/W Refresh Count Specify the number of continuous refresh cycles, when the refresh request occurs after the coincidence of the values of the refresh timer counter (RTCNT) and the refresh time constant register (RTCOR). These bits can make the period of occurrence of refresh long. 000: Once 001: Twice 010: 4 times 011: 6 times 100: 8 times 101: Reserved (setting prohibited) 110: Reserved (setting prohibited) 111: Reserved (setting prohibited)

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 277 of 1560 Mar 18, 2011 SH7080 Group

9.4.6 Refresh Timer Counter (RTCNT)

RTCNT is an 8-bit counter that increments using the clock selected by bits CKS2 to CKS0 in RTCSR. When RTCNT matches RTCOR, RTCNT is cleared to 0. The value in RTCNT returns to 0 after counting up to 255. When writing to RTCNT, write data with setting the upper 16 bits to H'A55A to cancel write protection. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000000000000000 RRRRRRRR R / W R / W R / W R / W R / W R / W R / W R / W Bit Bit Name Initial Value R/W Description 31 to ⎯ All 0 R/W Write Protect Cancellation When writing to RTCNT, write H'A55A to these bits to cancel write protection. These bits are always read as 0. 15 to 8 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. 7 to 0 All 0 R/W 8-bit counter

Section 9 Bus State Controller (BSC) Page 278 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

9.4.7 Refresh Time Constant Register (RTCOR)

RTCOR is an 8-bit register. When RTCOR matches RTCNT, the CMF bit in RTCSR is set to 1 and RTCNT is cleared to 0. When the RFSH bit in SDCR is set to 1, a memory refresh request is issued by this matching signal. This request is maintained until the refresh operation is performed. If the request is not processed when the next matching occurs, the previous request is ignored. When the CMIE bit in RTCSR is set to 1, an interrupt request is issued by this matching signal. The request is output continuously until the CMF bit in RTCSR is cleared. Clearing the CMF bit only affects the interrupt request and does not clear the refresh request. Therefore, a combination of refresh request and interval timer interrupt can be specified so that the number of refresh requests are counted by using timer interrupts while refresh is performed periodically. When writing to RTCOR, write data with setting the upper 16 bits to H'A55A to cancel write protection. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000000000000000 RRRRRRRR R / W R / W R / W R / W R / W R / W R / W R / W Bit Bit Name Initial Value R/W Description 31 to ⎯ All 0 R/W Write Protect Cancellation When writing to RTCOR, write H'A55A to these bits to cancel write protection. These bits are always read as 0. 15 to 8 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. 7 to 0 All 0 R/W 8-bit counter

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 279 of 1560 Mar 18, 2011 SH7080 Group

9.4.8 Bus Function Extending Register (BSCEHR)

BSCEHR is a 16-bit register that specifies the timing of bus release by the DTC and DMAC. It also specifies the application of priority in transfer operations and enables or disables the functions that have the effect of decreasing numbers of cycles over which the DTC is active. The differences in DTC operation made by the combinations of the DTLOCK, CSSTP1, and DTBST bits settings are described in section 8.5.9, DTC Bus Releasing Timing. Setting the CSSTP2 bit can improve the transfer performance of the DMAC in burst-mode transfer and of the DTC when the DTLOCK bit is 0. Furthermore, setting the CSSTP3 bit selects whether or not access to the external space by the CPU takes priority over DTC or DMAC transfer in cycle-steal mode. The DTC short address mode is implemented by setting the DTSA bit. For details of the short address mode, see section 8.4, Location of Transfer Information and DTC Vector Table. A DTC activation priority order can be set up for the DTC activation sources. The DTPR bit selects whether or not this priority order is valid or invalid when multiple sources issue activation requests before DTC activation. The corresponding bit from among DMMTU4 to DMMTU0 must be set for MTU2-triggered transfer by the DMAC in the burst mode. Do not modify this register while the DMAC or DTC is active. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R/W R/W R R/W R/W R/W R/W R/W R R R R/W R/W R/W R/W R/W DTLOCK CSSTP1 - CSSTP2 DTBST DTSA CSSTP3 DTPR - - - DMMTU4 DMMTU3 DMMTU2 DMMTU1 DMMTU0 Bit Bit Name Initial Value R/W Description

15 DTLOCK 0 R/W DTC Lock Enable

Specifies the timing of bus release by the DTC. 0: The DTC releases the bus on generation of the NOP cycle that follows vector read or write-back of transfer information. 1: The DTC releases the bus after vector read, on generation of the NOP cycle that follows vector read, after transfer information read, after a round of data transfer, or after write-back of transfer information.

Section 9 Bus State Controller (BSC) Page 280 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description

14 CSSTP1 0 R/W Select Bus Release on NOP Cycle Generation by DTC

Specifies whether or not the bus is released in response to requests from the CPU for external space access on generation of the NOP cycle that follows reading of the vector address. If, however, the CSSTP2 bit is 1, bus mastership is retained until all transfer is complete, regardless of the setting of this bit. 0: The bus is released on generation of the NOP cycle by the DTC. 1: The bus is not released on generation of the NOP cycle by the DTC. 13 ⎯ 0 R Reserved This bit is always read as 0. The write value should always be 0.

12 CSSTP2 0 R/W Select Bus Release during Burst-Mode-DMAC/DTC

This setting applies to DTC transfer when the DTLOCK bit is 0 and burst-mode DMAC transfer when the DMAC is in channel-fixed mode, and the activating request was an external request or was from MTU2. The value specifies whether the bus mastership is or is not to be released after each round of transfer in response to a request from the CPU for access to the external space.

• DMAC transfer 0: Release the bus after each round of data transfer. 1: Only release the bus after all data transfer is complete. Note: In round-robin mode, the bus is only released after all data transfer is complete, regardless of the setting of this bit.
• DTC transfer 0: When the DTLOCK and CSSTP1 bits are 0, the bus is released on generation of the NOP cycle after reading of the vector address. When the DTLOCK bit is 0 and the CSSTP1 bit is 1, the bus is released after each round of data transfer. 1: Only release the bus mastership after all data transfer is complete.

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 281 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description

11 DTBST 0 R/W DTC Burst Enable

Selects whether or not the DTC retains the bus mastership and remains continuously active until all transfer operations are complete when multiple DTC activation requests have been generated. 0: Release the bus on the completion of transfer for each individual DTC activation source. 1: Keep the DTC continuously active, i.e. only release the bus on completion of processing for all DTC activation sources. Notes: When this bit is set to 1, the following restrictions apply. 1. Clock setting with the frequency control register (FRQCR) must be Iφ: Bφ: Pφ: MIφ: MPφ: = 8: 4: 2. The vector information must be in on-chip ROM or on-chip RAM. 3. The transfer information must be in on-chip RAM. 4. Transfer must be between the on-chip RAM and an on-chip peripheral module or between external memory and an on-chip peripheral module.

10 DTSA 0 R/W DTC Short Address Mode

In this mode, the information that specifies a DTC transfer takes up only 3 longwords. 0: Each transfer information is read out as 4 longwords. The transfer information are arranged as shown in figure 8.2 (normal address mode). 1: Each transfer information is read out as 3 longwords. The transfer information are arranged as shown in figure 8.2 (short-address mode). Note: Transfer in short-address mode is only available between on-chip peripheral modules and on-chip RAM, because the higher-order 8 bits of the SAR and DAR are considered to be all 1.

Section 9 Bus State Controller (BSC) Page 282 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description

9 CSSTP3 0 R/W Select Priority fo r External Memory Access by CPU

Specifies whether or not access to the external space by the CPU takes priority over DTC or DMAC transfer in cycle-steal mode. 0: DMAC transfer and DTC transfer have priority. 1: External space access from the CPU has priority. Note: When this bit is 0, and access to internal I/O from the CPU is immediately followed by access to external space from the CPU, a NOP 1Bφ in duration is inserted between the two access cycles.

8 DTPR 0 R/W Application of Priority in DTC Activation

When multiple DTC activation requests are generated before the DTC is activated, specify whether transfer starts from the first request to have been generated or is in accord with the priority order for DTC activation requests. However, when multiple DTC activation requests have been issued while the DTC is active, the next transfer to be triggered will be that with the highest DTC activation priority. 0: Start transfer in response to the first request to have been generated. 1: Start transfer in accord with DTC activation request priority. Notes: When this bit is set to 1, the following restrictions apply. 1. The vector information must be in on-chip ROM or on-chip RAM. 2. The transfer information must be in on-chip RAM. 3. Skipping of transfer information reading is always disabled. 7 to 5 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 283 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description

4 DMMTU4 0 R/W Enable Burst-Mode DMAC Transfer with TGIA_4

Setting this bit to 1 enables burst-mode DMA transfer triggered by the TGIA_4 interrupt from MTU2. 0: DMA transfer in burst mode is disabled when TGIA_4 is the activation source. 1: DMA transfer in burst mode is enabled when TGIA_4 is the activation source. Note: Clear this bit during DMA transfer in cycle-steal mode.

3 DMMTU3 0 R/W Enable Burst-Mode DMAC Transfer with TGIA_3

Setting this bit to 1 enables burst-mode DMA transfer triggered by the TGIA_3 interrupt from MTU2. 0: DMA transfer in burst mode is disabled when TGIA_3 is the activation source. 1: DMA transfer in burst mode is enabled when TGIA_3 is the activation source. Note: Clear this bit during DMA transfer in cycle-steal mode.

2 DMMTU2 0 R/W Enable Burst-Mode DMAC Transfer with TGIA_2

Setting this bit to 1 enables burst-mode DMA transfer triggered by the TGIA_2 interrupt from MTU2. 0: DMA transfer in burst mode is disabled when TGIA_2 is the activation source. 1: DMA transfer in burst mode is enabled when TGIA_2 is the activation source. Note: Clear this bit during DMA transfer in cycle-steal mode.

Section 9 Bus State Controller (BSC) Page 284 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description

1 DMMTU1 0 R/W Enable Burst-Mode DMAC Transfer with TGIA_1

Setting this bit to 1 enables burst-mode DMA transfer triggered by the TGIA_1 interrupt from MTU2. 0: DMA transfer in burst mode is disabled when TGIA_1 is the activation source. 1: DMA transfer in burst mode is enabled when TGIA_1 is the activation source. Note: Clear this bit during DMA transfer in cycle-steal mode.

0 DMMTU0 0 R/W Enable Burst-Mode DMAC Transfer with TGIA_0

Setting this bit to 1 enables burst-mode DMA transfer triggered by the TGIA_0 interrupt from MTU2. 0: DMA transfer in burst mode is disabled when TGIA_0 is the activation source. 1: DMA transfer in burst mode is enabled when TGIA_0 is the activation source. Note: Clear this bit during DMA transfer in cycle-steal mode.

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 285 of 1560 Mar 18, 2011 SH7080 Group

9.5 Operation

9.5.1 Endian/Access Size and Data Alignment

This LSI supports big endian, in which the 0 address is the most significant byte (MSB) in the byte data. Three data bus widths (8 bits, 16 bits, and 32 bits) are available for normal memory and SRAM with byte selection, and two data bus widths (16 bits and 32 bits) are available for SDRAM. For PCMCIA interface, two data bus widths (8 bits and 16 bits) are available. For MPX-I/O, the data bus width is fixed at 8 bits or 16 bits, or 8 bits or 16 bits can be selected by the access address. For burst MPX-I/O, the data bus width is fixed at 32 bits. Data alignment is performed in accordance with the data bus width of the respective device. This also means that when longword data is read from a byte-width device, the read operation must be done four times. In this LSI, data alignment and conversion of data length are performed automatically between the respective interfaces. Tables 9.17 to 9.19 show the relationship between device data width and access unit. Table 9.17 32-Bit External De vice Access and Data Alignment Data Bus Strobe Signals Operation D31 to D24 D23 to D16 D15 to D7 to WRHH, DQMUU WRHL, DQMUL WRH, DQMLU WRL, DQMLL Byte access at 0 Data 7 to Data 0 Byte access at 1 ⎯ Data 7 to Data 0 Byte access at 2 ⎯ ⎯ Data 7 to Data 0 ⎯ ⎯ ⎯ Assert ⎯ Byte access at 3 ⎯ ⎯ ⎯ Data 7 to Data 0 ⎯ ⎯ ⎯ Assert Word access at 0 Data 15 to Data 8 Data 7 to Data 0 ⎯ ⎯ Assert Assert ⎯ ⎯ Word access at 2 ⎯ ⎯ Data 15 to Data 8 Data 7 to Data 0 ⎯ ⎯ Assert Assert Longword access at 0 Data 31 to Data 24 Data 23 to Data 16 Data 15 to Data 8 Data 7 to Data 0 Assert Assert Assert Assert

Section 9 Bus State Controller (BSC) Page 286 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 9.18 16-Bit External De vice Access and Data Alignment Data Bus Strobe Signals Operation D31 to D24 D23 to D16 D15 to D7 to WRHH, DQMUU WRHL, DQMUL WRH, DQMLU WRL, DQMLL Byte access at 0 ⎯ ⎯ Data 7 to Data 0 ⎯ ⎯ ⎯ Assert ⎯ Byte access at 1 ⎯ ⎯ ⎯ Data 7 to Data 0 ⎯ ⎯ ⎯ Assert Byte access at 2 ⎯ ⎯ Data 7 to Data 0 ⎯ ⎯ ⎯ Assert ⎯ Byte access at 3 ⎯ ⎯ ⎯ Data 7 to Data 0 ⎯ ⎯ ⎯ Assert Word access at 0 ⎯ ⎯ Data 15 to Data 8 Data 7 to Data 0 ⎯ ⎯ Assert Assert Word access at 2 ⎯ ⎯ Data 15 to Data 8 Data 7 to Data 0 ⎯ ⎯ Assert Assert 1st time at 0 ⎯ ⎯ Data 31 to Data 24 Data 23 to Data 16 ⎯ ⎯ Assert Assert Longword access at 0 2nd time at 2 ⎯ ⎯ Data 15 to Data 8 Data 7 to Data 0 ⎯ ⎯ Assert Assert

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 287 of 1560 Mar 18, 2011 SH7080 Group Table 9.19 8-Bit External De vice Access and Data Alignment Data Bus Strobe Signals Operation D31 to D24 D23 to D16 D15 to D7 to WRHH, DQMUU WRHL, DQMUL WRH, DQMLU WRL, DQMLL Byte access at 0 ⎯ ⎯ ⎯ Data 7 to Data 0 ⎯ ⎯ ⎯ Assert Byte access at 1 ⎯ ⎯ ⎯ Data 7 to Data 0 ⎯ ⎯ ⎯ Assert Byte access at 2 ⎯ ⎯ ⎯ Data 7 to Data 0 ⎯ ⎯ ⎯ Assert Byte access at 3 ⎯ ⎯ ⎯ Data 7 to Data 0 ⎯ ⎯ ⎯ Assert 1st time at 0 ⎯ ⎯ ⎯ Data 15 to Data 8 ⎯ ⎯ ⎯ Assert Word access at 0 2nd time at 1 ⎯ ⎯ ⎯ Data 7 to Data 0 ⎯ ⎯ ⎯ Assert 1st time at 2 ⎯ ⎯ ⎯ Data 15 to Data 8 ⎯ ⎯ ⎯ Assert Word access at 2 2nd time at 3 ⎯ ⎯ ⎯ Data 7 to Data 0 ⎯ ⎯ ⎯ Assert 1st time at 0 ⎯ ⎯ ⎯ Data 31 to Data 24 ⎯ ⎯ ⎯ Assert 2nd time at 1 ⎯ ⎯ ⎯ Data 23 to Data 16 ⎯ ⎯ ⎯ Assert Longword access at 0 3rd time at 2 ⎯ ⎯ ⎯ Data 15 to Data 8 ⎯ ⎯ ⎯ Assert 4th time at 3 ⎯ ⎯ ⎯ Data 7 to Data 0 ⎯ ⎯ ⎯ Assert

Section 9 Bus State Controller (BSC) Page 288 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

9.5.2 Normal Space Interface

Basic Timing: For access to a normal space, this LSI uses strobe signal output in consideration of the fact that mainly SRAM without a byte selection will be directly connected. When using SRAM with a byte-selection pin, see section 9.5.8, SRAM Interface with Byte Selection. Figure 9.2 shows the basic timings of normal space access. A no-wait normal access is completed in two cycles. The BS signal is asserted for one cycle to indicate the start of a bus cycle. CK Note: * The waveform for DACKn is when active low is specified. A29 to A0 RDWR RDWR D31 to D0 DACKn CSn T1 T2 RD WRxx BS D31 to D0 Read Write Figure 9.2 Normal Space Basic Access Timing (Access Wait 0)

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 289 of 1560 Mar 18, 2011 SH7080 Group There is no access size specification when reading. The correct access start address is output in the least significant bit of the address, but since there is no access size specification, 32 bits are always read in a 32-bit device or 16 bits are always read in a 16-bit device. When writing, only the WRxx signal for the byte to be written is asserted. It is necessary to control of outputing the data that has been read using RD when a buffer is established in the data bus. The RDWR signal is in a read state (high output) when no access has been carried out. Therefore, care must be taken when controlling the external data buffer using RDWR, to avoid collision. Figures 9.3 and 9.4 show the basic timings of continuous accesses to normal space. If the WM bit in CSnWCR is cleared to 0, a Tnop cycle is inserted to evaluate the external wait (figure 9.3). If the WM bit in CSnWCR is set to 1, external waits are ignored and no Tnop cycle is inserted (figure 9.4).

Section 9 Bus State Controller (BSC) Page 290 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Note: * The waveform for DACKn is when active low is specified. CK A29 to A0 RD RDWR D15 to D0 WRxx D15 to D0 WAIT CSn T1 T2 Tnop T1 T2 DACKn* BS Read Write Figure 9.3 Continuous Access for Normal Space 1 Bus Width = 16 Bits, Longword Access, WM Bit in CSnWCR = 0 (Access Wait = 0, Cycle Wait = 0)

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 291 of 1560 Mar 18, 2011 SH7080 Group CK A29 to A0 RDWR D15 to D0 CSn T1 T2 T1 T2 RD DACKn* WRxx WAIT D15 to D0 BS Read Write Note: * The waveform for DACKn is when active low is specified. Figure 9.4 Continuous Access for Normal Space 2 Bus Width = 16 Bits, Longword Access, WM Bit in CSnWCR = 1 (Access Wait = 0, Cycle Wait = 0)

Section 9 Bus State Controller (BSC) Page 292 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group A16 CS OE I/O7 I/O0 A18 CSn RD D31 D24 WRHH D23 D16 WRHL D15 WRH WRL This LSI 128 k × 8-bit SRAM . . . . A16 CS OE I/O7 I/O0 A16 CS OE I/O7 I/O0 A16 CS OE I/O7 I/O0 Figure 9.5 Example of 32-Bit Data-Width SRAM Connection

Section 9 Bus State Controller (BSC) Page 294 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

9.5.3 Access Wait Control

Wait cycle insertion on a normal space access can be controlled by the settings of bits WR3 to WR0 in CSnWCR. It is possible to insert wait cycles independently in read access and in write access. The specified number of Tw cycles is inserted as wait cycles in a normal space access shown in figure 9.8. CK A29 to A0 CSn RDWR BS DACKn* RD D31 to D0 WRxx D31 to D0 Tw Read Write Note: * The waveform for DACKn is when active low is specified. Figure 9.8 Wait Timing for Normal Space Access (Software Wait Only)

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 295 of 1560 Mar 18, 2011 SH7080 Group When the WM bit in CSnWCR is cleared to 0, the external wait input WAIT signal is also sampled. WAIT pin sampling is shown in figure 9.9. A 2-cycle wait is specified as a software wait. The WAIT signal is sampled at the falling edge of CK at the transition from the T1 or Tw cycle to the T2 cycle. CK A29 to A0 CSn BS RDWR RD D31 to D0 WRxx D31 to D0 WAIT Tw Tw Twx T2 Read Write Wait states inserted by WAIT signal DACKn* Note: * The waveform for DACKn is when active low is specified. Figure 9.9 Wait State Timing for Normal Space Access (Wait State Insertion Using WAIT Signal)

Section 9 Bus State Controller (BSC) Page 296 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

9.5.4 CSn Assert Period Extension

The number of cycles from CSn assertion to RD, WRxx assertion can be specified by setting bits SW1 and SW0 in CSnWCR. The number of cycles from RD, WRxx negation to CSn negation can be specified by setting bits HW1 and HW0. Therefore, a flexible interface to an external device can be obtained. Figure 9.10 shows an example. A Th cycle and a Tf cycle are added before and after an ordinary cycle, respectively. In these cycles, RD and WRxx are not asserted, while other signals are asserted. The data output is prolonged to the Tf cycle, and this prolongation is useful for devices with slow writing operations. Note: * The waveform for DACKn is when active low is specified. CK A29 to A0 CSn RDWR RD D31 to D0 WRxx D31 to D0 Th Read Write T2 Tf BS DACKn* Figure 9.10 CSn Assert Period Extension

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 297 of 1560 Mar 18, 2011 SH7080 Group

9.5.5 MPX-I/O Interface

Access timing for the MPX space is shown below. In the MPX space, CSn, AH, RD, and WRxx signals control the accessing. The basic access for the MPX space consists of 2 cycles of address output followed by an access to a normal space. The bus width for the address output cycle or the data input/output cycle is fixed to 8 bits or 16 bits. Alternatively, it can be 8 bits or 16 bits depending on the address to be accessed. Output of the addresses D15 to D0 or D7 to D0 is performed from cycle Ta2 to cycle Ta3. Because cycle Ta1 has a high-impedance state, collisions of addresses and data can be avoided without inserting idle cycles, even in continuous accesses. Address output is increased to 3 cycles by setting the MPXW bit in the CS5WCR register to 1. The RDWR signal is output at the same time as the CSn signal; it is high in the read cycle and low in the write cycle. The data cycle is the same as that in a normal space access. Timing charts are shown in figures 9.11 to 9.13. Note that the operation timing of the MPX-I/O interface differs between the SH7080 group and the SH7040. For example, the AH signal is negated (high-level) in the SH7080 group and asserted (low-level) in the SH7040 group during access to other than MPX-I/O space.

Section 9 Bus State Controller (BSC) Page 298 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group CK A25 to A16 CSn RDWR RD D15 to D0 WRxx D15 to D0 BS Read Write DACKn* Ta1 Ta2 Ta3 AH Address Address Data Data Note: * The waveform for DACKn is when active low is specified. Figure 9.11 Access Timing for MPX Space (Address Cycle No Wait, Data Cycle No Wait)

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 299 of 1560 Mar 18, 2011 SH7080 Group CK A25 to A16 CSn RDWR RD D15 to D0 WRxx D15 to D0 BS Read Write DACKn* Ta1 Ta2 Ta3 AH Address Address Data Data Tadw Note: * The waveform for DACKn is when active low is specified. Figure 9.12 Access Timing for MPX Space (Address Cycle Wait 1, Data Cycle No Wait)

Section 9 Bus State Controller (BSC) Page 300 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group CK A25 to A16 CSn RDWR RD D15 to D0 WRxx D15 to D0 BS Read Write DACKn* Ta1 Ta2 Ta3 AH Address Address Data Data Tadw Tw Twx WAIT Note: * The waveform for DACKn is when active low is specified. Figure 9.13 Access Timing for MPX Space (Address Cycle Access Wait 1, Data Cycle Wait 1, External Wait 1)

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 301 of 1560 Mar 18, 2011 SH7080 Group

9.5.6 SDRAM Interface

SDRAM Direct Connection: The SDRAM that can be connected to this LSI is a product that has 11/12/13 bits of row address, 8/9/10 bits of column address, 4 or less banks, and uses the A10 pin for setting precharge mode in read and write command cycles. The control signals for direct connection of SDRAM are RASU, RASL, CASU, CASL, RDWR, DQMUU, DQMLU, DQMLL, CKE, CS2, and CS3. All the signals other than CS2 and CS3 are common to all areas, and signals other than CKE are valid when CS2 or CS3 is asserted. SDRAM can be connected to up to 2 spaces. The data bus width of the area that is connected to SDRAM can be set to 32 or 16 bits. Burst read/single write (burst length 1) and burst read/burst write (burst length 1) are supported as SDRAM operating mode. Commands for SDRAM can be specified by RASU, RASL, CASU, CASL, RDWR, and specific address signals. These commands are shown below.

• NOP
• Auto-refresh (REF)
• Self-refresh (SELF)
• All banks precharge (PALL)
• Specified bank precharge (PRE)
• Bank active (ACTV)
• Read (READ)
• Read with precharge (READA)
• Write (WRIT)
• Write with precharge (WRITA)
• Write mode register (MRS) The byte to be accessed is specified by DQMUU, DQMUL, DQMLU and DQMLL. Reading or writing is performed for a byte whose corresponding DQMxx low. For details on the relationship between DQMxx and the byte to be accessed, refer to section 9.5.1, Endian/Access Size and Data Alignment. Figures 9.14 to 9.16 show shows an example of the connection of SDRAM with the LSI.

Section 9 Bus State Controller (BSC) Page 302 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group As shown in figure 9.16, two sets of SDRAMs of 32 Mbytes or smaller can be connected to the same CS space by using RASU, RASL, CASU, and CASL. In this case, a total of 8 banks are assigned to the same CS space: 4 banks specified by RASL and CASL, and 4 banks specified by RASU and CASU. When accessing the address with A25 = 0, RASL and CASL are asserted. When accessing the address with A25 = 1, RASU and CASU are asserted. A15 CKE CK CSn RASU CASU RASL CASL RDWR D31 D16 DQMUU DQMUL D15 DQMLU DQMLL 64M SDRAM (1M × 16 bits × 4 banks) . . . . A13 CKE CLK CS RAS CAS WE I/O15 I/O0 DQMU DQML A13 CKE CLK CS RAS CAS WE I/O15 I/O0 DQMU DQML This LSI Unused Unused Figure 9.14 Example of 32-Bit Data Width SDRAM Connection (RASU and CASU Are Not Used)

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 303 of 1560 Mar 18, 2011 SH7080 Group A14 CKE CK CSn RASU CASU RASL CASL RDWR D15 DQMLU DQMLL 64M SDRAM (1M × 16 bits × 4 banks) . . . . A13 CKE CLK CS RAS CAS WE I/O15 I/O0 DQMU DQML . . . . This LSI Unused Unused Figure 9.15 Example of 16-Bit Data Width SDRAM Connection (RASU and CASU Are Not Used)

Section 9 Bus State Controller (BSC) Page 304 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group A14 CKE CK CSn RASU CASU RASL CASL RDWR D15 DQMLU DQMLL 64M SDRAM (1M × 16 bits × 4 banks) A13 CKE CLK CS RAS CAS WE I/O15 I/O0 DQMU DQML A13 CKE CLK CS RAS CAS WE I/O15 I/O0 DQMU DQML This LSI Figure 9.16 Example of 16-Bit Data Width SDRAM Connection (RASU and CASU Are Used)

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 305 of 1560 Mar 18, 2011 SH7080 Group Address Multiplexing: An address multiplexing is specified so that SDRAM can be connected without external address multiplexing circuitry according to the setting of bits BSZ[1:0] in CSnBCR, and AxROW[1:0] and AxCOL[1:0] in SDCR. Tables 9.20 to 9.25 show the relationship between the settings of bits BSZ[1:0], AxROW[1:0], and AxCOL[1:0] and the bits output at the address pins. Do not specify those bits in the manner other than this table, otherwise the operation of this LSI is not guaranteed. A25 to A18 are not multiplexed and the original values of address are always output at these pins. When the data bus width is 16 bits (BSZ[1:0] = B'10), the A0 pin of SDRAM specifies a word address. Therefore, connect this A0 pin of SDRAM to the A1 pin of this LSI, then A1 pin to the A2 pin, and so on. When the data bus width is 32 bits (BSZ[1:0] = B'11), the A0 pin of SDRAM specifies a longword address. Therefore, connect this A0 pin of SDRAM to the A2 pin of this LSI, then A1 pin to the A3 pin, and so on.

Section 9 Bus State Controller (BSC) Page 306 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 9.20 Relationship between BSZ[1:0], A2ROW[1:0]/A3ROW[1:0], A2COL[1:0]/A3COL[1:0], and Address Multiplex Output (1)-1 Setting BSZ[1:0] A2ROW[1:0]/ A3ROW[1:0] A2COL[1:0]/ A3COL[1:0] 11 (32 bits) 00 (11 bits) 00 (8 bits) Output Pin of This LSI Row Address Output Cycle Column Address Output Cycle SDRAM Pin Function A17 A25 A17 A16 A24 A16 A15 A23 A15 Unused A14 A22 * A22 * A12 (BA1) Specifies bank A13 A21 * A21 * A11 (BA0) A12 A20 L/H * A10/AP Specifies address/precharge A11 A19 A11 A9 A10 A18 A10 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 A1 A2 A10 A2 A0 Address A1 A9 A1 Unused A0 A8 A0 Example of connected memory 64-Mbit product (512 kwords × 32 bits × 4 banks, column 8 bits product): 1 16-Mbit product (512 kwords × 16 bits × 2 banks, column 8 bits product): 2 Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to access mode. 2. Bank address specification

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 307 of 1560 Mar 18, 2011 SH7080 Group Table 9.20 Relationship between BSZ[1:0], A2ROW[1:0]/A3ROW[1:0], A2COL[1:0]/A3COL[1:0], and Address Multiplex Output (1)-2 Setting BSZ[1:0] A2ROW[1:0]/ A3ROW[1:0] A2COL[1:0]/ A3COL[1:0] 11 (32 bits) 01 (12 bits) 00 (8 bits) Output Pin of This LSI Row Address Output Cycle Column Address Output Cycle SDRAM Pin Function A17 A24 A17 A16 A23 A16 Unused A15 A23 * A23 * A13 (BA1) Specifies bank A14 A22 * A22 * A12 (BA0) A13 A21 A13 A11 Address A12 A20 L/H * A10/AP Specifies address/precharge A11 A19 A11 A9 A10 A18 A10 A8 A9 A17 A9 A7 A8 A16 A8 A6 A7 A15 A7 A5 A6 A14 A6 A4 A5 A13 A5 A3 A4 A12 A4 A2 A3 A11 A3 A1 A2 A10 A2 A0 Address A1 A9 A1 Unused A0 A8 A0 Example of connected memory 128-Mbit product (1 Mword × 32 bits × 4 banks, column 8 bits product): 1 64-Mbit product (1 Mword × 16 bits × 4 banks, column 8 bits product): 2 Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to access mode. 2. Bank address specification

Section 9 Bus State Controller (BSC) Page 308 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 9.21 Relationship between BSZ[1:0], A2ROW[1:0]/A3ROW[1:0], A2COL[1:0]/A3COL[1:0], and Address Multiplex Output (2)-1 Setting BSZ[1:0] A2ROW[1:0]/ A3ROW[1:0] A2COL[1:0]/ A3COL[1:0] 11 (32 bits) 01 (12 bits) 01 (9 bits) Output Pin of This LSI Row Address Output Cycle Column Address Output Cycle SDRAM Pin Function A17 A26 A17 A16 A25 A16 Unused A15 A24 * A24 * A13 (BA1) Specifies bank A14 A23 * A23 * A12 (BA0) A13 A22 A13 A11 Address A12 A21 L/H * A10/AP Specifies address/precharge A11 A20 A11 A9 A10 A19 A10 A8 A9 A18 A9 A7 A8 A17 A8 A6 A7 A16 A7 A5 A6 A15 A6 A4 A5 A14 A5 A3 A4 A13 A4 A2 A3 A12 A3 A1 A2 A11 A2 A0 Address A1 A10 A1 Unused A0 A9 A0 Example of connected memory 256-Mbit product (2 Mwords × 32 bits × 4 banks, column 9 bits product): 1 128-Mbit product (2 Mwords × 16 bits × 4 banks, column 9 bits product): 2 Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to access mode. 2. Bank address specification

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 309 of 1560 Mar 18, 2011 SH7080 Group Table 9.21 Relationship between BSZ[1:0], A2ROW[1:0]/A3ROW[1:0], A2COL[1:0]/A3COL[1:0], and Address Multiplex Output (2)-2 Setting BSZ[1:0] A2ROW[1:0]/ A3ROW[1:0] A2COL[1:0]/ A3COL[1:0] 11 (32 bits) 01 (12 bits) 10 (10 bits) Output Pin of This LSI Row Address Output Cycle Column Address Output Cycle SDRAM Pin Function A17 A27 A17 A16 A26 A16 Unused A15 A25 * A25 * A13 (BA1) Specifies bank A14 A24 * A24 * A12 (BA0) A13 A23 A13 A11 Address A12 A22 L/H * A10/AP Specifies address/precharge A11 A21 A11 A9 A10 A20 A10 A8 A9 A19 A9 A7 A8 A18 A8 A6 A7 A17 A7 A5 A6 A16 A6 A4 A5 A15 A5 A3 A4 A14 A4 A2 A3 A13 A3 A1 A2 A12 A2 A0 Address A1 A11 A1 Unused A0 A10 A0 Example of connected memory 512-Mbit product (4 Mwords × 32 bits × 4 banks, column 10 bits product): 1 256-Mbit product (4 Mwords × 16 bits × 4 banks, column 10 bits product): 2 Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to access mode. 2. Bank address specification 3. Only the RASL pin is asserted because the A25 pin specifies the bank address. RASU is not asserted.

Section 9 Bus State Controller (BSC) Page 310 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 9.22 Relationship between BSZ[1:0], A2ROW[1:0]/A3ROW[1:0], A2COL[1:0]/A3COL[1:0], and Address Multiplex Output (3) Setting BSZ[1:0] A2ROW[1:0]/ A3ROW[1:0] A2COL[1:0]/ A3COL[1:0] 11 (32 bits) 10 (13 bits) 01 (9 bits) Output Pin of This LSI Row Address Output Cycle Column Address Output Cycle SDRAM Pin Function A17 A26 A17 Unused A16 A25 * A25 * A14 (BA1) A15 A24 * A24 * A13 (BA0) Specifies bank A14 A23 A14 A12 A13 A22 A13 A11 Address A12 A21 L/H * A10/AP Specifies address/precharge A11 A20 A11 A9 A10 A19 A10 A8 A9 A18 A9 A7 A8 A17 A8 A6 A7 A16 A7 A5 A6 A15 A6 A4 A5 A14 A5 A3 A4 A13 A4 A2 A3 A12 A3 A1 A2 A11 A2 A0 Address A1 A10 A1 A0 A9 A0 Unused Example of connected memory 512-Mbit product (4 Mwords × 32 bits × 4 banks, column 9 bits product): 1 256-Mbit product (4 Mwords × 16 bits × 4 banks, column 9 bits product): 2 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification 3. Only the RASL pin is asserted because the A 25 pin specifies the bank address. RASU is not asserted.

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 311 of 1560 Mar 18, 2011 SH7080 Group Table 9.23 Relationship between BSZ[1:0], A2ROW[1:0]/A3ROW[1:0], A2COL[1:0]/A3COL[1:0], and Address Multiplex Output (4)-1 Setting BSZ[1:0] A2ROW[1:0]/ A3ROW[1:0] A2COL[1:0]/ A3COL[1:0] 10 (16 bits) 00 (11 bits) 00 (8 bits) Output Pin of This LSI Row Address Output Cycle Column Address Output Cycle SDRAM Pin Function A17 A25 A17 A16 A24 A16 A15 A23 A15 A14 A22 A14 Unused A13 A21 * A21 * A12 (BA1) A12 A20 * A20 * A11 (BA0) Specifies bank A11 A19 L/H * A10/AP Specifies address/precharge A10 A18 A10 A9 A9 A17 A9 A8 A8 A16 A8 A7 A7 A15 A7 A6 A6 A14 A6 A5 A5 A13 A5 A4 A4 A12 A4 A3 A3 A11 A3 A2 A2 A10 A2 A1 A1 A9 A1 A0 Address A0 A8 A0 Unused Example of connected memory 16-Mbit product (512 kwords × 16 bits × 2 banks, column 8 bits product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification

Section 9 Bus State Controller (BSC) Page 312 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 9.23 Relationship between BSZ[1:0], A2ROW[1:0]/A3ROW[1:0], A2COL[1:0]/A3COL[1:0], and Address Multiplex Output (4)-2 Setting BSZ[1:0] A2ROW[1:0]/ A3ROW[1:0] A2COL[1:0]/ A3COL[1:0] 10 (16 bits) 01 (12 bits) 00 (8 bits) Output Pin of This LSI Row Address Output Cycle Column Address Output Cycle SDRAM Pin Function A17 A25 A17 A16 A24 A16 A15 A23 A15 Unused A14 A22 * A22 * A13 (BA1) A13 A21 * A21 * A12 (BA0) Specifies bank A12 A20 A12 A11 Address A11 A19 L/H * A10/AP Specifies address/precharge A10 A18 A10 A9 A9 A17 A9 A8 A8 A16 A8 A7 A7 A15 A7 A6 A6 A14 A6 A5 A5 A13 A5 A4 A4 A12 A4 A3 A3 A11 A3 A2 A2 A10 A2 A1 A1 A9 A1 A0 Address A0 A8 A0 Unused Example of connected memory 64-Mbit product (1 Mword × 16 bits × 4 banks, column 8 bits product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 313 of 1560 Mar 18, 2011 SH7080 Group Table 9.24 Relationship between BSZ[1:0], A2ROW[1:0]/A3ROW[1:0], A2COL[1:0]/A3COL[1:0], and Address Multiplex Output (5)-1 Setting BSZ[1:0] A2ROW[1:0]/ A3ROW[1:0] A2COL[1:0]/ A3COL[1:0] 10 (16 bits) 01 (12 bits) 01 (9 bits) Output Pin of This LSI Row Address Output Cycle Column Address Output Cycle SDRAM Pin Function A17 A26 A17 A16 A25 A16 A15 A24 A15 Unused A14 A23 * A23 * A13 (BA1) A13 A22 * A22 * A12 (BA0) Specifies bank A12 A21 A12 A11 Address A11 A20 L/H * A10/AP Specifies address/precharge A10 A19 A10 A9 A9 A18 A9 A8 A8 A17 A8 A7 A7 A16 A7 A6 A6 A15 A6 A5 A5 A14 A5 A4 A4 A13 A4 A3 A3 A12 A3 A2 A2 A11 A2 A1 A1 A10 A1 A0 Address A0 A9 A0 Unused Example of connected memory 128-Mbit product (2 Mwords × 16 bits × 4 banks, column 9 bits product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification

Section 9 Bus State Controller (BSC) Page 314 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 9.24 Relationship between BSZ[1:0], A2ROW[1:0]/A3ROW[1:0], A2COL[1:0]/A3COL[1:0], and Address Multiplex Output (5)-2 Setting BSZ[1:0] A2ROW[1:0]/ A3ROW[1:0] A2COL[1:0]/ A3COL[1:0] 10 (16 bits) 01 (12 bits) 10 (10 bits) Output Pin of This LSI Row Address Output Cycle Column Address Output Cycle SDRAM Pin Function A17 A27 A17 A16 A26 A16 A15 A25 A15 Unused A14 A24 * A24 * A13 (BA1) A13 A23 * A23 * A12 (BA0) Specifies bank A12 A22 A12 A11 Address A11 A21 L/H * A10/AP Specifies address/precharge A10 A20 A10 A9 A9 A19 A9 A8 A8 A18 A8 A7 A7 A17 A7 A6 A6 A16 A6 A5 A5 A15 A5 A4 A4 A14 A4 A3 A3 A13 A3 A2 A2 A12 A2 A1 A1 A11 A1 A0 Address A0 A10 A0 Unused Example of connected memory 256-Mbit product (4 Mwords × 16 bits × 4 banks, column 10 bits product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 315 of 1560 Mar 18, 2011 SH7080 Group Table 9.25 Relationship between BSZ[1:0], A2ROW[1:0]/A3ROW[1:0], A2COL[1:0]/A3COL[1:0], and Address Multiplex Output (6)-1 Setting BSZ[1:0] A2ROW[1:0]/ A3ROW[1:0] A2COL[1:0]/ A3COL[1:0] 10 (16 bits) 10 (13 bits) 01 (9 bits) Output Pin of This LSI Row Address Output Cycle Column Address Output Cycle SDRAM Pin Function A17 A26 A17 A16 A25 A16 Unused A15 A24 * A24 * A14 (BA1) A14 A23 * A23 * A13 (BA0) Specifies bank A13 A22 A13 A12 A12 A21 A12 A11 Address A11 A20 L/H * A10/AP Specifies address/precharge A10 A19 A10 A9 A9 A18 A9 A8 A8 A17 A8 A7 A7 A16 A7 A6 A6 A15 A6 A5 A5 A14 A5 A4 A4 A13 A4 A3 A3 A12 A3 A2 A2 A11 A2 A1 A1 A10 A1 A0 Address A0 A9 A0 Unused Example of connected memory 256-Mbit product (4 Mwords × 16 bits × 4 banks, column 9 bits product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification

Section 9 Bus State Controller (BSC) Page 316 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 9.25 Relationship between BSZ[1:0], A2ROW[1:0]/A3ROW[1:0], A2COL[1:0]/A3COL[1:0], and Address Multiplex Output (6)-2 Setting BSZ[1:0] A2ROW[1:0]/ A3ROW[1:0] A2COL[1:0]/ A3COL[1:0] 10 (16 bits) 10 (13 bits) 10 (10 bits) Output Pin of This LSI Row Address Output Cycle Column Address Output Cycle SDRAM Pin Function A17 A27 A17 A16 A26 A16 Unused A15 A25 * A25 * A14 (BA1) A14 A24 * A24 * A13 (BA0) Specifies bank A13 A23 A13 A12 A12 A22 A12 A11 Address A11 A21 L/H * A10/AP Specifies address/precharge A10 A20 A10 A9 A9 A19 A9 A8 A8 A18 A8 A7 A7 A17 A7 A6 A6 A16 A6 A5 A5 A15 A5 A4 A4 A14 A4 A3 A3 A13 A3 A2 A2 A12 A2 A1 A1 A11 A1 A0 Address A0 A10 A0 Unused Example of connected memory 512-Mbit product (8 Mwords × 16 bits × 4 banks, column 10 bits product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 2. Bank address specification 3. Only the RASL pin is asserted because the A25 pin specifies the bank address. RASU is not asserted.

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 317 of 1560 Mar 18, 2011 SH7080 Group Burst Read: A burst read occurs in the following cases with this LSI.

• Access size in reading is larger than data bus width
• 16-byte transfer in DMAC This LSI always accesses SDRAM with burst length 1. For example, read access of burst length 1 is performed consecutively 4 times to read 16-byte continuous data from SDRAM that is connected to a 32-bit data bus. This access is called number of bursts 4. Table 9.26 shows the relationship between the access size and the number of bursts. Table 9.26 Relationship between Access Size and Number of Bursts Bus Width Access Size Number of Bursts 8 bits 1 16 bits 1 32 bits 2 16 bits 16 bytes 8 8 bits 1 16 bits 1 32 bits 32 bits 1 16 bytes 4 Figures 9.17 and 9.18 show a timing chart in burst read. In burst read, an ACTV command is output in the Tr cycle, the READ command is issued in the Tc1 to Tc3 cycles, the READA command is issued in the Tc4 cycle, and the read data is received at the rising edge of the external clock (CK) in the Td1 to Td4 cycles. The Tap cycle is used to wait for the completion of an auto- precharge induced by the READ command in the SDRAM. In the Tap cycle, a new command will not be issued to the same bank. However, access to another CS space or another bank in the same SDRAM space is enabled. The number of Tap cycles is specified by the WTRP1 and WTRP0 bits in CS3WCR. In this LSI, wait cycles can be inserted by specifying each bit in CSnWCR to connect the SDRAM in variable frequencies. Figure 9.18 shows an example in which wait cycles are inserted. The number of cycles from the Tr cycle where the ACTV command is output to the Tc1 cycle where the READA command is output can be specified using the WTRCD1 and WTRCD0 bits in CS3WCR. If the WTRCD1 and WTRCD0 bits specify one cycle or more, a Trw cycle where the NOP command is issued is inserted between the Tr cycle and Tc1 cycle. The number of cycles from the Tc1 cycle where the READA command is output to the Td1 cycle where the read data is

Section 9 Bus State Controller (BSC) Page 318 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group latched can be specified for the CS2 and CS3 spaces independently, using the A2CL1 and A2CL0 bits in CS2WCR or the A3CL1 and A3CL0 bits in CS3WCR. The number of cycles from Tc1 to Td1 corresponds to the synchronous DRAM CAS latency. The CAS latency for the synchronous DRAM is normally defined as up to three cycles. However, the CAS latency in this LSI can be specified as 1 to 4 cycles. This CAS latency can be achieved by connecting a latch circuit between this LSI and the SDRAM. A Tde cycle is an idle cycle required to transfer the read data into this LSI and occurs once for every burst read or every single read. Tc4 CK A25 to A0 CSn RDWR RASL, RASU DQMxx D31 to D0 BS Tap DACKn*2 Tr Tc2 Tc3Tc1 Td4 Tde Td2 Td3Td1 A12/A11*1 CASL, CASU Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 9.17 Burst Read Basic Timing (Auto-Precharge)

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 319 of 1560 Mar 18, 2011 SH7080 Group Tc4 CK A25 to A0 CSn RDWR RASL, RASU DQMxx D31 to D0 BS Tap DACKn*2 Tr Tc2 Tc3Tc1 Td4 Tde Td2 Td3Td1 A12/A11*1 CASL, CASU Trw Tw Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 9.18 Burst Read Wait Specification Timing (Auto-Precharge)

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 321 of 1560 Mar 18, 2011 SH7080 Group Burst Write: A burst write occurs in the following cases in this LSI.

• Access size in writing is larger than data bus width
• 16-byte transfer in DMAC This LSI always accesses SDRAM with burst length 1. For example, write access of burst length 1 is performed continuously 4 times to write 16-byte continuous data to the SDRAM that is connected to a 32-bit data bus. The relationship between the access size and the number of bursts is shown in table 9.26. Figure 9.20 shows a timing chart for burst writes. In burst write, an ACTV command is output in the Tr cycle, the WRIT command is issued in the Tc1 to Tc3 cycles, and the WRITA command is issued to execute an auto-precharge in the Tc4 cycle. In the write cycle, the write data is output simultaneously with the write command. After the write command with the auto-precharge is output, the Trw1 cycle that waits for the auto-precharge initiation is followed by the Tap cycle that waits for completion of the auto-precharge induced by the WRITA command in the SDRAM. Between the Trwl and Tap cycles, a new command will not be issued to the same bank. However, access to another CS space or another bank in the same SDRAM space is enabled. The number of cycles in a Trw1 cycle is specified by the TRWL1 and TRWL0 bits in CS3WCR. The number of cycles in a Tap cycle is specified by the WTRP1 and WTRP0 bits in CS3WCR.

Section 9 Bus State Controller (BSC) Page 322 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Tc4 CK A25 to A0 CSn RDWR RASL, RASU DQMxx D31 to D0 BS Tap DACKn*2 Tr Tc2 Tc3Tc1 Trwl A12/A11*1 CASL, CASU Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 9.20 Basic Timing for SDRAM Burst Write (Auto-Precharge)

Section 9 Bus State Controller (BSC) Page 324 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group the access is performed by issuing an ACTV command followed by a READ or WRIT command. If this is followed by an access to a different row address, the access time will be longer because of the precharging performed after the access request is issued. The number of cycles between issuance of the PRE command and the ACTV command is determined by the WTRP1 and WTRP0 bits in CS3WCR. In a write, when an auto-precharge is performed, a command cannot be issued to the same bank for a period of Trwl + Tap cycles after issuance of the WRITA command. When bank active mode is used, READ or WRIT commands can be issued successively if the row address is the same. The number of cycles can thus be reduced by Trwl + Tap cycles for each write. There is a limit on tRAS, the time for placing each bank in the active state. If there is no guarantee that another row address will be accessed within the period in which this value is maintained by program execution, it is necessary to set the refresh cycle to no more than the value of tRAS. A burst read cycle without auto-precharge is shown in figure 9.22, a burst read cycle for the same row address in figure 9.23, and a burst read cycle for different row addresses in figure 9.24. Similarly, a single write cycle without auto-precharge is shown in figure 9.25, a single write cycle for the same row address in figure 9.26, and a single write cycle for different row addresses in figure 9.27. In figure 9.23, a Tnop cycle in which no operation is performed is inserted before the Tc cycle that issues the READ command. The Tnop cycle is inserted to acquire two cycles of CAS latency for the DQMxx signal that specifies the read byte in the data read from the SDRAM. If the CAS latency is specified as two cycles or more, the Tnop cycle is not inserted because the two cycles of latency can be acquired even if the DQMxx signal is asserted after the Tc cycle. When bank active mode is set, if only accesses to the respective banks in area 3 are considered, as long as accesses to the same row address continue, the operation starts with the cycle in figure area or bank during this time has no effect. If there is an access to a different row address in the bank active state, after this is detected the bus cycle in figure 9.23 or 9.26 is executed instead of that in figure 9.24 or 9.27. In bank active mode, too, all banks become inactive after a refresh cycle or after the bus is released as the result of bus arbitration.

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 325 of 1560 Mar 18, 2011 SH7080 Group Tc4 CK A25 to A0 CSn RDWR RASL, RASU DQMxx D31 to D0 BS DACKn*2 Tr Tc2 Tc3Tc1 Td4Td2 Td3Td1 Tde A12/A11*1 CASL, CASU Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 9.22 Burst Read Timing (No Auto-Precharge)

Section 9 Bus State Controller (BSC) Page 326 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Tc4 CK A25 to A0 CSn RDWR RASL, RASU DQMxx D31 to D0 BS DACKn*2 Tc2 Tc3Tc1Tnop Td4 Tde Td2 Td3Td1 A12/A11*1 CASL, CASU Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 9.23 Burst Read Timing (Bank Active, Same Row Address)

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 327 of 1560 Mar 18, 2011 SH7080 Group Tc4 CK A25 to A0 CSn RDWR D31 to D0 BS Tpw DACKn*2 Tp Tc2 Tc3Tc1 Td4Td2 Td3Td1 A12/A11*1 TdeTr RASL, RASU DQMxx CASL, CASU Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 9.24 Burst Read Timing (Bank Active, Different Row Addresses)

Section 9 Bus State Controller (BSC) Page 328 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group CK A25 to A0 CSn RDWR D31 to D0 BS DACKn*2 Tr Tc1 A12/A11*1 RASL, RASU DQMxx CASL, CASU Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 9.25 Single Write Timing (No Auto-Precharge)

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 329 of 1560 Mar 18, 2011 SH7080 Group CK A25 to A0 CSn RDWR D31 to D0 BS DACKn*2 Tnop Tc1 A12/A11*1 RASL, RASU DQMxx CASL, CASU Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 9.26 Single Write Timing (Bank Active, Same Row Address)

Section 9 Bus State Controller (BSC) Page 330 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group CK A25 to A0 CSn RDWR D31 to D0 BS Tpw DACKn*2 Tp Tc1 A12/A11*1 Tr RASL, RASU DQMxx CASL, CASU Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 9.27 Single Write Timing (Bank Active, Different Row Addresses)

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 331 of 1560 Mar 18, 2011 SH7080 Group Refreshing: This LSI has a function for controlling SDRAM refreshing. Auto-refreshing can be performed by clearing the RMODE bit to 0 and setting the RFSH bit to 1 in SDCR. A continuous refreshing can be performed by setting the RRC[2:0] bits in RTCSR. If SDRAM is not accessed for a long period, self-refresh mode, in which the power consumption is low, can be activated by setting both the RMODE bit and the RFSH bit to 1. 1. Auto-refreshing The number of refreshings set by bits RRC[2:0] in RTCSR is performed at intervals determined by the input clock selected by bits CKS[2:0] in RTCSR, and the value set in RTCOR. Register settings should be made so as to satisfy the refresh interval stipulation for the SDRAM used. First make the settings for RTCOR, RTCNT, and the RMODE and RFSH bits in SDCR, then make the CKS[2:0] and RRC[2:0] settings. When the clock is selected by bits CKS[2:0], RTCNT starts counting up from the value at that time. The RTCNT value is constantly compared with the RTCOR value, and if the two values are the same, a refresh request is generated and an auto-refresh is performed for the number of times specified by the RRC[2:0]. At the same time, RTCNT is cleared to 0 and the count-up is restarted. Figure 9.28 shows the auto-refresh cycle timing. After starting auto-refreshing, PALL command is issued in the Tp cycle to make all the banks to precharged state from active state when some bank is being precharged. Then REF command is issued in the Trr cycle after inserting idle cycles of which number is specified by the WTRP[1:0] bits in CS3WCR. A new command is not issued for the duration of the number of cycles specified by the WTRC[1:0] bits in CS3WCR after the Trr cycle. The WTRC[1:0] bits must be set so as to satisfy the SDRAM refreshing cycle time stipulation (tRC). An idle cycle is inserted between the Tp cycle and Trr cycle when the setting value of the WTRP[1:0] bits in CS3WCR is one cycle or more.

Section 9 Bus State Controller (BSC) Page 332 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group CK A25 to A0 CSn RDWR D31 to D0 BS Tpw DACKn*2 Tp Trr A12/A11*1 Trc Trc Trc Hi-Z RASL, RASU DQMxx CASL, CASU Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 9.28 Auto-Refresh Timing 2. Self-refreshing Self-refresh mode is a kind of standby mode in which the refresh timing and refresh addresses are generated within SDRAM. Self-refreshing is activated by setting both the RMODE bit and the RFSH bit in SDCR to 1. After starting the self-refreshing, PALL command is issued in the Tp cycle after the completion of the precharging bank. A SELF command is then issued after inserting idle cycles of which number is specified by the WTRP[1:0] bits in CS3WCR. SDRAM cannot be accessed while in the self-refresh state. Self-refresh mode is cleared by clearing the RMODE bit to 0. After self-refresh mode has been cleared, command issuance is disabled for the number of cycles specified by the WTRC[1:0] bits in CS3WCR. Self-refresh timing is shown in figure 9.29. After self-refreshing is cleared, settings must be made so that auto-refreshing is performed at the correct intervals. When self-refreshing is activated from the state in which auto-refreshing is set, auto-refreshing is restarted if the RFSH bit is set to 1 and the RMODE bit is cleared to 0 when self-refresh mode is cleared. If the transition from clearing of self-refresh mode to the start of auto-refreshing takes time, making the RTCNT value 1 less than the RTCOR value will enable auto-refreshing to be started immediately.

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 333 of 1560 Mar 18, 2011 SH7080 Group After self-refreshing has been specified, the SDRAM stays in the self-refresh state even after this LSI enters the standby state. The self-refresh state continues after recovery from the standby state by interrupt. However, the CKE and other pins must be driven in the standby state by setting the HIZCNT bit in the CMNCR register to 1. The self-refresh state is not cleared by a manual reset. In case of a power-on reset, the bus state controller’s registers are initialized, and therefore the self-refresh state is cleared. CK A25 to A0 CSn RDWR D31 to D0 BS Tpw DACKn*2 Tp Trr A12/A11*1 Trc Trc Trc Hi-Z Trc Trc CKE RASL, RASU DQMxx CASL, CASU Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 9.29 Self-Refresh Timing

Section 9 Bus State Controller (BSC) Page 334 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Relationship between Refresh Requests and Bus Cycles: If a refresh request occurs during bus cycle execution, the refresh cycle must wait for the bus cycle to be completed. If a refresh request occurs while the bus is released by the bus arbitration function, the refresh will not be executed until the bus mastership is acquired. This LSI has the IRQOUT pin to request the bus while waiting for refresh execution. This LSI continues to assert IRQOUT (low level) until the bus is acquired. If a new refresh request occurs while waiting for the previous refresh request, the previous refresh request is deleted. To refresh correctly, a bus cycle longer than the refresh interval or the bus mastership occupation must be prevented from occurring. If a bus mastership is requested during self-refresh, the bus will not be released until the self- refresh is cleared. Power-On Sequence: In order to use SDRAM, mode setting must first be made for SDRAM after powering on. To perform SDRAM initialization correctly, the bus state controller registers must first be set, followed by a write to the SDRAM mode register. In SDRAM mode register setting, the address signal value at that time is latched by a combination of the CSn, RASU, RASL, CASU, CASL, and RDWR signals. If the value to be set is X, the bus state controller provides for value X to be written to the SDRAM mode register by performing a word-write to address H'FFF84000 + X for area 2 SDRAM, and to address H'FFF85000 + X for area 3 SDRAM. In this operation, the write data is ignored. To set burst read/single write (burst length 1), burst read/burst write (burst length 1), CAS latency 2 and 3, wrap type = sequential, and burst length 1 supported by the LSI, arbitrary data is written in a word-size access to the addresses shown in table 9.27. In this time, 0 is output at the external address pins of A12 and later.

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 335 of 1560 Mar 18, 2011 SH7080 Group Table 9.27 Access Address in SDRAM Mode Register Write

• Setting for Area 2 (SDMR2) Burst read/single write (burst length 1): Data Bus Width CAS Latency Access Address External Address Pin 16 bits 2 H'FFF84440 H'0000440

3 H'FFF84460 H'0000460

32 bits 2 H'FFF84880 H'0000880

3 H'FFF848C0 H'00008C0

Burst read/burst write (burst length 1): Data Bus Width CAS Latency Access Address External Address Pin 16 bits 2 H'FFF84040 H'0000040

3 H'FFF84060 H'0000060

32 bits 2 H'FFF84080 H'0000080

3 H'FFF840C0 H'00000C0

• Setting for Area 3 (SDMR3) Burst read/single write (burst length 1): Data Bus Width CAS Latency Access Address External Address Pin 16 bits 2 H'FFF85440 H'0000440

3 H'FFF85460 H'0000460

32 bits 2 H'FFF85880 H'0000880

3 H'FFF858C0 H'00008C0

Burst read/burst write (burst length 1): Data Bus Width CAS Latency Access Address External Address Pin 16 bits 2 H'FFF85040 H'0000040

3 H'FFF85060 H'0000060

32 bits 2 H'FFF85080 H'0000080

3 H'FFF850C0 H'00000C0

Section 9 Bus State Controller (BSC) Page 336 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Mode register setting timing is shown in figure 9.30. A PALL command (all bank precharge command) is firstly issued. An REF command (auto-refresh command) is then issued 8 times. An MRS command (mode register write command) is finally issued. Idle cycles, of which number is specified by the WTRP[1:0] bits in CS3WCR, are inserted between the PALL and the first REF. Idle cycles, of which number is specified by the WTRC[1:0] bits in CS3WCR, are inserted between REF and REF, and between the 8th REF and MRS. Idle cycles, of which number is one or more, are inserted between the MRS and a command to be issued next. It is necessary to keep idle time of certain cycles for SDRAM after power-on before issuing PALL command. Refer to the manual of the SDRAM for the idle time to be needed. When the pulse width of the reset signal is longer than the idle time, mode register setting can be started immediately after the reset, but care should be taken when the pulse width of the reset signal is shorter than the idle time. CK A25 to A0 CSn RDWR RASL, RASU DQMxx D31 to D0 BS Tpw DACKn*2 Tp Trr A12/A11*1 CASL, CASU Trc Trc Tmw Hi-Z TnopTrc Trr Trc REF REF MRSPALL Notes: 1. Address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn is when active low is specified. Figure 9.30 SDRAM Mode Register Write Timing (Based on JEDEC)

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 337 of 1560 Mar 18, 2011 SH7080 Group

9.5.7 Burst ROM (Clock Asynchronous) Interface

The burst ROM (clock asynchronous) interface is used to access a memory with a high-speed read function using a method of address switching called burst mode or page mode. In the burst ROM (clock asynchronous) interface, basically the same access as the normal space is performed, but the 2nd and subsequent accesses are performed only by changing the address, without negating the RD signal at the end of the first cycle. In the second and subsequent accesses, addresses are changed at the falling edge of the CK. For the first access cycle, the number of wait cycles specified by the W[3:0] bits in CSnWCR is inserted. For the second and subsequent access cycles, the number of wait cycles specified by the BW[1:0] bits in CSnWCR is inserted. In the access to the burst ROM (clock asynchronous), the BS signal is asserted only to the first access cycle. An external wait input is valid only to the first access cycle. In the single access that does not perform the burst operation in the burst ROM (clock asynchronous) interface, access timing is the same as a normal space. Table 9.28 lists the relationship between bus width, access size, and the number of bursts. Figure 9.31 shows a timing chart.

Section 9 Bus State Controller (BSC) Page 338 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 9.28 Relationship between Bus Width, Access Size, and Number of Bursts Bus Width BEN Bit Access Size Number of Bursts Number of Accesses Not affected 8 bits 1 1 Not affected 16 bits 2 1 Not affected 32 bits 4 1 0 16 1 8 bits 16 bytes 4 4 Not affected 8 bits 1 1 Not affected 16 bits 1 1 Not affected 32 bits 2 1 0 8 1 16 bits 16 bytes 2 4 Not affected 8 bits 1 1 Not affected 16 bits 1 1 32 bits Not affected 32 bits 1 1 Not affected 16 bytes 4 1

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 339 of 1560 Mar 18, 2011 SH7080 Group CK Address RD D31 to D0 DACK WAIT CS T1 Tw Tw TB2 Twb TB2 Twb TB2 Twb T2 RDWR BS Figure 9.31 Burst ROM (Clock Asynchronous) Access (Bus Width = 32 Bits, 16 byte Transfer (Number of Burst = 4), Access Wait for the 1st time = 2, Access Wait for 2nd Time and after = 1)

9.5.8 SRAM Interface with Byte Selection

The SRAM interface with byte selection is a memory interface which outputs a byte-selection pin (WRxx) in a read/write bus cycle. This interface has 16-bit data pins and accesses SRAMs having upper and lower byte-selection pins, such as UB and LB. When the BAS bit in CSnWCR is cleared to 0 (initial value), the write access timing of the SRAM interface with byte selection is the same as that for the normal space interface. While in read access of the SRAM interface with byte selection, the byte-selection signal is output from the WRxx pin, which is different from that for the normal space interface. The basic access timing is shown in figure 9.32. In write access, data is written to memory according to the timing of the byte-selection pin (WRxx). For details, refer to the Data Sheet for the corresponding memory. If the BAS bit in CSnWCR is set to 1, the WRxx pin and RDWR pin timings change. Figure 9.33 shows the basic access timing. In write access, data is written to memory according to the timing of the write enable pin (RDWR). The data hold timing from RDWR negation to data write must be acquired by setting the HW1 and HW0 bits in the CSnWCR register. Figure 9.34 shows the access timing when a software wait is specified.

Section 9 Bus State Controller (BSC) Page 340 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group CK A29 to A0 CSn WRxx RDWR RD RD D31 to D0 D31 to D0 RDWR BS DACKn* Read Write T1 T2 High Note: * The waveform for DACKn is when active low is specified. Figure 9.32 Basic Access Timing for SRAM with Byte Selection (BAS = 0)

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 341 of 1560 Mar 18, 2011 SH7080 Group CK A29 to A0 CSn WRxx RD RD D31 to D0 D31 to D0 RDWR RDWR BS DACKn* Read Write T1 T2 High Note: * The waveform for DACKn is when active low is specified. Figure 9.33 Basic Access Timing for SRAM with Byte Selection (BAS = 1)

Section 9 Bus State Controller (BSC) Page 342 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group CK A29 to A0 CSn RDWR WRxx D31 to D0 BS Read Write Tf DACKn* Th T1 Tw RD RDWR D31 to D0 RD High Note: * The waveform for DACKn is when active low is specified. Figure 9.34 Byte Selection SRAM Wait Timing

Section 9 Bus State Controller (BSC) Page 344 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

9.5.9 PCMCIA Interface

With this LSI, the PCMCIA interface can be specified in areas 5 and 6. Areas 5 and 6 can be used for the IC memory card and I/O card interface defined in the JEIDA specifications version 4.2 (PCMCIA2.1 Rev. 2.1) by specifying bits TYPE2 to TYPE0 in CSnBCR (n = 5 and 6) to B'101. In addition, bits SA1 and SA0 in CSnWCR (n = 5 and 6) assign the upper or lower 32 Mbytes of each area to IC memory card or I/O card interface. For example, if bits SA1 and SA0 in CS5WCR are set to 1 and cleared to 0, respectively, the upper 32 Mbytes of area 5 are used as IC memory card interface and the lower 32 Mbytes are used as I/O card interface. When the PCMCIA interface is used, the bus size must be specified as 8 bits or 16 bits using bits BSZ1 and BSZ0 in CS5BCR or CS6BCR. Figure 9.37 shows an example of a connection between this LSI and a PCMCIA card. To enable hot swapping (insertion and removal of the PCMCIA card with the system power turned on), tri- state buffers must be connected between the LSI and the PCMCIA card. In the JEIDA and PCMCIA standards, operation in big endian mode is not clearly defined. Consequently, the provided PCMCIA interface in big endian mode is available only for this LSI.

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 345 of 1560 Mar 18, 2011 SH7080 Group This LSI PC card (memory or I/O) A25 to A0 D7 to D0 CE1 CE2 OE WE/PGM IORD IOWR REG A25 to A0 D7 to D0 D15 to D8 RDWR CE1A CE2A RD WE ICIORD ICIOWR I/O ports WAIT IOIS16 G G DIR G G DIR D15 to D8 WAIT IOIS16 CD1, CD2Card detector Figure 9.37 Example of PCMCIA Interface Connection Basic Timing for Memory Card Interface: Figure 9.38 shows the basic timing of the PCMCIA IC memory card interface. If areas 5 and 6 are specified as the PCMCIA interface, accessing the common memory areas in areas 5 and 6 automatically accesses the bus with the IC memory card interface. If the external bus frequency (CK) increases, the setup times and hold times for the address pins (A25 to A0), card enable signals (CE1A, CE1B, CE2A, CE2B), and write data (D15 to D0) to the RD and WE signals become insufficient. To prevent this error, this LSI enables the setup times and hold times for areas 5 and 6 to be specified independently, using CS5WCR and CS6WCR. In the PCMCIA interface, as in the normal space interface, a software wait or hardware wait using the WAIT pin can be inserted. Figure 9.39 shows the PCMCIA memory bus wait timing.

Section 9 Bus State Controller (BSC) Page 346 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Tpcm1w CK A25 to A0 CExx RDWR RD D15 to D0 WE D15 to D0 BS Read Write Tpcm2Tpcm1 Tpcm1w Tpcm1w Figure 9.38 Basic Access Timing for PCMCIA Memory Card Interface

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 347 of 1560 Mar 18, 2011 SH7080 Group Tpcm1w CK A25 to A0 CExx RDWR RD D15 to D0 WE D15 to D0 BS Read Write Tpcm2Tpcm0 Tpcm1 Tpcm1wTpcm0w Tpcm2wTpcm1w Tpcm1w WAIT Figure 9.39 Wait Timing for PCMCIA Memory Card Interface (TED[3:0] = B'0010, TEH[3:0] = B'0001, Hardware Wait = 1) When 32 Mbytes of the memory space are used as IC memory card interface, a port is used to generate the REG signal that switches between the common memory and attribute memory. When the memory space used for the IC memory card interface is 16 Mbytes or less, pin A24 can be used as the REG signal by allocating a 16-Mbyte common memory space and a 16-Mbyte attribute memory space.

Section 9 Bus State Controller (BSC) Page 348 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group For 32-Mbyte capacity (I/O port is used for REG) Area 5: H'14000000 Attribute memory/common memory I/O space Attribute memory/common memory I/O space Area 5: H'16000000 Area 6: H'18000000 Area 6: H'1A000000 For 16-Mbyte capacity (A24 is used for REG) Area 5: H'14000000 Attribute memory I/O space Area 5: H'15000000 Area 5: H'16000000 H'17000000 Area 6: H'18000000 Area 6: H'19000000 Area 6: H'1A000000 H'1B000000 Common memory Attribute memory I/O space Common memory Figure 9.40 Example of PCMCIA Space Assignment (CS5WCR.SA[1:0] = B'10, CS6WCR.SA[1:0] = B'10)

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 349 of 1560 Mar 18, 2011 SH7080 Group Basic Timing for I/O Card Interface: Figures 9.41 and 9.42 show the basic timings for the PCMCIA I/O card interface. The I/O card and IC memory card interfaces are switched by an address to be accessed. When area 5 is specified as the PCMCIA and both bits SA1 and SA0 in CS5WCR are set to 1, I/O card areas are allocated to address ranges from H'16000000 to H'17FFFFFF and from H'14000000 to H'15FFFFFF. When area 6 is specified as the PCMCIA and both bits SA1 and SA0 in CS6WCR are set to 1, I/O card areas allocated to address ranges from H'1A000000 to H'1BFFFFFF and from H'18000000 to H'19FFFFFF. In addition, note that this LSI does not support little endian and the IOIS16 signal must be fixed low. Tpci1w CK A25 to A0 CExx RDWR ICIORD D15 to D0 ICIOWR D15 to D0 BS Read Write Tpci2Tpci1 Tpci1w Tpci1w Figure 9.41 Basic Timing for PCMCIA I/O Card Interface

Section 9 Bus State Controller (BSC) Page 350 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Tpci1w CK A25 to A0 CExx RDWR ICIORD D15 to D0 ICIOWR IOIS16 D15 to D0 BS Read Write Tpci2Tpci0 Tpci1 Tpci1wTpci0w Tpci2wTpci1w Tpci1w WAIT Figure 9.42 Wait Timing for PCMCIA I/O Card Interface Timing (TED[3:0] = B'0010, TEH[3:0] = B'0001, Hardware Wait 1)

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 351 of 1560 Mar 18, 2011 SH7080 Group

9.5.10 Burst MPX-I/O Interface

Figure 9.43 shows an example of a connection between the LSI and the burst MPX device. Figures 9.44 to 9.47 show the burst MPX space access timings. Area 6 can be specified as the burst address/data multiplex I/O (MPX-I/O) interface using the TYPE2 to TYPE0 bits in the CS6BCR register. This MPX-I/O interface enables the LSI to be easily connected to an external memory controller chip that uses an address/data multiplexed 32- bit single bus. In this case, the address and the access size for the MPX-I/O interface are output to D25 to D0 and D31 to D29, respectively, in address cycles. For the access sizes of D31 to D29, see the description of the CS6WCR register. Address pins A25 to A0 are used to output normal addresses. In the burst MPX-I/O interface, the bus size is fixed at 32 bits. The BSZ1 and BSZ0 bits in CS6BCR must be specified as 32 bits. In the burst MPX-I/O interface, a software wait and hardware wait using the WAIT pin can be inserted. In read cycles, a wait cycle is inserted automatically following the address output even if the software wait insertion is specified as 0. This LSI CS BS FRAME WE I/O31 I/O0 WAIT CS6 BS FRAME RDWR D31 WAIT Burst MPX device Figure 9.43 Burst MPX Device Connection Example

Section 9 Bus State Controller (BSC) Page 352 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Tm1 CK D31 to D0 A25 to A0 FRAME CS6 RDWR WAIT Tmd1w Tmd1 BS DACKn* A D Note: * The waveform for DACKn is when active low is specified. Figure 9.44 Burst MPX Space Access Timing (Single Read, No Wait or Software Wait 1)

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 353 of 1560 Mar 18, 2011 SH7080 Group Tm1 CK RDWR D31 to D0 A25 to A0 WAIT FRAME Tmd1w Tmd1w Tmd1 BS CS6 DACKn* AD Note: * The waveform for DACKn is when active low is specified. Figure 9.45 Burst MPX Space Access Timing (Single Write, Software Wait 1, Hardware Wait 1)

Section 9 Bus State Controller (BSC) Page 354 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Tm1 Tmd1w CK D31 to D0 A25 to A0 FRAME CS6 RDWR WAIT Tmd1 Tmd2 Tmd3 Tmd4 BS DACKn* A D0 D1 D2 D3 Note: * The waveform for DACKn is when active low is specified. Figure 9.46 Burst MPX Space Access Timing (Burst Read, No Wait or Software Wait 1)

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 355 of 1560 Mar 18, 2011 SH7080 Group Tm1 CK D31 to D0 A25 to A0 FRAME CS6 RDWR WAIT Tmd1 Tmd2 Tmd3 Tmd4 BS DACKn A D0 D1 D2 D3 Note: The waveform for DACKn is when active low is specified. Figure 9.47 Burst MPX Space Access Timing (Burst Write, No Wait)

Section 9 Bus State Controller (BSC) Page 356 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

9.5.11 Burst ROM (Clock Synchronous) Interface

The burst-ROM (clock synchronous) interface provides high-speed access to ROM that has a synchronous burst function. Access through this interface is basically performed in the same way as access to the normal space. If this interface is used, it must be placed in area 0. For the first access cycle, the number of wait cycles specified by the W3 to W0 bits in CS0WCR are inserted. For the second and subsequent access cycles, the number of wait cycles specified by the BW1 and BW0 bits in CS0WCR are inserted (0 to 3 cycles). In access to the burst ROM (clock synchronous), the BS signal is only asserted on the first access cycle. Furthermore, an external wait input is only valid for the first access cycle. Set burst length = 8 when the bus width is 16 bits and burst length = 4 when the bus width is 32 bits. The 8-bit bus width is not supported. All read access through this interface is in burst mode. For example, in accessing a longword when the bus width is 16 bits, the data from the first two read operations are valid but unnecessary data is read out in the next six dummy operations. This dummy reading slows down memory access rate, lengthening program-execution and DMA- transfer times. Avoiding this requires the effective use of 16-byte DMA transfer. Twb CK Address CS0 RDWR RD D15 to D0 DACKn* BS T1 T2Tw T2BTw T2B Twb Twb T2B T2B Twb Twb T2B T2B Twb T2B Twb WAIT Note: * The waveform for DACKn is when active low is specified. Figure 9.48 Burst ROM (Clock Synchronous) Access Timing (Burst Length = 8, Access Wait for the 1st time = 2, Access Wait for 2nd Time after = 1)

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 357 of 1560 Mar 18, 2011 SH7080 Group

9.5.12 Wait between Access Cycles

As the operating frequency of LSIs becomes higher, the off-operation of the data buffer often collides with the next data output when the data output from devices with slow access speed is completed. As a result of these collisions, the reliability of the device is low and malfunctions may occur. A function that avoids data collisions by inserting wait cycles between continuous access cycles has been newly added. The number of wait cycles between access cycles can be set by bits IWW[1:0], IWRWD[1:0], IWRWS[1:0], IWRRD[1:0], and IWRRS[1:0] in CSnBCR, and bits DMAIW[1:0] and DMAIWA in CMNCR. The conditions for setting the wait cycles between access cycles (idle cycles) are shown below. 1. Continuous accesses are write-read or write-write 2. Continuous accesses are read-write for different spaces 3. Continuous accesses are read-write for the same space 4. Continuous accesses are read-read for different spaces 5. Continuous accesses are read-read for the same space 6. Data output cycle of an exte rnal device caused by DMA transfer in single address mode is followed by data output from another device that includes this LSI (DMAIWA = 0) 7. Data output cycle of an exte rnal device caused by DMA transfer in single address mode is followed by any type of access (DMAIWA = 1) Besides the wait cycles between access cycles (idle cycles) described above, idle cycles must be inserted to reserve the minimum pulse width for a multiplexed pin (WRxx), and an interface with an internal bus. 8. Idle cycle of the external bus fo r the interface with the internal bus A. Insert one idle cycle imme diately before a write access cycle after an external bus idle cycle or a read cycle. B. Insert one idle cycle to tran sfer the read data to the internal bus when a read cycle of the external bus terminates. Insert two to three idle cycles including the idle cycle in A. for the write cycle immediately after a read cycle. 9. Idle cycle of the external bus for accessing different memory For accessing different memory, insert idle cycles as follows. The byte-selection SRAM interface with the BAS bit = 1 specified is handled as an SDRAM interface because the WRxx change timing is identical.

Section 9 Bus State Controller (BSC) Page 358 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group A. Insert one idle cycle to access the interface other than the SDRAM interface after the write access cycle is performed in the SDRAM interface. B. Insert one idle cycle to access the SDRA M interface after the normal space interface with the external wait invalidated or the byte-selection SRAM interface with the BAS bit = 0 specified is accessed. C. Insert one idle cycle to access the SD RAM interface after the MPX-I/O interface is accessed. D. Insert two idle cycles to access the MPX-I/O interface from the external bus that is in the idle status. E. Insert one idle cycle to access the MPX-I/O in terface after a read cycle is performed in the normal space interface, byte-selection SRAM interface with the BAS bit = 0, and the SDRAM interface. F. Insert two idle cycles to access the MPX-I/O interface after a write cycle is performed in the SDRAM interface. Tables 9.29 to 9.34 list the minimum number of idle cycles to be inserted for the normal space interface and the SDRAM interface. The CSnBCR Idle Setting column in the tables describes the number of idle cycles to be set for IWW, IWRWD, IWRWS, IWRRD, and IWRRS.

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 359 of 1560 Mar 18, 2011 SH7080 Group Table 9.29 Minimum Number of Idle Cycles between CPU Access Cycles in Normal Space Interface BSC Register Setting When Access Size is Less than Bus Width When Access Size Exceeds Bus Width CSnWCR. WM Setting CSnBCR Idle Setting Read to Read Write to Write Read to Write Write to Read Contin- uous Read Contin- uous Write* Read to Read* Write to Write Read to Write Write to Read Notes: The minimum numbers of idle cycles are described sequentially for I φ:Bφ = 4:1, 3:1, 2:1, and 1:1. 1. Minimum number of idle cycles between the word access to address 0 and the word access to address 2 in the 32-bit access with a 16-bit bus width, minimum number of idle cycles between the byte access to address 0 and the byte access to address 1 in the 16-bit access with an 8-bit bus width, minimum number of idle cycles between the byte accesses to address 0, to address 1, to address 2, and to address 3 in the 32-bit access with an 8-bit bus width, and minimum number of idle cycles between consecutive accesses in 16-byte transfer. 2. Other than the above cases

Section 9 Bus State Controller (BSC) Page 360 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 9.30 Minimum Number of Idle Cycles between Access Cycles during DMAC Dual Address Mode and DTC Transfer for the Normal Space Interface BSC Register Setting When Access Size is Less than Bus Width When Access Size Exceeds Bus Width CSnWCR. WM Setting CSnBCR Idle Setting Read to Write Write to Read Continuous Read* Read to Write* Continuous Write* Write to Read* 1 0 2 0 0 2 0 0 0 0 2 1 1 2 1 1 1 1 2 1 1 2 1 1 0 1 2 1 1 2 1 1 1 2 2 2 2 2 2 2 0 2 2 2 2 2 2 2 1 4 4 4 4 4 4 4 0 4 4 4 4 4 4 4 Notes: DMAC and DTC are driven by B φ. The minimum number of idle cycles is not affected by changing a clock ratio. 1. Minimum number of idle cycles between the word access to address 0 and the word access to address 2 in the 32-bit access with a 16-bit bus width, minimum number of idle cycles between the byte access to address 0 and the byte access to address 1 in the 16-bit access with an 8-bit bus width, minimum number of idle cycles between the byte accesses to address 0, to address 1, to address 2, and to address 3 in the 32-bit access with an 8-bit bus width, and minimum number of idle cycles between consecutive accesses in 16-byte transfer. 2. Other than the above cases.

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 361 of 1560 Mar 18, 2011 SH7080 Group Table 9.31 Minimum Number of Idle Cycles during DMAC Single Address Mode Transfer to the Normal Space Interface from the External Device with DACK (1) Transfer from the external device with DACK to the normal space interface BSC Register Setting* Minimum Number of Idle Cycles CSnWCR.WM Setting CMNCR.DMAIWA Setting CMNCR.DMAIW Idle Setting When Access Size is Greater than Bus Width* When Access Size is Less than or Equal to Bus Width* 1 0 ⎯ 0 1 * 0 0 ⎯ 1 1 1 1 0 0 1 * 0 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 2 2 2 0 1 2 2 2 1 1 4 4 4 0 1 4 4 4

Section 9 Bus State Controller (BSC) Page 362 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group (2) Transfer from the normal space interface to the external device with DACK BSC Register Setting* Minimum Number of Idle Cycles CSnWCR.WM Setting CSnBCR Idle Setting When Access Size is Greater than Bus Width* When Access Size is Less than or Equal to Bus Width* 1 0 0 2 0 0 1 3 1 1 1 2 0 1 1 3 1 2 2 2 0 2 2 3 1 4 4 4 0 4 4 4 Notes: DMAC is driven by B φ. The minimum number of idle cycles is not affected by changing a clock ratio. 1. Minimum number of idle cycles between the word access to address 0 and the word access to address 2 in the 32-bit access with a 16-bit bus width, minimum number of idle cycles between the byte access to address 0 and the byte access to address 1 in the 16-bit access with an 8-bit bus width, minimum number of idle cycles between the byte accesses to address 0, to address 1, to address 2, and to address 3 in the 32-bit access with an 8-bit bus width, and minimum number of idle cycles between consecutive accesses in 16-byte transfer. 2. Other than the above cases. 3. For single address mode transfer from the external device with DACK to the normal space interface, the minimum number of idle cycles is not affected by the IWW, IWRWD, IWRWS, IWRRD, and IWRRS bits in CSnBCR. 4. For single address mode transfer from the normal space interface to the external device with DACK, the minimum number of idle cycles is not affected by the DMAIWA and DMAIW bits in CMNCR. 5. When the HW[1:0] in the CSnWCR is set to specify 2.5 cycles or more, the number of idle cycles will be 0.

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 363 of 1560 Mar 18, 2011 SH7080 Group Table 9.32 Minimum Number of Idle Cycles between Access Cycles of CPU, the DMAC Dual Address Mode, and DTC for the SDRAM Interface BSC Register Setting CPU Access DMAC or DTC Access CSnBCR Idle Setting CS3WCR. WTRP Setting CS3WCR. TRWL Setting Read to Read Write to Write Read to Write Write to Read Read to Write Write to Read

Section 9 Bus State Controller (BSC) Page 364 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group BSC Register Setting CPU Access DMAC or DTC Access CSnBCR Idle Setting CS3WCR. WTRP Setting CS3WCR. TRWL Setting Read to Read Write to Write Read to Write Write to Read Read to Write Write to Read

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 365 of 1560 Mar 18, 2011 SH7080 Group BSC Register Setting CPU Access DMAC or DTC Access CSnBCR Idle Setting CS3WCR. WTRP Setting CS3WCR. TRWL Setting Read to Read Write to Write Read to Write Write to Read Read to Write Write to Read Note: The minimum numbers of idle cycles in CPU Access are described sequentially for I φ:Bφ = DMAC and DTC are driven by B φ. The minimum number of idle cycles is not affected by changing a clock ratio.

Section 9 Bus State Controller (BSC) Page 366 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 9.33 Minimum Number of Idle Cycles between Access Cycles of the DMAC Single Address Mode for the SDRAM Interface (1) Transfer from the external device with DACK to the SDRAM interface: BSC Register Setting* CMNCR.DMAIW Setting CS3WCR.WTRP Setting CS3WCR.TRWL Setting Minimum Number of Idle Cycles 0 1 0 1 * 0 1 1 1 0 1 2 2 0 1 3 3 0 2 0 1 0 2 1 2 0 2 2 3 0 2 3 4 0 3 0 2 0 3 1 3 0 3 2 4 0 3 3 5 0 4 0 3 0 4 1 4 0 4 2 5 0 4 3 6 1 1 0 1 1 1 1 1 1 1 2 2 1 1 3 3 1 2 0 1 1 2 1 2 1 2 2 3 1 2 3 4 1 3 0 2 1 3 1 3 1 3 2 4 1 3 3 5 1 4 0 3

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 367 of 1560 Mar 18, 2011 SH7080 Group BSC Register Setting* CMNCR.DMAIW Setting CS3WCR.WTRP Setting CS3WCR.TRWL Setting Minimum Number of Idle Cycles 1 4 1 4 1 4 2 5 1 4 3 6 2 1 0 2 2 1 1 2 2 1 2 2 2 1 3 3 2 2 0 2 2 2 1 2 2 2 2 3 2 2 3 4 2 3 0 2 2 3 1 3 2 3 2 4 2 3 3 5 2 4 0 3 2 4 1 4 2 4 2 5 2 4 3 6 4 1 0 4 4 1 1 4 4 1 2 4 4 1 3 4 4 2 0 4 4 2 1 4 4 2 2 4 4 2 3 4 4 3 0 4 4 3 1 4 4 3 2 4 4 3 3 5 4 4 0 4 4 4 1 4

Section 9 Bus State Controller (BSC) Page 368 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group BSC Register Setting* CMNCR.DMAIW Setting CS3WCR.WTRP Setting CS3WCR.TRWL Setting Minimum Number of Idle Cycles 4 4 2 5 4 4 3 6 Notes: DMAC is driven by B φ. The minimum number of idle cycles is not affected by changing a clock ratio. 1. For single address mode transfer from the external device with DACK to the SDRAM interface, the minimum number of idle cycles is not affected by the IWW, IWRWD, IWRWS, IWRRD, and IWRRS bits in CSnBCR. 2. Set the WTRCD bits to select 1 cycle or less.

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 369 of 1560 Mar 18, 2011 SH7080 Group Table 9.34 Minimum Number of Idle Cycles between Access Cycles of the DMAC Single Address Mode for the SDRAM Interface (2) Transfer from the SDRAM interface to the external device with DACK BSC Register Setting* CS3BCR Idle Setting CS3WCR.WTRP Setting Minimum Number of Idle Cycles 0 1 3 0 2 3 0 3 3 0 4 4 1 1 3 1 2 3 1 3 3 1 4 4 2 1 3 2 2 3 2 3 3 2 4 4 4 1 5 4 2 5 4 3 5 4 4 5 Notes: DMAC is driven by B φ. The minimum number of idle cycles is not affected by changing a clock ratio. * Other than the following cases. Single address mode transfer from the external device with DACK to the SDRAM interface, where the minimum number of idle cycles is not affected by the IWW, IWRWD, IWRWS, IWRRD, and IWRRS bits in CSnBCR. CMNCR.DMAIWA = 0, where the setting is identical to CMNCR.DMAIW[1:0] in table 9.33.

Section 9 Bus State Controller (BSC) Page 370 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

9.5.13 Bus Arbitration

This LSI owns the bus mastership in normal state and releases the bus only when receiving a bus request from an external device. This LSI has three bus masters: CPU, DMAC, and DTC. The bus mastership is given to these bus masters in accordance with the following priority. Request for bus mastership by external device (BREQ) > CPU > DTC > DMAC > CPU. However, when DTC or DMAC is requesting the bus mastership, the CPU does not obtain the bus mastership continuously. The following cases should be noted regarding the external space access request from the CPU. 1. When the CSSTP2 bit is 1 in the bus function extending register (BSCHER), the external space access request from the CPU has lower priority than the burst transfer request from the DMAC and DTC transfer request with DTLOCK = 0 in the bus function extending register (BSCHER). 2. When an activation request is generated in the order of DMAC and DTC while an external space is being accessed by the CPU, DMA transfer is executed first and then DTC transfer. Figure 9.49 shows the bus arbitration when the DTC and DMAC compete while an external space is accessed by the CPU.

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 371 of 1560 Mar 18, 2011 SH7080 Group DTC DMAC Priority determination Priority determination DTC DMAC DTC DMAC Transfer is started for the request that is generated first Transfer is started for the request that is generated first Transfer is started in accordance with the bus priority (DTC>DMAC) Transfer is started in accordance with the bus priority (DTC>DMAC) Internal bus External space access from CPU External space access from CPU External space access from CPU Access to on-chip peripheral module from CPU DMAC DTC DTC activation request

• When activation request is generated in the order of DMAC and DTC during external space access from CPU [Reference] When activation request is generated in the order of DMAC and DTC during access to an on-chip peripheral module by CPU
• When activation request is generated in the order of DTC and DMAC during external space access from CPU
• When activation request is generated for DTC and DMAC at the same time during external space access from CPU DMAC activation request Internal bus DTC activation request DMAC activation request Internal bus DTC activation request DMAC activation request Internal bus DTC activation request DMAC activation request Figure 9.49 Bus Arbitration when DTC and DMAC Compete during External Space Access from CPU

Section 9 Bus State Controller (BSC) Page 372 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group In addition, because the write buffer operates as described in section 9.5.14 (2), Access in View of LSI Internal Bus Master, arbitration between the CPU and DTC/DMAC is different depending on whether the external space access by the CPU is a write or read access. Figure 9.50 shows the bus arbitration when a DTC or DMAC activation request is generated while an external space is accessed by CPU.

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 373 of 1560 Mar 18, 2011 SH7080 Group DTC/DMAC DTC/DMAC DTC/DMACRead access to external space from CPU Read access to external space from CPU Write to external space from CPU Write to external space from CPU Write to external space 1 from CPU Write access to external space 1 from CPU Write to external space 2 from CPU Write access to external space 2 from CPU Write access to external space from CPU Write access to external space from CPU Read access to external space from CPU Read access to external space from CPU DTC/DMAC activation request is generated in this period. DTC/DMAC activation request is generated in this period. DTC/DMAC activation request is generated in this period. DTC/DMAC activation request is generated in this period. DTC/DMAC Internal bus External bus External bus External bus External bus

• When DTC/DMAC activation request is generated during read access to external space from CPU
• When DTC/DMAC activation request is generated during write access to external space from CPU (1)
• When DTC/DMAC activation request is generated during write access to external space from CPU (2) (When external space read request is generated by CPU during execution of write access to external space from CPU)
• When DTC/DMAC activation request is generated during write access to external space from CPU (3) (When external space write request is generated by CPU during execution of write access to external space from CPU) DTC/DMAC activation request DTC/DMAC activation request DTC/DMAC activation request DTC/DMAC activation request Internal bus Internal bus Internal bus Figure 9.50 Bus Arbitration when DTC or DMAC Activation Request Occurs during External Space Access from CPU

Section 9 Bus State Controller (BSC) Page 374 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group The states that do not allow bus arbitration are shown below. 1. Between the read and write cycles of a TAS instruction 2. Multiple bus cycles generated when the data bus width is smaller than the access size (for example, between bus cycles when longword access is made to a memory with a data bus width of 8 bits) 3. 16-byte transfer by the DMAC To prevent device malfunction while the bus mastership is transferred to the external device, the LSI negates all of the bus control signals before bus release. When the bus mastership is received, all of the bus control signals are first negated and then driven appropriately. In addition, to prevent noise while the bus control signal is in the high impedance state, pull-up resistors must be connected to these control signals. Bus mastership is transferred to the external device at the boundary of bus cycles. Namely, bus mastership is released immediately after receiving a bus request when a bus cycle is not being performed. The release of bus mastership is delayed until the bus cycle is complete when a bus cycle is in progress. Even when from outside the LSI it looks like a bus cycle is not being performed, a bus cycle may be performing internally, started by inserting wait cycles between access cycles. Therefore, it cannot be immediately determined whether or not bus mastership has been released by looking at the CSn signal or other bus control signals. The external bus release by the BREQ and BACK signal handshaking requires some overhead. If the slave has many tasks, multiple bus cycles should be executed in a bus mastership acquisition. Reducing the cycles required for master to slave bus mastership transitions streamlines the system design. The LSI has the bus mastership until a bus request is received from the external device. Upon acknowledging the assertion (low level) of the external bus request signal BREQ, the LSI releases the bus at the completion of the current bus cycle and asserts the BACK signal. After the LSI acknowledges the negation (high level) of the BREQ signal that indicates the slave has released the bus, it negates the BACK signal and resumes the bus usage. When the SDRAM interface is used, an all bank precharge command (PALL) is issued if any active banks exist and releases the bus after completion of the PALL command. Processing by this LSI continues even while bus mastership is released to an external device, unless an external device is accessed. When an external device is accessed, the LSI enters the state of waiting for bus mastership to be returned. While the bus is released, sleep mode, software standby mode, and deep software standby mode cannot be entered.

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 375 of 1560 Mar 18, 2011 SH7080 Group The bus release sequence is as follows. The address bus and data bus are placed in a high- impedance state synchronized with the rising edge of CK. The bus mastership acknowledge signal is asserted 0.5 cycles after the above high impedance state, synchronized with the falling edge of CK. The bus control signals such as CSn are placed in the high-impedance state at subsequent rising edges of CK. These bus control signals go high one cycle before being placed in the high- impedance state. Bus request signals are sampled at the falling edge of CK. By setting the HIZCNT bit in CMNR, the CKE, RASU, RASL, CASU, and CASL can be continued to be driven even after the bus is released using the values immediately before the bus release. The sequence for reclaiming the bus mastership from an external device is described below. At 1.5 cycles after the negation of BREQ is detected at the falling edge of CK, the bus control signals are driven high. The bus acknowledge signal is negated at the next falling edge of the clock. The fastest timing at which actual bus cycles can be resumed after bus control signal assertion is at the rising edge of the CK where address and data signals are driven. Figure 9.51 shows the bus arbitration timing in master mode. In an original external device designed by the user, multiple bus accesses may be generated continuously to reduce the overhead caused by bus arbitration. In this case, to execute SDRAM refresh correctly, the external device must be designed to release the bus mastership within the refresh interval time. This LSI has the IRQOUT pin to request the bus while waiting for refresh execution. This LSI continues to assert IRQOUT (low level) until the bus is acquired. When the external device receives this signal and releases the bus, the LSI acquires the bus and executes refresh. After BREQ assertion (low level; bus request), the BREQ signal should be negated (high level; bus release) only after the BACK is asserted (low level; bus acknowledge). If BREQ is negated before BACK is asserted, BACK may be asserted only for one cycle depending on the BREQ negation timing, and a bus conflict may occur between the external device and this LSI. CK Other bus control signals BREQ BACK A29 to A0 D31 to D0 CSn Figure 9.51 Bus Arbitration Timing

Section 9 Bus State Controller (BSC) Page 376 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Acceptance of mastership for the DMAC in bus arbitration takes 1Bφ, so a NOP 1Bφ in duration is inserted on the I bus. Acceptance of mastership for the DTC in bus arbitration does not require the insertion of a NOP, so bus access proceeds continuously.

9.5.14 Others

(1) Reset The bus state controller (BSC) can be initialized completely only at a power-on reset. At a power- on reset, all signals are negated and output buffers are turned off regardless of the bus cycle state. All control registers are initialized. In standby, sleep, and manual reset, control registers of the bus state controller are not initialized. At a manual reset, the current bus cycle being executed is completed and then the access wait state is entered. If a 16-byte transfer is performed by the DMAC is executed, the current access is cancelled in longword units because the access request is cancelled by the bus master at a manual reset. Since the RTCNT continues counting up during manual reset signal assertion, a refresh request occurs to initiate the refresh cycle. However, a bus arbitration request by the BREQ signal cannot be accepted during manual reset signal assertion. (2) Access in View of LSI Internal Bus Master There are three types of LSI internal buses: L bus, I bus, and peripheral bus. The CPU is connected to the L bus. The DMAC, DTC, and bus state controller are connected to the I bus. Low-speed peripheral modules are connected to the peripheral bus. On-chip memories are connected bidirectionally to the L bus and I bus. For an access of an external space or an on-chip peripheral module, the access is initiated via the I bus. Thus, the DMAC and DTC can be activated without bus arbitration with the CPU while the CPU is accessing an on-chip memory. Since the bus state controller (BSC) incorporates a one-stage write buffer, the BSC can execute an access via the I bus before the previous external bus cycle is completed in a write cycle. If the on- chip peripheral module is read or written after the external low-speed memory is written, the on- chip peripheral module can be accessed before the completion of the external low-speed memory write cycle. In read cycles, the CPU is placed in the wait state until read operation has been completed. To continue the process after the data write to the device has been completed, perform a dummy read to the same address to check for completion of the write before the next process to be executed.

Section 9 Bus State Controller (BSC) R01UH0198EJ0500 Rev. 5.00 Page 377 of 1560 Mar 18, 2011 SH7080 Group The write buffer of the BSC functions in the same way for an access by the DMAC and DTC. Accordingly, to perform dual address DMA transfers, the next read cycle is initiated before the previous write cycle is completed. Note, however, that if both the DMA source and destination addresses exist in external memory space, the next read cycle will not be initiated until the previous write cycle is completed. Since access cannot be performed correctly if any BSC register values are modified while the write buffer is operating, do not modify BSC registers immediately after a write access. If the BSC register need to be modified immediately after a write access, execute dummy read to confirm the completion of the write access, then modify the BSC register.

Section 9 Bus State Controller (BSC) Page 378 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

9.5.15 Access to On-Chip FLASH and On-Chip RAM by CPU

Access to the on-chip FLASH for read is synchronized with Iφ clock and is executed in one clock cycle. For details on programming and erasing, see section 23, Flash Memory. Access to the on-chip RAM for read/write is synchronized with I φ clock and is executed in one clock cycle. For details, see section 25, RAM.

9.5.16 Access to On-Chip Peripheral I/O Registers by CPU

Table 9.35 shows the number of cycles required for access to the on-chip peripheral I/O registers by the CPU. Table 9.35 Number of Cycles for Acces s to On-Chip Peripheral I/O Registers Number of Access Cycles Write (3 + n) × Iφ + (1 + m) × Bφ + 2 × Pφ Read (3 + n) × Iφ + (1 + m) × Bφ + 2 × Pφ + 2 × Iφ Notes: 1. When I φ:Bφ = 8:1, n = 0 to 7. When I φ:Bφ = 4:1, n = 0 to 3. When B φ:Pφ = 4:1, m = 0 to 3. When I φ:Bφ = 3:1, n = 0 to 2. When B φ:Pφ = 3:1, m = 0 to 2. When I φ:Bφ = 2:1, n = 0 to 1. When B φ:Pφ = 2:1, m = 0 to 1. When I φ:Bφ = 1:1, n = 0. When B φ:Pφ = 1:1, m = 0. n and m depend on the internal execution state. 2. The clock ratio of MI φ and MPφ does not affect the number of access cycles. Synchronous logic and a layered bus structure have been adopted for this LSI. Data on each bus are input and output in synchronization with rising edges of the corresponding clock signal. The L bus, I bus, and peripheral bus are synchronized with the Iφ, Bφ, and Pφ clock, respectively. Figure 9.52 shows an example of the timing of write access to a register in 2Pφ cycle access with the connected peripheral bus width of 16 bits when Iφ:Bφ:Pφ = 4:2:2. In access to the on-chip peripheral I/O registers, the CPU requires three cycles of Iφ for preparation of data transfer to the I bus after the data has been output to the L bus. After these three cycles, data can be transferred to the I bus in synchronization with rising edges of Bφ. However, as there are two Iφ clock cycles in a single Bφ clock cycle when Iφ: Bφ = 4:2, transfer of data from the L bus to the I bus takes (3 + n) × Iφ (n = 0 to 1) (3 × Iφ is indicated in figure 9.52). The relation between the timing of data output to the L bus and the rising edge of Bφ depends on the state of program execution. In the

Section 9 Bus State Controller (BSC) Page 380 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

9.5.17 Access to External Memory by CPU

Table 9.36 shows the number of cycles required for access to the external memory by the CPU. As the table shows, the number of cycles varies with the clock ratio, the access size, the external bus width of the LSI, and the setting for wait insertion. For details on the wait-insertion setting, see section 9.4, Register Descriptions. Table 9.36 Number of Ex ternal Access Cycles External Bus Width Access Size Write/Read Number of Access Cycles Write (1 + n) × Iφ + (3 + m) × Bφ Byte Read (1 + n) × Iφ + (3 + m) × Bφ + 1 × Iφ Write (1 + n) × Iφ + (3 + m) × Bφ + 1 × (2 + o) × Bφ Word Read (1 + n) × Iφ + (3 + m) × Bφ + 1 × (2 + o) × Bφ + 1 × Iφ Write (1 + n) × Iφ + (3 + m) × Bφ + 3 × (2 + o) × Bφ 8 bits Longword Read (1 + n) × Iφ + (3 + m) × Bφ + 3 × (2 + o) × Bφ + 1 × Iφ Write (1 + n) × Iφ + (3 + m) × Bφ Byte/Word Read (1 + n) × Iφ + (3 + m) × Bφ + 1 × Iφ Write (1 + n) × Iφ + (3 + m) × Bφ + 1 × (2 + o) × Bφ 16 bits Longword Read (1 + n) × Iφ + (3 + m) × Bφ + 1 × (2 + o) × Bφ + 1 × Iφ Write (1 + n) × Iφ + (3 + m) × Bφ 32 bits Byte/Word/ Longword Read (1 + n) × Iφ + (3 + m) × Bφ + 1 × Iφ Note: n: When I φ:Bφ = 8:1, n = 0 to 7. When I φ:Bφ = 4:1, n = 0 to 3. When I φ:Bφ = 3:1, n = 0 to 2. When I φ:Bφ = 2:1, n = 0 to 1. When I φ:Bφ = 1:1, n = 0. m, o: m: Wait setting, o: Wait setting + idle setting For details, see section 9.4, Register Descriptions. Synchronous logic and a layered bus structure have been adopted for this LSI circuit. Data on each bus are input and output in synchronization with rising edges of the corresponding clock signal. The L bus and I bus are synchronized with the Iφ and Bφ clocks, respectively. Figure 9.54 shows an example of the timing of write access to a word of data over the external bus, with a bus-width of 8 bits, when Iφ:Bφ = 2:1. Once the CPU has output the data to the L bus, data are transferred to the I bus in synchronization with rising edges of Bφ. There are two Iφ clock cycles in a single Bφ clock cycle when Iφ: Bφ = 2:1. Thus, when Iφ: Bφ = 2:1, data transfer from the L bus to the I bus

Section 9 Bus State Controller (BSC) Page 382 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Iφ L bus Bφ (CK) I bus External bus External access This access period is prolonged by a period of m. In this example, m = 0. For the numbers of cycles by which m prolongs the access process, see section 9.4, Register Descriptions. (1 + n) × Iφ (3 + m) × Bφ 1 × Iφ Figure 9.55 Timing of Read Access with Condition Iφ:Bφ = 4:1 and External Bus Width ≥ Data Width For access by the DMAC or the DTC, the access cycles are obtained by subtracting the cycles of Iφ required for L-bus access from the access cycles required for access by the CPU.

Section 10 Direct Memory Access Controller (DMAC) R01UH0198EJ0500 Rev. 5.00 Page 383 of 1560 Mar 18, 2011 SH7080 Group Section 10 Direct Memory Access Controller (DMAC) This LSI includes the direct memory access controller (DMAC). The DMAC can be used in place of the CPU to perform high-speed transfers between external devices that have DACK (transfer request acknowledge signal), external memory, on-chip memory, memory-mapped external devices, and on-chip peripheral modules.

10.1 Features

• Four channels (external requests can be received)
• 4-Gbyte physical address space
• Data transfer unit is selectable: Byte, word (2 bytes), longword (4 bytes), and 16 bytes (longword × 4)
• Maximum transfer count: 16,777,216 transfers
• Address mode: Dual address mode or single address mode can be selected.
• Transfer requests: External request, on-chip peripheral module request, or auto request can be selected.
• Selectable bus modes: Cycle steal mode (normal mode and intermittent mode) or burst mode can be selected.
• Selectable channel priority levels: The channel priority levels are selectable between fixed mode and round-robin mode.
• Interrupt request: An interrupt request can be generated to the CPU after transfers end by the specified counts.
• External request detection: There are following four types of DREQ input detection. ⎯ Low level detection ⎯ High level detection ⎯ Rising edge detection ⎯ Falling edge detection
• Transfer request acknowledge signal: Active levels for DACK can be set independently.

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10.2 Input/Output Pins

The external pins for the DMAC are described below. Table 10.1 lists the configuration of the pins that are connected to external bus. The DMAC has pins for 4 channels for external bus use. Table 10.1 Pin Configuration Channel Pin Name Symbol I/O Function DMA transfer request DREQ0 Input DMA transfer request input from external device to channel 0 DMA transfer request acknowledge DACK0 Output DMA transfer request acknowledge output from channel 0 to external device DMA transfer end TEND0 Output DMA transfer end output for channel 0 DMA transfer request DREQ1 Input DMA transfer request input from external device to channel 1 DMA transfer request acknowledge DACK1 Output DMA transfer request acknowledge output from channel 1 to external device DMA transfer end TEND1 Output DMA transfer end output for channel 1 DMA transfer request DREQ2 Input DMA transfer request input from external device to channel 2 DMA transfer request acknowledge DACK2 Output DMA transfer request acknowledge output from channel 2 to external device

3 DMA transfer request DREQ3 Input DMA transfer request input from

external device to channel 3 DMA transfer request acknowledge DACK3 Output DMA transfer request acknowledge output from channel 3 to external device

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10.3 Register Descriptions

The DMAC has the following registers. See section 27, List of Registers, for the addresses of these registers and the state of them in each processing status. The SAR for channel 0 is expressed such as SAR_0. Table 10.2 Register Configuration Channel Register Name Abbrevia- tion R/W Initial value Address Access Size

0 DMA source

address register_0 SAR_0 R/W H'00000000 H'FFFFEB20 16, 32 DMA destination address register_0 DAR_0 R/W H'00000000 H'FFFFEB24 16, 32 DMA transfer count register_0 DMATCR_0 R/W H'00000000 H'FFFFEB28 16, 32 DMA channel control register_0 CHCR_0 R/W H'00000000 H'FFFFEB2C 8, 16, 32

1 DMA source

address register_1 SAR_1 R/W H'00000000 H'FFFFEB30 16, 32 DMA destination address register_1 DAR_1 R/W H'00000000 H'FFFFEB34 16, 32 DMA transfer count register_1 DMATCR_1 R/W H'00000000 H'FFFFEB38 16, 32 DMA channel control register_1 CHCR_1 R/W H'00000000 H'FFFFEB3C 8, 16, 32

2 DMA source

address register_2 SAR_2 R/W H'00000000 H'FFFFEB40 16, 32 DMA destination address register_2 DAR_2 R/W H'00000000 H'FFFFEB44 16, 32 DMA transfer count register_2 DMATCR_2 R/W H'00000000 H'FFFFEB48 16, 32 DMA channel control register_2 CHCR_2 R/W H'00000000 H'FFFFEB4C 8, 16, 32

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3 DMA source

address register_3 SAR_3 R/W H'00000000 H'FFFFEB50 16, 32 DMA destination address register_3 DAR_3 R/W H'00000000 H'FFFFEB54 16, 32 DMA transfer count register_3 DMATCR_3 R/W H'00000000 H'FFFFEB58 16, 32 DMA channel control register_3 CHCR_3 R/W H'00000000 H'FFFFEB5C 8, 16, 32 Common DMA operation register DMAOR R/W H'0000 H'FFFFEB60 8, 16 Bus function extending register BSCEHR R/W H'0000 H'FFFFE89A 8, 16

10.3.1 DMA Source Address Registers_0 to _3 (SAR_0 to SAR_3)

SAR are 32-bit readable/writable registers that specify the source address of a DMA transfer. During a DMA transfer, these registers indicate the next source address. When the data is transferred from an external device with the DACK in single address mode, the SAR is ignored. To transfer data in 16 bits or in 32 bits, specify the address with 16-bit or 32-bit address boundary. When transferring data in 16-byte units, a 16-byte boundary must be set for the source address value. The initial value is undefined. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Section 10 Direct Memory Access Controller (DMAC) Page 388 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

10.3.2 DMA Destination Address Registers_0 to _3 (DAR_0 to DAR_3)

DAR are 32-bit readable/writable registers that specify the destination address of a DMA transfer. During a DMA transfer, these registers indicate the next destination address. When the data is transferred from an external device with the DACK in single address mode, the DAR is ignored. To transfer data in 16 bits or in 32 bits, specify the address with 16-bit or 32-bit address boundary. When transferring data in 16-byte units, a 16-byte boundary must be set for the destination address value. The initial value is undefined. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

10.3.3 DMA Transfer Count Registers_0 to _3 (DMATCR_0 to DMATCR_3)

DMATCR are 32-bit readable/writable registers that specify the DMA transfer count. The number of transfers is 1 when the setting is H'00000001, 16,777,215 when H'00FFFFFF is set, and 16,777,216 (the maximum) when H'00000000 is set. During a DMA transfer, these registers indicate the remaining transfer count. The upper eight bits of DMATCR are always read as 0, and the write value should always be 0. To transfer data in 16 bytes, one 16-byte transfer (128 bits) counts one. The initial value is undefined. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRRRRRR R / W R / W R / W R / W R / W R / W R / W R / W 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

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10.3.4 DMA Channel Control Registers_0 to _3 (CHCR_0 to CHCR_3)

CHCR are 32-bit readable/writable registers that control the DMA transfer mode. Bit: Initial value: R/W: Bit: Initial value: R/W: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRRRRRR R / W R / W RRRR R / W R / W 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/(W) * R/W Note: Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.* DM[1:0] SM[1:0] RS[3:0] DL DS TB TS[1:0] IE TE DE Bit Bit Name Initial Value R/W Descriptions 31 to 24 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

23 DO 0 R/W DMA Overrun

Selects whether DREQ is detected by overrun 0 or by overrun 1. 0: Detects DREQ by overrun 0 1: Detects DREQ by overrun 1

22 TL 0 R/W Transfer End Level

This bit specifies the TEND signal output is high active or low active. 0: Low-active output of TEND 1: High-active output of TEND 21, 20 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. 19 — 0 R Reserved Undefined value is set when the DMAC is activated. 18 — 0 R Reserved This bit is always read as 0. The write value should always be 0.

Section 10 Direct Memory Access Controller (DMAC) Page 390 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Descriptions

17 AM 0 R/W Acknowledge Mode

Selects whether DACK is output in data read cycle or in data write cycle in dual address mode. In single address mode, DACK is always output regardless of the specification by this bit. 0: DACK output in read cycle (dual address mode) 1: DACK output in write cycle (dual address mode)

16 AL 0 R/W Acknowledge Level

Specifies whether the DACK signal output is high active or low active. 0: Low-active output of DACK 1: High-active output of DACK 15, 14 DM[1:0] 00 R/W Destination Address Mode 1, 0 Specify whether the DMA destination address is incremented, decremented, or left fixed. (In single address mode, the DM1 and DM0 bits are ignored when data is transferred to an external device with DACK.) 00: Fixed destination address (setting prohibited in 16- byte transfer) 01: Destination address is incremented (+1 in byte-unit transfer, +2 in word-unit transfer, +4 in longword-unit transfer, +16 in 16-byte transfer) 10: Destination address is decremented (–1 in byte-unit transfer, –2 in word-unit transfer, –4 in longword-unit transfer; setting prohibited in 16-byte transfer) 11: Setting prohibited 13, 12 SM[1:0] 00 R/W Source Address Mode 1, 0 Specify whether the DMA source address is incremented, decremented, or left fixed. (In single address mode, SM1 and SM0 bits are ignored when data is transferred from an external device with DACK.) 00: Fixed source address (setting prohibited in 16-byte transfer) 01: Source address is incremented (+1 in byte-unit transfer, +2 in word-unit transfer, +4 in longword-unit transfer, +16 in 16-byte transfer) 10: Source address is decremented (–1 in byte-unit transfer, –2 in word-unit transfer, –4 in longword-unit transfer; setting prohibited in 16-byte transfer) 11: Setting prohibited

Section 10 Direct Memory Access Controller (DMAC) R01UH0198EJ0500 Rev. 5.00 Page 391 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Descriptions Resource Select 3 to 0 Specify which transfer requests will be sent to the DMAC. The changing of transfer request source should be done in the state that the DMA enable bit (DE) is set to 0. 0 0 0 0 External request, dual address mode 0 0 0 1 Setting prohibited 0 0 1 0 External request, single address mode External address space → External device with DACK 0 0 1 1 External request, single address mode External device with DACK → External address space 0 1 0 0 Auto request 0 1 0 1 Setting prohibited 0 1 1 0 MTU2 (TGIA_0) 0 1 1 1 MTU2 (TGIA_1) 1 0 0 0 MTU2 (TGIA_2) 1 0 0 1 MTU2 (TGIA_3) 1 0 1 0 MTU2 (TGIA_4) 1 0 1 1 A/D_1 (ADI_1) 1 1 0 0 SCI_0 (TXI_0) 1 1 0 1 SCI_0 (RXI_0) 1 1 1 0 SCI_1 (TXI_1) 1 1 1 1 SCI_1 (RXI_1) 11 to 8 RS[3:0] 0000 R/W DL DS R/W R/W DREQ Level and DREQ Edge Select Specify the detecting method of the DREQ pin input and the detecting level. If the transfer request source is specified as an on-chip peripheral module or if an auto-request is specified, these bits are invalid. 00: DREQ detected in low level 01: DREQ detected at falling edge 10: DREQ detected in high level 11: DREQ detected at rising edge

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5 TB 0 R/W Transfer Bus Mode

Specifies the bus mode when DMA transfers data. 0: Cycle steal mode 1: Burst mode Note: When performing DMA transfer in burst mode with MTU2 activation request, set the corresponding bit among DMMTU4 to DMMTU0 in bus function extending register (BSCEHR) (see section 9.4.8, Bus Function Extending Register (BSCEHR)). 4, 3 TS[1:0] 00 R/W Transfer Size 1, 0 Specify the size of data to be transferred. Select the size of data to be transferred when the source or destination is an on-chip peripheral module register of which transfer size is specified. 00: Byte size 01: Word size (2 bytes) 10: Longword size (4 bytes) 11: 16-byte unit (four longword transfers)

2 IE 0 R/W Interrupt Enable

Specifies whether or not an interrupt request is generated to the CPU at the end of the DMA transfer. Setting this bit to 1 generates an interrupt request (DEI) to the CPU when the TE bit is set to 1. 0: Interrupt request is disabled. 1: Interrupt request is enabled.

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1 TE 0 R/(W) * Transfer End Flag

Shows that DMA transfer ends. The TE bit is set to 1 when data transfer ends when DMATCR becomes to 0. The TE bit is not set to 1 in the following cases.

• DMA transfer ends due to an NMI interrupt or DMA address error before DMATCR is cleared to 0.
• DMA transfer is ended by clearing the DE bit and DME bit in the DMA operation register (DMAOR). To clear the TE bit, the TE bit should be written to 0 after reading 1. Even if the DE bit is set to 1 while this bit is set to 1, transfer is not enabled. 0: During the DMA transfer or DMA transfer has been interrupted [Clearing condition] Writing 0 after TE = 1 read 1: DMA transfer ends by the specified count (DMATCR =

0 DE 0 R/W DMA Enable

Enables or disables the DMA transfer. In auto request mode, DMA transfer starts by setting the DE bit and DME bit in DMAOR to 1. In this time, all of the bits TE, NMIF, and AE in DMAOR must be 0. In an external request or peripheral module request, DMA transfer starts if DMA transfer request is generated by the devices or peripheral modules after setting the bits DE and DME to 1. In this case, however, all of the bits TE, NMIF, and AE must be 0, which is the same as in the case of auto request mode. Clearing the DE bit to 0 can terminate the DMA transfer. 0: DMA transfer disabled 1: DMA transfer enabled Note: * Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.

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10.3.5 DMA Operation Register (DMAOR)

DMAOR is a 16-bit readable/writable register that specifies the priority level of channels at the DMA transfer. This register shows the DMA transfer status. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R R R/W R/W R R R/W R/W R R R R R R/(W) * R/(W)* R/W Note: Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.* - - CMS[1:0] - - PR[1:0] - - - - - AE NMIF DME Bit Bit Name Initial Value R/W Description 15, 14 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. 13, 12 CMS[1:0] 00 R/W Cycle Steal Mode Select 1, 0 Select either normal mode or intermittent mode in cycle steal mode. It is necessary that all channel's bus modes are set to cycle steal mode to make valid intermittent mode. 00: Normal mode 01: Setting prohibited 10: Intermittent mode 16 Executes one DMA transfer in each of 16 clocks of an external bus clock. 11: Intermittent mode 64 Executes one DMA transfer in each of 64 clocks of an external bus clock. 11, 10 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 10 Direct Memory Access Controller (DMAC) R01UH0198EJ0500 Rev. 5.00 Page 395 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description 9, 8 PR[1:0] 00 R/W Priority Mode 1, 0 Select the priority level between channels when there are transfer requests for multiple channels simultaneously. 00: CH0 > CH1 > CH2 > CH3 01: CH0 > CH2 > CH3 > CH1 10: Setting prohibited 11: Round-robin mode 7 to 3 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

2 AE 0 R/(W) * Address Error Flag

Indicates that an address error occurred during DMA transfer. If this bit is set, DMA transfer is disabled even if the DE bit in CHCR and the DME bit in DMAOR are set to 1. This bit can only be cleared by writing 0 after reading 0: No DMAC address error [Clearing condition]

• Writing AE = 0 after AE = 1 read 1: DMAC address error occurs

Section 10 Direct Memory Access Controller (DMAC) Page 396 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description

1 NMIF 0 R/(W) * NMI Flag

Indicates that an NMI interrupt occurred. If this bit is set, DMA transfer is disabled even if the DE bit in CHCR and the DME bit in DMAOR are set to 1. This bit can only be cleared by writing 0 after reading 1. When the NMI is input, the DMA transfer in progress can be done in one transfer unit. When the DMAC is not in operational, the NMIF bit is set to 1 even if the NMI interrupt was input. 0: No NMI interrupt [Clearing condition]

• Writing NMIF = 0 after NMIF = 1 read 1: NMI interrupt occurs Note: If the NMIF bit is read at the same point in time that it is set to 1, in some cases the read value will be 0 but the internal state will be as if it was read as 1. Therefore, subsequently writing 0 to NMIF will clear it to 0 in the same way as writing 0 to the flag after reading it as 1. To prevent the NMIF bit from being cleared to 0 inadvertently, always write 1 to the NMIF bit except in cases when explicitly clearing it. To explicitly clear the NMIF bit, write 0 to it after reading it as 1. Note that if the NMIF bit is not used, there is no problem with always writing 0 to it (and writing 0 to it after reading it as 1 explicitly to clear it).

0 DME 0 R/W DMA Master Enable

Enables or disables DMA transfers on all channels. If the DME bit and the DE bit in CHCR are set to 1, transfer is enabled. In this time, all of the bits TE in CHCR, NMIF, and AE in DMAOR must be 0. If this bit is cleared during transfer, transfers in all channels are terminated. 0: Disables DMA transfers on all channels 1: Enables DMA transfers on all channels Note: * Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.

10.3.6 Bus Function Extending Register (BSCEHR)

BSCEHR is a 16-bit readable/writable register that specifies the timing of bus release. It also sets the function to perform transfer by the DMAC preferentially. For details, see section 9.4.8, Bus Function Extending Register (BSCEHR).

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10.4 Operation

When there is a DMA transfer request, the DMAC starts the transfer according to the predetermined channel priority; when the transfer end conditions are satisfied, it ends the transfer. Transfers can be requested in three modes: auto request, external request, and on-chip peripheral module request. In bus mode, burst mode or cycle steal mode can be selected.

10.4.1 DMA Transfer Flow

After the DMA source address registers (SAR), DMA destination address registers (DAR), DMA transfer count registers (DMATCR), DMA channel control registers (CHCR), and DMA operation register (DMAOR) are set, the DMAC transfers data according to the following procedure: 1. Checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0) 2. When a transfer request occurs while transfer is enabled, the DMAC transfers one transfer unit of data (depending on the TS0 and TS1 settings). In auto request mode, the transfer begins automatically when the DE bit and DME bit are set to 1. The DMATCR value will be decremented for each transfer. The actual transfer flows vary by address mode and bus mode. 3. When the specified number of transfer ha ve been completed (when DMATCR reaches 0), the transfer ends normally. If the IE bit in CHCR is set to 1 at this time, a DEI interrupt is sent to the CPU. 4. When an address error or an NMI interrupt is generated, the transfer is aborted. Transfers are also aborted when the DE bit in CHCR or the DME bit in DMAOR is changed to 0. Notes: The state of data transfer and register s when transfer by the DMAC is interrupted 1. When DMAC address error has occurred: Data transfer is not performed. However, SAR, DAR, and DMATCR are updated. 2. When an NMI interrupt has occurred: Data transfer is stopped after transferring one transfer unit of data. SAR, DAR, and DMATCR are properly updated. 3. When the DE bit in the CHCR and the DME bit in DMAOR are cleared: Data transfer is stopped after transferring one transfer unit of data. SAR, DAR, and DMATCR are properly updated. Figure 10.2 shows a flowchart of this procedure.

Section 10 Direct Memory Access Controller (DMAC) Page 398 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Normal end NMIF = 1 or AE = 1 or DE = 0 or DME = 0? Bus mode, transfer request mode, DREQ detection selection system Initial settings (SAR, DAR, DMATCR, CHCR, DMAOR) Transfer (1 transfer unit); DMATCR – 1 → DMATCR, SAR and DAR updated DEI interrupt request (when IE = 1) TE = 1 No Yes No Yes No Yes Yes No Yes No Start Transfer aborted DMATCR = 0? Transfer request occurs?*1 DE, DME = 1 and NMIF, AE, TE = 0? NMIF = 1 or AE = 1 or DE = 0 or DME = 0? Transfer end Notes: 1. In auto-request mode, transfer begins when the NMIF, AE, and TE bits are all 0 and the DE and DME bits are set to 1. 2. DREQ = level detection in burst mode (external request) or cycle-steal mode. 3. DREQ = edge detection in burst mode (external request), or auto-request mode in burst mode. Figure 10.2 DMA Transfer Flowchart

Section 10 Direct Memory Access Controller (DMAC) R01UH0198EJ0500 Rev. 5.00 Page 399 of 1560 Mar 18, 2011 SH7080 Group

10.4.2 DMA Transfer Requests

DMA transfer requests are basically generated in either the data transfer source or destination, but they can also be generated by external devices or on-chip peripheral modules that are neither the source nor the destination. Transfers can be requested in three modes: auto request, external request, and on-chip peripheral module request. The request mode is selected in the RS3 to RS0 bits in CHCR0 to CHCR3. (1) Auto-Request Mode When there is no transfer request signal from an external source, as in a memory-to-memory transfer or a transfer between memory and an on-chip peripheral module unable to request a transfer, auto-request mode allows the DMAC to automatically generate a transfer request signal internally. When the DE bits in CHCR0 to CHCR3 and the DME bit in DMAOR are set to 1, the transfer begins so long as the AE and NMIF bits in DMAOR and the TE bits in CHCR0 to CHCR3 are all 0. (2) External Request Mode In this mode, a transfer is performed at the request signals (DREQ0 to DREQ3) of an external device. Choose one of the modes shown in table 10.3 according to the application system. When this mode is selected, if the DMA transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0), a transfer is performed upon a request at the DREQ input. Table 10.3 Selecting External Request Modes with RS Bits RS3 RS2 RS1 RS0 Address Mode Source Destination 0 0 0 0 Dual address mode Any Any 1 0 Single address mode External memory, memory-mapped external device External device with DACK

1 External device with

External memory, memory-mapped external device Choose to detect DREQ by either the edge or level of the signal input with the DL bit and DS bit in CHCR_0 to CHCR_3 as shown in table 10.4. The source of the transfer request does not have to be the data transfer source or destination.

Section 10 Direct Memory Access Controller (DMAC) Page 400 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 10.4 Selecting External Reque st Detection with DL, DS Bits CHCR_0 to CHCR_3 DL DS Detection of External Request

0 Low level detection 0

1 Falling edge detection

1 Rising edge detection

Note: Prior to setting CHCR_0 to CHCR_3, select the DREQ pin function by the pin function controller (PFC). When DREQ is accepted, the DREQ pin becomes request accept disabled state. After issuing acknowledge signal DACK for the accepted DREQ, the DREQ pin again becomes request accept enabled state. When DREQ is used by level detection, there are following two cases by the timing to detect the next DREQ after outputting DACK.

• Overrun 0: Transfer is aborted after the same number of transfer has been performed as requests.
• Overrun 1: Transfer is aborted after transfers have been performed for (the number of requests plus 1) times. The DO bits in CHCR_0 to CHCR_3 select this overrun 0 or overrun 1. Table 10.5 Selecting External Re quest Detection with DO Bit CHCR_0 to CHCR_3 DO External Request

0 Overrun 0

1 Overrun 1

Section 10 Direct Memory Access Controller (DMAC) R01UH0198EJ0500 Rev. 5.00 Page 401 of 1560 Mar 18, 2011 SH7080 Group (3) On-Chip Peripheral Module Request Mode In this mode, a transfer is performed at the transfer request signal of an on-chip peripheral module. The DMA receives ten transfer request signals in total: five compare match and input capture interrupts from multi-function timer pulse unit 2 (MTU2), receive data full interrupts (RXI) and transmit data empty interrupts (TXI) from two serial communication interface (SCI) channels, and the A/D conversion end interrupt (ADI) from the A/D converter. When this mode is selected, if the DMA transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0), a transfer is performed upon the input of a transfer request signal. The transfer request source does not need to be the data transfer source or destination. However, when the transmit data empty transfer request (TXI) from the SCI is specified as the transfer request source, the transfer destination must be the transmit data register (TDR) in the respective SCI channel. Similarly, when the receive data full transfer request (RXI) in the SCI is specified as the request source, the transfer source must be the receive data register (RDR) in the respective SCI channel. When the A/D conversion end transfer request (ADI) is specified as the transfer request source, the transfer source must be the respective register in the A/D converter. Table 10.6 Selecting On-Chip Peripheral Mo dule Request Modes with RS3 to RS0 Bits RS3 RS2 RS1 RS0 Transfer Request Source Transfer Request Signal Source Destination Bus Mode

0 MTU2 TGIA_0 Any * Any * Burst or cycle steal

1 MTU2 TGIA_1 Any * Any * Burst or cycle steal

1 0 MTU2 TGIA_2 Any * Any * Burst or cycle steal

1 MTU2 TGIA_3 Any * Any * Burst or cycle steal

0 MTU2 TGIA_4 Any * Any * Burst or cycle steal

1 A/D_1 ADI1 ADDR4 to

Any* Cycle steal 1 0 SCI_0 transmitter TXI_0 Any * SCTDR_0 Cycle steal

1 SCI_0 receiver RXI_0 SCRDR_0 Any * Cycle steal

1 0 SCI_1 transmitter TXI_1 Any * SCTDR_1 Cycle steal

1 SCI_1 receiver RXI_1 SCRDR_1 Any * Cycle steal

Notes: MTU2: Multi-function timer pulse unit 2 SCI_0 and SCI_1: Serial communication interface channels 0 and 1 ADDR4 to ADDR7: A/D data register in A/D converter channel 1 SCTDR_0 and SCTDR_1: Transmit data registers in SCI_0 and SCI_1 SCRDR_0 and SCRDR_1: Receive data registers in SCI_0 and SCI_1 * An external memory, a memory-mapped external device, an on-chip memory, or an on- chip peripheral module (except DMAC, DTC, BSC, and UBC)

Section 10 Direct Memory Access Controller (DMAC) Page 402 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group To output a transfer request signal from an on-chip peripheral module, set the interrupt enable bit corresponding to the transfer request signal in the on-chip peripheral module. When an interrupt request signal in an on-chip peripheral module is used to request DMA transfer, no interrupt is requested to the CPU. For details, refer to section 6.8, Data Transfer with Interrupt Request Signals. The transfer request signal shown in table 10.7 is automatically cancelled when the corresponding DMA transfer is performed. This cancellation occurs when one transfer unit is completed in cycle steal mode or at the end of burst transfer in burst mode.

10.4.3 Channel Priority

When the DMAC receives simultaneous transfer requests on two or more channels, it transfers data according to a predetermined priority. Two modes (fixed mode and round-robin mode) are selected by the bits PR1 and PR0 in DMAOR. (1) Fixed Mode In this mode, the priority levels among the channels remain fixed. There are two kinds of fixed modes as follows:

• CH0 > CH1 > CH2 > CH3
• CH0 > CH2 > CH3 > CH1 These are selected by the PR1 and the PR0 bits in DMAOR. (2) Round-Robin Mode In round-robin mode each time data of one transfer unit (word, byte, longword, or 16-byte unit) is transferred on one channel, the priority is rotated. The channel on which the transfer was just finished rotates to the bottom of the priority. The round-robin mode operation is shown in figure 10.3. The priority of round-robin mode is CH0 > CH1 > CH2 > CH3 immediately after reset. When round-robin mode is specified, do not mix the cycle steal mode and the burst mode in multiple channels' bus modes.

Section 10 Direct Memory Access Controller (DMAC) R01UH0198EJ0500 Rev. 5.00 Page 403 of 1560 Mar 18, 2011 SH7080 Group CH1 > CH2 > CH3 > CH0 CH0 > CH1 > CH2 > CH3 CH2 > CH3 > CH0 > CH1 CH0 > CH1 > CH2 > CH3 CH2 > CH3 > CH0 > CH1 CH0 > CH1 > CH2 > CH3 CH0 > CH1 > CH2 > CH3 CH3 > CH0 > CH1 > CH2 CH0 > CH1 > CH2 > CH3 (1) When channel 0 transfers Initial priority order Initial priority order Initial priority order Initial priority order Priority order after transfer Priority order does not change. Channel 2 becomes bottom priority. The priority of channels 0 and 1, which were higher than channel 2, are also shifted. If immediately after there is a request to transfer channel 1 only, channel 1 becomes bottom priority and the priority of channels 3 and 0, which were higher than channel 1, are also shifted. Channel 1 becomes bottom priority. The priority of channel 0, which was higher than channel 1, is also shifted. Channel 0 becomes bottom priority Priority order after transfer Priority order after transfer Priority order after transfer Post-transfer priority order when there is an immediate transfer request to channel 1 only (2) When channel 1 transfers (3) When channel 2 transfers (4) When channel 3 transfers Figure 10.3 Round-Robin Mode

Section 10 Direct Memory Access Controller (DMAC) R01UH0198EJ0500 Rev. 5.00 Page 405 of 1560 Mar 18, 2011 SH7080 Group (3) Activation priority when multiple DMAC activation requests are generated When multiple DMAC activation requests are generated, transfer is performed in the order of activation priority. However, if multiple DMAC activation requests are generated while the DMAC is not the bus master, transfer is started for the first activation request. In addition, if activation requests are generated while the CPU is accessing an external space, transfer is started for the first activation request and then the second request. Figure 10.5 shows the example of activation priority operation of the DMAC. Transfer is started for the request that is generated first Internal bus Priority determination Priority determination Priority determination Access to external space by the CPU DMAC is inactive DMAC is active DMAC (CH3) DMAC (CH2) DMAC (CH0) DMAC CH0 activation request (Priority: 1) DMAC CH1 activation request (Priority: 2) DMAC CH2 activation request (Priority: 3) DMAC CH3 activation request (Priority: 4) DMAC CH0 activation request (Priority: 1) DMAC CH1 activation request (Priority: 2) DMAC CH2 activation request (Priority: 3) DMAC CH3 activation request (Priority: 4) When multiple DMAC activation requests are generated while the CPU is accessing an external space DMAC (CH1) Transfer is performed according to the priority Internal bus Other than access to external space by the CPU DMAC is inactive DMAC is active DMAC (CH3) DMAC (CH0) DMAC (CH1) When multiple DMAC activation requests are generated while the CPU is not accessing an external space DMAC (CH2) Transfer is performed according to the priority Figure 10.5 Example of Activation Priority Operation of DMAC (Priority Fixed Mode (CH0 > CH1 > CH2 > CH3))

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10.4.4 DMA Transfer Types

DMA transfer has two types; single address mode transfer and dual address mode transfer. They depend on the number of bus cycles of access to source and destination. A data transfer timing depends on the bus mode, which has cycle steal mode and burst mode. The DMAC supports the transfers shown in table 10.7. Table 10.7 Supported DMA Transfers Destination Source External Device with DACK External Memory Memory- Mapped External Device On-Chip Peripheral Module On-Chip Memory External device with DACK Not available Dual, single Dual, single Not available Not available External memory Dual, single Dual Dual Dual Dual Memory-mapped external device Dual, single Dual Dual Dual Dual On-chip peripheral module Not available Dual Dual Dual Dual On-chip memory Not available Dual Dual Dual Dual Notes: 1. Dual: Dual address mode 2. Single: Single address mode 3. For on-chip peripheral modules, 16-byte transfer is available only by registers which can be accessed in longword units.

Section 10 Direct Memory Access Controller (DMAC) R01UH0198EJ0500 Rev. 5.00 Page 407 of 1560 Mar 18, 2011 SH7080 Group Address Modes:

• Dual Address Mode In dual address mode, both the transfer source and destination are accessed by an address. The source and destination can be located externally or internally. DMA transfer requires two bus cycles because data is read from the transfer source in a data read cycle and written to the transfer destination in a data write cycle. At this time, transfer data is temporarily stored in the DMAC. In the transfer between external memories as shown in figure 10.6, data is read to the DMAC from one external memory in a data read cycle, and then that data is written to the other external memory in a write cycle. Data buffer Address bus Data bus Address bus Data bus Memory Transfer source module Transfer destination module Memory Transfer source module Transfer destination module SAR DAR Data buffer SAR DAR The SAR value is an address, data is read from the transfer source module, and the data is temporarily stored in the DMAC. First bus cycle Second bus cycle The DAR value is an address and the value stored in the data buffer in the DMAC is written to the transfer destination module. DMAC DMAC Figure 10.6 Data Flow of Dual Address Mode Auto request, external request, and on-chip peripheral module request are available for the transfer request. DACK can be output in read cycle or write cycle in dual address mode. The AM bit in the channel control register (CHCR) can specify whether the DACK is output in read cycle or write cycle.

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• Single Address Mode In single address mode, either the transfer source or transfer destination peripheral device is accessed (selected) by means of the DACK signal, and the other device is accessed by an address. In this mode, the DMAC performs one DMA transfer in one bus cycle, accessing one of the external devices by outputting the DACK transfer request acknowledge signal to it, and at the same time outputting an address to the other device involved in the transfer. For example, in the case of transfer between external memory and an external device with DACK shown in figure 10.8, when the external device outputs data to the data bus, that data is written to the external memory in the same bus cycle. DMAC This LSI DACK DREQ External address bus External data bus External memory External device with DACK Data flow Figure 10.8 Data Flow in Single Address Mode Two kinds of transfer are possible in single address mode: transfer between an external device with DACK and a memory-mapped external device, and transfer between an external device with DACK and external memory. In both cases, only the external request signal (DREQ) is used for transfer requests.

Section 10 Direct Memory Access Controller (DMAC) R01UH0198EJ0500 Rev. 5.00 Page 413 of 1560 Mar 18, 2011 SH7080 Group Relationship between Request Modes and Bus Modes by DMA Transfer Category: Table 10.8 shows the relationship between request modes and bus modes by DMA transfer category. Table 10.8 Relationship between Request Modes and Bus Modes by DMA Transfer Category Address Mode Transfer Category Request Mode Bus Mode Transfer Size (Bits) Usable Channels External device with DACK and external memory External B/C 8/16/32/128 0 to 3 External device with DACK and memory- mapped external device External B/C 8/16/32/128 0 to 3 External memory and external memory All * B/C 8/16/32/128 0 to 3 External memory and memory-mapped external device All* B/C 8/16/32/128 0 to 3 Memory-mapped external device and memory- mapped external device All* B/C 8/16/32/128 0 to 3 External memory and on-chip peripheral module All * B/C * 8/16/32/128 * 0 to 3 Memory-mapped external device and on-chip peripheral module All* B/C * 8/16/32/128 * 0 to 3 On-chip peripheral module and on-chip peripheral module All* B/C * 8/16/32/128 * 0 to 3 On-chip memory and On-chip memory All * B/C 8/16/32/128 0 to 3 On-chip memory and memory-mapped external device All* B/C 8/16/32/128 0 to 3 On-chip memory and on-chip peripheral module All * B/C * 8/16/32/128 * 0 to 3 Dual On-chip memory and external memory All * B/C 8/16/32/128 0 to 3 Single External device with DACK and external memory External B/C 8/16/32 0 to 3 External device with DACK and memory- mapped external device External B/C 8/16/32 0 to 3 B: Burst mode, C: Cycle steal mode Notes: 1. External requests, auto requests, and on-chip peripheral module requests are all available. For on-chip peripheral module requests, however, the SCI and A/D converter cannot be specified as the transfer request source. 2. External requests, auto requests, and on-chip peripheral module requests are all available. However, when the SCI or A/D converter is the transfer request source, the request source register must be designated as the transfer source or the transfer destination. 3. Only cycle steal when the SCI or A/D converter is the transfer request source. 4. Access size permitted for the on-chip per ipheral module register functioning as the transfer source or transfer destination.

Section 10 Direct Memory Access Controller (DMAC) Page 414 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bus Mode and Channel Priority: When the priority is set in fixed mode (CH0 > CH1) and channel 1 is transferring in burst mode, if there is a transfer request to channel 0 with a higher priority, the transfer of channel 0 will begin immediately. At this time, if channel 0 is also operating in burst mode, the channel 1 transfer will continue after the channel 0 transfer has completely finished. When channel 0 is in cycle steal mode, channel 0 with a higher priority performs the transfer of one transfer unit and the channel 1 transfer is continuously performed without releasing the bus mastership. The bus mastership will then switch between the two in the order channel 0, channel 1, channel 0, and channel 1. Therefore, the bus state is such that the CPU cycle after the completion of cycle steal mode transfer has been replaced with the channel 1 burst mode transfer. (Hereinafter referred to as burst mode priority execution.) This example is shown in figure 10.13. When multiple channels are operating in burst modes, the channel with the highest priority is executed first. When DMA transfer is executed in the multiple channels, the bus mastership will not be given to the bus master until all competing burst transfers are complete. CPU DMA CH1 DMA CH1 DMA CH0 DMA CH1 DMA CH0 DMA CH1 DMA CH1 CPU CH0 CH1 CH0 DMAC CH0 and CH1 Cycle-steal mode DMAC CH1 Burst mode CPUCPU Priority: CH0 > CH1 CH0: Cycle-steal mode CH1: Burst mode DMAC CH1 Burst mode Figure 10.13 Bus State when Multiple Channels Are Operating In round-robin mode, the priority changes according to the specification shown in figure 10.3. However, the channel in cycle steal mode cannot be mixed with the channel in burst mode.

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10.4.5 Number of Bus Cycle States and DREQ Pin Sampling Timing

Number of Bus Cycle States: When the DMAC is the bus master, the number of bus cycle states is controlled by the bus state controller (BSC) in the same way as when the CPU is the bus master. For details, see section 9, Bus State Controller (BSC). DREQ Pin Sampling Timing: Figures 10.14 to 10.17 show the sample timing of the DREQ input in each bus mode, respectively. Determination of DMAC activation by DREQ takes 3 × Bcyc (Bcyc is the external clock (Bφ = CK) cycle). Timing of the DACK output for the first DREQ acceptance differs depending on the internal bus state, the AM bit setting in CHCR, and the configuration of the BSC regarding the transfer source/destination areas, but the fastest case is 6 × Bcyc. CK Bus cycle DREQ (Rising edge) DACK (Active-high) CPU Non-sensitive period 1st acceptance 2nd acceptance Acceptance started CPUCPU DMAC Figure 10.14 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection

Section 10 Direct Memory Access Controller (DMAC) Page 418 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group When 16-byte transfer to an external device is performed, when 8-bit or 16-bit external device is accessed in longword units, or when an 8-bit external device is accessed in word units, each DMA transfer unit is divided into multiple bus cycles. If negation of CS between bus cycles is specified in these cases, the DACK and TEND outputs are also divided for data alignment. This example is illustrated in figure 10.19. With divided DACK, sampling of DREQ is not detected correctly and a maximum of one extra overrun may occur. To avoid this, use the settings with which DACK is not divided, or in the case when DACK is divided, specify the transfer size that is smaller than the bus width of the external device. CK CS WRxx DACKn (Active-low) WAIT RD Address Data TENDn (Active-low) T1 T2 Taw T1 T2 Note: The DACK and TEND are asserted for the last transfer unit of the DMA transfer. When the transfer unit is divided into several bus cycles and the CS is negated between bus cycles, the DACK and TEND are also divided. Figure 10.19 BSC Ordinary Memory Access (No Wait, Idle Cycle 1, Longword Access to 16-Bit Device)

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10.4.6 Operation Timing

Figures 10.20 and 10.21 illustrate the timing of DMAC operations. Note: The DMAC request indicates the state of an internal bus request after determination of the source for DMAC activation. For details on the DREQ and DACK timing in each operating mode, see section 10.4.5, Number of Bus Cycle States and DREQ Pin Sampling Timing. Clock (Bφ) Data transfer Internal address DMAC activation request by DREQ pin DMAC request CSn R W Figure 10.20 Example of Timing of DMAC Operation—Activation by DREQ (in the Case of Cycle Stealing Transfer, Dual Address Mode, Low-Level Detection, Iφ:Bφ:Pφ = 1:1/2:1/2, Data Transfer from External Memory to External Memory, and Idle/Wait = 0)

Section 10 Direct Memory Access Controller (DMAC) Page 420 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Note: The DMAC request indicates the state of an internal bus request after determination of the source for DMAC activation. Clock (Bφ) Data transfer Internal address DMAC activation request DMAC request R W Figure 10.21 Example of DMAC Operation Timing— Activation by an On-Chip Peripheral Module (in the Case of Cycle Stealing Transfer, Dual Address Mode, Low-Level Detection, Iφ:Bφ:Pφ = 1:1/2:1/2, and Data Transfer from On-Chip Peripheral Module to On-Chip RAM)

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10.5 Usage Notes

10.5.1 Notes on Output from DACK Pin

When burst mode and cycle steal mode are specified in multiple channels at the same time, unnecessary DACK may be asserted at the end of burst transfer if the following conditions are all satisfied. 1. When DMA transfer is performed with burst mode and cycle steal mode being specified in multiple channels at the same time. 2. When dual address mode is specified for the channel used in burst mode and DACK output is enabled in write cycles. 3. When the DMAC cannot acquire the bus mastership after the end of burst transfer while the DMAC has accepted a cycle-steal transfer request. This can be avoided by one of the following actions. Action 1: After confirming the end of burst transfer (TE bit = 1), perform remaining DMA transfer in cycle steal mode. Action 2: Do not enable DACK in write cycles for the channel used in burst mode. Action 3: When performing DMA transfer in multiple channels at the same time, select either burst mode or cycle steal mode for all channels.

10.5.2 DMA Transfer by Peripheral Modules

During DMA transfer by peripheral modules, do not set the clock ratio of bus clock (Bφ):peripheral clock (Pφ), bus clock (Bφ):MTU2 clock (MPφ), and bus clock (Bφ):MTU2S clock (MIφ) to 1:1/3 or 1:1/4

10.5.3 Module Standby Mode Setting

DMAC operation can be enabled or disabled by setting the standby control register. The DMAC is disabled by default. After module standby mode is canceled, access to the DMAC registers is enabled. Note that software standby mode or module standby mode must not be entered while the DMAC is operating. Before entering software standby mode or module standby mode, return the channel control registers (CHCR_0 to CHCR_3) and DMA operation register (DMAOR) to their initial values. For details, refer to section 26, Power-Down Modes.

Section 10 Direct Memory Access Controller (DMAC) Page 422 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

10.5.4 Access to DMAC and DTC Registers through DMAC

Do not access the DMAC or DTC registers through DMAC operation. Do not access the DMAC registers through DTC operation.

10.5.5 Note on SCI as DMAC Activation Source

When the TXI interrupt in SCI is specified as a DMAC activation source, the TEND flag in the SCI must not be used as the transfer end flag.

10.5.6 CHCR Setting

Before modifying the CHCR setting, be sure to clear the DE bit in the respective channel.

10.5.7 Note on Multiple Channel Activation

Do not use the same on-chip request in multiple channels.

10.5.8 Note on Transfer Request Input

Transfer requests must be input after DMAC settings are completed.

10.5.9 Conflict between NMI Interrupt and DMAC Activation

When a conflict occurs between the generation of the NMI interrupt and the DMAC activation, the NMI interrupt has priority. Thus the NMI bit is set to 1 and the DMAC is not activated. It takes 1 × Bcyc + 3× Pcyc for determining DMAC stop by NMI, 3 × Bcyc for determining DMAC activation by DREQ, and 1 × Pcyc for determining DMAC activation by peripheral modules (Bcyc is the external bus clock cycle, and Pcyc is the peripheral clock cycle).

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10.5.10 Notes on Using Peripheral Module Request Modes

When using a DMA transfer for which A/D_1 (ADI_1), SCI_0 (TXI_0), SCI_0 (RXI_0), SCI_1 (TXI_1), or SCI_1 (RXI_1) is selected as the transfer request source, any interrupt requests from the peripheral module selected as the transfer request source are accepted and held as DMA transfer requests. As a result, a DMA transfer may occur in the absence of a DMA transfer request when one of the following conditions is met: 1. When A/D_1 (ADI_1), SCI_0 (TXI_0), SCI_0 (RXI_0), SCI_1 (TXI_1), or SCI_1 (RXI_1) is selected as the DMA transfer request source after an interrupt request (ADI_1, TXI_0, RXI_0, TXI_1, or RXI_1) was generated and the interrupt source flag (ADF in ADCSR, TDRE or RDRF in SCSSR) was cleared by the CPU or DTC. 2. When the interrupt source flag (ADF in ADCSR , TDRE or RDRF in SCSSR) is cleared by the CPU after A/D_1 (ADI_1), SCI_0 (TXI_0), SCI_0 (RXI_0), SCI_1 (TXI_1), or SCI_1 (RXI_1) was selected as the DMA transfer request source. 3. When DMA transfers are enabled (DE = 1) while interrupts are disabled (ADIE = 0 in ADCSR, TIE = 0 or RIE = 0 in SCSCR) for the peripheral module selected as the DMA transfer request source. This problem can be avoided by using one of the following workarounds: 1. When SCI_0 (TXI_0) or SCI_1 (TXI_1) is the transfer request source ⎯ Enable DMA transfers (DE = 1) after confirming that the transmit data empty interrupt (TE = 1 and TIE = 1 in SCSCR and TDRE = 1 in SCSSR) has been generated. 2. When A/D_1 (ADI_1), SCI_0 (RXI_0), or SCI_1 (RXI_1) is the transfer request source ⎯ Before using a DMA transfer, do not use a CPU interrupt or DTC transfer that uses the same interrupt request. ⎯ Only clear the interrupt source flag (ADF in ADCSR or RDRF in SCSSR) by a DMA transfer. Do not clear it by the CPU or DTC. When it is necessary to clear the interrupt source flag, perform one (dummy) DMA transfer while operation of the peripheral module is disabled (ADST = 0 in ADCR or RE = 0 in SCSCR). ⎯ Enable DMA transfers (DE = 1) after enabling the interrupt request (ADIE = 1 in ADCSR or RIE = 1 in SCSCR). Figure 10.22 shows an example DMA transfer sequence when SCI_0 (RXI_0) or SCI_1 (RXI_1) is selected as the transfer request source, and figure 10.23 shows an example dummy transfer sequence.

Section 10 Direct Memory Access Controller (DMAC) Page 424 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Disable serial receive (RE = 0 in SCSCR) Clear serial receive error flag Disable DMA transfers (DE = 0) Clear DMA transfer end state (clear TE) DMAC initial settings Enable serial receive and receive data full interrupt (RE = 1 and RIE = 1 in SCSCR) Enable DMA transfers (DE = 1) Disable serial receive and receive data full interrupt (RE = 0 and RIE = 0 in SCSCR) Disable DMAC operation (DME = 0) Clear DMAC error flag Enable DMAC operation (DME = 1) No No No Yes Yes Yes [3] [4] [5] [6] [7] [8] [9] [1] [2] Start DMA transfer Dummy transfer Interrupt source flag set to 1? RDRF = 1 in SCSSR? Disable DMA transfers (DE = 0) Clear DMA transfer end state (clear TE) Continue DMA transfer? DMA transfer end? TE = 1? [1] [1] Disable serial receive so no interrupt (RXI) occurs during the transfer sequence. [2] Clear the serial receive error flag. At this point, do not clear the interrupt source flag (RDRF in SCSSR). [3] If the interrupt source flag has been set to 1, perform a dummy transfer to clear it. [4] After enabling serial receive and the receive data full interrupt (RE = 1 and RIE = 1 in SCSCR), enable DMA transfers (DE = 1). [5] Wait for the DMA transfer to end. If the DEI interrupt is enabled (IE = 1), a DEI interrupt will be generated when the DMA transfer ends. [6] Disable DMA transfers (DE = 0). [7] Clear the DMA transfer end state (clear TE). [8] To continue DMA transfer operation, reset the DMAC. No dummy transfer is needed in this case. [9] Disable the receive data full interrupt (RIE = 0 in SCSCR) to disable interrupt requests. DMA transfer end Figure 10.22 Example DMA Transfer Sequence in Peripheral Module Request Mode (RXI)

Section 10 Direct Memory Access Controller (DMAC) R01UH0198EJ0500 Rev. 5.00 Page 425 of 1560 Mar 18, 2011 SH7080 Group Disable serial receive (RE = 0 in SCSCR) Clear serial receive error flag Disable DMA transfers (DE = 0) Clear DMA transfer end state (clear TE) Clear DMAC error flag Enable DMAC operation (DME = 1) DMAC initial settings SAR = SCRDR DAR = any value DMATCR = 1 Enable serial receive and receive data full interrupt (RE = 0 and RIE = 1 in SCSCR) Enable DMA transfers (DE = 1) Enable serial receive and receive data full interrupt (RE = 0 and RIE = 0 in SCSCR) Disable DMAC operation (DME = 0) No Yes [3] [4] [5] [6] [7] [8] [1] [2] Start dummy transfer Disable DMA transfers (DE = 0) Clear DMA transfer end state (clear TE) DMA transfer end? TE = 1? [1] [1] Disable serial receive so no interrupt (RXI) occurs during the transfer sequence. [2] Clear the serial receive error flag. At this point, do not clear the interrupt source flag (RDRF in SCSSR). [3] Initialize the DMAC. Set the DMA transfer count to 1 (DMATCR = 1). [4] While serial receive remains disabled, enable the receive data full interrupt (RE = 0 and RIE = 1 in SCSCR). [5] Wait for the DMA transfer to end. If the DEI interrupt is enabled (IE = 1), a DEI interrupt will be generated when the DMA transfer ends. [6] Disable DMA transfers (DE = 0). [7] Clear the DMA transfer end state (clear TE). [8] Disable the receive data full interrupt (RIE = 0 in SCSCR) to disable interrupt requests. Dummy transfer end Figure 10.23 Example Dummy Transfer Sequence (RXI)

Section 10 Direct Memory Access Controller (DMAC) Page 426 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

10.5.11 Number of Cycles per Access to On-Chip RAM by DMAC

The number of cycles required for read/write access to on-chip RAM from the DMAC is as shown in table 10.9, which differs depending on the frequency ratio of I φ (internal clock) to Bφ (external bus clock). Table 10.9 Number of Cycles per Access to On-Chip RAM by DMAC Setting of Iφ:Bφ Read Write 1:1 3 × Bcyc 3 × Bcyc 1:1/2 2 × Bcyc 1 × Bcyc 1:1/3 2 × Bcyc 1 × Bcyc 1:1/4 or less 1 × Bcyc 1 × Bcyc Notes: 1. Bcyc is the external bus clock cycle. 2. The number of cycles for access to the on-chip peripheral I/O or an external device are indicated in section 9.5.16, Access to On-Chip Peripheral I/O Registers by CPU, and section 9.5.17, Access to External Memory by CPU. The access cycles are obtained by subtracting the cycles of Iφ required for L-bus access from the cycles required for access by the CPU.

10.5.12 Note on DMAC Transfer in Burst Mode when Activation Source Is MTU2

The corresponding bit among DMMTU4 to DMMTU0 in the bus function extending register (BSCEHR) must be set when performing DMA transfer in burst mode with the MTU2 specified as the activation source. For details, see section 9.4.8, Bus Function Extending Register (BSCEHR).

10.5.13 Bus Function Extending Register (BSCEHR)

With the bus function extending register (BSCEHR), it is possible to set the function to perform transfer by the DMAC preferentially. For details, see section 9.4.8, Bus Function Extending Register (BSCEHR).

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 427 of 1560 Mar 18, 2011 SH7080 Group Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) This LSI has an on-chip multi-function timer pulse unit 2 (MTU2) that comprises six 16-bit timer channels.

11.1 Features

• Maximum 16 pulse input/output lines and three pulse input lines
• Selection of eight counter input clocks for each channel (four clocks for channel 5)
• The following operations can be set for channels 0 to 4: ⎯ Waveform output at compare match ⎯ Input capture function ⎯ Counter clear operation ⎯ Multiple timer counters (TCNT) can be written to simultaneously ⎯ Simultaneous clearing by compare match and input capture is possible ⎯ Register simultaneous input/output is possible by synchronous counter operation ⎯ A maximum 12-phase PWM output is possible in combination with synchronous operation
• Buffer operation settable for channels 0, 3, and 4
• Phase counting mode settable independently for each of channels 1 and 2
• Cascade connection operation
• Fast access via internal 16-bit bus
• 28 interrupt sources
• Automatic transfer of register data
• A/D converter start trigger can be generated
• Module standby mode can be settable
• A total of six-phase waveform output, which includes complementary PWM output, and positive and negative phases of reset PWM output by interlocking operation of channels 3 and 4, is possible.
• AC synchronous motor (brushless DC motor) drive mode using complementary PWM output and reset PWM output is settable by interlocking operation of channels 0, 3, and 4, and the selection of two types of waveform outputs (chopping and level) is possible.
• Dead time compensation counter available in channel 5
• In complementary PWM mode, interrupts at the crest and trough of the counter value and A/D converter start triggers can be skipped.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 428 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 11.1 MTU2 Functions Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Count clock MP φ/1 MPφ/4 MPφ/16 MPφ/64 TCLKA TCLKB TCLKC TCLKD MPφ/1 MPφ/4 MPφ/16 MPφ/64 MPφ/256 TCLKA TCLKB MPφ/1 MPφ/4 MPφ/16 MPφ/64 MPφ/1024 TCLKA TCLKB TCLKC MPφ/1 MPφ/4 MPφ/16 MPφ/64 MPφ/256 MPφ/1024 TCLKA TCLKB MPφ/1 MPφ/4 MPφ/16 MPφ/64 MPφ/256 MPφ/1024 TCLKA TCLKB MPφ/1 MPφ/4 MPφ/16 MP φ/64 General registers TGRA_0 TGRB_0 TGRE_0 TGRA_1 TGRB_1 TGRA_2 TGRB_2 TGRA_3 TGRB_3 TGRA_4 TGRB_4 TGRU_5 TGRV_5 TGRW_5 General registers/ buffer registers TGRC_0 TGRD_0 TGRF_0 — — TGRC_3 TGRD_3 TGRC_4 TGRD_4 I/O pins TIOC0A TIOC0B TIOC0C TIOC0D TIOC1A TIOC1B TIOC2A TIOC2B TIOC3A TIOC3B TIOC3C TIOC3D TIOC4A TIOC4B TIOC4C TIOC4D Input pins TIC5U TIC5V TIC5W Counter clear function TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture Compare match output Toggle output Input capture function Synchronous operation Complementary PWM mode AC synchronous motor drive mode

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 429 of 1560 Mar 18, 2011 SH7080 Group Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Phase counting mode Dead time compensation counter function DMAC activation TGRA_0 compare match or input capture TGRA_1 compare match or input capture TGRA_2 compare match or input capture TGRA_3 compare match or input capture TGRA_4 compare match or input capture DTC activation TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture and TCNT overflow or underflow TGR compare match or input capture A/D converter start trigger TGRA_0 compare match or input capture TGRE_0 compare match TGRA_1 compare match or input capture TGRA_2 compare match or input capture TGRA_3 compare match or input capture TGRA_4 compare match or input capture TCNT_4 underflow (trough) in complement ary PWM mode

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 430 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Interrupt sources 7 sources

• Compare match or input capture
• Compare match or input capture
• Compare match or input capture
• Compare match or input capture
• Compare match 0E
• Compare match 0F
• Overflow 4 sources
• Compare match or input capture
• Compare match or input capture
• Overflow
• Underflow 4 sources
• Compare match or input capture
• Compare match or input capture
• Overflow
• Underflow 5 sources
• Compare match or input capture
• Compare match or input capture
• Compare match or input capture
• Compare match or input capture Overflow 5 sources
• Compare match or input capture
• Compare match or input capture
• Compare match or input capture
• Compare match or input capture
• Overflow or underflow 3 sources
• Compare match or input capture
• Compare match or input capture
• Compare match or input capture

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 431 of 1560 Mar 18, 2011 SH7080 Group Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 A/D converter start request delaying function converter start request at a match between TADCOR A_4 and TCNT_4

• A/D converter start request at a match between TADCOR B_4 and TCNT_4 Interrupt skipping function — — — • Skips TGRA_3 compare match interrupts
• Skips TCIV_4 interrupts [Legend] √: Possible —: Not possible

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 433 of 1560 Mar 18, 2011 SH7080 Group

11.2 Input/Output Pins

Table 11.2 Pin Configuration Channel Pin Name I/O Function Common TCLKA Input External clock A input pin (Channel 1 phase counting mode A phase input) TCLKB Input External clock B input pin (Channel 1 phase counting mode B phase input) TCLKC Input External clock C input pin (Channel 2 phase counting mode A phase input) TCLKD Input External clock D input pin (Channel 2 phase counting mode B phase input)

0 TIOC0A I/O TGRA_0 input capture input/output compare output/PWM output pin

TIOC0B I/O TGRB_0 input capture input/output compare output/PWM output pin TIOC0C I/O TGRC_0 input capture input/output compare output/PWM output pin TIOC0D I/O TGRD_0 input capture input/output compare output/PWM output pin

1 TIOC1A I/O TGRA_1 input capture input/output compare output/PWM output pin

TIOC1B I/O TGRB_1 input capture input/output compare output/PWM output pin

2 TIOC2A I/O TGRA_2 input capture input/output compare output/PWM output pin

TIOC2B I/O TGRB_2 input capture input/output compare output/PWM output pin

3 TIOC3A I/O TGRA_3 input capture input/output compare output/PWM output pin

TIOC3B I/O TGRB_3 input capture input/output compare output/PWM output pin TIOC3C I/O TGRC_3 input capture input/output compare output/PWM output pin TIOC3D I/O TGRD_3 input capture input/output compare output/PWM output pin

4 TIOC4A I/O TGRA_4 input capture input/output compare output/PWM output pin

TIOC4B I/O TGRB_4 input capture input/output compare output/PWM output pin TIOC4C I/O TGRC_4 input capture input/output compare output/PWM output pin TIOC4D I/O TGRD_4 input capture input/output compare output/PWM output pin

5 TIC5U Input TGRU_5 input capture input/external pulse input pin

TIC5V Input TGRV_5 input capture input/external pulse input pin TIC5W Input TGRW_5 input capture input/external pulse input pin

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 434 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

11.3 Register Descriptions

The MTU2 has the following registers. For details on register addresses and register states during each process, refer to section 27, List of Registers. To distinguish registers in each channel, an underscore and the channel number are added as a suffix to the register name; TCR for channel 0 is expressed as TCR_0. Table 11.3 Register Configuration Register Name Abbrevia- tion R/W Initial value Address Access Size Timer control register_3 TCR_3 R/W H'00 H'FFFFC200 8, 16, 32 Timer control register_4 TCR_4 R/W H'00 H'FFFFC201 8 Timer mode register_3 TMDR_3 R/W H'00 H'FFFFC202 8, 16 Timer mode register_4 TMDR_4 R/W H'00 H'FFFFC203 8 Timer I/O control register H_3 TIORH_3 R/W H'00 H'FFFFC204 8, 16, 32 Timer I/O control register L_3 TIORL_3 R/W H'00 H'FFFFC205 8 Timer I/O control register H_4 TIORH_4 R/W H'00 H'FFFFC206 8, 16 Timer I/O control register L_4 TIORL_4 R/W H'00 H'FFFFC207 8 Timer interrupt enable register_3 TIER_3 R/W H'00 H'FFFFC208 8, 16 Timer interrupt enable register_4 TIER_4 R/W H'00 H'FFFFC209 8 Timer output master enable register TOER R/W H'C0 H'FFFFC20A 8 Timer gate control register TGCR R/W H'80 H'FFFFC20D 8 Timer output control register 1 TOCR1 R/W H'00 H'FFFFC20E 8, 16 Timer output control register 2 TOCR2 R/W H'00 H'FFFFC20F 8 Timer counter_3 TCNT_3 R/W H'0000 H'FFFFC210 16, 32 Timer counter_4 TCNT_4 R/W H'0000 H'FFFFC212 16 Timer cycle data register TCDR R/W H'FFFF H'FFFFC214 16, 32 Timer dead time data register TDDR R/W H'FFFF H'FFFFC216 16 Timer general register A_3 TGRA_3 R/W H'FFFF H'FFFFC218 16, 32 Timer general register B_3 TGRB_3 R/W H'FFFF H'FFFFC21A 16 Timer general register A_4 TGRA_4 R/W H'FFFF H'FFFFC21C 16, 32 Timer general register B_4 TGRB_4 R/W H'FFFF H'FFFFC21E 16

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 435 of 1560 Mar 18, 2011 SH7080 Group Register Name Abbrevia- tion R/W Initial value Address Access Size Timer subcounter TCNTS R H'0000 H'FFFFC220 16, 32 Timer cycle buffer register TCBR R/W H'FFFF H'FFFFC222 16 Timer general register C_3 TGRC_3 R/W H'FFFF H'FFFFC224 16, 32 Timer general register D_3 TGRD_3 R/W H'FFFF H'FFFFC226 16 Timer general register C_4 TGRC_4 R/W H'FFFF H'FFFFC228 16, 32 Timer general register D_4 TGRD_4 R/W H'FFFF H'FFFFC22A 16 Timer status register_3 TSR_3 R/W H'C0 H'FFFFC22C 8, 16 Timer status register_4 TSR_4 R/W H'C0 H'FFFFC22D 8 Timer interrupt skipping set register TITCR R/W H'00 H'FFFFC230 8, 16 Timer interrupt skipping counter TITCNT R H'00 H'FFFFC231 8 Timer buffer transfer set register TBTER R/W H'00 H'FFFFC232 8 Timer dead time enable register TDER R/W H'01 H'FFFFC234 8 Timer output level buffer register TOLBR R/W H'00 H'FFFFC236 8 Timer buffer operation transfer mode register_3 TBTM_3 R/W H'00 H'FFFFC238 8, 16 Timer buffer operation transfer mode register_4 TBTM_4 R/W H'00 H'FFFFC239 8 Timer A/D converter start request control register TADCR R/W H'0000 H'FFFFC240 16 Timer A/D converter start request cycle set register A_4 TADCORA_4 R/W H'FFFF H'FFFFC244 16, 32 Timer A/D converter start request cycle set register B_4 TADCORB_4 R/W H'FFFF H'FFFFC246 16 Timer A/D converter start request cycle set buffer register A_4 TADCOBRA_4 R/W H'FFFF H'FFFFC248 16, 32 Timer A/D converter start request cycle set buffer register B_4 TADCOBRB_4 R/W H'FFFF H'FFFFC24A 16

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 436 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Register Name Abbrevia- tion R/W Initial value Address Access Size Timer waveform control register TWCR R/W H'00 H'FFFFC260 8 Timer start register TSTR R/W H'00 H'FFFFC280 8, 16 Timer synchronous register TSYR R/W H'00 H'FFFFC281 8 Timer counter synchronous start register TCSYSTR R/W H'00 H'FFFFC282 8 Timer read/write enable register TRWER R/W H'01 H'FFFFC284 8 Timer control register_0 TCR_0 R/W H'00 H'FFFFC300 8, 16, 32 Timer mode register_0 TMDR_0 R/W H'00 H'FFFFC301 8 Timer I/O control register H_0 TIORH_0 R/W H'00 H'FFFFC302 8, 16 Timer I/O control register L_0 TIORL_0 R/W H'00 H'FFFFC303 8 Timer interrupt enable register_0 TIER_0 R/W H'00 H'FFFFC304 8, 16, 32 Timer status register_0 TSR_0 R/W H'C0 H'FFFFC305 8 Timer counter_0 TCNT_0 R/W H'0000 H'FFFFC306 16 Timer general register A_0 TGRA_0 R/W H'FFFF H'FFFFC308 16, 32 Timer general register B_0 TGRB_0 R/W H'FFFF H'FFFFC30A 16 Timer general register C_0 TGRC_0 R/W H'FFFF H'FFFFC30C 16, 32 Timer general register D_0 TGRD_0 R/W H'FFFF H'FFFFC30E 16 Timer general register E_0 TGRE_0 R/W H'FFFF H'FFFFC320 16, 32 Timer general register F_0 TGRF_0 R/W H'FFFF H'FFFFC322 16 Timer interrupt enable register 2_0 TIER2_0 R/W H'00 H'FFFFC324 8, 16 Timer status register 2_0 TSR2_0 R/W H'C0 H'FFFFC325 8 Timer buffer operation transfer mode register_0 TBTM_0 R/W H'00 H'FFFFC326 8 Timer control register_1 TCR_1 R/W H'00 H'FFFFC380 8, 16 Timer mode register_1 TMDR_1 R/W H'00 H'FFFFC381 8 Timer I/O control register_1 TIOR_1 R/W H'00 H'FFFFC382 8 Timer interrupt enable register_1 TIER_1 R/W H'00 H'FFFFC384 8, 16, 32 Timer status register_1 TSR_1 R/W H'C0 H'FFFFC385 8

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 437 of 1560 Mar 18, 2011 SH7080 Group Register Name Abbrevia- tion R/W Initial value Address Access Size Timer counter_1 TCNT_1 R/W H'0000 H'FFFFC386 16 Timer general register A_1 TGRA_1 R/W H'FFFF H'FFFFC388 16, 32 Timer general register B_1 TGRB_1 R/W H'FFFF H'FFFFC38A 16 Timer input capture control register TICCR R/W H'00 H'FFFFC390 8 Timer control register_2 TCR_2 R/W H'00 H'FFFFC400 8, 16 Timer mode register_2 TMDR_2 R/W H'00 H'FFFFC401 8 Timer I/O control register_2 TIOR_2 R/W H'00 H'FFFFC402 8 Timer interrupt enable register_2 TIER_2 R/W H'00 H'FFFFC404 8, 16, 32 Timer status register_2 TSR_2 R/W H'C0 H'FFFFC405 8 Timer counter_2 TCNT_2 R/W H'0000 H'FFFFC406 16 Timer general register A_2 TGRA_2 R/W H'FFFF H'FFFFC408 16, 32 Timer general register B_2 TGRB_2 R/W H'FFFF H'FFFFC40A 16 Timer counter U_5 TCNTU_5 R/W H'0000 H'FFFFC480 16, 32 Timer general register U_5 TGRU_5 R/W H'FFFF H'FFFFC482 16 Timer control register U_5 TCRU_5 R/W H'00 H'FFFFC484 8 Timer I/O control register U_5 TIORU_5 R/W H'00 H'FFFFC486 8 Timer counter V_5 TCNTV_5 R/W H'0000 H'FFFFC490 16, 32 Timer general register V_5 TGRV_5 R/W H'FFFF H'FFFFC492 16 Timer control register V_5 TCRV_5 R/W H'00 H'FFFFC494 8 Timer I/O control register V_5 TIORV_5 R/W H'00 H'FFFFC496 8 Timer counter W_5 TCNTW_5 R/W H'0000 H'FFFFC4A0 16, 32 Timer general register W_5 TGRW_5 R/W H'FFFF H'FFFFC4A2 16 Timer control register W_5 TCRW_5 R/W H'00 H'FFFFC4A4 8 Timer I/O control register W_5 TIORW_5 R/W H'00 H'FFFFC4A6 8 Timer status register_5 TSR_5 R/W H'00 H'FFFFC4B0 8 Timer interrupt enable register_5 TIER_5 R/W H'00 H'FFFFC4B2 8 Timer start register_5 TSTR_5 R/W H'00 H'FFFFC4B4 8 Timer compare match clear register TCNTCMPCLR R/W H'00 H'FFFFC4B6 8

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 438 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

11.3.1 Timer Control Register (TCR)

The TCR registers are 8-bit readable/writable registers that control the TCNT operation for each channel. The MTU2 has a total of eight TCR registers, one each for channels 0 to 4 and three (TCRU_5, TCRV_5, and TCRW_5) for channel 5. TCR register settings should be conducted only when TCNT operation is stopped. Bit: Initial value: R/W: 7654321 0 00000000 R/W R/W R/W R/W R/W R/W R/W R/W CCLR[2:0] CKEG[1:0] TPSC[2:0] Bit Bit Name Initial Value R/W Description 7 to 5 CCLR[2:0] 000 R/W Counter Clear 0 to 2 These bits select the TCNT counter clearing source. See tables 11.4 and 11.5 for details. 4, 3 CKEG[1:0] 00 R/W Clock Edge 0 and 1 These bits select the input clock edge. When the input clock is counted using both edges, the input clock period is halved (e.g. MPφ/4 both edges = MPφ/2 rising edge). If phase counting mode is used on channels 1 and 2, this setting is ignored and the phase counting mode setting has priority. Internal clock edge selection is valid when the input clock is MPφ/4 or slower. When MPφ/1, or the overflow/underflow of another channel is selected for the input clock, although values can be written, counter operation compiles with the initial value. 00: Count at rising edge 01: Count at falling edge 1x: Count at both edges 2 to 0 TPSC[2:0] 000 R/W Time Prescaler 0 to 2 These bits select the TCNT counter clock. The clock source can be selected independently for each channel. See tables 11.6 to 11.10 for details. [Legend] x: Don't care

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 439 of 1560 Mar 18, 2011 SH7080 Group Table 11.4 CCLR0 to CCLR2 (Channels 0, 3, and 4) Channel Bit 7 CCLR2 Bit 6 CCLR1 Bit 5 CCLR0 0, 3, 4 0 0 0 TCNT clearing disabled

1 TCNT cleared by TGRA compare match/input

1 0 TCNT cleared by TGRB compare match/input capture

1 TCNT cleared by counter clearing for another

channel performing synchronous clearing/ synchronous operation* 1 0 0 TCNT clearing disabled

1 TCNT cleared by TGRC compare match/input

capture* 1 0 TCNT cleared by TGRD compare match/input capture* channel performing synchronous clearing/ synchronous operation* Notes: 1. Synchronous operation is set by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. Table 11.5 CCLR0 to CCLR2 (Channels 1 and 2) Channel Bit 7 Reserved* Bit 6 CCLR1 Bit 5 CCLR0 1, 2 0 0 0 TCNT clearing disabled 1 0 TCNT cleared by TGRB compare match/input capture channel performing synchronous clearing/ synchronous operation* Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1. 2. Bit 7 is reserved in channels 1 and 2. It is always read as 0 and cannot be modified.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 440 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 11.6 TPSC0 to TPSC2 (Channel 0) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 0 0 0 0 Internal clock: counts on MP φ/1

1 Internal clock: counts on MP φ/4

1 0 Internal clock: counts on MP φ/16

1 Internal clock: counts on MP φ/64

1 0 0 External clock: counts on TCLKA pin input

1 External clock: counts on TCLKB pin input

1 0 External clock: counts on TCLKC pin input

1 External clock: counts on TCLKD pin input

Table 11.7 TPSC0 to TPSC2 (Channel 1) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 1 0 0 0 Internal clock: counts on MP φ/1 1 0 Internal clock: counts on MP φ/16 1 0 0 External clock: counts on TCLKA pin input 1 0 Internal clock: counts on MP φ/256

1 Counts on TCNT_2 overflow/underflow

Note: This setting is ignored when channel 1 is in phase counting mode.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 441 of 1560 Mar 18, 2011 SH7080 Group Table 11.8 TPSC0 to TPSC2 (Channel 2) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 2 0 0 0 Internal clock: counts on MP φ/1 1 0 Internal clock: counts on MP φ/16 1 0 0 External clock: counts on TCLKA pin input 1 0 External clock: counts on TCLKC pin input

1 Internal clock: counts on MP φ/1024

Note: This setting is ignored when channel 2 is in phase counting mode. Table 11.9 TPSC0 to TPSC2 (Channels 3 and 4) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 3, 4 0 0 0 Internal clock: counts on MP φ/1 1 0 Internal clock: counts on MP φ/16 1 0 0 Internal clock: counts on MP φ/256 1 0 External clock: counts on TCLKA pin input

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 442 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 11.10 TPSC1 and TPSC0 (Channel 5) Channel Bit 1 TPSC1 Bit 0 TPSC0 5 0 0 Internal clock: counts on MP φ/1 1 0 Internal clock: counts on MP φ/16 Note: Bits 7 to 2 are reserved in channel 5. These bits are always read as 0. The write value should always be 0.

11.3.2 Timer Mode Register (TMDR)

The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode of each channel. The MTU2 has five TMDR registers, one each for channels 0 to 4. TMDR register settings should be changed only when TCNT operation is stopped. Bit: Initial value: R/W: 7654321 0 00000000 - R/W R/W R/W R/W R/W R/W R/W - BFE BFB BFA MD[3:0] Bit Bit Name Initial Value R/W Description 7 — 0 — Reserved This bit is always read as 0. The write value should always be 0.

6 BFE 0 R/W Buffer Operation E

Specifies whether TGRE_0 and TGRF_0 are to operate in the normal way or to be used together for buffer operation. Compare match with TGRF occurs even when TGRF is used as a buffer register. In channels 1 to 4, this bit is reserved. It is always read as 0 and the write value should always be 0. 0: TGRE_0 and TGRF_0 operate normally 1: TGRE_0 and TGRF_0 used together for buffer operation

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 443 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description

5 BFB 0 R/W Buffer Operation B

Specifies whether TGRB is to operate in the normal way, or TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer register, TGRD input capture/output compare do not take place in modes other than complementary PWM mode, but compare match with TGRD occurs in complementary PWM mode. Since the TGFD flag will be set if a compare match occurs during Tb interval in complementary PWM mode, the TGIED bit in timer interrupt enable register 3/4 (TIER_3/4) should be cleared to 0. In channels 1 and 2, which have no TGRD, bit 5 is reserved. It is always read as 0 and cannot be modified. 0: TGRB and TGRD operate normally 1: TGRB and TGRD used together for buffer operation

4 BFA 0 R/W Buffer Operation A

Specifies whether TGRA is to operate in the normal way, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare do not take place in modes other than complementary PWM mode, but compare match with TGRC occurs in complementary PWM mode. Since the TGFC flag will be set if a compare match occurs on channel 4 during Tb interval in complementary PWM mode, the TGIEC bit in timer interrupt enable register 4 (TIER_4) should be cleared to 0. In channels 1 and 2, which have no TGRC, bit 4 is reserved. It is always read as 0 and cannot be modified. 0: TGRA and TGRC operate normally 1: TGRA and TGRC used together for buffer operation 3 to 0 MD[3:0] 0000 R/W Modes 0 to 3 These bits are used to set the timer operating mode. See table 11.11 for details.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 444 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 11.11 Setting of Operation Mode by Bits MD0 to MD3 Bit 3 MD3 Bit 2 MD2 Bit 1 MD1 Bit 0 MD0

1 Setting prohibited

1 PWM mode 2 *

1 0 0 Phase counting mode 1 *

1 Phase counting mode 2 *

1 0 Phase counting mode 3 *

1 Phase counting mode 4 *

1 0 0 0 Reset synchronous PWM mode *

1 Complementary PWM mode 1 (transmit at crest) *

1 0 Complementary PWM mode 2 (transmit at trough) *

1 Complementary PWM mode 2 (transmit at crest and

trough)* [Legend] x: Don't care Notes: 1. PWM mode 2 can not be set for channels 3 and 4. 2. Phase counting mode can not be set for channels 0, 3, and 4. 3. Reset synchronous PWM mode and complementary PWM mode can only be set for channel 3. When channel 3 is set to reset synchronous PWM mode or complementary PWM mode, the channel 4 settings become ineffective and automatically conform to the channel 3 settings. However, do not set channel 4 to reset synchronous PWM mode or complementary PWM mode. Reset synchronous PWM mode and complementary PWM mode cannot be set for channels 0, 1, and 2.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 445 of 1560 Mar 18, 2011 SH7080 Group

11.3.3 Timer I/O Control Register (TIOR)

The TIOR registers are 8-bit readable/writable registers that control the TGR registers. The MTU2 has a total of eleven TIOR registers, two each for channels 0, 3, and 4, one each for channels 1 and 2, and three (TIORU_5, TIORV_5, and TIORW_5) for channel 5. TIOR should be set when TMDR is set to select normal operation, PWM mode, or phase counting mode. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is cleared to 0 is specified. When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register.

• TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIORH_4 Bit: Initial value: R/W: 7654321 0 00000000 R/W R/W R/W R/W R/W R/W R/W R/W IOB[3:0] IOA[3:0] Bit Bit Name Initial Value R/W Description 7 to 4 IOB[3:0] 0000 R/W I/O Control B0 to B3 Specify the function of TGRB. See the following tables. TIORH_0: Table 11.12 TIOR_1: Table 11.14 TIOR_2: Table 11.15 TIORH_3: Table 11.16 TIORH_4: Table 11.18 3 to 0 IOA[3:0] 0000 R/W I/O Control A0 to A3 Specify the function of TGRA. See the following tables. TIORH_0: Table 11.20 TIOR_1: Table 11.22 TIOR_2: Table 11.23 TIORH_3: Table 11.24 TIORH_4: Table 11.26

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 446 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

• TIORL_0, TIORL_3, TIORL_4 Bit: Initial value: R/W: 7654321 0 00000000 R/W R/W R/W R/W R/W R/W R/W R/W IOD[3:0] IOC[3:0] Bit Bit Name Initial Value R/W Description 7 to 4 IOD[3:0] 0000 R/W I/O Control D0 to D3 Specify the function of TGRD. See the following tables. TIORL_0: Table 11.13 TIORL_3: Table 11.17 TIORL_4: Table 11.19 3 to 0 IOC[3:0] 0000 R/W I/O Control C0 to C3 Specify the function of TGRC. See the following tables. TIORL_0: Table 11.21 TIORL_3: Table 11.25 TIORL_4: Table 11.27
• TIORU_5, TIORV_5, TIORW_5 Bit: Initial value: R/W: 7654321 0 00000000 R R R R/W R/W R/W R/W R/W - - - IOC[4:0] Bit Bit Name Initial Value R/W Description 7 to 5 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 to 0 IOC[4:0] 00000 R/W I/O Control C0 to C4 Specify the function of TGRU_5, TGRV_5, and TGRW_5. For details, see table 11.28.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 447 of 1560 Mar 18, 2011 SH7080 Group Table 11.12 TIORH_0 (Channel 0) TGRB_0 Function TIOC0B Pin Function

0 Output retained * 0

1 Initial output is 0

0 Initial output is 0

Toggle output at compare match 0 0 Output retained

1 Initial output is 1

0 Initial output is 1

Toggle output at compare match 1 0 Input capture at rising edge

1 Input capture at falling edge

Input capture at both edges 1 x x Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] x: Don't care Note: * After power-on reset, 0 is output until TIOR is set.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 448 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 11.13 TIORL_0 (Channel 0) TGRD_0 Function TIOC0D Pin Function 0 0 0 0 Output retained * register* Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained Toggle output at compare match 1 0 0 0 Input capture at rising edge register* Input capture at both edges 1 x x Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] x: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFB bit in TMDR_0 is set to 1 and TGRD_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 449 of 1560 Mar 18, 2011 SH7080 Group Table 11.14 TIOR_1 (Channel 1) TGRB_1 Function TIOC1B Pin Function 0 0 0 0 Output retained * Output compare register Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained Toggle output at compare match 1 0 0 0 Input capture at rising edge Input capture at both edges 1 x x Input capture at generation of TGRC_0 compare match/input capture [Legend] x: Don't care Note: * After power-on reset, 0 is output until TIOR is set.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 450 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 11.15 TIOR_2 (Channel 2) TGRB_2 Function TIOC2B Pin Function 0 0 0 0 Output retained * Output compare register Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained Toggle output at compare match 1 x 0 0 Input capture at rising edge Input capture register Input capture at falling edge 1 x Input capture at both edges [Legend] x: Don't care Note: * After power-on reset, 0 is output until TIOR is set.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 451 of 1560 Mar 18, 2011 SH7080 Group Table 11.16 TIORH_3 (Channel 3) TGRB_3 Function TIOC3B Pin Function 0 0 0 0 Output retained * Output compare register Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained Toggle output at compare match 1 x 0 0 Input capture at rising edge Input capture register Input capture at falling edge 1 x Input capture at both edges [Legend] x: Don't care Note: * After power-on reset, 0 is output until TIOR is set.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 452 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 11.17 TIORL_3 (Channel 3) TGRD_3 Function TIOC3D Pin Function 0 0 0 0 Output retained * Output compare register* Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained Toggle output at compare match 1 x 0 0 Input capture at rising edge Input capture register* Input capture at falling edge 1 x Input capture at both edges [Legend] x: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFB bit in TMDR_3 is set to 1 and TGRD_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 453 of 1560 Mar 18, 2011 SH7080 Group Table 11.18 TIORH_4 (Channel 4) TGRB_4 Function TIOC4B Pin Function 0 0 0 0 Output retained * Output compare register Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained Toggle output at compare match 1 x 0 0 Input capture at rising edge Input capture register Input capture at falling edge 1 x Input capture at both edges [Legend] x: Don't care Note: * After power-on reset, 0 is output until TIOR is set.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 454 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 11.19 TIORL_4 (Channel 4) TGRD_4 Function TIOC4D Pin Function 0 0 0 0 Output retained * Output compare register* Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained Toggle output at compare match 1 x 0 0 Input capture at rising edge Input capture register* Input capture at falling edge 1 x Input capture at both edges [Legend] x: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFB bit in TMDR_4 is set to 1 and TGRD_4 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 455 of 1560 Mar 18, 2011 SH7080 Group Table 11.20 TIORH_0 (Channel 0) TGRA_0 Function TIOC0A Pin Function 0 0 0 0 Output retained * Output compare register Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained Toggle output at compare match 1 0 0 0 Input capture at rising edge Input capture at both edges 1 x x Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] x: Don't care Note: * After power-on reset, 0 is output until TIOR is set.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 456 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 11.21 TIORL_0 (Channel 0) TGRC_0 Function TIOC0C Pin Function 0 0 0 0 Output retained * Output compare register* Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained Toggle output at compare match 1 0 0 0 Input capture at rising edge register* Input capture at both edges 1 x x Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] x: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 457 of 1560 Mar 18, 2011 SH7080 Group Table 11.22 TIOR_1 (Channel 1) TGRA_1 Function TIOC1A Pin Function 0 0 0 0 Output retained * Output compare register Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained Toggle output at compare match 1 0 0 0 Input capture at rising edge Input capture at both edges 1 x x Input capture at generation of channel 0/TGRA_0 compare match/input capture [Legend] x: Don't care Note: * After power-on reset, 0 is output until TIOR is set.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 458 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 11.23 TIOR_2 (Channel 2) TGRA_2 Function TIOC2A Pin Function 0 0 0 0 Output retained * Output compare register Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained Toggle output at compare match 1 x 0 0 Input capture at rising edge Input capture register Input capture at falling edge 1 x Input capture at both edges [Legend] x: Don't care Note: * After power-on reset, 0 is output until TIOR is set.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 459 of 1560 Mar 18, 2011 SH7080 Group Table 11.24 TIORH_3 (Channel 3) TGRA_3 Function TIOC3A Pin Function 0 0 0 0 Output retained * Output compare register Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained Toggle output at compare match 1 x 0 0 Input capture at rising edge Input capture register Input capture at falling edge 1 x Input capture at both edges [Legend] x: Don't care Note: * After power-on reset, 0 is output until TIOR is set.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 460 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 11.25 TIORL_3 (Channel 3) TGRC_3 Function TIOC3C Pin Function 0 0 0 0 Output retained * Output compare register* Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained Toggle output at compare match 1 x 0 0 Input capture at rising edge Input capture register* Input capture at falling edge 1 x Input capture at both edges [Legend] x: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFA bit in TMDR_3 is set to 1 and TGRC_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 461 of 1560 Mar 18, 2011 SH7080 Group Table 11.26 TIORH_4 (Channel 4) TGRA_4 Function TIOC4A Pin Function 0 0 0 0 Output retained * Output compare register Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained Toggle output at compare match 1 x 0 0 Input capture at rising edge Input capture register Input capture at falling edge 1 x Input capture at both edges [Legend] x: Don't care Note: * After power-on reset, 0 is output until TIOR is set.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 462 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 11.27 TIORL_4 (Channel 4) TGRC_4 Function TIOC4C Pin Function 0 0 0 0 Output retained * Output compare register* Initial output is 0 0 output at compare match 1 0 Initial output is 0 1 output at compare match Toggle output at compare match 1 0 0 Output retained Toggle output at compare match 1 x 0 0 Input capture at rising edge Input capture register* Input capture at falling edge 1 x Input capture at both edges [Legend] x: Don't care Notes: 1. After power-on reset, 0 is output until TIOR is set. 2. When the BFA bit in TMDR_4 is set to 1 and TGRC_4 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 463 of 1560 Mar 18, 2011 SH7080 Group Table 11.28 TIORU_5, TIORV_5, and TIORW_5 (Channel 5) TGRU_5, TGRV_5, and TGRW_5 Function TIC5U, TIC5V, and TIC5W Pin Function 0 0 0 0 0 Compare match 1 0 0 0 0 Setting prohibited

1 Input capture at rising edge

1 0 Input capture at falling edge

1 Input capture at both edges

1 0 0 0 Setting prohibited

1 Measurement of low pulse width of external input signal

Capture at trough of complementary PWM mode 1 0 Measurement of low pulse width of external input signal Capture at crest of complementary PWM mode Capture at crest and trough of complementary PWM mode 1 0 0 Setting prohibited

1 Measurement of high pulse width of external input signal

Capture at trough of complementary PWM mode 1 0 Input capture register Measurement of high pulse width of external input signal Capture at crest of complementary PWM mode Capture at crest and trough of complementary PWM mode [Legend] x: Don't care

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 464 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

11.3.4 Timer Compare Match Clear Register (TCNTCMPCLR)

TCNTCMPCLR is an 8-bit readable/writable register that specifies requests to clear TCNTU_5, TCNTV_5, and TCNTW_5. The MTU2 has one TCNTCMPCLR in channel 5. Bit: Initial value: R/W: 7654321 0 00000000 R R R R R R/W R/W R/W ----- CMP CLR5U CMP CLR5V CMP CLR5W Bit Bit Name Initial Value R/W Description 7 to 3 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

2 CMPCLR5U 0 R/W TCNT Compare Clear 5U

Enables or disables requests to clear TCNTU_5 at TGRU_5 compare match or input capture. 0: Disables TCNTU_5 to be cleared to H'0000 at TCNTU_5 and TGRU_5 compare match or input capture 1: Enables TCNTU_5 to be cleared to H'0000 at TCNTU_5 and TGRU_5 compare match or input capture

1 CMPCLR5V 0 R/W TCNT Compare Clear 5V

Enables or disables requests to clear TCNTV_5 at TGRV_5 compare match or input capture. 0: Disables TCNTV_5 to be cleared to H'0000 at TCNTV_5 and TGRV_5 compare match or input capture 1: Enables TCNTV_5 to be cleared to H'0000 at TCNTV_5 and TGRV_5 compare match or input capture

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0 CMPCLR5W 0 R/W TCNT Compare Clear 5W

Enables or disables requests to clear TCNTW_5 at TGRW_5 compare match or input capture. 0: Disables TCNTW_5 to be cleared to H'0000 at TCNTW_5 and TGRW_5 compare match or input capture 1: Enables TCNTW_5 to be cleared to H'0000 at TCNTW_5 and TGRW_5 compare match or input capture

11.3.5 Timer Interrupt Enable Register (TIER)

The TIER registers are 8-bit readable/writable registers that control enabling or disabling of interrupt requests for each channel. The MTU2 has seven TIER registers, two for channel 0 and one each for channels 1 to 5.

• TIER_0, TIER_1, TIER_2, TIER_3, TIER_4 Bit: Initial value: R/W: 7654321 0 00000000 R/W R/W R/W R/W R/W R/W R/W R/W TTGE TTGE2 TCIEU TCIEV TGIED TGIEC TGIEB TGIEA Bit Bit Name Initial Value R/W Description

7 TTGE 0 R/W A/D Converter Start Request Enable

Enables or disables generation of A/D converter start requests by TGRA input capture/compare match. 0: A/D converter start request generation disabled 1: A/D converter start request generation enabled

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6 TTGE2 0 R/W A/D Converter Start Request Enable 2

Enables or disables generation of A/D converter start requests by TCNT_4 underflow (trough) in complementary PWM mode. In channels 0 to 3, bit 6 is reserved. It is always read as 0 and the write value should always be 0. 0: A/D converter start request generation by TCNT_4 underflow (trough) disabled 1: A/D converter start request generation by TCNT_4 underflow (trough) enabled

5 TCIEU 0 R/W Underflow Interrupt Enable

Enables or disables interrupt requests (TCIU) by the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1 and 2. In channels 0, 3, and 4, bit 5 is reserved. It is always read as 0 and the write value should always be 0. 0: Interrupt requests (TCIU) by TCFU disabled 1: Interrupt requests (TCIU) by TCFU enabled

4 TCIEV 0 R/W Overflow Interrupt Enable

Enables or disables interrupt requests (TCIV) by the TCFV flag when the TCFV flag in TSR is set to 1. 0: Interrupt requests (TCIV) by TCFV disabled 1: Interrupt requests (TCIV) by TCFV enabled

3 TGIED 0 R/W TGR Interrupt Enable D

Enables or disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channels 0, 3, and 4. In channels 1 and 2, bit 3 is reserved. It is always read as 0 and the write value should always be 0. 0: Interrupt requests (TGID) by TGFD bit disabled 1: Interrupt requests (TGID) by TGFD bit enabled

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2 TGIEC 0 R/W TGR Interrupt Enable C

Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0, 3, and 4. In channels 1 and 2, bit 2 is reserved. It is always read as 0 and the write value should always be 0. 0: Interrupt requests (TGIC) by TGFC bit disabled 1: Interrupt requests (TGIC) by TGFC bit enabled

1 TGIEB 0 R/W TGR Interrupt Enable B

Enables or disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1. 0: Interrupt requests (TGIB) by TGFB bit disabled 1: Interrupt requests (TGIB) by TGFB bit enabled

0 TGIEA 0 R/W TGR Interrupt Enable A

Enables or disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1. 0: Interrupt requests (TGIA) by TGFA bit disabled 1: Interrupt requests (TGIA) by TGFA bit enabled

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 468 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

• TIER2_0 Bit: Initial value: R/W: 7654321 0 00000000 R/W R R R R R R/W R/W TTGE2 - - - - - TGIEF TGIEE Bit Bit Name Initial Value R/W Description

7 TTGE2 0 R/W A/D Converter Start Request Enable 2

Enables or disables generation of A/D converter start requests by compare match between TCNT_0 and TGRE_0. 0: A/D converter start request generation by compare match between TCNT_0 and TGRE_0 disabled 1: A/D converter start request generation by compare match between TCNT_0 and TGRE_0 enabled 6 to 2 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

1 TGIEF 0 R/W TGR Interrupt Enable F

Enables or disables interrupt requests by compare match between TCNT_0 and TGRF_0. 0: Interrupt requests (TGIF) by TGFE bit disabled 1: Interrupt requests (TGIF) by TGFE bit enabled

0 TGIEE 0 R/W TGR Interrupt Enable E

Enables or disables interrupt requests by compare match between TCNT_0 and TGRE_0. 0: Interrupt requests (TGIE) by TGEE bit disabled 1: Interrupt requests (TGIE) by TGEE bit enabled

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 469 of 1560 Mar 18, 2011 SH7080 Group

• TIER_5 Bit: Initial value: R/W: 7654321 0 00000000 R R R R R R/W R/W R/W - - - - - TGIE5U TGIE5V TGIE5W Bit Bit Name Initial Value R/W Description 7 to 3 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

2 TGIE5U 0 R/W TGR Interrupt Enable 5U

Enables or disables interrupt requests (TGIU_5) by the CMFU5 bit when the CMFU5 bit in TSR_5 is set to 1. 0: Interrupt requests (TGIU_5) disabled 1: Interrupt requests (TGIU_5) enabled

1 TGIE5V 0 R/W TGR Interrupt Enable 5V

Enables or disables interrupt requests (TGIV_5) by the CMFV5 bit when the CMFV5 bit in TSR_5 is set to 1. 0: Interrupt requests (TGIV_5) disabled 1: Interrupt requests (TGIV_5) enabled

0 TGIE5W 0 R/W TGR Interrupt Enable 5W

Enables or disables interrupt requests (TGIW_5) by the CMFW5 bit when the CMFW5 bit in TSR_5 is set to 1. 0: Interrupt requests (TGIW_5) disabled 1: Interrupt requests (TGIW_5) enabled

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 470 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

11.3.6 Timer Status Register (TSR)

The TSR registers are 8-bit readable/writable registers that indicate the status of each channel. The MTU2 has seven TSR registers, two for channel 0 and one each for channels 1 to 5.

• TSR_0, TSR_1, TSR_2, TSR_3, TSR_4 Bit: Initial value: R/W: 76543210 11000000 RR R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. TCFD - TCFU TCFV TGFD TGFC TGFB TGFA Note: * Bit Bit Name Initial Value R/W Description

7 TCFD 1 R Count Direction Flag

Status flag that shows the direction in which TCNT counts in channels 1 to 4. In channel 0, bit 7 is reserved. It is always read as 1 and the write value should always be 1. 0: TCNT counts down 1: TCNT counts up 6 — 1 R Reserved This bit is always read as 1. The write value should always be 1.

5 TCFU 0 R/(W) *

Status flag that indicates that TCNT underflow has occurred when channels 1 and 2 are set to phase counting mode. Only 0 can be written, for flag clearing. In channels 0, 3, and 4, bit 5 is reserved. It is always read as 0 and the write value should always be 0. [Setting condition]

• When the TCNT value underflows (changes from H'0000 to H'FFFF) [Clearing condition]
• When 0 is written to TCFU after reading TCFU = 1*

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4 TCFV 0 R/(W) *

Status flag that indicates that TCNT overflow has occurred. Only 0 can be written, for flag clearing. [Setting condition]

• When the TCNT value overflows (changes from H'FFFF to H'0000) In channel 4, when the TCNT_4 value underflows (changes from H'0001 to H'0000) in complementary PWM mode, this flag is also set. [Clearing condition]
• When 0 is written to TCFV after reading TCFV = 1* In cannel 4, when DTC is activated by TCIV interrupt and the DISEL bit of MRB in DTC is 0, this flag is also cleared.

3 TGFD 0 R/(W) *

Input Capture/Output Compare Flag D Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0, 3, and 4. Only 0 can be written, for flag clearing. In channels 1 and 2, bit 3 is reserved. It is always read as 0 and the write value should always be 0. [Setting conditions]

• When TCNT = TGRD and TGRD is functioning as output compare register
• When TCNT value is transferred to TGRD by input capture signal and TGRD is functioning as input capture register [Clearing conditions]
• When DTC is activated by TGID interrupt and the DISEL bit of MRB in DTC is 0
• When 0 is written to TGFD after reading TGFD = 1*

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 472 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description

2 TGFC 0 R/(W) *

Input Capture/Output Compare Flag C Status flag that indicates the occurrence of TGRC input capture or compare match in channels 0, 3, and 4. Only 0 can be written, for flag clearing. In channels 1 and 2, bit 2 is reserved. It is always read as 0 and the write value should always be 0. [Setting conditions]

• When TCNT = TGRC and TGRC is functioning as output compare register
• When TCNT value is transferred to TGRC by input capture signal and TGRC is functioning as input capture register [Clearing conditions]
• When DTC is activated by TGIC interrupt and the DISEL bit of MRB in DTC is 0
• When 0 is written to TGFC after reading TGFC = 1*

1 TGFB 0 R/(W) *

Input Capture/Output Compare Flag B Status flag that indicates the occurrence of TGRB input capture or compare match. Only 0 can be written, for flag clearing. [Setting conditions]

• When TCNT = TGRB and TGRB is functioning as output compare register
• When TCNT value is transferred to TGRB by input capture signal and TGRB is functioning as input capture register [Clearing conditions]
• When DTC is activated by TGIB interrupt and the DISEL bit of MRB in DTC is 0
• When 0 is written to TGFB after reading TGFB = 1*

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 473 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description

0 TGFA 0 R/(W) *

Input Capture/Output Compare Flag A Status flag that indicates the occurrence of TGRA input capture or compare match. Only 0 can be written, for flag clearing. [Setting conditions]

• When TCNT = TGRA and TGRA is functioning as output compare register
• When TCNT value is transferred to TGRA by input capture signal and TGRA is functioning as input capture register [Clearing conditions]
• When DMAC is activated by TGIA interrupt
• When DTC is activated by TGIA interrupt and the DISEL bit of MRB in DTC is 0
• When 0 is written to TGFA after reading TGFA = 1* Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 2. If another flag setting condition occurs before writing 0 to the bit after reading it as 1, the flag will not be cleared by writing 0 to it once. In this case, read the bit as 1 again and write 0 to it.

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• TSR2_0 Bit: Initial value: R/W: 76543210 11000000 RRRRRR R/(W)* R/(W)* Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. - - - - - - TGFF TGFE Note: * Bit Bit Name Initial Value R/W Description 7, 6 — All 1 R Reserved These bits are always read as 1. The write value should always be 1. 5 to 2 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

1 TGFF 0 R/(W) *

Status flag that indicates the occurrence of compare match between TCNT_0 and TGRF_0. [Setting condition]

• When TCNT_0 = TGRF_0 and TGRF_0 is functioning as a compare register [Clearing condition]
• When 0 is written to TGFF after reading TGFF = 1*

0 TGFE 0 R/(W) *

Status flag that indicates the occurrence of compare match between TCNT_0 and TGRE_0. [Setting condition]

• When TCNT_0 = TGRE_0 and TGRE_0 is functioning as compare register [Clearing condition]
• When 0 is written to TGFE after reading TGFE = 1* Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 2. If another flag setting condition occurs before writing 0 to the bit after reading it as 1, the flag will not be cleared by writing 0 to it once. In this case, read the bit as 1 again and write 0 to it.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 475 of 1560 Mar 18, 2011 SH7080 Group

• TSR_5 Bit: Initial value: R/W: 76543210 00000000 RRRRR R/(W)* R/(W)* R/(W)* Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. - - - - - CMFU5 CMFV5 CMFW5 Note: * Bit Bit Name Initial Value R/W Description 7 to 3 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

2 CMFU5 0 R/(W) *

Compare Match/Input Capture Flag U5 Status flag that indicates the occurrence of TGRU_5 input capture or compare match. [Setting conditions]

• When TCNTU_5 = TGRU_5 and TGRU_5 is functioning as output compare register
• When TCNTU_5 value is transferred to TGRU_5 by input capture signal and TGRU_5 is functioning as input capture register
• When TCNTU_5 value is transferred to TGRU_5 and TGRU_5 is functioning as a register for measuring the pulse width of the external input signal. The transfer timing is specified by the IOC bits in timer I/O control register U_5 (TIORU_5).* [Clearing conditions]
• When DTC is activated by a TGIU_5 interrupt and the DISEL bit of MRB in DTC is 0
• When 0 is written to CMFU5 after reading CMFU5 = 1

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 476 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description

1 CMFV5 0 R/(W) *

Compare Match/Input Capture Flag V5 Status flag that indicates the occurrence of TGRV_5 input capture or compare match. [Setting conditions]

• When TCNTV_5 = TGRV_5 and TGRV_5 is functioning as output compare register
• When TCNTV_5 value is transferred to TGRV_5 by input capture signal and TGRV_5 is functioning as input capture register
• When TCNTV_5 value is transferred to TGRV_5 and TGRV_5 is functioning as a register for measuring the pulse width of the external input signal. The transfer timing is specified by the IOC bits in timer I/O control register V_5 (TIORV_5).* [Clearing conditions]
• When DTC is activated by a TGIV_5 interrupt and the DISEL bit of MRB in DTC is 0
• When 0 is written to CMFV5 after reading CMFV5 = 1

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 477 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description

0 CMFW5 0 R/(W) *

Compare Match/Input Capture Flag W5 Status flag that indicates the occurrence of TGRW_5 input capture or compare match. [Setting conditions]

• When TCNTW_5 = TGRW_5 and TGRW_5 is functioning as output compare register
• When TCNTW_5 value is transferred to TGRW_5 by input capture signal and TGRW_5 is functioning as input capture register
• When TCNTW_5 value is transferred to TGRW_5 and TGRW_5 is functioning as a register for measuring the pulse width of the external input signal. The transfer timing is specified by the IOC bits in timer I/O control register W_5 (TIORW_5).* [Clearing conditions]
• When DTC is activated by a TGIW_5 interrupt and the DISEL bit of MRB in DTC is 0
• When 0 is written to CMFW5 after reading CMFW5 = Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 2. The transfer timing is specified by the IOC bit in timer I/O control registers U_5/V_5/W_5 (TIORU_5, TIORV_5, TIORW_5).

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11.3.7 Timer Buffer Operation Transfer Mode Register (TBTM)

The TBTM registers are 8-bit readable/writable registers that specify the timing for transferring data from the buffer register to the timer general register in PWM mode. The MTU2 has three TBTM registers, one each for channels 0, 3, and 4. Bit: Initial value: R/W: 7654321 0 00000000 R R R R R R/W R/W R/W ----- TTSE TTSB TTSA Bit Bit Name Initial Value R/W Description 7 to 3 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

2 TTSE 0 R/W Timing Select E

Specifies the timing for transferring data from TGRF_0 to TGRE_0 when they are used together for buffer operation. In channels 3 and 4, bit 2 is reserved. It is always read as 0 and the write value should always be 0. When using channel 0 in other than PWM mode, do not set this bit to 1. 0: When compare match E occurs in channel 0 1: When TCNT_0 is cleared

1 TTSB 0 R/W Timing Select B

Specifies the timing for transferring data from TGRD to TGRB in each channel when they are used together for buffer operation. When using a channel in other than PWM mode, do not set this bit to1. 0: When compare match B occurs in each channel 1: When TCNT is cleared in each channel

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0 TTSA 0 R/W Timing Select A

Specifies the timing for transferring data from TGRC to TGRA in each channel when they are used together for buffer operation. When using a channel in other than PWM mode, do not set this bit to 1. 0: When compare match A occurs in each channel 1: When TCNT is cleared in each channel

11.3.8 Timer Input Capture Control Register (TICCR)

TICCR is an 8-bit readable/writable register that specifies input capture conditions when TCNT_1 and TCNT_2 are cascaded. The MTU2 has one TICCR in channel 1. Bit: Initial value: R/W: 7654321 0 00000000 R R R R R/W R/W R/W R/W - - - - I2BE I2AE I1BE I1AE Bit Bit Name Initial Value R/W Description 7 to 4 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

3 I2BE 0 R/W Input Capture Enable

Specifies whether to include the TIOC2B pin in the TGRB_1 input capture conditions. 0: Does not include the TIOC2B pin in the TGRB_1 input capture conditions 1: Includes the TIOC2B pin in the TGRB_1 input capture conditions

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 480 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description

2 I2AE 0 R/W Input Capture Enable

Specifies whether to include the TIOC2A pin in the TGRA_1 input capture conditions. 0: Does not include the TIOC2A pin in the TGRA_1 input capture conditions 1: Includes the TIOC2A pin in the TGRA_1 input capture conditions

1 I1BE 0 R/W Input Capture Enable

Specifies whether to include the TIOC1B pin in the TGRB_2 input capture conditions. 0: Does not include the TIOC1B pin in the TGRB_2 input capture conditions 1: Includes the TIOC1B pin in the TGRB_2 input capture conditions

0 I1AE 0 R/W Input Capture Enable

Specifies whether to include the TIOC1A pin in the TGRA_2 input capture conditions. 0: Does not include the TIOC1A pin in the TGRA_2 input capture conditions 1: Includes the TIOC1A pin in the TGRA_2 input capture conditions

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 481 of 1560 Mar 18, 2011 SH7080 Group

11.3.9 Timer Synchronous Clear Register (TSYCR)

TSYCR is an 8-bit readable/writable register that specifies conditions for clearing TCNT_3 and TCNT_4 in the MTU2S in synchronization with the MTU2. The MTU2S has one TSYCRS in channel 3 but the MTU2 has no TSYCR. Bit: Initial value: R/W: 7654321 0 00000000 R/W R/W R/W R/W R/W R/W R/W R/W CE0A CE0B CE0C CE0D CE1A CE1B CE2A CE2B Bit Bit Name Initial Value R/W Description

7 CE0A 0 R/W Clear Enable 0A

Enables or disables counter clearing when the TGFA flag of TSR_0 in the MTU2 is set. 0: Disables counter clearing by the TGFA flag in TSR_0 1: Enables counter clearing by the TGFA flag in TSR_0

6 CE0B 0 R/W Clear Enable 0B

Enables or disables counter clearing when the TGFB flag of TSR_0 in the MTU2 is set. 0: Disables counter clearing by the TGFB flag in TSR_0 1: Enables counter clearing by the TGFB flag in TSR_0

5 CE0C 0 R/W Clear Enable 0C

Enables or disables counter clearing when the TGFC flag of TSR_0 in the MTU2 is set. 0: Disables counter clearing by the TGFC flag in TSR_0 1: Enables counter clearing by the TGFC flag in TSR_0

4 CE0D 0 R/W Clear Enable 0D

Enables or disables counter clearing when the TGFD flag of TSR_0 in the MTU2 is set. 0: Disables counter clearing by the TGFD flag in TSR_0 1: Enables counter clearing by the TGFD flag in TSR_0

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 482 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description

3 CE1A 0 R/W Clear Enable 1A

Enables or disables counter clearing when the TGFA flag of TSR_1 in the MTU2 is set. 0: Disables counter clearing by the TGFA flag in TSR_1 1: Enables counter clearing by the TGFA flag in TSR_1

2 CE1B 0 R/W Clear Enable 1B

Enables or disables counter clearing when the TGFB flag of TSR_1 in the MTU2 is set. 0: Disables counter clearing by the TGFB flag in TSR_1 1: Enables counter clearing by the TGFB flag in TSR_1

1 CE2A 0 R/W Clear Enable 2A

Enables or disables counter clearing when the TGFA flag of TSR_2 in the MTU2 is set. 0: Disables counter clearing by the TGFA flag in TSR_2 1: Enables counter clearing by the TGFA flag in TSR_2

0 CE2B 0 R/W Clear Enable 2B

Enables or disables counter clearing when the TGFB flag of TSR_2 in the MTU2 is set. 0: Disables counter clearing by the TGFB flag in TSR_2 1: Enables counter clearing by the TGFB flag in TSR_2

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 483 of 1560 Mar 18, 2011 SH7080 Group

11.3.10 Timer A/D Converter Start Request Control Register (TADCR)

TADCR is a 16-bit readable/writable register that enables or disables A/D converter start requests and specifies whether to link A/D converter start requests with interrupt skipping operation. The MTU2 has one TADCR in channel 4. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 000000000 0 * 00 * 0* 0* 0* 0* R/W R/W R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W Note: Do not set to 1 when complementary PWM mode is not selected.* BF[1:0] - - - - - - UT4AE DT4AE UT4BE DT4BE ITA3AE ITA4VE ITB3AE ITB4VE Bit Bit Name Initial Value R/W Description 15, 14 BF[1:0] 00 R/W TADCOBRA_4/TADCOBRB_4 Transfer Timing Select Select the timing for transferring data from TADCOBRA_4 and TADCOBRB_4 to TADCORA_4 and TADCORB_4. For details, see table 11.29. 13 to 8 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

7 UT4AE 0 R/W Up-Count TRG4AN Enable

Enables or disables A/D converter start requests (TRG4AN) during TCNT_4 up-count operation. 0: A/D converter start requests (TRG4AN) disabled during TCNT_4 up-count operation 1: A/D converter start requests (TRG4AN) enabled during TCNT_4 up-count operation

6 DT4AE 0 * R/W Down-Count TRG4AN Enable

Enables or disables A/D converter start requests (TRG4AN) during TCNT_4 down-count operation. 0: A/D converter start requests (TRG4AN) disabled during TCNT_4 down-count operation 1: A/D converter start requests (TRG4AN) enabled during TCNT_4 down-count operation

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 484 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description

5 UT4BE 0 R/W Up-Count TRG4BN Enable

Enables or disables A/D converter start requests (TRG4BN) during TCNT_4 up-count operation. 0: A/D converter start requests (TRG4BN) disabled during TCNT_4 up-count operation 1: A/D converter start requests (TRG4BN) enabled during TCNT_4 up-count operation

4 DT4BE 0 * R/W Down-Count TRG4BN Enable

Enables or disables A/D converter start requests (TRG4BN) during TCNT_4 down-count operation. 0: A/D converter start requests (TRG4BN) disabled during TCNT_4 down-count operation 1: A/D converter start requests (TRG4BN) enabled during TCNT_4 down-count operation

3 ITA3AE 0 * R/W TGIA_3 Interrupt Skipping Link Enable

Select whether to link A/D converter start requests (TRG4AN) with TGIA_3 interrupt skipping operation. 0: Does not link with TGIA_3 interrupt skipping 1: Links with TGIA_3 interrupt skipping

2 ITA4VE 0 * R/W TCIV_4 Interrupt Skipping Link Enable

Select whether to link A/D converter start requests (TRG4AN) with TCIV_4 interrupt skipping operation. 0: Does not link with TCIV_4 interrupt skipping 1: Links with TCIV_4 interrupt skipping

1 ITB3AE 0 * R/W TGIA_3 Interrupt Skipping Link Enable

Select whether to link A/D converter start requests (TRG4BN) with TGIA_3 interrupt skipping operation. 0: Does not link with TGIA_3 interrupt skipping 1: Links with TGIA_3 interrupt skipping

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 485 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description

0 ITB4VE 0 * R/W TCIV_4 Interrupt Skipping Link Enable

Select whether to link A/D converter start requests (TRG4BN) with TCIV_4 interrupt skipping operation. 0: Does not link with TCIV_4 interrupt skipping 1: Links with TCIV_4 interrupt skipping Notes: 1. TADCR must not be accessed in eight bits; it should always be accessed in 16 bits. 2. When interrupt skipping is disabled (the T3AEN and T4VEN bits in the timer interrupt skipping set register (TITCR) are cleared to 0 or the skipping count set bits (3ACOR and 4VCOR) in TITCR are cleared to 0), do not link A/D converter start requests with interrupt skipping operation (clear the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in the timer A/D converter start request control register (TADCR) to 0). 3. If link with interrupt skipping is enabled while interrupt skipping is disabled, A/D converter start requests will not be issued. * Do not set to 1 when complementary PWM mode is not selected. Table 11.29 Setting of Transfer Timing by BF1 and BF0 Bits Bit 7 Bit 6 BF1 BF0 Description 0 0 Does not transfer data from the cycle set buffer register to the cycle set register. 0 1 Transfers data from the cycle set buffer register to the cycle set register at the crest of the TCNT_4 count.* 1 0 Transfers data from the cycle set buffer register to the cycle set register at the trough of the TCNT_4 count.* 1 1 Transfers data from the cycle set buffer register to the cycle set register at the crest and trough of the TCNT_4 count.* Notes: 1. Data is transferred from the cycle set buffer register to the cycle set register when the crest of the TCNT_4 count is reached in complementary PWM mode, when compare match occurs between TCNT_3 and TGRA_3 in reset-synchronized PWM mode, or when compare match occurs between TCNT_4 and TGRA_4 in PWM mode 1 or normal operation mode. 2. These settings are prohibited when complementary PWM mode is not selected.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 486 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

11.3.11 Timer A/D Converter Start Request Cycle Set Registers (TADCORA_4 and

TADCORB_4) TADCORA_4 and TADCORB_4 are 16-bit readable/writable registers. When the TCNT_4 count reaches the value in TADCORA_4 or TADCORB_4, a corresponding A/D converter start request will be issued. TADCORA_4 and TADCORB_4 are initialized to H'FFFF. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 1111111111111111 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: TADCORA_4 and TADCORB_4 must not be accessed in eight bits; they should always be accessed in 16 bits.

11.3.12 Timer A/D Converter Start Request Cycle Set Buffer Registers (TADCOBRA_4

and TADCOBRB_4) TADCOBRA_4 and TADCOBRB_4 are 16-bit readable/writable registers. When the crest or trough of the TCNT_4 count is reached, these register values are transferred to TADCORA_4 and TADCORB_4, respectively. TADCOBRA_4 and TADCOBRB_4 are initialized to H'FFFF. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 1111111111111111 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: TADCOBRA_4 and TADCOBRB_4 must not be accessed in eight bits; they should always be accessed in 16 bits.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 487 of 1560 Mar 18, 2011 SH7080 Group

11.3.13 Timer Counter (TCNT)

The TCNT counters are 16-bit readable/writable counters. The MTU2 has eight TCNT counters, one each for channels 0 to 4 and three (TCNTU_5, TCNTV_5, and TCNTW_5) for channel 5. The TCNT counters are initialized to H'0000 by a reset. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: The TCNT counters must not be accessed in eight bits; they should always be accessed in 16 bits.

11.3.14 Timer General Register (TGR)

The TGR registers are 16-bit readable/writable registers. The MTU2 has 21 TGR registers, six for channel 0, two each for channels 1 and 2, four each for channels 3 and 4, and three for channel 5. TGRA, TGRB, TGRC, and TGRD function as either output compare or input capture registers. TGRC and TGRD for channels 0, 3, and 4 can also be designated for operation as buffer registers. TGR buffer register combinations are TGRA and TGRC, and TGRB and TGRD. TGRE_0 and TGRF_0 function as compare registers. When the TCNT_0 count matches the TGRE_0 value, an A/D converter start request can be issued. TGRF can also be designated for operation as a buffer register. TGR buffer register combination is TGRE and TGRF. TGRU_5, TGRV_5, and TGRW_5 function as compare match, input capture, or external pulse width measurement registers. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 1111111111111111 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: The TGR registers must not be accessed in eight bits; they should always be accessed in 16 bits. TGR registers are initialized to H'FFFF .

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 488 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

11.3.15 Timer Start Register (TSTR)

TSTR is an 8-bit readable/writable register that selects operation/stoppage of TCNT for channels 0 to 4. TSTR_5 is an 8-bit readable/writable register that selects operation/stoppage of TCNTU_5, TCNTV_5, and TCNTW_5 for channel 5. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter.

• TSTR Bit: Initial value: R/W: 7654321 0 00000000 R/W R/W R R R R/W R/W R/W CST4 CST3 - - - CST2 CST1 CST0 Bit Bit Name Initial Value R/W Description

7 CST4 0 R/W

6 CST3 0 R/W

These bits select operation or stoppage for TCNT. If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: TCNT_4 and TCNT_3 count operation is stopped 1: TCNT_4 and TCNT_3 performs count operation 5 to 3 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

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2 CST2 0 R/W

1 CST1 0 R/W

0 CST0 0 R/W

These bits select operation or stoppage for TCNT. If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: TCNT_2 to TCNT_0 count operation is stopped 1: TCNT_2 to TCNT_0 performs count operation

• TSTR_5 Bit: Initial value: R/W: 7654321 0 00000000 R R R R R R/W R/W R/W - - - - - CSTU5 CSTV5 CSTW5 Bit Bit Name Initial Value R/W Description 7 to 3 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

2 CSTU5 0 R/W Counter Start U5

Selects operation or stoppage for TCNTU_5. 0: TCNTU_5 count operation is stopped 1: TCNTU_5 performs count operation

1 CSTV5 0 R/W Counter Start V5

Selects operation or stoppage for TCNTV_5. 0: TCNTV_5 count operation is stopped 1: TCNTV_5 performs count operation

0 CSTW5 0 R/W Counter Start W5

Selects operation or stoppage for TCNTW_5. 0: TCNTW_5 count operation is stopped 1: TCNTW_5 performs count operation

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 490 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

11.3.16 Timer Synchronous Register (TSYR)

TSYR is an 8-bit readable/writable register that selects independent operation or synchronous operation for the channel 0 to 4 TCNT counters. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. Bit: Initial value: R/W: 7654321 0 00000000 R/W R/W R R R R/W R/W R/W SYNC4 SYNC3 - - - SYNC2 SYNC1 SYNC0 Bit Bit Name Initial Value R/W Description

7 SYNC4 0 R/W

6 SYNC3 0 R/W

Timer Synchronous operation 4 and 3 These bits are used to select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, the TCNT synchronous presetting of multiple channels, and synchronous clearing by counter clearing on another channel, are possible. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing source must also be set by means of bits CCLR0 to CCLR2 in TCR. 0: TCNT_4 and TCNT_3 operate independently (TCNT presetting/clearing is unrelated to other channels) 1: TCNT_4 and TCNT_3 performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible 5 to 3 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 491 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description

2 SYNC2 0 R/W

1 SYNC1 0 R/W

0 SYNC0 0 R/W

Timer Synchronous operation 2 to 0 These bits are used to select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, the TCNT synchronous presetting of multiple channels, and synchronous clearing by counter clearing on another channel, are possible. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing source must also be set by means of bits CCLR0 to CCLR2 in TCR. 0: TCNT_2 to TCNT_0 operates independently (TCNT presetting /clearing is unrelated to other channels) 1: TCNT_2 to TCNT_0 performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 492 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

11.3.17 Timer Counter Synchronous Start Register (TCSYSTR)

TCSYSTR is an 8-bit readable/writable register that specifies synchronous start of the MTU2 and MTU2S counters. Note that the MTU2S does not have TCSYSTR. Bit: Initial value: R/W: 7654321 0 00000000 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R/(W) * R/(W)* Note: Only 1 can be written to set the register.* SCH0 SCH1 SCH2 SCH3 SCH4 - SCH3S SCH4S Bit Bit Name Initial Value R/W Description

7 SCH0 0 R/(W) * Synchronous Start

Controls synchronous start of TCNT_0 in the MTU2. 0: Does not specify synchronous start for TCNT_0 in the MTU2 1: Specifies synchronous start for TCNT_0 in the MTU2 [Clearing condition]

• When 1 is set to the CST0 bit of TSTR in MTU2 while SCH0 = 1

6 SCH1 0 R/(W) * Synchronous Start

Controls synchronous start of TCNT_1 in the MTU2. 0: Does not specify synchronous start for TCNT_1 in the MTU2 1: Specifies synchronous start for TCNT_1 in the MTU2 [Clearing condition]

• When 1 is set to the CST1 bit of TSTR in MTU2 while SCH1 = 1

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 493 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description

5 SCH2 0 R/(W) * Synchronous Start

Controls synchronous start of TCNT_2 in the MTU2. 0: Does not specify synchronous start for TCNT_2 in the MTU2 1: Specifies synchronous start for TCNT_2 in the MTU2 [Clearing condition]

• When 1 is set to the CST2 bit of TSTR in MTU2 while SCH2 = 1

4 SCH3 0 R/(W) * Synchronous Start

Controls synchronous start of TCNT_3 in the MTU2. 0: Does not specify synchronous start for TCNT_3 in the MTU2 1: Specifies synchronous start for TCNT_3 in the MTU2 [Clearing condition]

• When 1 is set to the CST3 bit of TSTR in MTU2 while SCH3 = 1

3 SCH4 0 R/(W) * Synchronous Start

Controls synchronous start of TCNT_4 in the MTU2. 0: Does not specify synchronous start for TCNT_4 in the MTU2 1: Specifies synchronous start for TCNT_4 in the MTU2 [Clearing condition]

• When 1 is set to the CST4 bit of TSTR in MTU2 while SCH4 = 1 2 — 0 R Reserved This bit is always read as 0. The write value should always be 0.

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1 SCH3S 0 R/(W) * Synchronous Start

Controls synchronous start of TCNT_3S in the MTU2S. 0: Does not specify synchronous start for TCNT_3S in the MTU2S 1: Specifies synchronous start for TCNT_3S in the MTU2S [Clearing condition]

• When 1 is set to the CST3 bit of TSTRS in MTU2S while SCH3S = 1

0 SCH4S 0 R/(W) * Synchronous Start

Controls synchronous start of TCNT_4S in the MTU2S. 0: Does not specify synchronous start for TCNT_4S in the MTU2S 1: Specifies synchronous start for TCNT_4S in the MTU2S [Clearing condition]

• When 1 is set to the CST4 bit of TSTRS in MTU2S while SCH4S = 1 Note: * Only 1 can be written to set the register.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 495 of 1560 Mar 18, 2011 SH7080 Group

11.3.18 Timer Read/Write Enable Register (TRWER)

TRWER is an 8-bit readable/writable register that enables or disables access to the registers and counters which have write-protection capability against accidental modification in channels 3 and Bit: Initial value: R/W: 7654321 0 00000001 RRRRRRR R / W Bit Bit Name Initial Value R/W Description 7 to 1 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

0 RWE 1 R/W Read/Write Enable

Enables or disables access to the registers which have write-protection capability against accidental modification. 0: Disables read/write access to the registers 1: Enables read/write access to the registers [Clearing condition]

• When 0 is written to the RWE bit after reading RWE = 1
• Registers and counters having write-protection capability against accidental modification 22 registers: TCR_3, TCR_4, TMDR_3, TMDR_4, TIORH_3, TIORH_4, TIORL_3, TIORL_4, TIER_3, TIER_4, TGRA_3, TGRA_4, TGRB_3, TGRB_4, TOER, TOCR1, TOCR2, TGCR, TCDR, TDDR, TCNT_3, and TCNT4.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 496 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

11.3.19 Timer Output Master Enable Register (TOER)

TOER is an 8-bit readable/writable register that enables/disables output settings for output pins TIOC4D, TIOC4C, TIOC3D, TIOC4B, TIOC4A, and TIOC3B. These pins do not output correctly if the TOER bits have not been set. Set TOER of CH3 and CH4 prior to setting TIOR of CH3 and CH4. Bit: Initial value: R/W: 7654321 0 11000000 R R R/W R/W R/W R/W R/W R/W - - OE4D OE4C OE3D OE4B OE4A OE3B Bit Bit Name Initial Value R/W Description 7, 6 — All 1 R Reserved These bits are always read as 1. The write value should always be 1.

5 OE4D 0 R/W Master Enable TIOC4D

This bit enables/disables the TIOC4D pin MTU2 output. 0: MTU2 output is disabled (inactive level)* 1: MTU2 output is enabled

4 OE4C 0 R/W Master Enable TIOC4C

This bit enables/disables the TIOC4C pin MTU2 output. 0: MTU2 output is disabled (inactive level)* 1: MTU2 output is enabled

3 OE3D 0 R/W Master Enable TIOC3D

This bit enables/disables the TIOC3D pin MTU2 output. 0: MTU2 output is disabled (inactive level)* 1: MTU2 output is enabled

2 OE4B 0 R/W Master Enable TIOC4B

This bit enables/disables the TIOC4B pin MTU2 output. 0: MTU2 output is disabled (inactive level)* 1: MTU2 output is enabled

1 OE4A 0 R/W Master Enable TIOC4A

This bit enables/disables the TIOC4A pin MTU2 output. 0: MTU2 output is disabled (inactive level)* 1: MTU2 output is enabled

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0 OE3B 0 R/W Master Enable TIOC3B

This bit enables/disables the TIOC3B pin MTU2 output. 0: MTU2 output is disabled (inactive level)* 1: MTU2 output is enabled Note: * The inactive level is determined by the settings in timer output control registers 1 and 2 (TOCR1 and TOCR2). For details, refer to section 11.3.20, Timer Output Control Register 1 (TOCR1), and section 11.3.21, Timer Output Control Register 2 (TOCR2). Set these bits to 1 to enable MTU2 output in other than complementary PWM or reset- synchronized PWM mode. When these bits are set to 0, low level is output.

11.3.20 Timer Output Control Register 1 (TOCR1)

TOCR1 is an 8-bit readable/writable register that enables/disables PWM synchronized toggle output in complementary PWM mode/reset synchronized PWM mode, and controls output level inversion of PWM output. Bit: Initial value: R/W: 7654321 0 00000000 R R/W R R R/(W) * R/W R/W R/W Note: This bit can be set to 1 only once after a power-on reset. After 1 is written, 0 cannot be written to the bit.* - PSYE - - TOCL TOCS OLSN OLSP Bit Bit Name Initial value R/W Description 7 — 0 R Reserved This bit is always read as 0. The write value should always be 0.

6 PSYE 0 R/W PWM Synchronous Output Enable

This bit selects the enable/disable of toggle output synchronized with the PWM period. 0: Toggle output is disabled 1: Toggle output is enabled 5, 4 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

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3 TOCL 0 R/(W) *

TOC Register Write Protection* This bit selects the enable/disable of write access to the TOCS, OLSN, and OLSP bits in TOCR1. 0: Write access to the TOCS, OLSN, and OLSP bits is enabled 1: Write access to the TOCS, OLSN, and OLSP bits is disabled

2 TOCS 0 R/W TOC Select

This bit selects either the TOCR1 or TOCR2 setting to be used for the output level in complementary PWM mode and reset-synchronized PWM mode. 0: TOCR1 setting is selected 1: TOCR2 setting is selected

1 OLSN 0 R/W Output Level Select N *

This bit selects the reverse phase output level in reset- synchronized PWM mode/complementary PWM mode. See table 11.30.

0 OLSP 0 R/W Output Level Select P *

This bit selects the positive phase output level in reset- synchronized PWM mode/complementary PWM mode. See table 11.31. Notes: 1. This bit can be set to 1 only once after a power on reset. After 1 is written, 0 cannot be written to the bit. 2. Setting the TOCL bit to 1 prevents accidental modification when the CPU goes out of control. 3. Clearing the TOCS0 bit to 0 makes this bit setting valid. Table 11.30 Output Level Select Function Bit 1 Function Compare Match Output OLSN Initial Output Active Level Up Count Down Count

0 High level Low level High level Low level

1 Low level High level Low level High level

Note: The reverse phase waveform initial output value changes to active level after elapse of the dead time after count start.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 499 of 1560 Mar 18, 2011 SH7080 Group Table 11.31 Output Level Select Function Bit 0 Function Compare Match Output OLSP Initial Output Active Level Up Count Down Count

0 High level Low level Low level High level

1 Low level High level High level Low level

Figure 11.2 shows an example of complementary PWM mode output (1 phase) when OLSN = 1, OLSP = 1. TCNT_3 and TCNT_4 values TGRA_3 TGRA_4 TDDR H'0000 Time TCNT_4 TCNT_3 Positive phase output Reverse phase output Active level Compare match output (up count) Initial output Initial output Active level Compare match output (down count) Compare match output (down count) Compare match output (up count) Active level Figure 11.2 Complementary PWM Mode Output Level Example

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 500 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

11.3.21 Timer Output Control Register 2 (TOCR2)

TOCR2 is an 8-bit readable/writable register that controls output level inversion of PWM output in complementary PWM mode and reset-synchronized PWM mode. Bit: Initial value: R/W: 7654321 0 00000000 R/W R/W R/W R/W R/W R/W R/W R/W BF[1:0] OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P Bit Bit Name Initial value R/W Description 7, 6 BF[1:0] 00 R/W TOLBR Buffer Transfer Timing Select These bits select the timing for transferring data from TOLBR to TOCR2. For details, see table 11.32.

5 OLS3N 0 R/W Output Level Select 3N *

This bit selects the output level on TIOC4D in reset- synchronized PWM mode/complementary PWM mode. See table 11.33.

4 OLS3P 0 R/W Output Level Select 3P *

This bit selects the output level on TIOC4B in reset- synchronized PWM mode/complementary PWM mode. See table 11.34.

3 OLS2N 0 R/W Output Level Select 2N *

This bit selects the output level on TIOC4C in reset- synchronized PWM mode/complementary PWM mode. See table 11.35.

2 OLS2P 0 R/W Output Level Select 2P *

This bit selects the output level on TIOC4A in reset- synchronized PWM mode/complementary PWM mode. See table 11.36.

1 OLS1N 0 R/W Output Level Select 1N *

This bit selects the output level on TIOC3D in reset- synchronized PWM mode/complementary PWM mode. See table 11.37.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 501 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial value R/W Description

0 OLS1P 0 R/W Output Level Select 1P *

This bit selects the output level on TIOC3B in reset- synchronized PWM mode/complementary PWM mode. See table 11.38. Note: * Setting the TOCS bit in TOCR1 to 1 makes this bit setting valid. Table 11.32 Setting of Bits BF1 and BF0 Bit 7 Bit 6 Description BF1 BF0 Complementary PWM Mode Reset-Synchronized PWM Mode 0 0 Does not transfer data from the buffer register (TOLBR) to TOCR2. Does not transfer data from the buffer register (TOLBR) to TOCR2. 0 1 Transfers data from the buffer register (TOLBR) to TOCR2 at the crest of the TCNT_4 count. Transfers data from the buffer register (TOLBR) to TOCR2 when TCNT_3/TCNT_4 is cleared 1 0 Transfers data from the buffer register (TOLBR) to TOCR2 at the trough of the TCNT_4 count. Setting prohibited 1 1 Transfers data from the buffer register (TOLBR) to TOCR2 at the crest and trough of the TCNT_4 count. Setting prohibited Table 11.33 TIOC4D Output Level Select Function Bit 5 Function Compare Match Output OLS3N Initial Output Active Level Up Count Down Count Note: The reverse phase waveform initial output value changes to the active level after elapse of the dead time after count start.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 502 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 11.34 TIOC4B Output Level Select Function Bit 4 Function Compare Match Output OLS3P Initial Output Active Level Up Count Down Count Table 11.35 TIOC4C Output Level Select Function Bit 3 Function Compare Match Output OLS2N Initial Output Active Level Up Count Down Count Note: The reverse phase waveform initial output value changes to the active level after elapse of the dead time after count start. Table 11.36 TIOC4A Output Level Select Function Bit 2 Function Compare Match Output OLS2P Initial Output Active Level Up Count Down Count Table 11.37 TIOC3D Output Level Select Function Bit 1 Function Compare Match Output OLS1N Initial Output Active Level Up Count Down Count Note: The reverse phase waveform initial output value changes to the active level after elapse of the dead time after count start.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 503 of 1560 Mar 18, 2011 SH7080 Group Table 11.38 TIOC4B Output Level Select Function Bit 0 Function Compare Match Output OLS1P Initial Output Active Level Up Count Down Count

11.3.22 Timer Output Level Buffer Register (TOLBR)

TOLBR is an 8-bit readable/writable register that functions as a buffer for TOCR2 and specifies the PWM output level in complementary PWM mode and reset-synchronized PWM mode. Bit: Initial value: R/W: 7654321 0 00000000 R R R/W R/W R/W R/W R/W R/W - - OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P Bit Bit Name Initial value R/W Description 7, 6 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

5 OLS3N 0 R/W Specifies the buffer value to be transferred to the

OLS3N bit in TOCR2.

4 OLS3P 0 R/W Specifies the buffer value to be transferred to the

OLS3P bit in TOCR2.

3 OLS2N 0 R/W Specifies the buffer value to be transferred to the

OLS2N bit in TOCR2.

2 OLS2P 0 R/W Specifies the buffer value to be transferred to the

OLS2P bit in TOCR2.

1 OLS1N 0 R/W Specifies the buffer value to be transferred to the

OLS1N bit in TOCR2.

0 OLS1P 0 R/W Specifies the buffer value to be transferred to the

OLS1P bit in TOCR2.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 504 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Figure 11.3 shows an example of the PWM output level setting procedure in buffer operation. Set bit TOCS Set TOCR2 Set TOLBR [1] [2] [3] [1] Set bit TOCS in TOCR1 to 1 to enable the TOCR2 setting. [2] Use bits BF1 and BF0 in TOCR2 to select the TOLBR buffer transfer timing. Use bits OLS3N to OLS1N and OLS3P to OLS1P to specify the PWM output levels. [3] The TOLBR initial setting must be the same value as specified in bits OLS3N to OLS1N and OLS3P to OLS1P in TOCR2. Figure 11.3 PWM Output Level Setting Procedure in Buffer Operation

11.3.23 Timer Gate Control Register (TGCR)

TGCR is an 8-bit readable/writable register that controls the waveform output necessary for brushless DC motor control in reset-synchronized PWM mode/complementary PWM mode. These register settings are ineffective for anything other than complementary PWM mode/reset- synchronized PWM mode. Bit: Initial value: R/W: 7654321 0 10000000 R R/W R/W R/W R/W R/W R/W R/W -B D C N PF B * WF VF UF Bit Bit Name Initial value R/W Description 7 — 1 R Reserved This bit is always read as 1. The write value should always be 1.

6 BDC 0 R/W Brushless DC Motor

This bit selects whether to make the functions of this register (TGCR) effective or ineffective. 0: Ordinary output 1: Functions of this register are made effective

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 505 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial value R/W Description

5 N 0 R/W Reverse Phase Output (N) Control

This bit selects whether the level output or the reset- synchronized PWM/complementary PWM output while the reverse pins (TIOC3D, TIOC4C, and TIOC4D) are output. 0: Level output 1: Reset synchronized PWM/complementary PWM output

4 P 0 R/W Positive Phase Output (P) Control

This bit selects whether the level output or the reset- synchronized PWM/complementary PWM output while the positive pin (TIOC3B, TIOC4A, and TIOC4B) are output. 0: Level output 1: Reset synchronized PWM/complementary PWM output

3 FB * 0 R/W External Feedback Signal Enable

This bit selects whether the switching of the output of the positive/reverse phase is carried out automatically with the MTU2/channel 0 TGRA, TGRB, TGRC input capture signals or by writing 0 or 1 to bits 2 to 0 in TGCR. 0: Output switching is external input (Input sources are channel 0 TGRA, TGRB, TGRC input capture signal) 1: Output switching is carried out by software (TGCR's UF, VF, WF settings).

2 WF 0 R/W

1 VF 0 R/W

0 UF 0 R/W

Output Phase Switch 2 to 0 These bits set the positive phase/negative phase output phase on or off state. The setting of these bits is valid only when the FB bit in this register is set to 1. In this case, the setting of bits 2 to 0 is a substitute for external input. See table 11.39. Note: * When the MTU2S is used to set the BDC bit to 1, do not set the FB bit to 0.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 506 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 11.39 Output level Select Function Function Bit 2 Bit 1 Bit 0 TIOC3B TIOC4A TIOC4B TIOC3D TIOC4C TIOC4D WF VF UF U Phase V Phase W Phase U Phase V Phase W Phase 0 0 0 OFF OFF OFF OFF OFF OFF

1 ON OFF OFF OFF OFF ON

1 OFF ON OFF OFF OFF ON

1 0 0 OFF OFF ON OFF ON OFF

1 ON OFF OFF OFF ON OFF

1 OFF OFF OFF OFF OFF OFF

11.3.24 Timer Subcounter (TCNTS)

TCNTS is a 16-bit read-only counter that is used only in complementary PWM mode. The initial value of TCNTS is H'0000. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRRRRRRRRRRRRRR Note: Accessing the TCNTS in 8-bit units is prohibited. Always access in 16-bit units.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 507 of 1560 Mar 18, 2011 SH7080 Group

11.3.25 Timer Dead Time Data Register (TDDR)

TDDR is a 16-bit register, used only in complementary PWM mode, that specifies the TCNT_3 and TCNT_4 counter offset values. In complementary PWM mode, when the TCNT_3 and TCNT_4 counters are cleared and then restarted, the TDDR register value is loaded into the TCNT_3 counter and the count operation starts. The initial value of TDDR is H'FFFF. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 1111111111111111 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: Accessing the TDDR in 8-bit units is prohibited. Always access in 16-bit units.

11.3.26 Timer Cycle Data Register (TCDR)

TCDR is a 16-bit register used only in complementary PWM mode. Set half the PWM carrier sync value as the TCDR register value. This register is constantly compared with the TCNTS counter in complementary PWM mode, and when a match occurs, the TCNTS counter switches direction (decrement to increment). The initial value of TCDR is H'FFFF. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 1111111111111111 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: Accessing the TCDR in 8-bit units is prohibited. Always access in 16-bit units.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 508 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

11.3.27 Timer Cycle Buffer Register (TCBR)

TCBR is a 16-bit register used only in complementary PWM mode. It functions as a buffer register for the TCDR register. The TCBR register values are transferred to the TCDR register with the transfer timing set in the TMDR register. The initial value of TCBR is H'FFFF. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 1111111111111111 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: Accessing the TCBR in 8-bit units is prohibited. Always access in 16-bit units.

11.3.28 Timer Interrupt Skipping Set Register (TITCR)

TITCR is an 8-bit readable/writable register that enables or disables interrupt skipping and specifies the interrupt skipping count. The MTU2 has one TITCR. Bit: Initial value: R/W: 7654321 0 00000000 R/W R/W R/W R/W R/W R/W R/W R/W T3AEN 3ACOR[2:0] T4VEN 4VCOR[2:0] Bit Bit Name Initial value R/W Description

7 T3AEN 0 R/W T3AEN

Enables or disables TGIA_3 interrupt skipping. 0: TGIA_3 interrupt skipping disabled 1: TGIA_3 interrupt skipping enabled 6 to 4 3ACOR[2:0] 000 R/W These bits specify the TGIA_3 interrupt skipping count within the range from 0 to 7.* For details, see table 11.40.

3 T4VEN 0 R/W T4VEN

Enables or disables TCIV_4 interrupt skipping. 0: TCIV_4 interrupt skipping disabled 1: TCIV_4 interrupt skipping enabled

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 509 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial value R/W Description 2 to 0 4VCOR[2:0] 000 R/W These bits specify the TCIV_4 interrupt skipping count within the range from 0 to 7.* For details, see table 11.41. Note: * When 0 is specified for the interrupt skipping count, no interrupt skipping will be performed. Before changing the interrupt skipping count, be sure to clear the T3AEN and T4VEN bits to 0 to clear the skipping counter (TITCNT). Table 11.40 Setting of Interrupt Skipping Count by Bits 3ACOR2 to 3ACOR0 Bit 6 Bit 5 Bit 4 3ACOR2 3ACOR1 3ACOR0 Description 0 0 0 Does not skip TGIA_3 interrupts. 0 0 1 Sets the TGIA_3 interrupt skipping count to 1. 0 1 0 Sets the TGIA_3 interrupt skipping count to 2. 0 1 1 Sets the TGIA_3 interrupt skipping count to 3. 1 0 0 Sets the TGIA_3 interrupt skipping count to 4. 1 0 1 Sets the TGIA_3 interrupt skipping count to 5. 1 1 0 Sets the TGIA_3 interrupt skipping count to 6. 1 1 1 Sets the TGIA_3 interrupt skipping count to 7. Table 11.41 Setting of Interrupt Skipping Count by Bits 4VCOR2 to 4VCOR0 Bit 2 Bit 1 Bit 0 4VCOR2 4VCOR1 4VCOR0 Description 0 0 0 Does not skip TCIV_4 interrupts. 0 0 1 Sets the TCIV_4 interrupt skipping count to 1. 0 1 0 Sets the TCIV_4 interrupt skipping count to 2. 0 1 1 Sets the TCIV_4 interrupt skipping count to 3. 1 0 0 Sets the TCIV_4 interrupt skipping count to 4. 1 0 1 Sets the TCIV_4 interrupt skipping count to 5. 1 1 0 Sets the TCIV_4 interrupt skipping count to 6. 1 1 1 Sets the TCIV_4 interrupt skipping count to 7.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 510 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

11.3.29 Timer Interrupt Skipping Counter (TITCNT)

TITCNT is an 8-bit readable/writable counter. The MTU2 has one TITCNT. TITCNT retains its value even after stopping the count operation of TCNT_3 and TCNT_4. Bit: Initial value: R/W: 7654321 0 00000000 RRRRRRRR - 3ACNT[2:0] - 4VCNT[2:0] Bit Bit Name Initial Value R/W Description 7 — 0 R Reserved This bit is always read as 0. 6 to 4 3ACNT[2:0] 000 R TGIA_3 Interrupt Counter While the T3AEN bit in TITCR is set to 1, the count in these bits is incremented every time a TGIA_3 interrupt occurs. [Clearing conditions]

• When the 3ACNT2 to 3ACNT0 value in TITCNT matches the 3ACOR2 to 3ACOR0 value in TITCR
• When the T3AEN bit in TITCR is cleared to 0
• When the 3ACOR2 to 3ACOR0 bits in TITCR are cleared to 0 3 — 0 R Reserved This bit is always read as 0. 2 to 0 4VCNT[2:0] 000 R TCIV_4 Interrupt Counter While the T4VEN bit in TITCR is set to 1, the count in these bits is incremented every time a TCIV_4 interrupt occurs. [Clearing conditions]
• When the 4VCNT2 to 4VCNT0 value in TITCNT matches the 4VCOR2 to 4VCOR2 value in TITCR
• When the T4VEN bit in TITCR is cleared to 0
• When the 4VCOR2 to 4VCOR2 bits in TITCR are cleared to 0 Note: To clear the TITCNT, clear the T3AEN and T4VEN bits in TITCR to 0.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 511 of 1560 Mar 18, 2011 SH7080 Group

11.3.30 Timer Buffer Transfer Set Register (TBTER)

TBTER is an 8-bit readable/writable register that enables or disables transfer from the buffer registers* used in complementary PWM mode to the temporary registers and specifies whether to link the transfer with interrupt skipping operation. The MTU2 has one TBTER. Bit: Initial value: R/W: 7654321 0 00000000 RRRRRR R / W R / W Bit Bit Name Initial Value R/W Description 7 to 2 — All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 BTE[1:0] 00 R/W These bits enable or disable transfer from the buffer registers* used in complementary PWM mode to the temporary registers and specify whether to link the transfer with interrupt skipping operation. For details, see table 11.42. Note: * Applicable buffer registers: TGRC_3, TGRD_3, TGRC_4, TGRD_4, and TCBR

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 512 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 11.42 Setting of Bits BTE1 and BTE0 Bit 1 Bit 0 BTE1 BTE0 Description 0 0 Enables transfer from the buffer registers to the temporary registers * and does not link the transfer with interrupt skipping operation. 0 1 Disables transfer from the buffer registers to the temporary registers. 1 0 Links transfer from the buffer registers to the temporary registers with interrupt skipping operation.* 1 1 Setting prohibited Notes: 1. Data is transferred according to the MD3 to MD0 bit setting in TMDR. For details, refer to section 11.4.8, Complementary PWM Mode. 2. When interrupt skipping is disabled (the T3AEN and T4VEN bits are cleared to 0 in the timer interrupt skipping set register (TITCR) or the skipping count set bits (3ACOR and 4VCOR) in TITCR are cleared to 0)), be sure to disable link of buffer transfer with interrupt skipping (clear the BTE1 bit in the timer buffer transfer set register (TBTER) to 0). If link with interrupt skipping is enabled while interrupt skipping is disabled, buffer transfer will not be performed.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 513 of 1560 Mar 18, 2011 SH7080 Group

11.3.31 Timer Dead Time Enable Register (TDER)

TDER is an 8-bit readable/writable register that controls dead time generation in complementary PWM mode. The MTU2 has one TDER in channel 3. TDER must be modified only while TCNT stops. Bit: Initial value: R/W: 7654321 0 00000001 RRRRRRR R / ( W ) Bit Bit Name Initial Value R/W Description 7 to 1 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

0 TDER 1 R/(W) Dead Time Enable

Specifies whether to generate dead time. 0: Does not generate dead time 1: Generates dead time* [Clearing condition]

• When 0 is written to TDER after reading TDER = 1 Note: * TDDR must be set to 1 or a larger value.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 514 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

11.3.32 Timer Waveform Control Register (TWCR)

TWCR is an 8-bit readable/writable register that controls the waveform when synchronous counter clearing occurs in TCNT_3 and TCNT_4 in complementary PWM mode and specifies whether to clear the counters at TGRA_3 compare match. The CCE bit and WRE bit in TWCR must be modified only while TCNT stops. Bit: Initial value: R/W: 7654321 0 Note: Do not set to 1 when complementary PWM mode is not selected.* 0* 0000000 R/(W) R R R R R R/(W) R/(W) C C E ----- S C C W R E Bit Bit Name Initial Value R/W Description

7 CCE 0 * R/(W) Compare Match Clear Enable

Specifies whether to clear counters at TGRA_3 compare match in complementary PWM mode. 0: Does not clear counters at TGRA_3 compare match 1: Clears counters at TGRA_3 compare match [Setting condition]

• When 1 is written to CCE after reading CCE = 0 6 to 2 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 515 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description

1 SCC 0 R/(W) Synchronous Clearing Control

Specifies whether to clear TCNT_3 and TCNT_4 in the MTU2S when synchronous counter clearing between the MTU2 and MTU2S occurs in complementary PWM mode. When using this control, place the MTU2S in complementary PWM mode. When modifying the SCC bit while the counters are operating, do not modify the CCE or WRE bits. Counter clearing synchronized with the MTU2 is disabled by the SCC bit setting only when synchronous clearing occurs outside the Tb interval at the trough. When synchronous clearing occurs in the Tb interval at the trough including the period immediately after TCNT_3 and TCNT_4 start operation, TCNT_3 and TCNT_4 in the MTU2S are cleared. For the Tb interval at the trough in complementary PWM mode, see figure 11.40. In the MTU2, this bit is reserved. It is always read as 0 and the write value should always be 0. 0: Enables clearing of TCNT_3 and TCNT_4 in the MTU2S by MTU2–MTU2S synchronous clearing operation 1: Disables clearing of TCNT_3 and TCNT_4 in the MTU2S by MTU2–MTU2S synchronous clearing operation [Setting condition]

• When 1 is written to SCC after reading SCC = 0

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 516 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description

0 WRE 0 R/(W) Initial Output Suppression Enable

Selects the waveform output when synchronous counter clearing occurs in complementary PWM mode. The initial output is suppressed only when synchronous clearing occurs within the Tb interval at the trough in complementary PWM mode. When synchronous clearing occurs outside this interval, the initial value specified in TOCR is output regardless of the WRE bit setting. The initial value is also output when synchronous clearing occurs in the Tb interval at the trough immediately after TCNT_3 and TCNT_4 start operation. For the Tb interval at the trough in complementary PWM mode, see figure 11.40. 0: Outputs the initial value specified in TOCR 1: Suppresses initial output [Setting condition]

• When 1 is written to WRE after reading WRE = 0 Note: * Do not set to 1 when complementary PWM mode is not selected.

11.3.33 Bus Master Interface

The timer counters (TCNT), general registers (TGR), timer subcounter (TCNTS), timer cycle buffer register (TCBR), timer dead time data register (TDDR), timer cycle data register (TCDR), timer A/D converter start request control register (TADCR), timer A/D converter start request cycle set registers (TADCOR), and timer A/D converter start request cycle set buffer registers (TADCOBR) are 16-bit registers. A 16-bit data bus to the bus master enables 16-bit read/writes. 8- bit read/write is not possible. Always access in 16-bit units. All registers other than the above registers are 8-bit registers. These are connected to the CPU by a 16-bit data bus, so 16-bit read/writes and 8-bit read/writes are both possible.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 517 of 1560 Mar 18, 2011 SH7080 Group

11.4 Operation

11.4.1 Basic Functions

Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, cycle counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Always select MTU2 external pins set function using the pin function controller (PFC). Counter Operation: When one of bits CST0 to CST4 in TSTR or bits CSTU5, CSTV5, and CSTW5 in TSTR_5 is set to 1, the TCNT counter for the corresponding channel begins counting. TCNT can operate as a free-running counter, periodic counter, for example. 1. Example of Count Operation Setting Procedure Figure 11.4 shows an example of the count operation setting procedure. Operation selection Select counter clock Periodic counter Select counter clearing source Select output compare register Set period Free-running counter Start count operation <Free-running counter> <Periodic counter> Start count operation [1] [2] [3] [4] [5] [5] [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] For periodic counter operation, select the TGR to be used as the TCNT clearing source with bits CCLR2 to CCLR0 in TCR. [3] Designate the TGR selected in [2] as an output compare register by means of TIOR. [4] Set the periodic counter cycle in the TGR selected in [2]. [5] Set the CST bit in TSTR to 1 to start the counter operation. Figure 11.4 Example of Counter Operation Setting Procedure

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 523 of 1560 Mar 18, 2011 SH7080 Group

11.4.2 Synchronous Operation

In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 4 can all be designated for synchronous operation. Channel 5 cannot be used for synchronous operation. Example of Synchronous Operation Setting Procedure: Figure 11.12 shows an example of the synchronous operation setting procedure. No Yes Set synchronous operation <Synchronous presetting> <Counter clearing> <Synchronous clearing> Clearing source generation channel? Select counter clearing source Start count Set synchronous counter clearing Start count [1] [3] [5] [4] [5] [2] Synchronous operation selection [1] Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation. [2] When the TCNT counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other TCNT counters. [3] Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc. [4] Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source. [5] Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation. Set TCNT Synchronous presetting Synchronous clearing Figure 11.12 Example of Synchronous Operation Setting Procedure

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 524 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Example of Synchronous Operation: Figure 11.13 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. Three-phase PWM waveforms are output from pins TIOC0A, TIOC1A, and TIOC2A. At this time, synchronous presetting, and synchronous clearing by TGRB_0 compare match, are performed for channel 0 to 2 TCNT counters, and the data set in TGRB_0 is used as the PWM cycle. For details of PWM modes, see section 11.4.5, PWM Modes. TCNT_0 to TCNT_2 values H'0000 TIOC0A TIOC1A TGRB_0 Synchronous clearing by TGRB_0 compare match TGRA_2 TGRA_1 TGRB_2 TGRA_0 TGRB_1 TIOC2A Time Figure 11.13 Example of Synchronous Operation

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 525 of 1560 Mar 18, 2011 SH7080 Group

11.4.3 Buffer Operation

Buffer operation, provided for channels 0, 3, and 4, enables TGRC and TGRD to be used as buffer registers. In channel 0, TGRF can also be used as a buffer register. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register. Note: TGRE_0 cannot be designated as an input capture register and can only operate as a compare match register. Table 11.43 shows the register combinations used in buffer operation. Table 11.43 Register Combinat ions in Buffer Operation Channel Timer General Re gister Buffer Register

0 TGRA_0 TGRC_0

TGRB_0 TGRD_0 TGRE_0 TGRF_0

3 TGRA_3 TGRC_3

TGRB_3 TGRD_3

4 TGRA_4 TGRC_4

TGRB_4 TGRD_4

• When TGR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. This operation is illustrated in figure 11.14. Buffer register Timer general register TCNTComparator Compare match signal Figure 11.14 Compare Match Buffer Operation

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 529 of 1560 Mar 18, 2011 SH7080 Group TCNT_0 value H'0000 TGRA_0 Time TIOCA TGRC_0 H'0520 H'0520 H'0450 H'0450 H'0200 H'0520H'0450H'0200 H'0200 TGRB_0 TGRA_0 Transfer Figure 11.19 Example of Buffer Operation When TCNT_0 Clearing Is Selected for TGRC_0 to TGRA_0 Transfer Timing

11.4.4 Cascaded Operation

In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 counter clock upon overflow/underflow of TCNT_2 as set in bits TPSC0 to TPSC2 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode. Table 11.44 shows the register combinations used in cascaded operation. Note: When phase counting mode is set for channel 1, the counter clock setting is invalid and the counters operates independently in phase counting mode. Table 11.44 Cascaded Combinations Combination Upper 16 Bits Lower 16 Bits Channels 1 and 2 TCNT_1 TCNT_2 For simultaneous input capture of TCNT_1 and TCNT_2 during cascaded operation, additional input capture input pins can be specified by the input capture control register (TICCR). For input capture in cascade connection, refer to section 11.7.22, Simultaneous Capture of TCNT_1 and TCNT_2 in Cascade Connection.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 530 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 11.45 shows the TICCR setting and input capture input pins. Table 11.45 TICCR Setting and Input Capture Input Pins Target Input Capture TICCR Setting Input Capture Input Pins I2AE bit = 0 (initial value) TIOC1A Input capture from TCNT_1 to TGRA_1 I2AE bit = 1 TIOC1A, TIOC2A I2BE bit = 0 (initial value) TIOC1B Input capture from TCNT_1 to TGRB_1 I2BE bit = 1 TIOC1B, TIOC2B I1AE bit = 0 (initial value) TIOC2A Input capture from TCNT_2 to TGRA_2 I1AE bit = 1 TIOC2A, TIOC1A I1BE bit = 0 (initial value) TIOC2B Input capture from TCNT_2 to TGRB_2 I1BE bit = 1 TIOC2B, TIOC1B Example of Cascaded Operation Setting Procedure: Figure 11.20 shows an example of the setting procedure for cascaded operation. Cascaded operation Set cascading Start count <Cascaded operation> [1] [2] [1] Set bits TPSC2 to TPSC0 in the channel 1 TCR to B'1111 to select TCNT_2 overflow/ underflow counting. [2] Set the CST bit in TSTR for the upper and lower channel to 1 to start the count operation. Figure 11.20 Cascaded Operation Setting Procedure Cascaded Operation Example (a): Figure 11.21 illustrates the operation when TCNT_2 overflow/underflow counting has been set for TCNT_1 and phase counting mode has been designated for channel 2. TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 532 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Cascaded Operation Example (c): Figure 11.23 illustrates the operation when TCNT_1 and TCNT_2 have been cascaded and the I2AE and I1AE bits in TICCR have been set to 1 to include the TIOC2A and TIOC1A pins in the TGRA_1 and TGRA_2 input capture conditions, respectively. In this example, the IOA0 to IOA3 bits in both TIOR_1 and TIOR_2 have selected both the rising and falling edges for the input capture timing. Under these conditions, the ORed result of TIOC1A and TIOC2A input is used for the TGRA_1 and TGRA_2 input capture conditions. TCNT_2 value H'0000 TGRA_1 TGRA_2 Time TIOC1A TIOC2A TCNT_1 H'0514 H'0514 H'0513H'0512 H'0513H'0512 H'C256 H'C256 H'FFFF H'6128 H'6128 H'2064 H'2064 H'9192 H'9192 Figure 11.23 Cascaded Operation Example (c) Cascaded Operation Example (d): Figure 11.24 illustrates the operation when TCNT_1 and TCNT_2 have been cascaded and the I2AE bit in TICCR has been set to 1 to include the TIOC2A pin in the TGRA_1 input capture conditions. In this example, the IOA0 to IOA3 bits in TIOR_1 have selected TGRA_0 compare match or input capture occurrence for the input capture timing while the IOA0 to IOA3 bits in TIOR_2 have selected the TIOC2A rising edge for the input capture timing. Under these conditions, as TIOR_1 has selected TGRA_0 compare match or input capture occurrence for the input capture timing, the TIOC2A edge is not used for TGRA_1 input capture condition although the I2AE bit in TICCR has been set to 1.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 533 of 1560 Mar 18, 2011 SH7080 Group TCNT_2 value H'0000 H'0000 TGRA_1 TGRA_2 Time TIOC1A TIOC2A TCNT_1 H'0513H'0512 H'0513 H'D000 H'FFFF H'D000 TCNT_0 value Time TGRA_0 Compare match between TCNT_0 and TGRA_0 Figure 11.24 Cascaded Operation Example (d)

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 534 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

11.4.5 PWM Modes

In PWM mode, PWM waveforms are output from the output pins. The output level can be selected as 0, 1, or toggle output in response to a compare match of each TGR. TGR registers settings can be used to output a PWM waveform in the range of 0% to 100% duty. Designating TGR compare match as the counter clearing source enables the period to be set in that register. All channels can be designated for PWM mode independently. Synchronous operation is also possible. There are two PWM modes, as described below. 1. PWM mode 1 PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and TGRC with TGRD. The output specified by bits IOA0 to IOA3 and IOC0 to IOC3 in TIOR is output from the TIOCA and TIOCC pins at compare matches A and C, and the output specified by bits IOB0 to IOB3 and IOD0 to IOD3 in TIOR is output at compare matches B and D. The initial output value is the value set in TGRA or TGRC. If the set values of paired TGRs are identical, the output value does not change when a compare match occurs. In PWM mode 1, a maximum 8-phase PWM output is possible. 2. PWM mode 2 PWM output is generated using one TGR as the cycle register and the others as duty registers. The output specified in TIOR is performed by means of compare matches. Upon counter clearing by a synchronization register compare match, the output value of each pin is the initial value set in TIOR. If the set values of the cycle and duty registers are identical, the output value does not change when a compare match occurs. In PWM mode 2, a maximum 8-phase PWM output is possible in combination use with synchronous operation. The correspondence between PWM output pins and registers is shown in table 11.46.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 535 of 1560 Mar 18, 2011 SH7080 Group Table 11.46 PWM Output Registers and Output Pins Output Pins Channel Registers PWM Mode 1 PWM Mode 2 TGRA_0 TIOC0A TGRB_0 TIOC0A TIOC0B TGRC_0 TIOC0C TGRD_0 TIOC0C TIOC0D TGRA_1 TIOC1A 1 TGRB_1 TIOC1A TIOC1B TGRA_2 TIOC2A 2 TGRB_2 TIOC2A TIOC2B TGRA_3 Cannot be set TGRB_3 TIOC3A Cannot be set TGRC_3 Cannot be set TGRD_3 TIOC3C Cannot be set

4 TGRA_4 Cannot be set

TGRB_4 TIOC4A Cannot be set TGRC_4 TIOC4C Cannot be set TGRD_4 Cannot be set Note: In PWM mode 2, PWM output is not possible for the TGR register in which the period is set.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 539 of 1560 Mar 18, 2011 SH7080 Group

11.4.6 Phase Counting Mode

In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1 and 2. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC0 to TPSC2 and bits CKEG0 and CKEG1 in TCR. However, the functions of bits CCLR0 and CCLR1 in TCR, and of TIOR, TIER, and TGR, are valid, and input capture/compare match and interrupt functions can be used. This can be used for two-phase encoder pulse input. If overflow occurs when TCNT is counting up, the TCFV flag in TSR is set; if underflow occurs when TCNT is counting down, the TCFU flag is set. The TCFD bit in TSR is the count direction flag. Reading the TCFD flag reveals whether TCNT is counting up or down. Table 11.47 shows the correspondence between external clock pins and channels. Table 11.47 Phase Counting Mode Clock Input Pins External Clock Pins Channels A-Phase B-Phase When channel 1 is set to phase counting mode TCLKA TCLKB When channel 2 is set to phase counting mode TCLKC TCLKD Example of Phase Counting Mode Setting Procedure: Figure 11.29 shows an example of the phase counting mode setting procedure. Phase counting mode Select phase counting mode Start count <Phase counting mode> [1] [2] [1] Select phase counting mode with bits MD3 to MD0 in TMDR. [2] Set the CST bit in TSTR to 1 to start the count operation. Figure 11.29 Example of Phase Counting Mode Setting Procedure

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 544 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Phase Counting Mode Application Example: Figure 11.34 shows an example in which channel 1 is in phase counting mode, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB. Channel 0 operates with TCNT counter clearing by TGRC_0 compare match; TGRA_0 and TGRC_0 are used for the compare match function and are set with the speed control period and position control period. TGRB_0 is used for input capture, with TGRB_0 and TGRD_0 operating in buffer mode. The channel 1 counter input clock is designated as the TGRB_0 input capture source, and the pulse widths of 2-phase encoder 4-multiplication pulses are detected. TGRA_1 and TGRB_1 for channel 1 are designated for input capture, and channel 0 TGRA_0 and TGRC_0 compare matches are selected as the input capture source and store the up/down-counter values for the control periods. This procedure enables the accurate detection of position and speed.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 545 of 1560 Mar 18, 2011 SH7080 Group TCNT_1 TCNT_0 Channel 1 TGRA_1 (speed period capture) TGRA_0 (speed control period) TGRB_1 (position period capture) TGRC_0 (position control period) TGRB_0 (pulse width capture) TGRD_0 (buffer operation) Channel 0 TCLKA TCLKB Edge detection circuit Figure 11.34 Phase Counting Mode Application Example

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 546 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

11.4.7 Reset-Synchronized PWM Mode

In the reset-synchronized PWM mode, three-phase output of positive and negative PWM waveforms that share a common wave transition point can be obtained by combining channels 3 and 4. When set for reset-synchronized PWM mode, the TIOC3B, TIOC3D, TIOC4A, TIOC4C, TIOC4B, and TIOC4D pins function as PWM output pins and TCNT3 functions as an upcounter. Table 11.52 shows the PWM output pins used. Table 11.53 shows the settings of the registers. Table 11.52 Output Pins for Reset-Synchronized PWM Mode Channel Output Pin Description

3 TIOC3B PWM output pin 1

TIOC3D PWM output pin 1' (negative-phase waveform of PWM output 1)

4 TIOC4A PWM output pin 2

TIOC4C PWM output pin 2' (negative-phase waveform of PWM output 2) TIOC4B PWM output pin 3 TIOC4D PWM output pin 3' (negative-phase waveform of PWM output 3) Table 11.53 Register Settings for Reset-Synchronized PWM Mode Register Description of Setting TCNT_3 Initial setting of H'0000 TCNT_4 Initial setting of H'0000 TGRA_3 Set count cycle for TCNT_3 TGRB_3 Sets the turning point for PWM waveform output by the TIOC3B and TIOC3D pins TGRA_4 Sets the turning point for PWM waveform output by the TIOC4A and TIOC4C pins TGRB_4 Sets the turning point for PWM waveform output by the TIOC4B and TIOC4D pins

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 547 of 1560 Mar 18, 2011 SH7080 Group Procedure for Selecting the Reset-Synchronized PWM Mode: Figure 11.35 shows an example of procedure for selecting the reset synchronized PWM mode. Stop counting Select counter clock and counter clear source Set TGR Reset-synchronized PWM mode Brushless DC motor control setting Set TCNT Enable waveform output Set reset-synchronized PWM mode PWM cycle output enabling, PWM output level setting Start count operation Reset-synchronized PWM mode [1] Clear the CST3 and CST4 bits in the TSTR to 0 to halt the counting of TCNT. The reset-synchronized PWM mode must be set up while TCNT_3 and TCNT_4 are halted. [2] Set bits TPSC2 to TPSC0 and CKEG1 and CKEG0 in the TCR_3 to select the counter clock and clock edge for channel 3. Set bits CCLR2 to CCLR0 in the TCR_3 to select TGRA compare-match as a counter clear source. [3] When performing brushless DC motor control, set bit BDC in the timer gate control register (TGCR) and set the feedback signal input source and output chopping or gate signal direct output. [4] Reset TCNT_3 and TCNT_4 to H'0000. [5] TGRA_3 is the period register. Set the waveform period value in TGRA_3. Set the transition timing of the PWM output waveforms in TGRB_3, TGRA_4, and TGRB_4. Set times within the compare-match range of TCNT_3. X ≤ TGRA_3 (X: set value). [6] Select enabling/disabling of toggle output synchronized with the PMW cycle using bit PSYE in the timer output control register (TOCR1), and set the PWM output level with bits OLSP and OLSN. When specifying the PWM output level by using TOLBR as a buffer for TOCR2, see figure 11.3. [7] Set bits MD3 to MD0 in TMDR_3 to B'1000 to select the reset-synchronized PWM mode. Do not set to TMDR_4. [8] Set the enabling/disabling of the PWM waveform output pin in TOER. [9] Set the port control register and the port I/O register. [10] Set the CST3 bit in the TSTR to 1 to start the count operation. [1] [2] [3] [4] [5] [6] [7] [8] PFC setting [9] [10] Note: The output waveform starts to toggle operation at the point of TCNT_3 = TGRA_3 = X by setting X = TGRA, i.e., cycle = duty. Figure 11.35 Procedure for Selecting Reset-Synchronized PWM Mode

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 548 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Reset-Synchronized PWM Mode Operation: Figure 11.36 shows an example of operation in the reset-synchronized PWM mode. TCNT_3 and TCNT_4 operate as upcounters. The counter is cleared when a TCNT_3 and TGRA_3 compare-match occurs, and then begins incrementing from H'0000. The PWM output pin output toggles with each occurrence of a TGRB_3, TGRA_4, TGRB_4 compare-match, and upon counter clears. TGRA_3 TGRB_3 TGRB_4 H'0000 TGRA_4 TIOC3B TIOC3D TIOC4A TIOC4C TIOC4B TIOC4D Time TCNT_3 and TCNT_4 values Figure 11.36 Reset-Synchronized PWM Mode Operation Example (When TOCR’s OLSN = 1 and OLSP = 1)

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 549 of 1560 Mar 18, 2011 SH7080 Group

11.4.8 Complementary PWM Mode

In the complementary PWM mode, three-phase output of non-overlapping positive and negative PWM waveforms can be obtained by combining channels 3 and 4. PWM waveforms without non- overlapping interval is also available. In complementary PWM mode, TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D pins function as PWM output pins, the TIOC3A pin can be set for toggle output synchronized with the PWM period. TCNT_3 and TCNT_4 function as up/down counters. Table 11.54 shows the PWM output pins used. Table 11.55 shows the settings of the registers used. A function to directly cut off the PWM output by using an external signal is supported as a port function. Table 11.54 Output Pins for Complementary PWM Mode Channel Output Pin Description

3 TIOC3A Toggle output synchronized with PWM period (or I/O port)

TIOC3C I/O port * TIOC3D PWM output pin 1' (non-overlapping negative-phase waveform of PWM output 1; PWM output without non-overlapping interval is also available) TIOC4C PWM output pin 2' (non-overlapping negative-phase waveform of PWM output 2; PWM output without non-overlapping interval is also available) TIOC4D PWM output pin 3' (non-overlapping negative-phase waveform of PWM output 3; PWM output without non-overlapping interval is also available) Note: * Avoid setting the TIOC3C pin as a timer I/O pin in the complementary PWM mode.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 550 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 11.55 Register Settings for Complementary PWM Mode Channel Counter/Register Description Read/Write from CPU

3 TCNT_3 Start of up-count from value set

setting* TGRA_3 Set TCNT_3 upper limit value (1/2 carrier cycle + dead time) Maskable by TRWER setting* TGRB_3 PWM output 1 compare register Maskable by TRWER setting* TGRC_3 TGRA_3 buffer register Always readable/writable TGRD_3 PWM output 1/TGRB_3 buffer register Always readable/writable

4 TCNT_4 Up-count start, initialized to

H'0000 Maskable by TRWER setting* TGRA_4 PWM output 2 compare register Maskable by TRWER setting* TGRB_4 PWM output 3 compare register Maskable by TRWER setting* TGRC_4 PWM output 2/TGRA_4 buffer register Always readable/writable TGRD_4 PWM output 3/TGRB_4 buffer register Always readable/writable Timer dead time data register (TDDR) Set TCNT_4 and TCNT_3 offset value (dead time value) Maskable by TRWER setting* Timer cycle data register (TCDR) Set TCNT_4 upper limit value (1/2 carrier cycle) Maskable by TRWER setting* Timer cycle buffer register (TCBR) TCDR buffer register Always readable/writable Subcounter (TCNTS) Subcounter for dead time generation Read-only Temporary register 1 (TEMP1) PWM output 1/TGRB_3 temporary register Not readable/writable Temporary register 2 (TEMP2) PWM output 2/TGRA_4 temporary register Not readable/writable Temporary register 3 (TEMP3) PWM output 3/TGRB_4 temporary register Not readable/writable Note: * Access can be enabled or disabled according to the setting of bit 0 (RWE) in TRWER (timer read/write enable register).

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 551 of 1560 Mar 18, 2011 SH7080 Group TGRC_3 TDDR TCNT_3 TGRD_3 TGRD_4TGRC_4 TGRB_3 Temp 1 TGRA_4 Temp 2 TGRB_4 Temp 3 TCNTS TCNT_4 TGRA_3 TCDR TCBR Comparator Comparator Match signal Match signal Output controller Output protection circuit PWM cycle output PWM output 1 PWM output 2 PWM output 3 PWM output 4 PWM output 5 PWM output 6 POE0 POE1 POE2 POE3 External cutoff input External cutoff interrupt : Registers that can always be read or written from the CPU : Registers that cannot be read or written from the CPU (except for TCNTS, which can only be read) : Registers that can be read or written from the CPU (but for which access disabling can be set by TRWER) TGRA_3 compare- match interrupt TCNT_4 underflow interrupt Figure 11.37 Block Diagram of Channels 3 and 4 in Complementary PWM Mode

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 552 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Example of Complementary PWM Mode Setting Procedure: An example of the complementary PWM mode setting procedure is shown in figure 11.38. Complementary PWM mode Stop count operation Counter clock, counter clear source selection Brushless DC motor control setting TCNT setting Inter-channel synchronization setting TGR setting Enable/disable dead time generation Start count operation [1] Clear bits CST3 and CST4 in the timer start register (TSTR) to 0, and halt timer counter (TCNT) operation. Perform complementary PWM mode setting when TCNT_3 and TCNT_4 are stopped. [2] Set the same counter clock and clock edge for channels 3 and 4 with bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in the timer control register (TCR). Use bits CCLR2 to CCLR0 to set synchronous clearing only when restarting by a synchronous clear from another channel during complementary PWM mode operation. [3] When performing brushless DC motor control, set bit BDC in the timer gate control register (TGCR) and set the feedback signal input source and output chopping or gate signal direct output. [4] Set the dead time in TCNT_3. Set TCNT_4 to H'0000. [5] Set only when restarting by a synchronous clear from another channel during complementary PWM mode operation. In this case, synchronize the channel generating the synchronous clear with channels 3 and 4 using the timer synchro register (TSYR). [6] Set the output PWM duty in the duty registers (TGRB_3, TGRA_4, TGRB_4) and buffer registers (TGRD_3, TGRC_4, TGRD_4). Set the same initial value in each corresponding TGR. [7] This setting is necessary only when no dead time should be generated. Make appropriate settings in the timer dead time enable register (TDER) so that no dead time is generated. [8] Set the dead time in the dead time register (TDDR), 1/2 the carrier cycle in the carrier cycle data register (TCDR) and carrier cycle buffer register (TCBR), and 1/2 the carrier cycle plus the dead time in TGRA_3 and TGRC_3. When no dead time generation is selected, set 1 in TDDR and 1/2 the carrier cycle + 1 in TGRA_3 and TGRC_3. [9] Select enabling/disabling of toggle output synchronized with the PWM cycle using bit PSYE in the timer output control register 1 (TOCR1), and set the PWM output level with bits OLSP and OLSN. When specifying the PWM output level by using TOLBR as a buffer for TOCR_2, see figure 11.3. [10] Select complementary PWM mode in timer mode register 3 (TMDR_3). Do not set in TMDR_4. [11] Set enabling/disabling of PWM waveform output pin output in the timer output master enable register (TOER). [12] Set the port control register and the port I/O register. [13] Set bits CST3 and CST4 in TSTR to 1 simultaneously to start the count operation. [1] [2] [3] [4] [5] [6] [7] [8] [9] [11] Dead time, carrier cycle setting PWM cycle output enabling, PWM output level setting Complementary PWM mode setting Enable waveform output Start count operation <Complementary PWM mode> [10] PFC setting [12] [13] Figure 11.38 Example of Complementary PWM Mode Setting Procedure

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 553 of 1560 Mar 18, 2011 SH7080 Group Outline of Complementary PWM Mode Operation: In complementary PWM mode, 6-phase PWM output is possible. Figure 11.39 illustrates counter operation in complementary PWM mode, and figure 11.40 shows an example of complementary PWM mode operation. 1. Counter Operation In complementary PWM mode, three counters—TCNT_3, TCNT_4, and TCNTS—perform up/down-count operations. TCNT_3 is automatically initialized to the value set in TDDR when complementary PWM mode is selected and the CST bit in TSTR is 0. When the CST bit is set to 1, TCNT_3 counts up to the value set in TGRA_3, then switches to down-counting when it matches TGRA_3. When the TCNT3 value matches TDDR, the counter switches to up-counting, and the operation is repeated in this way. TCNT_4 is initialized to H'0000. When the CST bit is set to 1, TCNT4 counts up in synchronization with TCNT_3, and switches to down-counting when it matches TCDR. On reaching H'0000, TCNT4 switches to up-counting, and the operation is repeated in this way. TCNTS is a read-only counter. It need not be initialized. When TCNT_3 matches TCDR during TCNT_3 and TCNT_4 up/down-counting, down- counting is started, and when TCNTS matches TCDR, the operation switches to up-counting. When TCNTS matches TGRA_3, it is cleared to H'0000. When TCNT_4 matches TDDR during TCNT_3 and TCNT_4 down-counting, up-counting is started, and when TCNTS matches TDDR, the operation switches to down-counting. When TCNTS reaches H'0000, it is set with the value in TGRA_3. TCNTS is compared with the compare register and temporary register in which the PWM duty is set during the count operation only. Counter value TGRA_3 TCDR TDDR H'0000 TCNT_4 TCNTS TCNT_3 TCNT_3 TCNT_4 TCNTS Time Figure 11.39 Complementary PWM Mode Counter Operation

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 554 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group 2. Register Operation In complementary PWM mode, nine registers are used, comprising compare registers, buffer registers, and temporary registers. Figure 11.40 shows an example of complementary PWM mode operation. The registers which are constantly compared with the counters to perform PWM output are TGRB_3, TGRA_4, and TGRB_4. When these registers match the counter, the value set in bits OLSN and OLSP in the timer output control register (TOCR) is output. The buffer registers for these compare registers are TGRD_3, TGRC_4, and TGRD_4. Between a buffer register and compare register there is a temporary register. The temporary registers cannot be accessed by the CPU. Data in a compare register is changed by writing the new data to the corresponding buffer register. The buffer registers can be read or written at any time. The data written to a buffer register is constantly transferred to the temporary register in the Ta interval. Data is not transferred to the temporary register in the Tb interval. Data written to a buffer register in this interval is transferred to the temporary register at the end of the Tb interval. The value transferred to a temporary register is transferred to the compare register when TCNTS for which the Tb interval ends matches TGRA_3 when counting up, or H'0000 when counting down. The timing for transfer from the temporary register to the compare register can be selected with bits MD3 to MD0 in the timer mode register (TMDR). Figure 11.40 shows an example in which the mode is selected in which the change is made in the trough. In the Tb interval (Tb1 in figure 11.40) in which data transfer to the temporary register is not performed, the temporary register has the same function as the compare register, and is compared with the counter. In this interval, therefore, there are two compare match registers for one-phase output, with the compare register containing the pre-change data, and the temporary register containing the new data. In this interval, the three counters—TCNT_3, TCNT_4, and TCNTS—and two registers—compare register and temporary register—are compared, and PWM output controlled accordingly.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 555 of 1560 Mar 18, 2011 SH7080 Group TGRA_3 TCDR TGRA_4 TGRC_4 TDDR H'0000 Buffer register TGRC_4 Temporary register TEMP2 Compare register TGRA_4 Output waveform Output waveform Tb2 Ta Tb1 Ta Tb2 Ta TCNT_3 TCNT_4 TCNTS (Output waveform is active-low) H'6400 H'0080 H'6400 H'6400 H'0080 H'0080 Transfer from temporary register to compare register Transfer from temporary register to compare register Figure 11.40 Example of Complementary PWM Mode Operation

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 556 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group 3. Initialization In complementary PWM mode, there are six registers that must be initialized. In addition, there is a register that specifies whether to generate dead time (it should be used only when dead time generation should be disabled). Before setting complementary PWM mode with bits MD3 to MD0 in the timer mode register (TMDR), the following initial register values must be set. TGRC_3 operates as the buffer register for TGRA_3, and should be set with 1/2 the PWM carrier cycle + dead time Td. The timer cycle buffer register (TCBR) operates as the buffer register for the timer cycle data register (TCDR), and should be set with 1/2 the PWM carrier cycle. Set dead time Td in the timer dead time data register (TDDR). When dead time is not needed, the TDER bit in the timer dead time enable register (TDER) should be cleared to 0, TGRC_3 and TGRA_3 should be set to 1/2 the PWM carrier cycle + 1, and TDDR should be set to 1. Set the respective initial PWM duty values in buffer registers TGRD_3, TGRC_4, and TGRD_4. The values set in the five buffer registers excluding TDDR are transferred simultaneously to the corresponding compare registers when complementary PWM mode is set. Set TCNT_4 to H'0000 before setting complementary PWM mode. Table 11.56 Registers and Counters Requiring Initialization Register/Counter Set Value TGRC_3 1/2 PWM carrier cycle + dead time Td (1/2 PWM carrier cycle + 1 when dead time generation is disabled by TDER) TDDR Dead time Td (1 when dead time generation is disabled by TDER) TCBR 1/2 PWM carrier cycle TGRD_3, TGRC_4, TGRD_4 Initial PWM duty value for each phase TCNT_4 H'0000 Note: The TGRC_3 set value must be the sum of 1/2 the PWM carrier cycle set in TCBR and dead time Td set in TDDR. When dead time generation is disabled by TDER, TGRC_3 must be set to 1/2 the PWM carrier cycle + 1.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 557 of 1560 Mar 18, 2011 SH7080 Group 4. PWM Output Level Setting In complementary PWM mode, the PWM pulse output level is set with bits OLSN and OLSP in timer output control register 1 (TOCR1) or bits OLS1P to OLS3P and OLS1N to OLS3N in timer output control register 2 (TOCR2). The output level can be set for each of the three positive phases and three negative phases of 6- phase output. Complementary PWM mode should be cleared before setting or changing output levels. 5. Dead Time Setting In complementary PWM mode, PWM pulses are output with a non-overlapping relationship between the positive and negative phases. This non-overlap time is called the dead time. The non-overlap time is set in the timer dead time data register (TDDR). The value set in TDDR is used as the TCNT_3 counter start value, and creates non-overlap between TCNT_3 and TCNT_4. Complementary PWM mode should be cleared before changing the contents of TDDR. 6. Dead Time Suppressing Dead time generation is suppressed by clearing the TDER bit in the timer dead time enable register (TDER) to 0. TDER can be cleared to 0 only when 0 is written to it after reading TDER = 1. TGRA_3 and TGRC_3 should be set to 1/2 PWM carrier cycle + 1 and the timer dead time data register (TDDR) should be set to 1. By the above settings, PWM waveforms without dead time can be obtained. Figure 11.41 shows an example of operation without dead time.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 558 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group TGRA_3=TCDR+1 TCDR TGRA_4 TGRC_4 TDDR=1 H'0000 Buffer register TGRC_4 Temporary register TEMP2 Compare register TGRA_4 Output waveform Output waveform Initial output Initial output T a Tb1 Ta Tb2 Ta TCNT_3 TCNT_4 TCNTS Output waveform is active-low. Data1 Data2 Data1 Data2 Data1 Data2 Transfer from temporary register to compare register Figure 11.41 Example of Operation without Dead Time

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 559 of 1560 Mar 18, 2011 SH7080 Group 7. PWM Cycle Setting In complementary PWM mode, the PWM pulse cycle is set in two registers—TGRA_3, in which the TCNT_3 upper limit value is set, and TCDR, in which the TCNT_4 upper limit value is set. The settings should be made so as to achieve the following relationship between these two registers: With dead time: TGRA_3 set value = TCDR set value + TDDR set value Without dead time: TGRA_3 set value = TCDR set value + 1 The TGRA_3 and TCDR settings are made by setting the values in buffer registers TGRC_3 and TCBR. The values set in TGRC_3 and TCBR are transferred simultaneously to TGRA_3 and TCDR in accordance with the transfer timing selected with bits MD3 to MD0 in the timer mode register (TMDR). The updated PWM cycle is reflected from the next cycle when the data update is performed at the crest, and from the current cycle when performed in the trough. Figure 11.42 illustrates the operation when the PWM cycle is updated at the crest. See the following section, Register Data Updating, for the method of updating the data in each buffer register. Counter value TGRC_3 update TGRA_3 update TGRA_3 TCNT_3 TCNT_4 Time Figure 11.42 Example of PWM Cycle Updating

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 560 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group 8. Register Data Updating In complementary PWM mode, the buffer register is used to update the data in a compare register. The update data can be written to the buffer register at any time. There are five PWM duty and carrier cycle registers that have buffer registers and can be updated during operation. There is a temporary register between each of these registers and its buffer register. When subcounter TCNTS is not counting, if buffer register data is updated, the temporary register value is also rewritten. Transfer is not performed from buffer registers to temporary registers when TCNTS is counting; in this case, the value written to a buffer register is transferred after TCNTS halts. The temporary register value is transferred to the compare register at the data update timing set with bits MD3 to MD0 in the timer mode register (TMDR). Figure 11.43 shows an example of data updating in complementary PWM mode. This example shows the mode in which data updating is performed at both the counter crest and trough. When rewriting buffer register data, a write to TGRD_4 must be performed at the end of the update. Data transfer from the buffer registers to the temporary registers is performed simultaneously for all five registers after the write to TGRD_4. A write to TGRD_4 must be performed after writing data to the registers to be updated, even when not updating all five registers, or when updating the TGRD_4 data. In this case, the data written to TGRD_4 should be the same as the data prior to the write operation.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 561 of 1560 Mar 18, 2011 SH7080 Group Data update timing: counter crest and trough Transfer from temporary register to compare register Transfer from temporary register to compare register Transfer from temporary register to compare register Transfer from temporary register to compare register Transfer from temporary register to compare register Transfer from temporary register to compare register Counter value TGRA_3 TGRC_4 TGRA_4 H'0000 BR data1 data2 data3 data4 data5 data6 data1 data1 data2 data3 data4 data6 data2 data3 data4 data5 data6Temp_R GR Time : Compare register : Buffer register Figure 11.43 Example of Data Update in Complementary PWM Mode

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 562 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group 9. Initial Output in Complementary PWM Mode In complementary PWM mode, the initial output is determined by the setting of bits OLSN and OLSP in timer output control register 1 (TOCR1) or bits OLS1N to OLS3N and OLS1P to OLS3P in timer output control register 2 (TOCR2). This initial output is the PWM pulse non-active level, and is output from when complementary PWM mode is set with the timer mode register (TMDR) until TCNT_4 exceeds the value set in the dead time register (TDDR). Figure 11.44 shows an example of the initial output in complementary PWM mode. An example of the waveform when the initial PWM duty value is smaller than the TDDR value is shown in figure 11.45. Timer output control register settings OLSN bit: 0 (initial output: high; active level: low) OLSP bit: 0 (initial output: high; active level: low) TCNT_3 and TCNT_4 values TGRA_4 TDDR TCNT_3 TCNT_4 Initial output Dead time Time Active level Active level TCNT_3 and TCNT_4 count start (TSTR setting) Complementary PWM mode (TMDR setting) Positive phase output Negative phase output Figure 11.44 Example of Initial Output in Complementary PWM Mode (1)

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 563 of 1560 Mar 18, 2011 SH7080 Group Timer output control register settings OLSN bit: 0 (initial output: high; active level: low) OLSP bit: 0 (initial output: high; active level: low) TCNT_3 and TCNT_4 values TGRA_4 TDDR TCNT_3 TCNT_4 Initial output Time Active level TCNT_3 and TCNT_4 count start (TSTR setting) Complementary PWM mode (TMDR setting) Positive phase output Negative phase output Figure 11.45 Example of Initial Output in Complementary PWM Mode (2)

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 564 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group 10. Complementary PWM Mode PWM Output Generation Method In complementary PWM mode, 3-phase output is performed of PWM waveforms with a non- overlap time between the positive and negative phases. This non-overlap time is called the dead time. A PWM waveform is generated by output of the output level selected in the timer output control register in the event of a compare-match between a counter and data register. While TCNTS is counting, data register and temporary register values are simultaneously compared to create consecutive PWM pulses from 0 to 100%. The relative timing of on and off compare- match occurrence may vary, but the compare-match that turns off each phase takes precedence to secure the dead time and ensure that the positive phase and negative phase on times do not overlap. Figures 11.46 to 11.48 show examples of waveform generation in complementary PWM mode. The positive phase/negative phase off timing is generated by a compare-match with the solid- line counter, and the on timing by a compare-match with the dotted-line counter operating with a delay of the dead time behind the solid-line counter. In the T1 period, compare-match a that turns off the negative phase has the highest priority, and compare-matches occurring prior to a are ignored. In the T2 period, compare-match c that turns off the positive phase has the highest priority, and compare-matches occurring prior to c are ignored. In normal cases, compare-matches occur in the order a → b → c → d (or c → d → a' → b'), as shown in figure 11.46. If compare-matches deviate from the a → b → c → d order, since the time for which the negative phase is off is less than twice the dead time, the figure shows the positive phase is not being turned on. If compare-matches deviate from the c → d → a' → b' order, since the time for which the positive phase is off is less than twice the dead time, the figure shows the negative phase is not being turned on. If compare-match c occurs first following compare-match a, as shown in figure 11.47, compare-match b is ignored, and the negative phase is turned off by compare-match d. This is because turning off of the positive phase has priority due to the occurrence of compare-match c (positive phase off timing) before compare-match b (positive phase on timing) (consequently, the waveform does not change since the positive phase goes from off to off). Similarly, in the example in figure 11.48, compare-match a' with the new data in the temporary register occurs before compare-match c, but other compare-matches occurring up to c, which turns off the positive phase, are ignored. As a result, the negative phase is not turned on. Thus, in complementary PWM mode, compare-matches at turn-off timings take precedence, and turn-on timing compare-matches that occur before a turn-off timing compare-match are ignored.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 569 of 1560 Mar 18, 2011 SH7080 Group 11. Complementary PWM Mode 0% and 100% Duty Output In complementary PWM mode, 0% and 100% duty cycles can be output as required. Figures 11.49 to 11.53 show output examples. 100% duty output is performed when the data register value is set to H'0000. The waveform in this case has a positive phase with a 100% on-state. 0% duty output is performed when the data register value is set to the same value as TGRA_3. The waveform in this case has a positive phase with a 100% off-state. On and off compare-matches occur simultaneously, but if a turn-on compare-match and turn- off compare-match for the same phase occur simultaneously, both compare-matches are ignored and the waveform does not change. 12. Toggle Output Synchronized with PWM Cycle In complementary PWM mode, toggle output can be performed in synchronization with the PWM carrier cycle by setting the PSYE bit to 1 in the timer output control register (TOCR). An example of a toggle output waveform is shown in figure 11.54. This output is toggled by a compare-match between TCNT_3 and TGRA_3 and a compare- match between TCNT4 and H'0000. The output pin for this toggle output is the TIOC3A pin. The initial output is 1. TGRA_3 H'0000 Toggle output TIOC3A pin TCNT_4 TCNT_3 Figure 11.54 Example of Toggle Output Waveform Synchronized with PWM Output

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 571 of 1560 Mar 18, 2011 SH7080 Group 14. Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode Setting the WRE bit in TWCR to 1 suppresses initial output when synchronous counter clearing occurs in the Tb interval at the trough in complementary PWM mode and controls abrupt change in duty cycle at synchronous counter clearing. Initial output suppression is applicable only when synchronous clearing occurs in the Tb interval at the trough as indicated by (10) or (11) in figure 11.56. When synchronous clearing occurs outside that interval, the initial value specified by the OLS bits in TOCR is output. Even in the Tb interval at the trough, if synchronous clearing occurs in the initial value output period (indicated by (1) in figure 11.56) immediately after the counters start operation, initial value output is not suppressed. When using the initial output suppression function, make sure to set compare registers TGRB_3, TGRA_4, and TGRB_4 to a value twice or more the setting of dead time data register TDDR. If synchronous clearing occurs with the compare registers set to a value less than twice the setting of TDDR, the PWM output dead time may be too short (or nonexistent) or illegal active-level PWM negative-phase output may occur during the initial output suppression interval. For details, see section 11.7.23, Notes on Output Waveform Control During Synchronous Counter Clearing in Complementary PWM Mode. This function can be used in both the MTU2 and MTU2S. In the MTU2, synchronous clearing generated in channels 0 to 2 in the MTU2 can cause counter clearing in complementary PWM mode; in the MTU2S, compare match or input capture flag setting in channels 0 to 2 in the MTU2 can cause counter clearing.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 572 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Tb intervalTb interval Tb interval TGRA_3 TGRB_3 TCDR TCNT_3 TCNT_4 TDDR H'0000 Positive phase Negative phase Output waveform is active-low Counter start Figure 11.56 Timing for Synchronous Counter Clearing

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 573 of 1560 Mar 18, 2011 SH7080 Group ⎯ Example of Procedure for Setting Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode An example of the procedure for setting output waveform control at synchronous counter clearing in complementary PWM mode is shown in figure 11.57. Stop count operation Output waveform control at synchronous counter clearing Set TWCR and complementary PWM mode Start count operation Output waveform control at synchronous counter clearing [1] [2] [3] [1] Clear bits CST3 and CST4 in the timer start register (TSTR) to 0, and halt timer counter (TCNT) operation. Perform TWCR setting while TCNT_3 and TCNT_4 are stopped. [2] Read bit WRE in TWCR and then write 1 to it to suppress initial value output at counter clearing. [3] Set bits CST3 and CST4 in TSTR to 1 to start count operation. Figure 11.57 Example of Procedure for Setting Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode ⎯ Examples of Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode Figures 11.58 to 11.61 show examples of output waveform control in which the MTU2 operates in complementary PWM mode and synchronous counter clearing is generated while the WRE bit in TWCR is set to 1. In the examples shown in figures 11.58 to 11.61, synchronous counter clearing occurs at timing (3), (6), (8), and (11) shown in figure 11.56, respectively. In the MTU2S, these examples are equivalent to the cases when the MTU2S operates in complementary PWM mode and synchronous counter clearing is generated while the SCC bit is cleared to 0 and the WRE bit is set to 1 in TWCR.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 576 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group 15. Suppressing MTU2–MTU2S Synchronous Counter Clearing In the MTU2S, setting the SCC bit in TWCR to 1 suppresses synchronous counter clearing caused by the MTU2. Synchronous counter clearing is suppressed only within the interval shown in figure 11.62. When using this function, the MTU2S should be set to complementary PWM mode. For details of synchronous clearing caused by the MTU2, refer to the description about MTU2S counter clearing caused by MTU2 flag setting source (MTU2-MTU2S synchronous counter clearing) in section 11.4.10, MTU2–MTU2S Synchronous Operation. Tb interval at the crest Tb interval at the trough Tb interval at the crest Tb interval at the trough TGRA_3 TGRB_3 TCDR TDDR H'0000 Tb interval immediately after counter operation starts MTU2-MTU2S synchronous counter clearing is suppressed. MTU2-MTU2S synchronous counter clearing is suppressed. Figure 11.62 MTU2–MTU2S Synchronous Clearing-Suppressed Interval Specified by SCC Bit in TWCR

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 577 of 1560 Mar 18, 2011 SH7080 Group ⎯ Example of Procedure for Suppressing MTU2–MTU2S Synchronous Counter Clearing An example of the procedure for suppressing MTU2–MTU2S synchronous counter clearing is shown in figure 11.63. Stop count operation (MTU2 and MTU2S) MTU2-MTU2S synchronous counter clearing suppress Start count operation (MTU2 and MTU2S) Output waveform control at synchronous counter clearing and synchronous counter clearing suppress [1] [3]

• Set the following.
• Complementary PWM mode (MTU2S)
• Compare match/input capture operation (MTU2)
• Bit WRE in TWCR (MTU2S) [2] Set bit SCC in TWCR (MTU2S) [4] [1] Clear bits CST of the timer start register (TSTR) in the MTU2S to 0, and halt count operation. Clear bits CST of TSTR in the MTU2 to 0, and halt count operation. [2] Set the complementary PWM mode in the MTU2S and compare match/input capture operation in the MTU2. When bit WRE in TWCR should be set, make appropriate setting here. [3] Set bits CST3 and CST4 of TSTR in the MTU2S to 1 to start count operation. For MTU2-MTU2S synchronous counter clearing, set bits CST of TSTR in the MTU2 to 1 to start count operation in any one of TCNT_0 to TCNT_2. [4] Read TWCR and then set bit SCC in TWCR to 1 to suppress MTU2-MTU2S synchronous counter clearing*. Here, do not modify the CCE and WRE bit values in TWCR of the MTU2S. MTU2-MTU2S synchronous counter clearing is suppressed in the intervals shown in figure 11.62. Note: * The SCC bit value can be modified during counter operation. However, if a synchronous clearing occurs when bit SCC is modified from 0 to 1, the synchronous clearing may not be suppressed. If a synchronous clearing occurs when bit SCC is modified from 1 to 0, the synchronous clearing may be suppressed. Figure 11.63 Example of Procedure for Suppressing MTU2–MTU2S Synchronous Counter Clearing ⎯ Examples of Suppression of MTU2–MTU2S Synchronous Counter Clearing Figures 11.64 to 11.67 show examples of operation in which the MTU2S operates in complementary PWM mode and MTU2–MTU2S synchronous counter clearing is suppressed by setting the SCC bit in TWCR in the MTU2S to 1. In the examples shown in figures 11.64 to 11.67, synchronous counter clearing occurs at timing (3), (6), (8), and (11) shown in figure 11.56, respectively. In these examples, the WRE bit in TWCR of the MTU2S is set to 1.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 578 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group TGRA_3 TGRB_3 TCDR TDDR H'0000 Positive phase Negative phase Output waveform is active-low. MTU2-MTU2S synchronous clearing TCNT_3 (MTU2S) TCNT_4 (MTU2S) Bit WRE = 1 Bit SCC = 1 Counters are not cleared Figure 11.64 Example of Synchronous Clearing in Dead Time during Up-Counting (Timing (3) in Figure 11.56; Bit WRE Is 1 and Bit SCC Is 1 in TWCR of MTU2S)

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 579 of 1560 Mar 18, 2011 SH7080 Group Positive phase Negative phase Output waveform is active-low. MTU2-MTU2S synchronous clearing Bit WRE = 1 Bit SCC = 1 Counters are not cleared TGRA_3 TGRB_3 TCDR TDDR H'0000 TCNT_3 (MTU2S) TCNT_4 (MTU2S) Figure 11.65 Example of Synchronous Clearing in Interval Tb at Crest (Timing (6) in Figure 11.56; Bit WRE Is 1 and Bit SCC Is 1 in TWCR of MTU2S)

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 580 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Positive phase Negative phase Output waveform is active-low. MTU2-MTU2S synchronous clearing Bit WRE = 1 Bit SCC = 1 Counters are not cleared TGRA_3 TGRB_3 TCDR TDDR H'0000 TCNT_3 (MTU2S) TCNT_4 (MTU2S) Figure 11.66 Example of Synchronous Clearing in Dead Time during Down-Counting (Timing (8) in Figure 11.56; Bit WRE Is 1 and Bit SCC Is 1 in TWCR of MTU2S)

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 581 of 1560 Mar 18, 2011 SH7080 Group Positive phase Negative phase Output waveform is active-low. MTU2-MTU2S synchronous clearing Bit WRE = 1 Bit SCC = 1 TGRA_3 TGRB_3 TCDR TDDR H'0000 TCNT_3 (MTU2S) TCNT_4 (MTU2S) Counters are cleared Initial value output is suppressed. Figure 11.67 Example of Synchronous Clearing in Interval Tb at Trough (Timing (11) in Figure 11.56; Bit WRE Is 1 and Bit SCC Is 1 in TWCR of MTU2S)

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 583 of 1560 Mar 18, 2011 SH7080 Group 17. Example of AC Synchronous Motor (Brushless DC Motor) Drive Waveform Output In complementary PWM mode, a brushless DC motor can easily be controlled using the timer gate control register (TGCR). Figures 11.69 to 11.72 show examples of brushless DC motor drive waveforms created using TGCR. When output phase switching for a 3-phase brushless DC motor is performed by means of external signals detected with a Hall element, etc., clear the FB bit in TGCR to 0. In this case, the external signals indicating the polarity position are input to channel 0 timer input pins TIOC0A, TIOC0B, and TIOC0C (set with PFC). When an edge is detected at pin TIOC0A, TIOC0B, or TIOC0C, the output on/off state is switched automatically. When the FB bit is 1, the output on/off state is switched when the UF, VF, or WF bit in TGCR is cleared to 0 or set to 1. The drive waveforms are output from the complementary PWM mode 6-phase output pins. With this 6-phase output, in the case of on output, it is possible to use complementary PWM mode output and perform chopping output by setting the N bit or P bit to 1. When the N bit or P bit is 0, level output is selected. The 6-phase output active level (on output level) can be set with the OLSN and OLSP bits in the timer output control register (TOCR) regardless of the setting of the N and P bits. External input TIOC0A pin TIOC0B pin TIOC0C pin TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin 6-phase output When BDC = 1, N = 0, P = 0, FB = 0, output active level = high Figure 11.69 Example of Output Phase Switching by External Input (1)

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 585 of 1560 Mar 18, 2011 SH7080 Group TGCR UF bit VF bit WF bit TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin 6-phase output When BDC = 1, N = 1, P = 1, FB = 1, output active level = high Figure 11.72 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (2) 18. A/D Converter Start Request Setting In complementary PWM mode, an A/D converter start request can be issued using a TGRA_3 compare-match, TCNT_4 underflow (trough), or compare-match on a channel other than channels 3 and 4. When start requests using a TGRA_3 compare-match are specified, A/D conversion can be started at the crest of the TCNT_3 count. A/D converter start requests can be set by setting the TTGE bit to 1 in the timer interrupt enable register (TIER). To issue an A/D converter start request at a TCNT_4 underflow (trough), set the TTGE2 bit in TIER_4 to 1.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 589 of 1560 Mar 18, 2011 SH7080 Group Buffer register Temporary register General register TCNT_3 TCNT_4 Data1 Data2 Data* Data2 Data* Data2 (1) (2) (3) Buffer transfer is suppressed Note: * When buffer transfer at the crest is selected. data1 Bit BTE1 in TBTER Bit BTE0 in TBTER (1) No data is transferred from the buffer register to the temporary register in the buffer transfer-disabled period (bits BTE1 and BTE0 in TBTER are set to 0 and 1, respectively). (2) Data is transferred from the temporary register to the general register even in the buffer transfer-disabled period. (3) After buffer transfer is enabled, data is transferred from the buffer register to the temporary register. [Legend] Figure 11.76 Example of Operation when Buffer Transfer Is Suppressed (BTE1 = 0 and BTE0 = 1)

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 590 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group (1) When buffer register is rewritten within one carrier cycle after the TGIA_3 interrupt TGIA_3 interrupt generated Buffer register rewrite timing TGIA_3 interrupt generated Buffer register rewrite timing 0210 1 Data1 Data2Data Data1 Data2Data Data1 Data2Data (2) When buffer register is rewritten after one carrier cycle has elapsed after the TGIA_3 interrupt TGIA_3 interrupt generated TGIA_3 interrupt generated Buffer register rewrite timing 0210 1 Data1Data Data1Data Data1Data Buffer transfer-enabled period Bits 6 to 4 in TITCR Bits 6 to 4 in TITCNT Buffer register Temporary register General register Buffer transfer-enabled period Bits 6 to 4 in TITCR Bits 6 to 4 in TITCNT Buffer register Temporary register General register Note: Bits MD3 to MD0 in TMDR_3 are set to 1101, selecting buffer transfer at the crest. The skipping count is set to two. T3AEN is set to 1, and T4VEN is cleared to 0. Figure 11.77 Example of Operation when Buffer Transfer Is Linked with Interrupt Skipping (BTE1 = 1 and BTE0 = 0)

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 591 of 1560 Mar 18, 2011 SH7080 Group Note: Bits MD3 to MD0 in TMDR_3 are set to 1111, selectin g buffer transfer at the crest and trough. The skipping count is set to three. T3AEN and T4VEN are set to 1. 00 12 30 123 01 23012 3 Skipping counter 3ACNT Skipping counter 4VCNT Buffer transfer-enabled period (T3AEN set to 1) Buffer transfer-enabled period (T4VEN set to 1) Buffer transfer-enabled period (T3AEN and T4VEN set to 1) Figure 11.78 Relationship between Bits T3AEN and T4VEN in Timer Interrupt Skipping Set Register (TITCR) and Buffer Transfer-Enabled Period

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 592 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Complementary PWM Mode Output Protection Function: Complementary PWM mode output has the following protection functions. 1. Register and counter miswrite prevention function With the exception of the buffer registers, which can be rewritten at any time, access by the CPU can be enabled or disabled for the mode registers, control registers, compare registers, and counters used in complementary PWM mode by means of the RWE bit in the timer read/write enable register (TRWER). The applicable registers are some (21 in total) of the registers in channels 3 and 4 shown in the following: ⎯ TCR_3 and TCR_4, TMDR_3 and TMDR_4, TIORH_3 and TIORH_4, TIORL_3 and TIORL_4, TIER_3 and TIER_4, TCNT_3 and TCNT_4, TGRA_3 and TGRA_4, TGRB_3 and TGRB_4, TOER, TOCR, TGCR, TCDR, and TDDR. This function enables miswriting due to CPU runaway to be prevented by disabling CPU access to the mode registers, control registers, and counters. When the applicable registers are read in the access-disabled state, undefined values are returned. Writing to these registers is ignored. 2. Halting of PWM output by external signal The 6-phase PWM output pins can be set automatically to the high-impedance state by inputting specified external signals. There are four external signal input pins. See section 13, Port Output Enable (POE), for details. 3. Halting of PWM output when oscillator is stopped If it is detected that the clock input to this LSI has stopped, the 6-phase PWM output pins automatically go to the high-impedance state. The pin states are not guaranteed when the clock is restarted. See section 4.7, Function for Detecting Oscillator Stop.

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11.4.9 A/D Converter Start Request Delaying Function

A/D converter start requests can be issued in channel 4 by making settings in the timer A/D converter start request control register (TADCR), timer A/D converter start request cycle set registers (TADCORA_4 and TADCORB_4), and timer A/D converter start request cycle set buffer registers (TADCOBRA_4 and TADCOBRB_4). The A/D converter start request delaying function compares TCNT_4 with TADCORA_4 or TADCORB_4, and when their values match, the function issues a respective A/D converter start request (TRG4AN or TRG4BN). A/D converter start requests (TRG4AN and TRG4BN) can be skipped in coordination with interrupt skipping by making settings in the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in TADCR. 1. Example of Procedure for Specifying A/D Converter Start Request Delaying Function Figure 11.79 shows an example of procedure for specifying the A/D converter start request delaying function. Set A/D converter start request cycle A/D converter start request delaying function

• Set the timing of transfer from cycle set buffer register
• Set linkage with interrupt skipping
• Enable A/D converter start request delaying function A/D converter start request delaying function [1] [2] [1] Set the cycle in the timer A/D converter start request cycle buffer register (TADCOBRA_4 or TADCOBRB_4) and timer A/D converter start request cycle register (TADCORA_4 or TADCORB_4). (The same initial value must be specified in the cycle buffer register and cycle register.) [2] Use bits BF1 and BF2 in the timer A/D converter start request control register (TADCR) to specify the timing of transfer from the timer A/D converter start request cycle buffer register to A/D converter start request cycle register.
• Specify whether to link with interrupt skipping through bits ITA3AE, ITA4VE, ITB3AE, and ITB4VE.
• Use bits TU4AE, DT4AE, UT4BE, and DT4BE to enable A/D conversion start requests (TRG4AN or TRG4BN). Notes: 1. Perform TADCR setting while TCNT_4 is stopped. 2. Do not set BF1 to 1 when complementary PWM mode is not selected. 3. Do not set ITA3AE, ITA4VE, ITB3AE, ITB4VE, DT4AE, or DT4BE to 1 when complementary PWM mode is not selected. Figure 11.79 Example of Procedure for Specifying A/D Converter Start Request Delaying Function

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 595 of 1560 Mar 18, 2011 SH7080 Group Note: This function must be used in combination with interrupt skipping. When interrupt skipping is disabled (the T3AEN and T4VEN bits in the timer interrupt skipping set register (TITCR) are cleared to 0 or the skipping count set bits (3ACOR and 4VCOR) in TITCR are cleared to 0), make sure that A/D converter start requests are not linked with interrupt skipping (clear the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in the timer A/D converter start request control register (TADCR) to 0). TADCORA_4 TCNT_4 A/D converter start request (TRG4AN) Note: When the interrupt skipping count is set to two. TGIA_3 interrupt skipping counter TCIV_4 interrupt skipping counter TGIA_3 A/D request-enabled period TCIV_4 A/D request-enabled period When linked with TGIA_3 and TCIV_4 interrupt skipping When linked with TGIA_3 interrupt skipping When linked with TCIV_4 interrupt skipping 00 01 00 01 02 00 01 00 01 02 (UT4AE/DT4AE = 1) Figure 11.81 Example of A/D Converter Start Request Signal (TRG4AN) Operation Linked with Interrupt Skipping

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 596 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group A/D converter start request (TRG4AN) Note: When the interrupt skipping count is set to two. TGIA_3 interrupt skipping counter TCIV_4 interrupt skipping counter TGIA_3 A/D request-enabled period TCIV_4 A/D request-enabled period When linked with TGIA_3 and TCIV_4 interrupt skipping When linked with TGIA_3 interrupt skipping When linked with TCIV_4 interrupt skipping TADCORA_4 TCNT_4 00 01 00 01 02 00 01 00 01 02 UT4AE = 1 DT4AE = 0 Figure 11.82 Example of A/D Converter Start Request Signal (TRG4AN) Operation Linked with Interrupt Skipping

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11.4.10 MTU2–MTU2S Synchronous Operation

MTU2–MTU2S Synchronous Counter Start: The counters in the MTU2 and MTU2S which operate at different clock systems can be started synchronously by making the TCSYSTR settings in the MTU2. 1. Example of MTU2–MTU 2S Synchronous Counter Start Setting Procedure Figure 11.83 shows an example of synchronous counter start setting procedure. Stop count operation MTU2-MTU2S synchronous counter start Set the necessary operation <Counter operation starts> [1] [2] Set TCSYSTR [3] [1] Use TSTR registers in the MTU2 and MTU2S and halt the counters used for synchronous start operation. [2] Specify necessary operation with appropriate registers such as TCR and TMDR. [3] In TCSYSTR in the MTU2, set the bits corresponding to the counters to be started synchronously to 1. The TSTRs are automatically set appropriately and the counters start synchronously. Notes: 1. Even if a bit in TCSYSTR corresponding to an operating counter is cleared to 0, the counter will not stop. To stop the counter, clear the corresponding bit in TSTR to 0 directly. 2. To start channels 3 and 4 in reset-synchronized PWM mode or complementary PWM mode, make appropriate settings in TCYSTR according to the TSTR setting for the respective mode. For details, refer to section 11.4.7, Reset-Synchronized PWM Mode, and section 11.4.8, Complementary PWM Mode. Figure 11.83 Example of Synchronous Counter Start Setting Procedure

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 598 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group 2. Examples of Synchronous Counter Start Operation Figures 11.84 (1), 11.84 (2), 11.84 (3), and 11.84 (4) show examples of synchronous counter start operation when the clock frequency ratio between the MTU2 and MTU2S is 1:1, 1:2, 1:3, and 1:4, respectively. In these examples, the counter clock of the MTU2 is MPφ/1. MTU2 clock MTU2S clock MTU2/TSTR MTU2S/TSTR H'51TCSYSTR H'00 H'42H'00 H'80H'00 H'00 H'0001MTU2/TCNT_1 H'0000 H'0002 H'0001 H'0002MTU2S/TCNT_4 H'0000 Automatically cleared after TCSYSTR setting is made Figure 11.84 (1) Example of Synchronous Counter Start Operation (MTU2-to-MTU2S Clock Frequency Ratio = 1:1)

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 600 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group MTU2 clock MTU2S clock Automatically cleared after TCSYSTR setting is made MTU2/TSTR MTU2S/TSTR H'51TCSYSTR H'00 H'42H'00 H'80H'00 H'00 H'0001MTU2/TCNT_1 H'0000 H'0002 H'0001 MTU2S/TCNT_4 H'0000 H'0002 H'0003 H'0004 Figure 11.84 (4) Example of Synchronous Counter Start Operation (MTU2-to-MTU2S Clock Frequency Ratio = 1:4)

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11.4.11 External Pulse Width Measurement

The pulse widths of up to three external input lines can be measured in channel 5. Example of External Pulse Width Measurement Setting Procedure: Select counter clock External pulse width measurement Select pulse width measuring conditions Start count operation <External pulse width measurement> [1] Use bits TPSC1 and TPSC0 in TCR to select the counter clock. [2] In TIOR, select the high level or low level for the pulse width measuring condition. [3] Set bits CST in TSTR to 1 to start count operation. Notes: 1. Do not set bits CMPCLR5U, CMPCLR5V, or CMPCLR5W in TCNTCMPCLR to 1. 2. Do not set bits TGIE5U, TGIE5V, or TGIE5W in TIER_5 to 1. 3. The value in TCNT is not captured in TGR. [1] [2] [3] Figure 11.87 Example of External Pulse Width Measurement Setting Procedure Example of External Pulse Width Measurement: 0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 0007 000A 000B TIC5U TCNTU_5 MPφ Figure 11.88 Example of External Pulse Width Measurement (Measuring High Pulse Width)

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11.4.12 Dead Time Compensation

By measuring the delay of the output waveform and reflecting it to duty, the external pulse width measurement function can be used as the dead time compensation function while the complementary PWM is in operation. Tdead Tdelay Upper arm signal Lower arm signal Inverter output detection signal Dead time delay signal Figure 11.89 Delay in Dead Time in Complementary PWM Operation

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11.4.13 TCNT Capture at Crest and/or Trough in Complementary PWM Operation

The TCNT value is captured in TGR at either the crest or trough or at both the crest and trough during complementary PWM operation. The timing for capturing in TGR can be selected by TIOR. Figure 11.92 is an operating example in which TCNT is used as a free-running counter without being cleared, and the TCNT value is captured in TGR at the specified timing (either crest or trough, or both crest and trough). Tdead Tdelay Upper arm signal Lower arm signal Inverter output monitor signal Dead time delay signal TGRA_4 3E5B 3E5B 3F37 3F37 3FAF 3FAF3DE7 TCNT[15:0] TGR[15:0] Up-count/down-count signal (udflg) 3DE7 3ED3 3ED3 Figure 11.92 TCNT Capturing at Crest and/or Trough in Complementary PWM Operation

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11.5 Interrupt Sources

11.5.1 Interrupt Sources and Priorities

There are three kinds of MTU2 interrupt source; TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled bit, allowing the generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The interrupt request is cleared by clearing the status flag to 0. Relative channel priorities can be changed by the interrupt controller, however the priority order within a channel is fixed. For details, see section 6, Interrupt Controller (INTC). Table 11.57 lists the MTU2 interrupt sources.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 608 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 11.57 MTU2 Interrupts Channel Name Interrupt Source Interrupt Flag DMAC Activation DTC Activation Priority

0 TGIA_0 TGRA_0 input capture/compare match TGFA_0 Possible Possible High

TGIB_0 TGRB_0 input capture/compare match TGFB_0 Not possible Possible TGIC_0 TGRC_0 input capture/compare match TGFC_0 Not possible Possible TGID_0 TGRD_0 input capture/compare match TGFD_0 Not possible Possible TCIV_0 TCNT_0 overflow TCFV_0 Not possible Not possible TGIE_0 TGRE_0 compare match TGFE_0 Not possible Not possible TGIF_0 TGRF_0 compare match TGFF_0 Not possible Not possible

1 TGIA_1 TGRA_1 input capture/compare match TGFA_1 Possible Possible

TGIB_1 TGRB_1 input capture/compare match TGFB_1 Not possible Possible TCIV_1 TCNT_1 overflow TCFV_1 Not possible Not possible TCIU_1 TCNT_1 underflow TCFU_1 Not possible Not possible

2 TGIA_2 TGRA_2 input capture/compare match TGFA_2 Possible Possible

TGIB_2 TGRB_2 input capture/compare match TGFB_2 Not possible Possible TCIV_2 TCNT_2 overflow TCFV_2 Not possible Not possible TCIU_2 TCNT_2 underflow TCFU_2 Not possible Not possible

3 TGIA_3 TGRA_3 input capture/compare match TGFA_3 Possible Possible

TGIB_3 TGRB_3 input capture/compare match TGFB_3 Not possible Possible TGIC_3 TGRC_3 input capture/compare match TGFC_3 Not possible Possible TGID_3 TGRD_3 input capture/compare match TGFD_3 Not possible Possible TCIV_3 TCNT_3 overflow TCFV_3 Not possible Not possible

4 TGIA_4 TGRA_4 input capture/compare match TGFA_4 Possible Possible

TGIB_4 TGRB_4 input capture/compare match TGFB_4 Not possible Possible TGIC_4 TGRC_4 input capture/compare match TGFC_4 Not possible Possible TGID_4 TGRD_4 input capture/compare match TGFD_4 Not possible Possible TCIV_4 TCNT_4 overflow/underflow TCFV_4 Not possible Possible

5 TGIU_5 TGRU_5 input capture/compare match TGFU_5 Not possible Possible

TGIV_5 TGRV_5 input capture/compare match TGFV_5 Not possible Possible TGIW_5 TGRW_5 input capture/compare match TGFW_5 Not possible Possible Low Note: This table shows the initial state immediately after a reset. The relative channel priorities can be changed by the interrupt controller.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 609 of 1560 Mar 18, 2011 SH7080 Group Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The MTU2 has 21 input capture/compare match interrupts, six for channel 0, four each for channels 3 and 4, two each for channels 1 and 2, and three for channel 5. The TGFE_0 and TGFF_0 flags in channel 0 are not set by the occurrence of an input capture. Overflow Interrupt: An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt request is cleared by clearing the TCFV flag to 0. The MTU2 has five overflow interrupts, one for each channel. Underflow Interrupt: An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt request is cleared by clearing the TCFU flag to 0. The MTU2 has two underflow interrupts, one each for channels 1 and 2.

11.5.2 DTC/DMAC Activation

DTC Activation: The DTC can be activated by the TGR input capture/compare match interrupt in each channel or the overflow interrupt in channel 4. For details, see section 8, Data Transfer Controller (DTC). A total of 20 MTU2 input capture/compare match interrupts and overflow interrupts can be used as DTC activation sources, four each for channels 0 and 3, two each for channels 1 and 2, five for channel 4, and three for channel 5. DMAC Activation: The DMAC can be activated by the TGRA input capture/compare match interrupt in each channel. For details, see section 10, Direct Memory Access Controller (DMAC). In the MTU2, a total of five TGRA input capture/compare match interrupts can be used as DMAC activation sources, one each for channels 0 to 4. When the DMAC is activated by the MTU2, the activation source is cleared at the point the DMAC requests the internal bus mastership. Therefore, the request for DMAC transfer may be kept pending for a certain period even after the activation source is cleared depending on the internal bus state. To initiate burst transfer by the DMAC using an MTU2 interrupt, setting of the bus function extending register (BSCEHR) is necessary. For details, see section 9.4.8, Bus Function Extending Register (BSCEHR).

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11.5.3 A/D Converter Activation

The A/D converter can be activated by one of the following three methods in the MTU2. Table 11.58 shows the relationship between interrupt sources and A/D converter start request signals. A/D Converter Activation by TGRA Input Capture/Compare Match or at TCNT_4 Trough in Complementary PWM Mode: The A/D converter can be activated by the occurrence of a TGRA input capture/compare match in each channel. In addition, if complementary PWM operation is performed while the TTGE2 bit in TIER_4 is set to 1, the A/D converter can be activated at the trough of TCNT_4 count (TCNT_4 = H'0000). A/D converter start request signal TRGAN is issued to the A/D converter under either one of the following conditions.

• When the TGFA flag in TSR is set to 1 by the occurrence of a TGRA input capture/compare match on a particular channel while the TTGE bit in TIER is set to 1
• When the TCNT_4 count reaches the trough (TCNT_4 = H'0000) during complementary PWM operation while the TTGE2 bit in TIER_4 is set to 1 When either condition is satisfied, if A/D converter start signal TRGAN from the MTU2 is selected as the trigger in the A/D converter, A/D conversion will start. A/D Converter Activation by Compare Match between TCNT_0 and TGRE_0: The A/D converter can be activated by generating A/D converter start request signal TRG0N when a compare match occurs between TCNT_0 and TGRE_0 in channel 0. When the TGFE flag in TSR2_0 is set to 1 by the occurrence of a compare match between TCNT_0 and TGRE_0 in channel 0 while the TTGE2 bit in TIER2_0 is set to 1, A/D converter start request TGR0N is issued to the A/D converter. If A/D converter start signal TGR0N from the MTU2 is selected as the trigger in the A/D converter, A/D conversion will start. A/D Converter Activation by A/D Converter Start Request Delaying Function: The A/D converter can be activated by generating A/D converter start request signal TRG4AN or TRG4BN when the TCNT_4 count matches the TADCORA or TADCORB value if the TAD4AE or TAD4BE bit in the A/D converter start request control register (TADCR) is set to 1. For details, refer to section 11.4.9, A/D Converter Start Request Delaying Function. A/D conversion will start if A/D converter start signal TRG4AN from the MTU2 is selected as the trigger in the A/D converter when TRG4AN is generated or if TRG4BN from the MTU2 is selected as the trigger in the A/D converter when TRG4BN is generated.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 611 of 1560 Mar 18, 2011 SH7080 Group Table 11.58 Interrupt Sources and A/D Converter Start Request Signals Target Registers Interrupt Source A/D Converter Start Request Signal TGRA_0 and TCNT_0 TGRA_1 and TCNT_1 TGRA_2 and TCNT_2 TGRA_3 and TCNT_3 TGRA_4 and TCNT_4 Input capture/compare match TCNT_4 TCNT_4 Trough in complementary PWM mode TRGAN TGRE_0 and TCNT_0 Compare match TRG0N TADCORA and TCNT_4 TRG4AN TADCORB and TCNT_4 TRG4BN

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11.6 Operation Timing

11.6.1 Input/Output Timing

TCNT Count Timing: Figures 11.93 and 11.94 show TCNT count timing in internal clock operation, and figure 11.95 shows TCNT count timing in external clock operation (normal mode), and figure 11.96 shows TCNT count timing in external clock operation (phase counting mode). TCNT TCNT input clock Internal clock MPφ Falling edge Rising edge N - 1 N N + 1 Figure 11.93 Count Timing in Internal Clock Operation (Channels 0 to 4) TCNT TCNT input clock Internal clock MPφ Rising edge N - 1 N Figure 11.94 Count Timing in Internal Clock Operation (Channel 5) MPφ TCNT TCNT input clock External clock Falling edge Rising edge N - 1 N N + 1 Figure 11.95 Count Timing in External Clock Operation (Channels 0 to 4)

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11.6.2 Interrupt Signal Timing

TGF Flag Setting Timing in Case of Compare Match: Figures 11.109 and 11.110 show the timing for setting of the TGF flag in TSR on compare match, and TGI interrupt request signal timing. TGR TCNT TCNT input clock N N N + 1 Compare match signal TGF flag TGI interrupt MPφ Figure 11.109 TGI Interrupt Timing (Compare Match) (Channels 0 to 4) TGR TCNT TCNT input clock N N - 1 N Compare match signal TGF flag TGI interrupt MPφ Figure 11.110 TGI Interrupt Timing (Compare Match) (Channel 5)

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11.7 Usage Notes

11.7.1 Module Standby Mode Setting

MTU2 operation can be disabled or enabled using the standby control register. The initial setting is for MTU2 operation to be halted. Register access is enabled by clearing module standby mode. For details, refer to section 26, Power-Down Modes.

11.7.2 Input Clock Restrictions

The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The MTU2 will not operate properly at narrower pulse widths. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure 11.120 shows the input clock conditions in phase counting mode. Overlap Phase differ- ence Phase differ- enceOverlap TCLKA (TCLKC) TCLKB (TCLKD) Pulse width Pulse width Pulse width Pulse width Notes: Phase difference and overlap Pulse width : 1.5 states or more : 2.5 states or more Figure 11.120 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode

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11.7.3 Caution on Period Setting

When counter clearing on compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula:

• Channels 0 to 4 f = MPφ (N + 1)
• Channel 5 f = MPφ N Where f: Counter frequency MP φ: MTU2 peripheral clock operating frequency N: TGR set value

11.7.4 Contention between TCNT Write and Clear Operations

If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 11.121 shows the timing in this case. Counter clear signal Write signal Address TCNT address TCNT TCNT write cycle T1 T2 N H'0000 MPφ Counter clear signal Write signal Address TCNT address TCNT TCNT write cycle T1 T2 N H'0000 MPφ Figure 11.121 Contention between TCNT Write and Clear Operations

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11.7.5 Contention between TCNT Write and Increment Operations

If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 11.122 shows the timing in this case. TCNT input clock Write signal Address TCNT address TCNT TCNT write cycle T1 T2 NM TCNT write data MPφ Figure 11.122 Contention between TCNT Write and Increment Operations

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11.7.6 Contention between TGR Write and Compare Match

If a compare match occurs in the T2 state of a TGR write cycle, the TGR write is executed and the compare match signal is also generated. Figure 11.123 shows the timing in this case. Compare match signal Write signal Address TGR address TCNT TGR write cycle T1 T2 NM TGR write data TGR N N + 1 MPφ Figure 11.123 Contention between TGR Write and Compare Match

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11.7.7 Contention between Buffer Register Write and Compare Match

If a compare match occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR by the buffer operation is the data before write. Figure 11.124 shows the timing in this case. Address Write signal Compare match signal Compare match buffer signal TGR write cycle T1 T2 Buffer register address N N M Buffer register write data Buffer register TGR MPφ Figure 11.124 Contention between Buffer Register Write and Compare Match

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11.7.8 Contention between Buffer Register Write and TCNT Clear

When the buffer transfer timing is set at the TCNT clear by the buffer transfer mode register (TBTM), if TCNT clear occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR by the buffer operation is the data before write. Figure 11.125 shows the timing in this case. Address Write signal TCNT clear signal Buffer transfer signal TGR write cycle T1 T2 Buffer register address N N M Buffer register write data Buffer register TGR MPφ Figure 11.125 Contention between Buffer Register Write and TCNT Clear

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11.7.9 Contention between TGR Read and Input Capture

If an input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data in the buffer before input capture transfer for channels 0 to 4, and the data after input capture transfer for channel 5. Figures 11.126 and 11.127 show the timing in this case. Input capture signal Read signal Address TGR read cycle T1 T2 TGR Internal data bus TGR address MPφ N N M Figure 11.126 Contention between TGR Read and Input Capture (Channels 0 to 4) Input capture signal Read signal Address TGR read cycle T1 T2 TGR Internal data bus TGR address MPφ M NM Figure 11.127 Contention between TGR Read and Input Capture (Channel 5)

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11.7.10 Contention between TGR Write and Input Capture

If an input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed for channels 0 to 4. For channel 5, write to TGR is performed and the input capture signal is generated. Figures 11.128 and 11.129 show the timing in this case. Input capture signal Write signal Address TCNT TGR write cycle T1 T2 MTGR M TGR address MPφ Figure 11.128 Contention between TGR Write and Input Capture (Channels 0 to 4) Input capture signal Write signal Address TCNT TGR write cycle T1 T2 NTGR M TGR address MPφ TGR write data Figure 11.129 Contention between TGR Write and Input Capture (Channel 5)

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11.7.11 Contention between Buffer Register Write and Input Capture

If an input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 11.130 shows the timing in this case. Input capture signal Write signal Address TCNT Buffer register write cycle T1 T2 NTGR N M MBuffer register Buffer register address MPφ Figure 11.130 Contention between Buffer Register Write and Input Capture

11.7.12 TCNT_2 Write and Overflow/Underflow Contention in Cascade Connection

With timer counters TCNT_1 and TCNT_2 in a cascade connection, when a contention occurs during TCNT_1 count (during a TCNT_2 overflow/underflow) in the T2 state of the TCNT_2 write cycle, the write to TCNT_2 is conducted, and the TCNT_1 count signal is disabled. At this point, if there is match with TGRA_1 and the TCNT_1 value, a compare signal is issued. Furthermore, when the TCNT_1 count clock is selected as the input capture source of channel 0, TGRA_0 to TGRD_0 carry out the input capture operation. In addition, when the compare match/input capture is selected as the input capture source of TGRB_1, TGRB_1 carries out input capture operation. The timing is shown in figure 11.131. For cascade connections, be sure to synchronize settings for channels 1 and 2 when setting TCNT clearing.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 633 of 1560 Mar 18, 2011 SH7080 Group T1 T2 H'FFFE H'FFFF N N + 1 H'FFFF M M N P QP M Disabled TCNT_2 write data TCNT_2 address TCNT write cycle Address Write signal TCNT_2 TGRA_2 to TGRB_2 Ch2 compare- match signal A/B TCNT_1 input clock TCNT_1 TGRA_1 Ch1 compare- match signal A TGRB_1 Ch1 input capture signal B TCNT_0 TGRA_0 to TGRD_0 Ch0 input capture signal A to D MPφ Figure 11.131 TCNT_2 Write and Overflow/Underflow Contention with Cascade Connection

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11.7.13 Counter Value during Complementary PWM Mode Stop

When counting operation is suspended with TCNT_3 and TCNT_4 in complementary PWM mode, TCNT_3 has the timer dead time register (TDDR) value, and TCNT_4 is held at H'0000. When restarting complementary PWM mode, counting begins automatically from the initialized state. This explanatory diagram is shown in figure 11.132. When counting begins in another operating mode, be sure that TCNT_3 and TCNT_4 are set to the initial values. TGRA_3 TCDR TDDR H'0000 TCNT_3 TCNT_4 Complementary PWM mode operation Complementary PWM mode operation Counter operation stop Complementary PMW restart Figure 11.132 Counter Value during Complementary PWM Mode Stop

11.7.14 Buffer Operation Setting in Complementary PWM Mode

In complementary PWM mode, conduct rewrites by buffer operation for the PWM cycle setting register (TGRA_3), timer cycle data register (TCDR), and duty setting registers (TGRB_3, TGRA_4, and TGRB_4). In complementary PWM mode, channel 3 and channel 4 buffers operate in accordance with bit settings BFA and BFB of TMDR_3. When TMDR_3's BFA bit is set to 1, TGRC_3 functions as a buffer register for TGRA_3. At the same time, TGRC_4 functions as the buffer register for TGRA_4, and TCBR functions as the TCDR's buffer register.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 635 of 1560 Mar 18, 2011 SH7080 Group

11.7.15 Reset Sync PWM Mode Buffer Operation and Compare Match Flag

When setting buffer operation for reset sync PWM mode, set the BFA and BFB bits in TMDR_4 to 0. The TIOC4C pin will be unable to produce its waveform output if the BFA bit in TMDR_4 is set to 1. In reset sync PWM mode, the channel 3 and channel 4 buffers operate in accordance with the BFA and BFB bit settings of TMDR_3. For example, if the BFA bit in TMDR_3 is set to 1, TGRC_3 functions as the buffer register for TGRA_3. At the same time, TGRC_4 functions as the buffer register for TGRA_4. The TGFC bit and TGFD bit in TSR_3 and TSR_4 are not set when TGRC_3 and TGRD_3 are operating as buffer registers. Figure 11.133 shows an example of operations for TGR_3, TGR_4, TIOC3, and TIOC4, with TMDR_3's BFA and BFB bits set to 1, and TMDR_4's BFA and BFB bits set to 0. TGRA_3 TGRC_3 TGRB_3, TGRA_4, TGRB_4 TGRD_3, TGRC_4, TGRD_4 H'0000 TIOC3A TIOC3B TIOC3D TIOC4A TIOC4C TIOC4B TIOC4D TGFC TGFD TGRA_3, TGRC_3 TGRB_3, TGRD_3, TGRA_4, TGRC_4, TGRB_4, TGRD_4 Buffer transfer with compare match A3TCNT3 Not set Not set Point a Point b Figure 11.133 Buffer Operation and Compare-Match Flags in Reset Synchronous PWM Mode

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11.7.16 Overflow Flags in Reset Synchronous PWM Mode

When set to reset synchronous PWM mode, TCNT_3 and TCNT_4 start counting when the CST3 bit of TSTR is set to 1. At this point, TCNT_4's count clock source and count edge obey the TCR_3 setting. In reset synchronous PWM mode, with cycle register TGRA_3's set value at H'FFFF, when specifying TGR3A compare-match for the counter clear source, TCNT_3 and TCNT_4 count up to H'FFFF, then a compare-match occurs with TGRA_3, and TCNT_3 and TCNT_4 are both cleared. At this point, TSR's overflow flag TCFV bit is not set. Figure 11.134 shows a TCFV bit operation example in reset synchronous PWM mode with a set value for cycle register TGRA_3 of H'FFFF, when a TGRA_3 compare-match has been specified without synchronous setting for the counter clear source. TGRA_3 (H'FFFF) H'0000 TCFV_3 TCFV_4 TCNT_3 = TCNT_4 Counter cleared by compare match 3A Not set Not set Figure 11.134 Reset Synchronous PWM Mode Overflow Flag

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11.7.17 Contention between Overflow/Underflow and Counter Clearing

If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 11.135 shows the operation timing when a TGR compare match is specified as the clearing source, and when H'FFFF is set in TGR. Counter clear signal TCNT TCNT input clock H'FFFF H'0000 TGF TCFV Disabled MPφ Figure 11.135 Contention between Overflow and Counter Clearing

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 638 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

11.7.18 Contention between TCNT Write and Overflow/Underflow

If there is an up-count or down-count in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 11.136 shows the operation timing when there is contention between TCNT write and overflow. Disabled Write signal Address TCNT address TCNT TCNT write cycle T1 T2 H'FFFF M TCNT write data TCFV flag MPφ Figure 11.136 Contention between TCNT Write and Overflow

11.7.19 Cautions on Transition from Normal Operation or PWM Mode 1 to Reset-

When making a transition from channel 3 or 4 normal operation or PWM mode 1 to reset- synchronized PWM mode, if the counter is halted with the output pins (TIOC3B, TIOC3D, TIOC4A, TIOC4C, TIOC4B, TIOC4D) in the high-level state, followed by the transition to reset- synchronized PWM mode and operation in that mode, the initial pin output will not be correct. When making a transition from normal operation to reset-synchronized PWM mode, write H'11 to registers TIORH_3, TIORL_3, TIORH_4, and TIORL_4 to initialize the output pins to low level output, then set an initial register value of H'00 before making the mode transition. When making a transition from PWM mode 1 to reset-synchronized PWM mode, first switch to normal operation, then initialize the output pins to low level output and set an initial register value of H'00 before making the transition to reset-synchronized PWM mode.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 639 of 1560 Mar 18, 2011 SH7080 Group

11.7.20 Output Level in Complementary PWM Mode and Reset-Synchronized PWM Mode

When channels 3 and 4 are in complementary PWM mode or reset-synchronized PWM mode, the PWM waveform output level is set with the OLSP and OLSN bits in the timer output control register (TOCR). In the case of complementary PWM mode or reset-synchronized PWM mode, TIOR should be set to H'00.

11.7.21 Interrupts in Module Standby Mode

If module standby mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DTC/DMAC activation source. Interrupts should therefore be disabled before entering module standby mode.

11.7.22 Simultaneous Capture of TCNT_1 and TCNT_2 in Cascade Connection

When timer counters 1 and 2 (TCNT_1 and TCNT_2) are operated as a 32-bit counter in cascade connection, the cascade counter value cannot be captured successfully even if input-capture input is simultaneously done to TIOC1A and TIOC2A or to TIOC1B and TIOC2B. This is because the input timing of TIOC1A and TIOC2A or of TIOC1B and TIOC2B may not be the same when external input-capture signals to be input into TCNT_1 and TCNT_2 are taken in synchronization with the internal clock. For example, TCNT_1 (the counter for upper 16 bits) does not capture the count-up value by overflow from TCNT_2 (the counter for lower 16 bits) but captures the count value before the count-up. In this case, the values of TCNT_1 = H'FFF1 and TCNT_2 = H'0000 should be transferred to TGRA_1 and TGRA_2 or to TGRB_1 and TGRB_2, but the values of TCNT_1 = H'FFF0 and TCNT_2 = H'0000 are erroneously transferred. The MTU2 has a new function that allows simultaneous capture of TCNT_1 and TCNT_2 with a single input-capture input as the trigger. This function allows reading of the 32-bit counter such that TCNT_1 and TCNT_2 are captured at the same time. For details, see section, 11.3.8, Timer Input Capture Control Register (TICCR).

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 640 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

11.7.23 Notes on Output Waveform Control During Synchronous Counter Clearing in

In complementary PWM mode, when output waveform control during synchronous counter clearing is enabled (WRE in the TWCR register set to 1), the following problems may occur when condition (1) or condition (2), below, is satisfied.

• Dead time for the PWM output pins may be too short (or nonexistent).
• Active-level output from the PWM negative-phase pins may occur outside the correct active- level output interval Condition (1): When synchronous clearing occurs in the PWM output dead time interval within initial output suppression interval (10) (figure 11.137). Condition (2): When synchronous clearing occurs within initial output suppression interval (10) or (11) and TGRB_3 ≤ TDDR, TGRA_4 ≤ TDDR, or TGRB_4 ≤ TDDR is true (figure 11.138). TCNT3 TCNT4 TDDR TGRA_3 TGR TDDR Synchronous clearing Dead time Note: PWM output is low-active. PWM output (positive phase) PWM output (negative phase) Shortened dead time Initial output suppression Tb interval Tb interval (10) (10)(11) (11) Figure 11.137 Condition (1) Synchronous Clearing Example

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 641 of 1560 Mar 18, 2011 SH7080 Group TCNT3 TCNT4 TGRA_3 TGR TDDR Synchronous clearing Dead time Note: PWM output is low-active. PWM output (positive phase) PWM output (negative phase) Initial output suppression Tb interval Tb interval Active-level output occurs at synchronous clearing even though no active-level output interval has been set. Nonexistent dead time Figure 10.138 Condition (2) Synchronous Clearing Example The following workaround can be used to avoid these problems. When using synchronous clearing, make sure to set compare registers TGRB_3, TGRA_4, and TGRB_4 to a value twice or more the setting of dead time data register TDDR.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 642 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

11.8 MTU2 Output Pin Initialization

11.8.1 Operating Modes

The MTU2 has the following six operating modes. Waveform output is possible in all of these modes.

• Normal mode (channels 0 to 4)
• PWM mode 1 (channels 0 to 4)
• PWM mode 2 (channels 0 to 2)
• Phase counting modes 1 to 4 (channels 1 and 2)
• Complementary PWM mode (channels 3 and 4)
• Reset-synchronized PWM mode (channels 3 and 4) The MTU2 output pin initialization method for each of these modes is described in this section.

11.8.2 Reset Start Operation

The MTU2 output pins (TIOC*) are initialized low by a reset and in standby mode. Since MTU2 pin function selection is performed by the pin function controller (PFC), when the PFC is set, the MTU2 pin states at that point are output to the ports. When MTU2 output is selected by the PFC immediately after a reset, the MTU2 output initial level, low, is output directly at the port. When the active level is low, the system will operate at this point, and therefore the PFC setting should be made after initialization of the MTU2 output pins is completed. Note: Channel number and port notation are substituted for *.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 643 of 1560 Mar 18, 2011 SH7080 Group 11.8.3 Operation in Case of Re-Setting Due to Error During Operation, etc. If an error occurs during MTU2 operation, MTU2 output should be cut by the system. Cutoff is performed by switching the pin output to port output with the PFC and outputting the inverse of the active level. For large-current pins, output can also be cut by hardware, using port output enable (POE). The pin initialization procedures for re-setting due to an error during operation, etc., and the procedures for restarting in a different mode after re-setting, are shown below. The MTU2 has six operating modes, as stated above. There are thus 36 mode transition combinations, but some transitions are not available with certain channel and mode combinations. Possible mode transition combinations are shown in table 11.59. Table 11.59 Mode Transition Combinations After Before Normal PWM1 PWM2 PCM CPWM RPWM PWM2 (13) (14) (15) (16) None None PCM (17) (18) (19) (20) None None CPWM (21) (22) None None (23) (24) (25) RPWM (26) (27) None None (28) (29) [Legend] Normal: Normal mode PWM1: PWM mode 1 PWM2: PWM mode 2 PCM: Phase counting modes 1 to 4 CPWM: Complementary PWM mode RPWM: Reset-synchronized PWM mode

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 644 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

11.8.4 Overview of Initialization Procedures and Mode Transitions in Case of Error

during Operation, etc.

• When making a transition to a mode (Normal, PWM1, PWM2, PCM) in which the pin output level is selected by the timer I/O control register (TIOR) setting, initialize the pins by means of a TIOR setting.
• In PWM mode 1, since a waveform is not output to the TIOC*B (TIOC *D) pin, setting TIOR will not initialize the pins. If initialization is required, carry it out in normal mode, then switch to PWM mode 1.
• In PWM mode 2, since a waveform is not output to the cycle register pin, setting TIOR will not initialize the pins. If initialization is required, carry it out in normal mode, then switch to PWM mode 2.
• In normal mode or PWM mode 2, if TGRC and TGRD operate as buffer registers, setting TIOR will not initialize the buffer register pins. If initialization is required, clear buffer mode, carry out initialization, then set buffer mode again.
• In PWM mode 1, if either TGRC or TGRD operates as a buffer register, setting TIOR will not initialize the TGRC pin. To initialize the TGRC pin, clear buffer mode, carry out initialization, then set buffer mode again.
• When making a transition to a mode (CPWM, RPWM) in which the pin output level is selected by the timer output control register (TOCR) setting, switch to normal mode and perform initialization with TIOR, then restore TIOR to its initial value, and temporarily disable channel 3 and 4 output with the timer output master enable register (TOER). Then operate the unit in accordance with the mode setting procedure (TOCR setting, TMDR setting, TOER setting). Note: Channel number is substituted for * indicated in this article.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 645 of 1560 Mar 18, 2011 SH7080 Group Pin initialization procedures are described below for the numbered combinations in table 11.59. The active level is assumed to be low. Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Normal Mode: Figure 11.139 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in normal mode after re-setting. RESET TMDR (normal) TOER (1) PFC (MTU2) TIOR (1 init 0 out) TSTR (1) Match Error occurs PFC (PORT) TSTR (0) TMDR (normal) TIOR (1 init 0 out) PFC (MTU2) TSTR (1) MTU2 module output TIOC*A TIOC*B Port output PEn PEn n = 0 to 15 Hi-Z Hi-Z Figure 11.139 Error Occurrence in Normal Mode, Recovery in Normal Mode 1. After a reset, MTU2 output is low a nd ports are in the high-impedance state. 2. After a reset, the TMDR setting is for normal mode. 3. For channels 3 and 4, enable output with TOER before initializing the pins with TIOR. 4. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence.) 5. Set MTU2 output with the PFC. 6. The count operation is started by TSTR. 7. Output goes low on compare-match occurrence. 8. An error occurs. 9. Set port output with the PFC and output the inverse of the active level. 10. The count operation is stopped by TSTR. 11. Not necessary when restarting in normal mode. 12. Initialize the pins with TIOR. 13. Set MTU2 output with the PFC. 14. Operation is restarted by TSTR.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 646 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in PWM Mode 1: Figure 11.140 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in PWM mode 1 after re-setting. RESET TMDR (normal) TOER (1) PFC (MTU2) TIOR (1 init 0 out) TSTR (1) Match Error occurs PFC (PORT) TSTR (0) TMDR (PWM1) TIOR (1 init 0 out) PFC (MTU2) TSTR (1) MTU2 module output TIOC*A TIOC*B Port output PEn PEn Not initialized (TIOC*B) n = 0 to 15 Hi-Z Hi-Z Figure 11.140 Error Occurrence in Normal Mode, Recovery in PWM Mode 1 1 to 10 are the same as in figure 11.139. 11. Set PWM mode 1. 12. Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized. If initialization is required, initialize in normal mode, then switch to PWM mode 1.) 13. Set MTU2 output with the PFC. 14. Operation is restarted by TSTR.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 647 of 1560 Mar 18, 2011 SH7080 Group Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in PWM Mode 2: Figure 11.141 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in PWM mode 2 after re-setting. RESET TMDR (normal) TOER (1) PFC (MTU2) TIOR (1 init 0 out) TSTR (1) Match Error occurs PFC (PORT) TSTR (0) TMDR (PWM2) TIOR (1 init 0 out) PFC (MTU2) TSTR (1) MTU2 module output TIOC*A TIOC*B Port output PEn PEn Not initialized (cycle register) n = 0 to 15 Hi-Z Hi-Z Figure 11.141 Error Occurrence in Normal Mode, Recovery in PWM Mode 2 1 to 10 are the same as in figure 11.139. 11. Set PWM mode 2. 12. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized. If initialization is required, initialize in normal mode, then switch to PWM mode 2.) 13. Set MTU2 output with the PFC. 14. Operation is restarted by TSTR. Note: PWM mode 2 can only be set for channels 0 to 2, and therefore TOER setting is not necessary.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 648 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Phase Counting Mode: Figure 11.142 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in phase counting mode after re-setting. RESET TMDR (normal) TOER (1) PFC (MTU2) TIOR (1 init 0 out) TSTR (1) Match Error occurs PFC (PORT) TSTR (0) TMDR (PCM) TIOR (1 init 0 out) PFC (MTU2) TSTR (1) MTU2 module output TIOC*A TIOC*B Port output PEn PEn n = 0 to 15 Hi-Z Hi-Z Figure 11.142 Error Occurrence in Normal Mode, Recovery in Phase Counting Mode 1 to 10 are the same as in figure 11.139. 11. Set phase counting mode. 12. Initialize the pins with TIOR. 13. Set MTU2 output with the PFC. 14. Operation is restarted by TSTR. Note: Phase counting mode can only be set for channels 1 and 2, and therefore TOER setting is not necessary.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 649 of 1560 Mar 18, 2011 SH7080 Group Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Complementary PWM Mode: Figure 11.143 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in complementary PWM mode after re- setting. RESET TMDR (normal) TOER (1) PFC (MTU2) TIOR (1 init 0 out) TSTR (1) Match Error occurs PFC (PORT) TSTR (0) TIOR (0 init 0 out) TIOR (disabled) TOER (0) TOCR TMDR (CPWM) TOER (1) PFC (MTU2) TSTR (1) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 Hi-Z Hi-Z Hi-Z Figure 11.143 Error Occurrence in Normal Mode, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 11.139. 11. Initialize the normal mode waveform generation section with TIOR. 12. Disable operation of the normal mode waveform generation section with TIOR. 13. Disable channel 3 and 4 output with TOER. 14. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR. 15. Set complementary PWM. 16. Enable channel 3 and 4 output with TOER. 17. Set MTU2 output with the PFC. 18. Operation is restarted by TSTR.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 650 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Reset-Synchronized PWM Mode: Figure 11.144 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in reset-synchronized PWM mode after re-setting. RESET TMDR (normal) TOER (1) PFC (MTU2) TIOR (1 init 0 out) TSTR (1) Match Error occurs PFC (PORT) TSTR (0) TIOR (0 init 0 out) TIOR (disabled) TOER (0) TOCR TMDR (RPWM) TOER (1) PFC (MTU2) TSTR (1) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 Hi-Z Hi-Z Hi-Z Figure 11.144 Error Occurrence in Normal Mode, Recovery in Reset-Synchronized PWM Mode 1 to 13 are the same as in figure 11.139. 14. Select the reset-synchronized PWM output level and cyclic output enabling/disabling with TOCR. 15. Set reset-synchronized PWM. 16. Enable channel 3 and 4 output with TOER. 17. Set MTU2 output with the PFC. 18. Operation is restarted by TSTR.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 651 of 1560 Mar 18, 2011 SH7080 Group Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Normal Mode: Figure 11.145 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in normal mode after re-setting. RESET TMDR (PWM1) TOER (1) PFC (MTU2) TIOR (1 init 0 out) TSTR (1) Match Error occurs PFC (PORT) TSTR (0) TMDR (normal) TIOR (1 init 0 out) PFC (MTU2) TSTR (1) MTU2 module output TIOC*A TIOC*B Port output PEn PEn Not initialized (TIOC*B) n = 0 to 15 Hi-Z Hi-Z Figure 11.145 Error Occurrence in PWM Mode 1, Recovery in Normal Mode 1. After a reset, MTU2 output is low a nd ports are in the high-impedance state. 2. Set PWM mode 1. 3. For channels 3 and 4, enable output with TOER before initializing the pins with TIOR. 4. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence. In PWM mode 1, the TIOC*B side is not initialized.) 5. Set MTU2 output with the PFC. 6. The count operation is started by TSTR. 7. Output goes low on compare-match occurrence. 8. An error occurs. 9. Set port output with the PFC and output the inverse of the active level. 10. The count operation is stopped by TSTR. 11. Set normal mode. 12. Initialize the pins with TIOR. 13. Set MTU2 output with the PFC. 14. Operation is restarted by TSTR.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 652 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in PWM Mode 1: Figure 11.146 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in PWM mode 1 after re-setting. RESET TMDR (PWM1) TOER (1) PFC (MTU2) TIOR (1 init 0 out) TSTR (1) Match Error occurs PFC (PORT) TSTR (0) TMDR (PWM1) TIOR (1 init 0 out) PFC (MTU2) TSTR (1) MTU2 module output TIOC*A TIOC*B Port output PEn PEn Not initialized (TIOC*B) Not initialized (TIOC*B) n = 0 to 15 Hi-Z Hi-Z Figure 11.146 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 1 1 to 10 are the same as in figure 11.145. 11. Not necessary when restarting in PWM mode 1. 12. Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized.) 13. Set MTU2 output with the PFC. 14. Operation is restarted by TSTR.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 653 of 1560 Mar 18, 2011 SH7080 Group Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in PWM Mode 2: Figure 11.147 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in PWM mode 2 after re-setting. RESET TMDR (PWM1) TOER (1) PFC (MTU2) TIOR (1 init 0 out) TSTR (1) Match Error occurs PFC (PORT) TSTR (0) TMDR (PWM2) TIOR (1 init 0 out) PFC (MTU2) TSTR (1) MTU2 module output TIOC*A TIOC*B Port output PEn PEn Not initialized (TIOC*B) Not initialized (cycle register) n = 0 to 15 Hi-Z Hi-Z Figure 11.147 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 2 1 to 10 are the same as in figure 11.145. 11. Set PWM mode 2. 12. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.) 13. Set MTU2 output with the PFC. 14. Operation is restarted by TSTR. Note: PWM mode 2 can only be set for channels 0 to 2, and therefore TOER setting is not necessary.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 654 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Phase Counting Mode: Figure 11.148 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in phase counting mode after re-setting. RESET TMDR (PWM1) TOER (1) PFC (MTU2) TIOR (1 init 0 out) TSTR (1) Match Error occurs PFC (PORT) TSTR (0) TMDR (PCM) TIOR (1 init 0 out) PFC (MTU2) TSTR (1) MTU2 module output TIOC*A TIOC*B Port output PEn PEn Not initialized (TIOC*B) n = 0 to 15 Hi-Z Hi-Z Figure 11.148 Error Occurrence in PWM Mode 1, Recovery in Phase Counting Mode 1 to 10 are the same as in figure 11.145. 11. Set phase counting mode. 12. Initialize the pins with TIOR. 13. Set MTU2 output with the PFC. 14. Operation is restarted by TSTR. Note: Phase counting mode can only be set for channels 1 and 2, and therefore TOER setting is not necessary.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 655 of 1560 Mar 18, 2011 SH7080 Group Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Complementary PWM Mode: Figure 11.149 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in complementary PWM mode after re- setting. RESET TMDR (PWM1) TOER (1) PFC (MTU2) TIOR (1 init 0 out) TSTR (1) Match Error occurs PFC (PORT) TSTR (0) TMDR (normal) TIOR (0 init 0 out) TIOR (disabled) TOER (0) TOCR TMDR (CPWM) TOER (1) PFC (MTU2) TSTR (1) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 Not initialized (TIOC3B) Not initialized (TIOC3D) Hi-Z Hi-Z Hi-Z Figure 11.149 Error Occurrence in PWM Mode 1, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 11.145. 11. Set normal mode for initialization of the normal mode waveform generation section. 12. Initialize the PWM mode 1 waveform generation section with TIOR. 13. Disable operation of the PWM mode 1 waveform generation section with TIOR. 14. Disable channel 3 and 4 output with TOER. 15. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR. 16. Set complementary PWM. 17. Enable channel 3 and 4 output with TOER. 18. Set MTU2 output with the PFC. 19. Operation is restarted by TSTR.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 656 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Reset-Synchronized PWM Mode: Figure 11.150 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in reset-synchronized PWM mode after re-setting. RESET TMDR (PWM1) TOER (1) PFC (MTU2) TIOR (1 init 0 out) TSTR (1) Match Error occurs PFC (PORT) TSTR (0) TMDR (normal) TIOR (0 init 0 out) TIOR (disabled) TOER (0) TOCR TMDR (RPWM) TOER (1) PFC (MTU2) TSTR (1) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 Not initialized (TIOC3B) Not initialized (TIOC3D) Hi-Z Hi-Z Hi-Z Figure 11.150 Error Occurrence in PWM Mode 1, Recovery in Reset-Synchronized PWM Mode 1 to 14 are the same as in figure 11.149. 15. Select the reset-synchronized PWM output level and cyclic output enabling/disabling with TOCR. 16. Set reset-synchronized PWM. 17. Enable channel 3 and 4 output with TOER. 18. Set MTU2 output with the PFC. 19. Operation is restarted by TSTR.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 657 of 1560 Mar 18, 2011 SH7080 Group Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in Normal Mode: Figure 11.151 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in normal mode after re-setting. RESET TMDR (PWM2) TIOR (1 init 0 out) TSTR (1) PFC (MTU2) Match Error occurs PFC (PORT) TSTR (0) TMDR (normal) TIOR (1 init 0 out) PFC (MTU2) TSTR (1) MTU2 module output TIOC*A TIOC*B Port output PEn PEn Not initialized (cycle register) n = 0 to 15 Hi-Z Hi-Z Figure 11.151 Error Occurrence in PWM Mode 2, Recovery in Normal Mode 1. After a reset, MTU2 output is low a nd ports are in the high-impedance state. 2. Set PWM mode 2. 3. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence. In PWM mode 2, the cycle register pins are not initialized. In the example, TIOC *A is the cycle register.) 4. Set MTU2 output with the PFC. 5. The count operation is started by TSTR. 6. Output goes low on compare-match occurrence. 7. An error occurs. 8. Set port output with the PFC and output the inverse of the active level. 9. The count operation is stopped by TSTR. 10. Set normal mode. 11. Initialize the pins with TIOR. 12. Set MTU2 output with the PFC. 13. Operation is restarted by TSTR.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 658 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in PWM Mode 1: Figure 11.152 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in PWM mode 1 after re-setting. RESET TMDR (PWM2) TIOR (1 init 0 out) TSTR (1) PFC (MTU2) Match Error occurs PFC (PORT) TSTR (0) TMDR (PWM1) TIOR (1 init 0 out) PFC (MTU2) TSTR (1) MTU2 module output TIOC*A TIOC*B Port output PEn PEn Not initialized (TIOC*B) Not initialized (cycle register) n = 0 to 15 Hi-Z Hi-Z Figure 11.152 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 1 1 to 9 are the same as in figure 11.151. 10. Set PWM mode 1. 11. Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized.) 12. Set MTU2 output with the PFC. 13. Operation is restarted by TSTR.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 659 of 1560 Mar 18, 2011 SH7080 Group Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in PWM Mode 2: Figure 11.153 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in PWM mode 2 after re-setting. RESET TMDR (PWM2) TIOR (1 init 0 out) TSTR (1) PFC (MTU2) Match Error occurs PFC (PORT) TSTR (0) TMDR (PWM2) TIOR (1 init 0 out) PFC (MTU2) TSTR (1) MTU2 module output TIOC*A TIOC*B Port output PEn PEn Not initialized (cycle register) Not initialized (cycle register) n = 0 to 15 Hi-Z Hi-Z Figure 11.153 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 2 1 to 9 are the same as in figure 11.151. 10. Not necessary when restarting in PWM mode 2. 11. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.) 12. Set MTU2 output with the PFC. 13. Operation is restarted by TSTR.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 660 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in Phase Counting Mode: Figure 11.154 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in phase counting mode after re-setting. RESET TMDR (PWM2) TIOR (1 init 0 out) TSTR (1) PFC (MTU2) Match Error occurs PFC (PORT) TSTR (0) TMDR (PCM) TIOR (1 init 0 out) PFC (MTU2) TSTR (1) MTU2 module output TIOC*A TIOC*B Port output PEn PEn Not initialized (cycle register) n = 0 to 15 Hi-Z Hi-Z Figure 11.154 Error Occurrence in PWM Mode 2, Recovery in Phase Counting Mode 1 to 9 are the same as in figure 11.151. 10. Set phase counting mode. 11. Initialize the pins with TIOR. 12. Set MTU2 output with the PFC. 13. Operation is restarted by TSTR.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 661 of 1560 Mar 18, 2011 SH7080 Group Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in Normal Mode: Figure 11.155 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in normal mode after re-setting. RESET TMDR (PCM) TIOR (1 init 0 out) TSTR (1) PFC (MTU2) Match Error occurs PFC (PORT) TSTR (0) TMDR (normal) TIOR (1 init 0 out) PFC (MTU2) TSTR (1) MTU2 module output TIOC*A TIOC*B Port output PEn PEn n = 0 to 15 Hi-Z Hi-Z Figure 11.155 Error Occurrence in Phase Counting Mode, Recovery in Normal Mode 1. After a reset, MTU2 output is low a nd ports are in the high-impedance state. 2. Set phase counting mode. 3. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence.) 4. Set MTU2 output with the PFC. 5. The count operation is started by TSTR. 6. Output goes low on compare-match occurrence. 7. An error occurs. 8. Set port output with the PFC and output the inverse of the active level. 9. The count operation is stopped by TSTR. 10. Set in normal mode. 11. Initialize the pins with TIOR. 12. Set MTU2 output with the PFC. 13. Operation is restarted by TSTR.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 662 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in PWM Mode 1: Figure 11.156 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in PWM mode 1 after re-setting. RESET TMDR (PCM) TIOR (1 init 0 out) TSTR (1) PFC (MTU2) Match Error occurs PFC (PORT) TSTR (0) TMDR (PWM1) TIOR (1 init 0 out) PFC (MTU2) TSTR (1) MTU2 module output TIOC*A TIOC*B Port output PEn PEn Not initialized (TIOC*B) n = 0 to 15 Hi-Z Hi-Z Figure 11.156 Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 1 1 to 9 are the same as in figure 11.155. 10. Set PWM mode 1. 11. Initialize the pins with TIOR. (In PWM mode 1, the TIOC *B side is not initialized.) 12. Set MTU2 output with the PFC. 13. Operation is restarted by TSTR.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 663 of 1560 Mar 18, 2011 SH7080 Group Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in PWM Mode 2: Figure 11.157 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in PWM mode 2 after re-setting. RESET TMDR (PCM) TIOR (1 init 0 out) TSTR (1) PFC (MTU2) Match Error occurs PFC (PORT) TSTR (0) TMDR (PWM2) TIOR (1 init 0 out) PFC (MTU2) TSTR (1) MTU2 module output TIOC*A TIOC*B Port output PEn PEn n = 0 to 15 Hi-Z Hi-Z Not initialized (cycle register) Figure 11.157 Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 2 1 to 9 are the same as in figure 11.155. 10. Set PWM mode 2. 11. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.) 12. Set MTU2 output with the PFC. 13. Operation is restarted by TSTR.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 664 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in Phase Counting Mode: Figure 11.158 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in phase counting mode after re-setting. RESET TMDR (PCM) TIOR (1 init 0 out) TSTR (1) PFC (MTU2) Match Error occurs PFC (PORT) TSTR (0) TMDR (PCM) TIOR (1 init 0 out) PFC (MTU2) TSTR (1) MTU2 module output TIOC*A TIOC*B Port output PEn PEn n = 0 to 15 Hi-Z Hi-Z Figure 11.158 Error Occurrence in Phase Counting Mode, Recovery in Phase Counting Mode 1 to 9 are the same as in figure 11.155. 10. Not necessary when restarting in phase counting mode. 11. Initialize the pins with TIOR. 12. Set MTU2 output with the PFC. 13. Operation is restarted by TSTR.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 665 of 1560 Mar 18, 2011 SH7080 Group Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Normal Mode: Figure 11.159 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in normal mode after re-setting. RESET TOCR TMDR (CPWM) PFC (MTU2) TOER (1) TSTR (1) Match Error occurs PFC (PORT) TSTR (0) TMDR (normal) TIOR (1 init 0 out) PFC (MTU2) TSTR (1) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 Hi-Z Hi-Z Hi-Z Figure 11.159 Error Occurrence in Complementary PWM Mode, Recovery in Normal Mode 1. After a reset, MTU2 output is low a nd ports are in the high-impedance state. 2. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR. 3. Set complementary PWM. 4. Enable channel 3 and 4 output with TOER. 5. Set MTU2 output with the PFC. 6. The count operation is started by TSTR. 7. The complementary PWM waveform is output on compare-match occurrence. 8. An error occurs. 9. Set port output with the PFC and output the inverse of the active level. 10. The count operation is stopped by TSTR. (MTU2 output becomes the complementary PWM output initial value.) 11. Set normal mode. (MTU2 output goes low.) 12. Initialize the pins with TIOR. 13. Set MTU2 output with the PFC. 14. Operation is restarted by TSTR.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 666 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in PWM Mode 1: Figure 11.160 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in PWM mode 1 after re-setting. RESET TOCR TMDR (CPWM) PFC (MTU2) TOER (1) TSTR (1) Match Error occurs PFC (PORT) TSTR (0) TMDR (PWM1) TIOR (1 init 0 out) PFC (MTU2) TSTR (1) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 Not initialized (TIOC3B) Not initialized (TIOC3D) Hi-Z Hi-Z Hi-Z Figure 11.160 Error Occurrence in Complementary PWM Mode, Recovery in PWM Mode 1 1 to 10 are the same as in figure 11.159. 11. Set PWM mode 1. (MTU2 output goes low.) 12. Initialize the pins with TIOR. (In PWM mode 1, the TIOC *B side is not initialized.) 13. Set MTU2 output with the PFC. 14. Operation is restarted by TSTR.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 667 of 1560 Mar 18, 2011 SH7080 Group Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode: Figure 11.161 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in complementary PWM mode after re-setting (when operation is restarted using the cycle and duty settings at the time the counter was stopped). RESET TOCR TMDR (CPWM) PFC (MTU2) TOER (1) TSTR (1) Match Error occurs PFC (PORT) TSTR (0) PFC (MTU2) TSTR (1) Match MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 Hi-Z Hi-Z Hi-Z Figure 11.161 Error Occurrence in Complementary PWM Mode, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 11.159. 11. Set MTU2 output with the PFC. 12. Operation is restarted by TSTR. 13. The complementary PWM waveform is output on compare-match occurrence.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 668 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode: Figure 11.162 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in complementary PWM mode after re-setting (when operation is restarted using completely new cycle and duty settings). RESET TOCR TMDR (CPWM) PFC (MTU2) TOER (1) TSTR (1) Match Error occurs PFC (PORT) TSTR (0) TMDR (normal) TOER (0) TOCR TMDR (CPWM) TOER (1) PFC (MTU2) TSTR (1) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 Hi-Z Hi-Z Hi-Z Figure 11.162 Error Occurrence in Complementary PWM Mode, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 11.159. 11. Set normal mode and make new settings. (MTU2 output goes low.) 12. Disable channel 3 and 4 output with TOER. 13. Select the complementary PWM mode output level and cyclic output enabling/disabling with TOCR. 14. Set complementary PWM. 15. Enable channel 3 and 4 output with TOER. 16. Set MTU2 output with the PFC. 17. Operation is restarted by TSTR.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 669 of 1560 Mar 18, 2011 SH7080 Group Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Reset-Synchronized PWM Mode: Figure 11.163 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in reset-synchronized PWM mode after re-setting. RESET TOCR TMDR (CPWM) PFC (MTU2) TOER (1) TSTR (1) Match Error occurs PFC (PORT) TSTR (0) TMDR (normal) TOER (0) TOCR TMDR (RPWM) TOER (1) PFC (MTU2) TSTR (1) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 Hi-Z Hi-Z Hi-Z Figure 11.163 Error Occurrence in Complementary PWM Mode, Recovery in Reset-Synchronized PWM Mode 1 to 10 are the same as in figure 11.159. 11. Set normal mode. (MTU2 output goes low.) 12. Disable channel 3 and 4 output with TOER. 13. Select the reset-synchronized PWM mode output level and cyclic output enabling/disabling with TOCR. 14. Set reset-synchronized PWM. 15. Enable channel 3 and 4 output with TOER. 16. Set MTU2 output with the PFC. 17. Operation is restarted by TSTR.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 670 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Operation when Error Occurs during Reset-Synchronized PWM Mode Operation, and Operation is Restarted in Normal Mode: Figure 11.164 shows an explanatory diagram of the case where an error occurs in reset-synchronized PWM mode and operation is restarted in normal mode after re-setting. RESET TOCR TMDR (RPWM) PFC (MTU2) TOER (1) TSTR (1) Match Error occurs PFC (PORT) TSTR (0) TMDR (normal) TIOR (1 init 0 out) PFC (MTU2) TSTR (1) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 Hi-Z Hi-Z Hi-Z Figure 11.164 Error Occurrence in Reset-Synchronized PWM Mode, Recovery in Normal Mode 1. After a reset, MTU2 output is low a nd ports are in the high-impedance state. 2. Select the reset-synchronized PWM output level and cyclic output enabling/disabling with TOCR. 3. Set reset-synchronized PWM. 4. Enable channel 3 and 4 output with TOER. 5. Set MTU2 output with the PFC. 6. The count operation is started by TSTR. 7. The reset-synchronized PWM waveform is output on compare-match occurrence. 8. An error occurs. 9. Set port output with the PFC and output the inverse of the active level. 10. The count operation is stopped by TSTR. (MTU2 output becomes the reset-synchronized PWM output initial value.) 11. Set normal mode. (MTU2 positive phase output is low, and negative phase output is high.) 12. Initialize the pins with TIOR. 13. Set MTU2 output with the PFC. 14. Operation is restarted by TSTR.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 671 of 1560 Mar 18, 2011 SH7080 Group Operation when Error Occurs during Reset-Synchronized PWM Mode Operation, and Operation is Restarted in PWM Mode 1: Figure 11.165 shows an explanatory diagram of the case where an error occurs in reset-synchronized PWM mode and operation is restarted in PWM mode 1 after re-setting. RESET TOCR TMDR (RPWM) PFC (MTU2) TOER (1) TSTR (1) Match Error occurs PFC (PORT) TSTR (0) TMDR (PWM1) TIOR (1 init 0 out) PFC (MTU2) TSTR (1) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 Not initialized (TIOC3B) Not initialized (TIOC3D) Hi-Z Hi-Z Hi-Z Figure 11.165 Error Occurrence in Reset-Synchronized PWM Mode, Recovery in PWM Mode 1 1 to 10 are the same as in figure 11.164. 11. Set PWM mode 1. (MTU2 positive phase output is low, and negative phase output is high.) 12. Initialize the pins with TIOR. (In PWM mode 1, the TIOC *B side is not initialized.) 13. Set MTU2 output with the PFC. 14. Operation is restarted by TSTR.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 672 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Operation when Error Occurs during Reset-Synchronized PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode: Figure 11.166 shows an explanatory diagram of the case where an error occurs in reset-synchronized PWM mode and operation is restarted in complementary PWM mode after re-setting. RESET TOCR TMDR (RPWM) PFC (MTU2) TOER (1) TSTR (1) Match Error occurs PFC (PORT) TSTR (0) TOER (0) TOCR TMDR (CPWM) TOER (1) PFC (MTU2) TSTR (1) MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 Hi-Z Hi-Z Hi-Z Figure 11.166 Error Occurrence in Reset-Synchronized PWM Mode, Recovery in Complementary PWM Mode 1 to 10 are the same as in figure 11.164. 11. Disable channel 3 and 4 output with TOER. 12. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR. 13. Set complementary PWM. (The MTU2 cyclic output pin goes low.) 14. Enable channel 3 and 4 output with TOER. 15. Set MTU2 output with the PFC. 16. Operation is restarted by TSTR.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) R01UH0198EJ0500 Rev. 5.00 Page 673 of 1560 Mar 18, 2011 SH7080 Group Operation when Error Occurs during Reset-Synchronized PWM Mode Operation, and Operation is Restarted in Reset-Synchronized PWM Mode: Figure 11.167 shows an explanatory diagram of the case where an error occurs in reset-synchronized PWM mode and operation is restarted in reset-synchronized PWM mode after re-setting. RESET TOCR TMDR (RPWM) PFC (MTU2) TOER (1) TSTR (1) Match Error occurs PFC (PORT) TSTR (0) PFC (MTU2) TSTR (1) Match MTU2 module output TIOC3A TIOC3B TIOC3D Port output PE9 PE8 PE11 Hi-Z Hi-Z Hi-Z Figure 11.167 Error Occurrence in Reset-Synchronized PWM Mode, Recovery in Reset-Synchronized PWM Mode 1 to 10 are the same as in figure 11.164. 11. Set MTU2 output with the PFC. 12. Operation is restarted by TSTR. 13. The reset-synchronized PWM waveform is output on compare-match occurrence.

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2) Page 674 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

Section 12 Multi-Function Timer Pulse Unit 2S (MTU2S) R01UH0198EJ0500 Rev. 5.00 Page 675 of 1560 Mar 18, 2011 SH7080 Group Section 12 Multi-Function Timer Pulse Unit 2S (MTU2S) This LSI has an on-chip multi-function timer pulse unit 2S (MTU2S) that comprises three 16-bit timer channels. The MTU2S includes channels 3 to 5 of the MTU2. For details, refer to section 11, Multi-Function Timer Pulse Unit 2 (MTU2). To distinguish from the MTU2, "S" is added to the end of the MTU2S input/output pin and register names. For example, TIOC3A is called TIOC3AS and TGRA_3 is called TGRA_3S in this section. The MTU2S can operate at 80 MHz max. for complementary PWM output functions or at 40 MHz max. for the other functions.

Section 12 Multi-Function Timer Pulse Unit 2S (MTU2S) Page 676 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 12.1 MTU2S Functions Item Channel 3 Channel 4 Channel 5 Count clock MI φ/1 MIφ/4 MIφ/16 MIφ/64 MIφ/256 MIφ/1024 MIφ/1 MIφ/4 MIφ/16 MIφ/64 MIφ/256 MIφ/1024 MIφ/1 MIφ/4 MIφ/16 MIφ/64 General registers (TGR) TGRA_3S TGRB_3S TGRA_4S TGRB_4S TGRU_5S TGRV_5S TGRW_5S General registers/ buffer registers TGRC_3S TGRD_3S TGRC_4S TGRD_4S I/O pins TIOC3AS TIOC3BS TIOC3CS TIOC3DS TIOC4AS TIOC4BS TIOC4CS TIOC4DS Input pins TIC5US TIC5VS TIC5WS Counter clear function TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture 0 output √ √ — 1 output √ √ — Compare match output Toggle output √ √ — Input capture function √ √ √ Synchronous operation √ √ — PWM mode 1 √ √ — PWM mode 2 — — — Complementary PWM mode √ √ — Reset PWM mode √ √ — AC synchronous motor drive mode — — — Phase counting mode — — — Buffer operation √ √ —

Section 12 Multi-Function Timer Pulse Unit 2S (MTU2S) R01UH0198EJ0500 Rev. 5.00 Page 677 of 1560 Mar 18, 2011 SH7080 Group Item Channel 3 Channel 4 Channel 5 Counter function of compensation for dead time — — √ DTC activation TGR compare match or input capture TGR compare match or input capture and TCNT overflow or underflow TGR compare match or input capture A/D converter start trigger TGRA_3S compare match or input capture TGRA_4S compare match or input capture TCNT_4S underflow (trough) in complementary PWM mode Interrupt sources 5 sources

• Compare match or input capture 3AS
• Compare match or input capture 3BS
• Compare match or input capture 3CS
• Compare match or input capture 3DS
• Overflow 5 sources
• Compare match or input capture 4AS
• Compare match or input capture 4BS
• Compare match or input capture 4CS
• Compare match or input capture 4DS
• Overflow or underflow 3 sources
• Compare match or input capture 5US
• Compare match or input capture 5VS
• Compare match or input capture 5WS A/D converter start request delaying function — • A/D converter start request at a match between TADCORA_4S and TCNT_4S
• A/D converter start request at a match between TADCORB_4S and TCNT_4S

Section 12 Multi-Function Timer Pulse Unit 2S (MTU2S) Page 678 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Item Channel 3 Channel 4 Channel 5 Interrupt skipping function

• Skips TGRA_3S compare match interrupts
• Skips TCIV_4S interrupts [Legend] √: Possible —: Not possible

Section 12 Multi-Function Timer Pulse Unit 2S (MTU2S) R01UH0198EJ0500 Rev. 5.00 Page 679 of 1560 Mar 18, 2011 SH7080 Group

12.1 Input/Output Pins

Table 12.2 Pin Configuration Channel Symbol I/O Function

3 TIOC3AS I/O TGRA_3S input capture input/output compare output/PWM output pin

TIOC3BS I/O TGRB_3S input capture input/output compare output/PWM output pin TIOC3CS I/O TGRC_3S input capture input/output compare output/PWM output pin TIOC3DS I/O TGRD_3S input capture input/output compare output/PWM output pin

4 TIOC4AS I/O TGRA_4S input capture input/output compare output/PWM output pin

TIOC4BS I/O TGRB_4S input capture input/output compare output/PWM output pin TIOC4CS I/O TGRC_4S input capture input/output compare output/PWM output pin TIOC4DS I/O TGRD_4S input capture input/output compare output/PWM output pin

5 TIC5US Input TGRU_5S input capture input/external pulse input pin

TIC5VS Input TGRV_5S input capture input/external pulse input pin TIC5WS Input TGRW_5S input capture input/external pulse input pin

Section 12 Multi-Function Timer Pulse Unit 2S (MTU2S) Page 680 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

12.2 Register Descriptions

The MTU2S has the following registers. For details on register addresses and register states during each process, refer to section 27, List of Registers. To distinguish registers in each channel, an underscore and the channel number are added as a suffix to the register name; TCR for channel 3 is expressed as TCR_3S. Table 12.3 Register Configuration Register Name Abbrevia- tion R/W Initial Value Address Access Size Timer control register_3S TCR_3S R/W H'00 H'FFFFC600 8, 16, 32 Timer control register_4S TCR_4S R/W H'00 H'FFFFC601 8 Timer mode register_3S TMDR_3S R/W H'00 H'FFFFC602 8, 16 Timer mode register_4S TMDR_4S R/W H'00 H'FFFFC603 8 Timer I/O control register H_3S TIORH_3S R/W H'00 H'FFFFC604 8, 16, 32 Timer I/O control register L_3S TIORL_3S R/W H'00 H'FFFFC605 8 Timer I/O control register H_4S TIORH_4S R/W H'00 H'FFFFC606 8, 16 Timer I/O control register L_4S TIORL_4S R/W H'00 H'FFFFC607 8 Timer interrupt enable register_3S TIER_3S R/W H'00 H'FFFFC608 8, 16 Timer interrupt enable register_4S TIER_4S R/W H'00 H'FFFFC609 8 Timer output master enable register S TOERS R/W H'C0 H'FFFFC60A 8 Timer gate control register S TGCRS R/W H'80 H'FFFFC60D 8 Timer output control register 1S TOCR1S R/W H'00 H'FFFFC60E 8, 16 Timer output control register 2S TOCR2S R/W H'00 H'FFFFC60F 8 Timer counter_3S TCNT_3S R/W H'0000 H'FFFFC610 16, 32 Timer counter_4S TCNT_4S R/W H'0000 H'FFFFC612 16 Timer cycle data register S TCDRS R/W H'FFFF H'FFFFC614 16, 32 Timer dead time data register S TDDRS R/W H'FFFF H'FFFFC616 16 Timer general register A_3S TGRA_3S R/W H'FFFF H'FFFFC618 16, 32 Timer general register B_3S TGRB_3S R/W H'FFFF H'FFFFC61A 16 Timer general register A_4S TGRA_4S R/W H'FFFF H'FFFFC61C 16, 32 Timer general register B_4S TGRB_4S R/W H'FFFF H'FFFFC61E 16

Section 12 Multi-Function Timer Pulse Unit 2S (MTU2S) R01UH0198EJ0500 Rev. 5.00 Page 681 of 1560 Mar 18, 2011 SH7080 Group Register Name Abbrevia- tion R/W Initial Value Address Access Size Timer subcounter S TCNTSS R H'0000 H'FFFFC620 16, 32 Timer cycle buffer register S TCBRS R/W H'FFFF H'FFFFC622 16 Timer general register C_3S TGRC_3S R/W H'FFFF H'FFFFC624 16, 32 Timer general register D_3S TGRD_3S R/W H'FFFF H'FFFFC626 16 Timer general register C_4S TGRC_4S R/W H'FFFF H'FFFFC628 16, 32 Timer general register D_4S TGRD_4S R/W H'FFFF H'FFFFC62A 16 Timer status register_3S TSR_3S R/W H'C0 H'FFFFC62C 8, 16 Timer status register_4S TSR_4S R/W H'C0 H'FFFFC62D 8 Timer interrupt skipping set register S TITCRS R/W H'00 H'FFFFC630 8, 16 Timer interrupt skipping counter S TITCNTS R H'00 H'FFFFC631 8 Timer buffer transfer set register S TBTERS R/W H'00 H'FFFFC632 8 Timer dead time enable register S TDERS R/W H'01 H'FFFFC634 8 Timer output level buffer register S TOLBRS R/W H'00 H'FFFFC636 8 Timer buffer operation transfer mode register_3S TBTM_3S R/W H'00 H'FFFFC638 8, 16 Timer buffer operation transfer mode register_4S TBTM_4S R/W H'00 H'FFFFC639 8 Timer A/D converter start request control register S TADCRS R/W H'0000 H'FFFFC640 16 Timer A/D converter start request cycle set register A_4S TADCORA_4S R/W H'FFFF H'FFFFC644 16, 32 Timer A/D converter start request cycle set register B_4S TADCORB_4S R/W H'FFFF H'FFFFC646 16 Timer A/D converter start request cycle set buffer register A_4S TADCOBRA_4S R/W H'FFFF H'FFFFC648 16, 32 Timer A/D converter start request cycle set buffer register B_4S TADCOBRB_4S R/W H'FFFF H'FFFFC64A 16

Section 12 Multi-Function Timer Pulse Unit 2S (MTU2S) Page 682 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Register Name Abbrevia- tion R/W Initial Value Address Access Size Timer synchronous clear register S TSYCRS R/W H'00 H'FFFFC650 8 Timer waveform control register S TWCRS R/W H'00 H'FFFFC660 8 Timer start register S TSTRS R/W H'00 H'FFFFC680 8, 16 Timer synchronous register S TSYRS R/W H'00 H'FFFFC681 8 Timer read/write enable register S TRWERS R/W H'01 H'FFFFC684 8 Timer counter U_5S TCNTU_5S R/W H'0000 H'FFFFC880 16, 32 Timer general register U_5S TGRU_5S R/W H'FFFF H'FFFFC882 16 Timer control register U_5S TCRU_5S R/W H'00 H'FFFFC884 8 Timer I/O control register U_5S TIORU_5S R/W H'00 H'FFFFC886 8 Timer counter V_5S TCNTV_5S R/W H'0000 H'FFFFC890 16, 32 Timer general register V_5S TGRV_5S R/W H'FFFF H'FFFFC892 16 Timer control register V_5S TCRV_5S R/W H'00 H'FFFFC894 8 Timer I/O control register V_5S TIORV_5S R/W H'00 H'FFFFC896 8 Timer counter W_5S TCNTW_5S R/W H'0000 H'FFFFC8A0 16, 32 Timer general register W_5S TGRW_5S R/W H'FFFF H'FFFFC8A2 16 Timer control register W_5S TCRW_5S R/W H'00 H'FFFFC8A4 8 Timer I/O control register W_5S TIORW_5S R/W H'00 H'FFFFC8A6 8 Timer status register_5S TSR_5S R/W H'00 H'FFFFC8B0 8 Timer interrupt enable register_5S TIER_5S R/W H'00 H'FFFFC8B2 8 Timer start register_5S TS TR_5S R/W H'00 H'FFFFC8B4 8 Timer compare match clear register S TCNTCMPCLRS R/W H'00 H'FFFFC8B6 8

Section 13 Port Output Enable (POE) R01UH0198EJ0500 Rev. 5.00 Page 683 of 1560 Mar 18, 2011 SH7080 Group Section 13 Port Output Enable (POE) The port output enable (POE) can be used to place the high-current pins (pins multiplexed with TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D in the MTU2 and TIOC3BS, TIOC3DS, TIOC4AS, TIOC4BS, TIOC4CS, and TIOC4DS in the MTU2S) and the pins for channel 0 of the MTU2 (pins multiplexed with TIOC0A, TIOC0B, TIOC0C, and TIOC0D) in high-impedance state, depending on the change on POE0 to POE8 input pins and the output status of the high-current pins, or by modifying register settings. It can also simultaneously generate interrupt requests.

13.1 Features

• Each of the POE0 to POE8 input pins can be set for falling edge, Pφ/8 × 16, Pφ/16 × 16, or Pφ/128 × 16 low-level sampling.
• High-current pins and the pins for channel 0 of the MTU2 can be placed in high-impedance state by POE0 to POE8 pin falling-edge or low-level sampling.
• High-current pins can be placed in high-impedance state when the high-current pin output levels are compared and simultaneous active-level output continues for one cycle or more.
• High-current pins and the pins for channel 0 of the MTU2 can be placed in high-impedance state by modifying the POE register settings.
• Interrupts can be generated by input-level sampling or output-level comparison results. The POE has input level detection circuits, output level comparison circuits, and a high-impedance request/interrupt request generating circuit as shown in figure 13.1. In addition to control by the POE, high-current pins can be placed in high-impedance state when the oscillator stops or in software standby state. For details, refer to section 21.1.11, High-Current Port Control Register (HCPCR), and appendix A, Pin States.

Section 13 Port Output Enable (POE) R01UH0198EJ0500 Rev. 5.00 Page 685 of 1560 Mar 18, 2011 SH7080 Group

13.2 Input/Output Pins

Table 13.1 Pin Configuration Pin Name Symbol I/O Description Port output enable input pins 0 to 3 POE0 to POE3 Input Input request signals to place high- current pins for MTU2 in high- impedance state Port output enable input pins 4 to 7 POE4 to POE7 Input Input request signals to place high- current pins for MTU2S in high- impedance state Port output enable input pin 8 POE8 Input Inputs a request signal to place pins for channel 0 in MTU2 in high- impedance state

Section 13 Port Output Enable (POE) Page 686 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 13.2 shows output-level comparisons with pin combinations. Table 13.2 Pin Combinations Pin Combination I/O Description PE9/TIOC3B and PE11/TIOC3D PE12/TIOC4A and PE14/TIOC4C PE13/TIOC4B and PE15/TIOC4D Output The high-current pins for the MTU2 are placed in high-impedance state when the pins simultaneously output an active level (low level when the output level select P (OLSP) bit of the timer output control register (TOCR) in the MTU2 is 0 or high level when the bit is 1) for one or more cycles of the peripheral clock (Pφ). This active level comparison is done when the MTU2 output function or general output function is selected in the pin function controller. If another function is selected, the output level is not checked. Pin combinations for output comparison and high- impedance control can be selected by POE registers. PD9/TIOC3BS and PD11/TIOC3DS PD12/TIOC4AS and PD14/TIOC4CS PD13/TIOC4BS and PD15/TIOC4DS PD29/TIOC3BS and PD28/TIOC3DS PD27/TIOC4AS and PD25/TIOC4CS PD26/TIOC4BS and PD24/TIOC4DS PE16/TIOC3BS and PE17/TIOC3DS PE18/TIOC4AS and PE20/TIOC4CS PE19/TIOC4BS and PE21/TIOC4DS Output The high-current pins for the MTU2S are placed in high-impedance state when the pins simultaneously output an active level (low level when the output level select P (OLSP) bit of the timer output control register (TOCR) in the MTU2S is 0 or high level when the bit is 1) for one or more cycles of the peripheral clock (Pφ). This active level comparison is done when the MTU2S output function or general output function is selected in the pin function controller. If another function is selected, the output level is not checked. Pin combinations for output comparison and high- impedance control can be selected by POE registers.

Section 13 Port Output Enable (POE) R01UH0198EJ0500 Rev. 5.00 Page 687 of 1560 Mar 18, 2011 SH7080 Group

13.3 Register Descriptions

The POE has the following registers. For details on register addresses and register states during each processing, refer to section 27, List of Registers. Table 13.3 Register Configuration Register Name Abbrevia- tion R/W Initial value Address Access Size Input level control/status register 1 ICSR1 R/W H'0000 H'FFFFD000 8, 16, 32 Output level control/status register 1 OCSR1 R/W H'0000 H'FFFFD002 8, 16 Input level control/status register 2 ICSR2 R/W H'0000 H'FFFFD004 8, 16, 32 Output level control/status register 2 OCSR2 R/W H'0000 H'FFFFD006 8, 16 Input level control/status register 3 ICSR3 R/W H'0000 H'FFFFD008 8, 16 Software port output enable register SPOER R/W H'00 H'FFFFD00A 8 Port output enable control register 1 POECR1 R/W H'00 H'FFFFD00B 8 Port output enable control register 2 POECR2 R/W H'7700 H'FFFFD00C 8, 16

Section 13 Port Output Enable (POE) Page 688 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

13.3.1 Input Level Control/Status Register 1 (ICSR1)

ICSR1 is a 16-bit readable/writable register that selects the POE0 to POE3 pin input modes, controls the enable/disable of interrupts, and indicates status. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1 RRR R / W R / W *2 R/W*2 R/W*2 R/W*2 R/W*2 R/W*2 R/W*2 R/W*2 Notes: Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. Can be modified only once after a power-on reset. POE3F POE2F POE1F POE0F - - - PIE1 POE3M[1:0] POE2M[1:0] POE1M[1:0] POE0M[1:0] Bit Bit Name Initial value R/W Description

15 POE3F 0 R/(W) *

This flag indicates that a high impedance request has been input to the POE3 pin. [Clearing conditions]

• By writing 0 to POE3F after reading POE3F = 1 (when the falling edge is selected by bits 7 and 6 in ICSR1)
• By writing 0 to POE3F after reading POE3F = 1 after a high level input to POE3 is sampled at Pφ/8, Pφ/16, or Pφ/128 clock (when low-level sampling is selected by bits 7 and 6 in ICSR1) [Setting condition]
• When the input set by ICSR1 bits 7 and 6 occurs at the POE3 pin

Section 13 Port Output Enable (POE) R01UH0198EJ0500 Rev. 5.00 Page 689 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial value R/W Description

14 POE2F 0 R/(W) *

This flag indicates that a high impedance request has been input to the POE2 pin. [Clearing conditions]

• By writing 0 to POE2F after reading POE2F = 1 (when the falling edge is selected by bits 5 and 4 in ICSR1)
• By writing 0 to POE2F after reading POE2F = 1 after a high level input to POE2 is sampled at Pφ/8, Pφ/16, or Pφ/128 clock (when low-level sampling is selected by bits 5 and 4 in ICSR1) [Setting condition]
• When the input set by ICSR1 bits 5 and 4 occurs at the POE2 pin

13 POE1F 0 R/(W) *

This flag indicates that a high impedance request has been input to the POE1 pin. [Clearing conditions]

• By writing 0 to POE1F after reading POE1F = 1 (when the falling edge is selected by bits 3 and 2 in ICSR1)
• By writing 0 to POE1F after reading POE1F = 1 after a high level input to POE1 is sampled at Pφ/8, Pφ/16, or Pφ/128 clock (when low-level sampling is selected by bits 3 and 2 in ICSR1) [Setting condition]
• When the input set by ICSR1 bits 3 and 2 occurs at the POE1 pin

Section 13 Port Output Enable (POE) Page 690 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial value R/W Description

12 POE0F 0 R/(W) *

This flag indicates that a high impedance request has been input to the POE0 pin. [Clearing conditions]

• By writing 0 to POE0F after reading POE0F = 1 (when the falling edge is selected by bits 1 and 0 in ICSR1)
• By writing 0 to POE0F after reading POE0F = 1 after a high level input to POE0 is sampled at Pφ/8, Pφ/16, or Pφ/128 clock (when low-level sampling is selected by bits 1 and 0 in ICSR1) [Setting condition]
• When the input set by ICSR1 bits 1 and 0 occurs at the POE0 pin 11 to 9 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0.

8 PIE1 0 R/W Port Interrupt Enable 1

This bit enables/disables interrupt requests when any one of the POE0F to POE3F bits of the ICSR1 is set to 1. 0: Interrupt requests disabled 1: Interrupt requests enabled 7, 6 POE3M[1:0] 00 R/W * POE3 mode 1, 0 These bits select the input mode of the POE3 pin. 00: Accept request on falling edge of POE3 input 01: Accept request when POE3 input has been sampled for 16 Pφ/8 clock pulses and all are low level. 10: Accept request when POE3 input has been sampled for 16 Pφ/16 clock pulses and all are low level. 11: Accept request when POE3 input has been sampled for 16 Pφ/128 clock pulses and all are low level.

Section 13 Port Output Enable (POE) R01UH0198EJ0500 Rev. 5.00 Page 691 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial value R/W Description 5, 4 POE2M[1:0] 00 R/W * POE2 mode 1, 0 These bits select the input mode of the POE2 pin. 00: Accept request on falling edge of POE2 input 01: Accept request when POE2 input has been sampled for 16 Pφ/8 clock pulses and all are low level. 10: Accept request when POE2 input has been sampled for 16 Pφ/16 clock pulses and all are low level. 11: Accept request when POE2 input has been sampled for 16 Pφ/128 clock pulses and all are low level. 3, 2 POE1M[1:0] 00 R/W * POE1 mode 1, 0 These bits select the input mode of the POE1 pin. 00: Accept request on falling edge of POE1 input 01: Accept request when POE1 input has been sampled for 16 Pφ/8 clock pulses and all are low level. 10: Accept request when POE1 input has been sampled for 16 Pφ/16 clock pulses and all are low level. 11: Accept request when POE1 input has been sampled for 16 Pφ/128 clock pulses and all are low level. 1, 0 POE0M[1:0] 00 R/W * POE0 mode 1, 0 These bits select the input mode of the POE0 pin. 00: Accept request on falling edge of POE0 input 01: Accept request when POE0 input has been sampled for 16 Pφ/8 clock pulses and all are low level. 10: Accept request when POE0 input has been sampled for 16 Pφ/16 clock pulses and all are low level. 11: Accept request when POE0 input has been sampled for 16 Pφ/128 clock pulses and all are low level. Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 2. Can be modified only once after a power-on reset.

Section 13 Port Output Enable (POE) Page 692 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

13.3.2 Output Level Control/Status Register 1 (OCSR1)

OCSR1 is a 16-bit readable/writable register that controls the enable/disable of both output level comparison and interrupts, and indicates status. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRRR R / W RRRRRRRRR/(W)*1 R/W*2 Notes: Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. Can be modified only once after a power-on reset. Bit Bit Name Initial value R/W Description

15 OSF1 0 R/(W) *

This flag indicates that any one of the three pairs of MTU2 2-phase outputs to be compared has simultaneously become an active level. [Clearing condition]

• By writing 0 to OSF1 after reading OSF1 = 1 [Setting condition]
• When any one of the three pairs of 2-phase outputs has simultaneously become an active level 14 to 10 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0.

9 OCE1 0 R/W *

Output Short High-Impedance Enable 1 This bit specifies whether to place the pins in high- impedance state when the OSF1 bit in OCSR1 is set to 1. 0: Does not place the pins in high-impedance state 1: Places the pins in high-impedance state

8 OIE1 0 R/W Output Short Interrupt Enable 1

This bit enables or disables interrupt requests when the OSF1 bit in OCSR is set to 1. 0: Interrupt requests disabled 1: Interrupt requests enabled

Section 13 Port Output Enable (POE) R01UH0198EJ0500 Rev. 5.00 Page 693 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial value R/W Description 7 to 0 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 2. Can be modified only once after a power-on reset.

13.3.3 Input Level Control/Status Register 2 (ICSR2)

ICSR2 is a 16-bit readable/writable register that selects the POE4 to POE7 pin input modes, controls the enable/disable of interrupts, and indicates status. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1 RRR R / W R / W *2 R/W*2 R/W*2 R/W*2 R/W*2 R/W*2 R/W*2 R/W*2 Notes: Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. Can be modified only once after a power-on reset. POE7F POE6F POE5F POE4F - - - PIE2 POE7M[1:0] POE6M[1:0] POE5M[1:0] POE4M[1:0] Bit Bit Name Initial value R/W Description

15 POE7F 0 R/(W) *

This flag indicates that a high impedance request has been input to the POE7 pin. [Clearing conditions]

• By writing 0 to POE7F after reading POE7F = 1 (when the falling edge is selected by bits 7 and 6 in ICSR2)
• By writing 0 to POE7F after reading POE7F = 1 after a high level input to POE7 is sampled at Pφ/8, Pφ/16, or Pφ/128 clock (when low-level sampling is selected by bits 7 and 6 in ICSR2) [Setting condition]
• When the input condition set by bits 7 and 6 in ICSR2 occurs at the POE7 pin

Section 13 Port Output Enable (POE) Page 694 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial value R/W Description

14 POE6F 0 R/(W) *

This flag indicates that a high impedance request has been input to the POE6 pin. [Clearing conditions]

• By writing 0 to POE6F after reading POE6F = 1 (when the falling edge is selected by bits 5 and 4 in ICSR2)
• By writing 0 to POE6F after reading POE6F = 1 after a high level input to POE6 is sampled at Pφ/8, Pφ/16, or Pφ/128 clock (when low-level sampling is selected by bits 5 and 4 in ICSR2) [Setting condition]
• When the input condition set by bits 5 and 4 in ICSR2 occurs at the POE6 pin

13 POE5F 0 R/(W) *

This flag indicates that a high impedance request has been input to the POE5 pin. [Clearing conditions]

• By writing 0 to POE5F after reading POE5F = 1 (when the falling edge is selected by bits 3 and 2 in ICSR2)
• By writing 0 to POE5F after reading POE5F = 1 after a high level input to POE5 is sampled at Pφ/8, Pφ/16, or Pφ/128 clock (when low-level sampling is selected by bits 3 and 2 in ICSR2) [Setting condition]
• When the input condition set by bits 3 and 2 in ICSR2 occurs at the POE5 pin

Section 13 Port Output Enable (POE) R01UH0198EJ0500 Rev. 5.00 Page 695 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial value R/W Description

12 POE4F 0 R/(W) *

This flag indicates that a high impedance request has been input to the POE4 pin. [Clearing conditions]

• By writing 0 to POE4F after reading POE4F = 1 (when the falling edge is selected by bits 1 and 0 in ICSR2)
• By writing 0 to POE4F after reading POE4F = 1 after a high level input to POE4 is sampled at Pφ/8, Pφ/16, or Pφ/128 clock (when low-level sampling is selected by bits 1 and 0 in ICSR2) [Setting condition]
• When the input condition set by bits 1 and 0 in ICSR2 occurs at the POE4 pin 11 to 9 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

8 PIE2 0 R/W Port Interrupt Enable 2

This bit enables/disables interrupt requests when any one of the POE4F to POE7F bits of the ICSR2 is set to 1. 0: Interrupt requests disabled 1: Interrupt requests enabled 7, 6 POE7M[1:0] 00 R/W * POE7 mode 1 and 0 These bits select the input mode of the POE7 pin. 00: Accept request on falling edge of POE7 input 01: Accept request when POE7 input has been sampled for 16 Pφ/8 clock pulses and all are at a low level. 10: Accept request when POE7 input has been sampled for 16 Pφ/16 clock pulses and all are at a low level. 11: Accept request when POE7 input has been sampled for 16 Pφ/128 clock pulses and all are at a low level.

Section 13 Port Output Enable (POE) Page 696 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial value R/W Description 5, 4 POE6M[1:0] 00 R/W * POE6 mode 1 and 0 These bits select the input mode of the POE6 pin. 00: Accept request on falling edge of POE6 input 01: Accept request when POE6 input has been sampled for 16 Pφ/8 clock pulses and all are at a low level. 10: Accept request when POE6 input has been sampled for 16 Pφ/16 clock pulses and all are at a low level. 11: Accept request when POE6 input has been sampled for 16 Pφ/128 clock pulses and all are at a low level. 3, 2 POE5M[1:0] 00 R/W * POE5 mode 1 and 0 These bits select the input mode of the POE5 pin. 00: Accept request on falling edge of POE5 input 01: Accept request when POE5 input has been sampled for 16 Pφ/8 clock pulses and all are at a low level. 10: Accept request when POE5 input has been sampled for 16 Pφ/16 clock pulses and all are at a low level. 11: Accept request when POE5 input has been sampled for 16 Pφ/128 clock pulses and all are at a low level. 1, 0 POE4M[1:0] 00 R/W * POE4 mode 1 and 0 These bits select the input mode of the POE4 pin. 00: Accept request on falling edge of POE4 input 01: Accept request when POE4 input has been sampled for 16 Pφ/8 clock pulses and all are at a low level. 10: Accept request when POE4 input has been sampled for 16 Pφ/16 clock pulses and all are at a low level. 11: Accept request when POE4 input has been sampled for 16 Pφ/128 clock pulses and all are at a low level. Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 2. Can be modified only once after a power-on reset.

Section 13 Port Output Enable (POE) R01UH0198EJ0500 Rev. 5.00 Page 697 of 1560 Mar 18, 2011 SH7080 Group

13.3.4 Output Level Control/Status Register 2 (OCSR2)

OCSR2 is a 16-bit readable/writable register that controls the enable/disable of both output level comparison and interrupts, and indicates status. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 R/(W)*1 RRRRR R / W *2 R / W RRRRRRRR Notes: Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. Can be modified only once after a power-on reset. Bit Bit Name Initial value R/W Description

15 OSF2 0 R/(W) *

This flag indicates that any one of the three pairs of MTU2S 2-phase outputs to be compared has simultaneously become an active level. [Clearing condition]

• By writing 0 to OSF2 after reading OSF2 = 1 [Setting condition]
• When any one of the three pairs of 2-phase outputs has simultaneously become an active level 14 to 10 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0.

9 OCE2 0 R/W *

Output Short High-Impedance Enable 2 This bit specifies whether to place the pins in high- impedance state when the OSF2 bit in OCSR2 is set to 1. 0: Does not place the pins in high-impedance state 1: Places the pins in high-impedance state

8 OIE2 0 R/W Output Short Interrupt Enable 2

This bit enables or disables interrupt requests when the OSF2 bit in OCSR2 is set to 1. 0: Interrupt requests disabled 1: Interrupt requests enabled

Section 13 Port Output Enable (POE) Page 698 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial value R/W Description 7 to 0 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 2. Can be modified only once after a power-on reset.

13.3.5 Input Level Control/Status Register 3 (ICSR3)

ICSR3 is a 16-bit readable/writable register that selects the POE8 pin input mode, controls the enable/disable of interrupts, and indicates status. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRR R/(W)*1 RR R / W *2 R / W RRRRRR R / W *2 R/W*2 Notes: Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. Can be modified only once after a power-on reset. POE8F - - POE8E - - - - -- - - PIE3 - POE8M[1:0] Bit Bit Name Initial value R/W Description 15 to 13 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

12 POE8F 0 R/(W) *

This flag indicates that a high impedance request has been input to the POE8 pin. [Clearing conditions]

• By writing 0 to POE8F after reading POE8F = 1 (when the falling edge is selected by bits 1 and 0 in ICSR3)
• By writing 0 to POE8F after reading POE8F = 1 after a high level input to POE8 is sampled at Pφ/8, Pφ /16, or Pφ/128 clock (when low-level sampling is selected by bits 1 and 0 in ICSR3) [Setting condition]
• When the input condition set by bits 1 and 0 in ICSR3 occurs at the POE8 pin

Section 13 Port Output Enable (POE) R01UH0198EJ0500 Rev. 5.00 Page 699 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial value R/W Description 11, 10 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0.

9 POE8E 0 R/W *

POE8 High-Impedance Enable This bit specifies whether to place the pins in high- impedance state when the POE8F bit in ICSR3 is set to 1. 0: Does not place the pins in high-impedance state 1: Places the pins in high-impedance state

8 PIE3 0 R/W Port Interrupt Enable 3

This bit enables or disables interrupt requests when the POE8 bit in ICSR3 is set to 1. 0: Interrupt requests disabled 1: Interrupt requests enabled 7 to 2 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1, 0 POE8M[1:0] 00 R/W * POE8 mode 1 and 0 These bits select the input mode of the POE8 pin. 00: Accept request on falling edge of POE8 input 01: Accept request when POE8 input has been sampled for 16 Pφ/8 clock pulses and all are low level. 10: Accept request when POE8 input has been sampled for 16 Pφ/16 clock pulses and all are low level. 11: Accept request when POE8 input has been sampled for 16 Pφ/128 clock pulses and all are low level. Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 2. Can be modified only once after a power-on reset.

Section 13 Port Output Enable (POE) Page 700 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

13.3.6 Software Port Output Enable Register (SPOER)

SPOER is an 8-bit readable/writable register that controls high-impedance state of the pins. Bit: Initial value: R/W: 7654321 0 00000000 R R R R R R/W R/W R/W ----- MTU2S HIZ MTU2 CH0HIZ MTU2 CH34HIZ Bit Bit Name Initial value R/W Description 7 to 3 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

2 MTU2SHIZ 0 R/W MTU2S Output High-Impedance

This bit specifies whether to place the high-current pins for the MTU2S in high-impedance state. 0: Does not place the pins in high-impedance state [Clearing conditions]

• Power-on reset
• By writing 0 to MTU2SHIZ after reading MTU2SHIZ = 1 1: Places the pins in high-impedance state [Setting condition]
• By writing 1 to MTU2SHIZ

1 MTU2CH0HIZ 0 R/W MTU2 Channel 0 Output High-Impedance

This bit specifies whether to place the pins for channel 0 in the MTU2 in high-impedance state. 0: Does not place the pins in high-impedance state [Clearing conditions]

• Power-on reset
• By writing 0 to MTU2CH0HIZ after reading MTU2CH0HIZ = 1 1: Places the pins in high-impedance state [Setting condition]
• By writing 1 to MTU2CH0HIZ

Section 13 Port Output Enable (POE) R01UH0198EJ0500 Rev. 5.00 Page 701 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial value R/W Description

0 MTU2CH34HIZ 0 R/W MTU2 Channel 3 and 4 Output High-Impedance

This bit specifies whether to place the high-current pins for the MTU2 in high-impedance state. 0: Does not place the pins in high-impedance state [Clearing conditions]

• Power-on reset
• By writing 0 to MTU2CH34HIZ after reading MTU2CH34HIZ = 1 1: Places the pins in high-impedance state [Setting condition]
• By writing 1 to MTU2CH34HIZ

13.3.7 Port Output Enable Control Register 1 (POECR1)

POECR1 is an 8-bit readable/writable register that controls high-impedance state of the pins. Bit: Initial value: R/W: 7654321 0 00000000 RRRR R / W * R/W* R/W* R/W* Note: Can be modified only once after a power-on reset.* ---- MTU2 PE3ZE MTU2 PE2ZE MTU2 PE1ZE MTU2 PE0ZE Bit Bit Name Initial value R/W Description 7 to 4 — All 0 R Reserved These bits are always read as 0. The write value should always be 0.

3 MTU2PE3ZE 0 R/W * MTU2 PE3 High-Impedance Enable

This bit specifies whether to place the PE3/TIOC0D pin for channel 0 in the MTU2 in high-impedance state when either POE8F or MTU2CH0HIZ bit is set to 1. 0: Does not place the pin in high-impedance state 1: Places the pin in high-impedance state

Section 13 Port Output Enable (POE) Page 702 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial value R/W Description

2 MTU2PE2ZE 0 R/W * MTU2 PE2 High-Impedance Enable

This bit specifies whether to place the PE2/TIOC0C pin for channel 0 in the MTU2 in high-impedance state when either POE8F or MTU2CH0HIZ bit is set to 1. 0: Does not place the pin in high-impedance state 1: Places the pin in high-impedance state

1 MTU2PE1ZE 0 R/W * MTU2 PE1 High-Impedance Enable

This bit specifies whether to place the PE1/TIOC0B pin for channel 0 in the MTU2 in high-impedance state when either POE8F or MTU2CH0HIZ bit is set to 1. 0: Does not place the pin in high-impedance state 1: Places the pin in high-impedance state

0 MTU2PE0ZE 0 R/W * MTU2 PE0 High-Impedance Enable

This bit specifies whether to place the PE0/TIOC0A pin for channel 0 in the MTU2 in high-impedance state when either POE8F or MTU2CH0HIZ bit is set to 1. 0: Does not place the pin in high-impedance state 1: Places the pin in high-impedance state Note: * Can be modified only once after a power-on reset.

Section 13 Port Output Enable (POE) R01UH0198EJ0500 Rev. 5.00 Page 703 of 1560 Mar 18, 2011 SH7080 Group

13.3.8 Port Output Enable Control Register 2 (POECR2)

POECR2 is a 16-bit readable/writable register that controls high-impedance state of the pins. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0111011100000000 RR / W * R/W* R/W* RR / W * R/W* R/W* RR / W * R/W* R/W* RR / W * R/W* R/W* Note: Can be modified only once after a power-on reset.* - MTU2 P1CZE MTU2 P2CZE MTU2 P3CZE - MTU2S P1CZE MTU2S P2CZE MTU2S P3CZE - MTU2S P4CZE MTU2S P5CZE MTU2S P6CZE - MTU2S P7CZE MTU2S P8CZE MTU2S P9CZE Bit Bit Name Initial value R/W Description 15 — 0 R Reserved This bit is always read as 0. The write value should always be 0.

14 MTU2P1CZE 1 R/W * MTU2 Port 1 Output Comparison/High-Impedance

This bit specifies whether to compare output levels for the MTU2 high-current PE9/TIOC3B and PE11/TIOC3D pins and to place them in high- impedance state when the OSF1 bit is set to 1 while the OCE1 bit is 1 or when any one of the POE0F, POE1F, POE2F, POE3F, and MTU2CH34HIZ bits is set to 1. 0: Does not compare output levels or place the pins in high-impedance state 1: Compares output levels and places the pins in high-impedance state

Section 13 Port Output Enable (POE) Page 704 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial value R/W Description

13 MTU2P2CZE 1 R/W * MTU2 Port 2 Output Comparison/High-Impedance

This bit specifies whether to compare output levels for the MTU2 high-current PE12/TIOC4A and PE14/TIOC4C pins and to place them in high- impedance state when the OSF1 bit is set to 1 while the OCE1 bit is 1 or when any one of the POE0F, POE1F, POE2F, POE3F, and MTU2CH34HIZ bits is set to 1. 0: Does not compare output levels or place the pins in high-impedance state 1: Compares output levels and places the pins in high-impedance state

12 MTU2P3CZE 1 R/W * MTU2 Port 3 Output Comparison/High-Impedance

This bit specifies whether to compare output levels for the MTU2 high-current PE13/TIOC4B and PE15/TIOC4D pins and to place them in high- impedance state when the OSF1 bit is set to 1 while the OCE1 bit is 1 or when any one of the POE0F, POE1F, POE2F, POE3F, and MTU2CH34HIZ bits is set to 1. 0: Does not compare output levels or place the pins in high-impedance state 1: Compares output levels and places the pins in high-impedance state 11 — 0 R Reserved This bit is always read as 0. The write value should always be 0.

Section 13 Port Output Enable (POE) R01UH0198EJ0500 Rev. 5.00 Page 705 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial value R/W Description

10 MTU2SP1CZE 1 R/W * MTU2S Port 1 Output Comparison/High-Impedance

This bit specifies whether to compare output levels for the MTU2S high-current PE16/TIOC3BS and PE17/TIOC3DS pins and to place them in high- impedance state when the OSF2 bit is set to 1 while the OCE2 bit is 1 or when any one of the POE4F, POE5F, POE6F, POE7F, and MTU2SHIZ bits is set to 1. 0: Does not compare output levels or place the pins in high-impedance state 1: Compares output levels and places the pins in high-impedance state

9 MTU2SP2CZE 1 R/W * MTU2S Port 2 Output Comparison/High-Impedance

This bit specifies whether to compare output levels for the MTU2S high-current PE18/TIOC4AS and PE20/TIOC4CS pins and to place them in high- impedance state when the OSF2 bit is set to 1 while the OCE2 bit is 1 or when any one of the POE4F, POE5F, POE6F, POE7F, and MTU2SHIZ bits is set to 1. 0: Does not compare output levels or place the pins in high-impedance state 1: Compares output levels and places the pins in high-impedance state

8 MTU2SP3CZE 1 R/W * MTU2S Port 3 Output Comparison/High-Impedance

This bit specifies whether to compare output levels for the MTU2S high-current PE19/TIOC4BS and PE21/TIOC4DS pins and to place them in high- impedance state when the OSF2 bit is set to 1 while the OCE2 bit is 1 or when any one of the POE4F, POE5F, POE6F, POE7F, and MTU2SHIZ bits is set to 1. 0: Does not compare output levels or place the pins in high-impedance state 1: Compares output levels and places the pins in high-impedance state

Section 13 Port Output Enable (POE) Page 706 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial value R/W Description 7 — 0 R Reserved This bit is always read as 0. The write value should always be 0.

6 MTU2SP4CZE 0 R/W * MTU2S Port 4 Output Comparison/High-Impedance

This bit specifies whether to compare output levels for the MTU2S high-current PD9/TIOC3BS and PD11/TIOC3DS pins and to place them in high- impedance state when the OSF2 bit is set to 1 while the OCE2 bit is 1 or when any one of the POE4F, POE5F, POE6F, POE7F, and MTU2SHIZ bits is set to 1. 0: Does not compare output levels or place the pins in high-impedance state 1: Compares output levels and places the pins in high-impedance state

5 MTU2SP5CZE 0 R/W * MTU2S Port 5 Output Comparison/High-Impedance

This bit specifies whether to compare output levels for the MTU2S high-current PD12/TIOC4AS and PD14/TIOC4CS pins and to place them in high- impedance state when the OSF2 bit is set to 1 while the OCE2 bit is 1 or when any one of the POE4F, POE5F, POE6F, POE7F, and MTU2SHIZ bits is set to 1. 0: Does not compare output levels or place the pins in high-impedance state 1: Compares output levels and places the pins in high-impedance state

Section 13 Port Output Enable (POE) R01UH0198EJ0500 Rev. 5.00 Page 707 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial value R/W Description

4 MTU2SP6CZE 0 R/W * MTU2S Port 6 Output Comparison/High-Impedance

This bit specifies whether to compare output levels for the MTU2S high-current PD13/TIOC4BS and PD15/TIOC4DS pins and to place them in high- impedance state when the OSF2 bit is set to 1 while the OCE2 bit is 1 or when any one of the POE4F, POE5F, POE6F, POE7F, and MTU2SHIZ bits is set to 1. 0: Does not compare output levels or place the pins in high-impedance state 1: Compares output levels and places the pins in high-impedance state 3 — 0 R Reserved This bit is always read as 0. The write value should always be 0.

2 MTU2SP7CZE 0 R/W * MTU2S Port 7 Output Comparison/High-Impedance

This bit specifies whether to compare output levels for the MTU2S high-current PD29/TIOC3BS and PD28/TIOC3DS pins and to place them in high- impedance state when the OSF2 bit is set to 1 while the OCE2 bit is 1 or when any one of the POE4F, POE5F, POE6F, POE7F, and MTU2SHIZ bits is set to 1. 0: Does not compare output levels or place the pins in high-impedance state 1: Compares output levels and places the pins in high-impedance state

Section 13 Port Output Enable (POE) Page 708 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial value R/W Description

1 MTU2SP8CZE 0 R/W * MTU2S Port 8 Output Comparison/High-Impedance

This bit specifies whether to compare output levels for the MTU2S high-current PD27/TIOC4AS and PD25/TIOC4CS pins and to place them in high- impedance state when the OSF2 bit is set to 1 while the OCE2 bit is 1 or when any one of the POE4F, POE5F, POE6F, POE7F, and MTU2SHIZ bits is set to 1. 0: Does not compare output levels or place the pins in high-impedance state 1: Compares output levels and places the pins in high-impedance state

0 MTU2SP9CZE 0 R/W * MTU2S Port 9 Output Comparison/High-Impedance

This bit specifies whether to compare output levels for the MTU2S high-current PD26/TIOC4BS and PD24/TIOC4DS pins and to place them in high- impedance state when the OSF2 bit is set to 1 while the OCE2 bit is 1 or when any one of the POE4F, POE5F, POE6F, POE7F, and MTU2SHIZ bits is set to 1. 0: Does not compare output levels or place the pins in high-impedance state 1: Compares output levels and places the pins in high-impedance state Note: * Can be modified only once after a power-on reset.

Section 13 Port Output Enable (POE) R01UH0198EJ0500 Rev. 5.00 Page 709 of 1560 Mar 18, 2011 SH7080 Group

13.4 Operation

Table 13.4 shows the target pins for high-impedance control and conditions to place the pins in high-impedance state. Table 13.4 Target Pins and Condi tions for High-Impedance Control Pins Conditions Detailed Conditions MTU2 high-current pins (PE9/TIOC3B and PE11/TIOC3D) Input level detection, output level comparison, or SPOER setting MTU2P1CZE • ((POE3F + POE2F + POE1F + POE0F) + (OSF1 • OCE1) + (MTU2CH34HIZ)) MTU2 high-current pins (PE12/TIOC4A and PE14/TIOC4C) Input level detection, output level comparison, or SPOER setting MTU2P2CZE • ((POE3F + POE2F + POE1F + POE0F) + (OSF1 • OCE1) + (MTU2CH34HIZ)) MTU2 high-current pins (PE13/TIOC4B and PE15/TIOC4D) Input level detection, output level comparison, or SPOER setting MTU2P3CZE • ((POE3F + POE2F + POE1F + POE0F) + (OSF1 • OCE1) + (MTU2CH34HIZ)) MTU2S high-current pins (PE16/TIOC3BS and PE17/TIOC3DS) Input level detection, output level comparison, or SPOER setting MTU2SP1CZE • ((POE4F + POE5F + POE6F + POE7F) + (OSF2 • OCE2) + (MTU2SHIZ)) MTU2S high-current pins (PE18/TIOC4AS and PE20/TIOC4CS) Input level detection, output level comparison, or SPOER setting MTU2SP2CZE • ((POE4F + POE5F + POE6F + POE7F) + (OSF2 • OCE2) + (MTU2SHIZ)) MTU2S high-current pins (PE19/TIOC4BS and PE21/TIOC4DS) Input level detection, output level comparison, or SPOER setting MTU2SP3CZE • ((POE4F + POE5F + POE6F + POE7F) + (OSF2 • OCE2) + (MTU2SHIZ)) MTU2S high-current pins (PD9/TIOC3BS and PD11/TIOC3DS) Input level detection, output level comparison, or SPOER setting MTU2SP4CZE • ((POE4F + POE5F + POE6F + POE7F) + (OSF2 • OCE2) + (MTU2SHIZ)) MTU2S high-current pins (PD12/TIOC4AS and PD14/TIOC4CS) Input level detection, output level comparison, or SPOER setting MTU2SP5CZE • ((POE4F + POE5F + POE6F + POE7F) + (OSF2 • OCE2) + (MTU2SHIZ)) MTU2S high-current pins (PD13/TIOC4BS and PD15/TIOC4DS) Input level detection, output level comparison, or SPOER setting MTU2SP6CZE • ((POE4F + POE5F + POE6F + POE7F) + (OSF2 • OCE2) + (MTU2SHIZ)) MTU2S high-current pins (PD29/TIOC3BS and PD28/TIOC3DS) Input level detection, output level comparison, or SPOER setting MTU2SP7CZE • ((POE4F + POE5F + POE6F + POE7F) + (OSF2 • OCE2) + (MTU2SHIZ))

Section 13 Port Output Enable (POE) Page 710 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Pins Conditions Detailed Conditions MTU2S high-current pins (PD27/TIOC4AS and PD25/TIOC4CS) Input level detection, output level comparison, or SPOER setting MTU2SP8CZE • ((POE4F + POE5F + POE6F + POE7F) + (OSF2 • OCE2) + (MTU2SHIZ)) MTU2S high-current pins (PD26/TIOC4BS and PD24/TIOC4DS) Input level detection, output level comparison, or SPOER setting MTU2SP9CZE • ((POE4F + POE5F + POE6F + POE7F) + (OSF2 • OCE2) + (MTU2SHIZ)) MTU2 channel 0 pin (PE0/TIOC0A) Input level detection or SPOER setting MTU2PE0ZE ((POE8F • POE8E) + (MTU2CH0HIZ)) MTU2 channel 0 pin (PE1/TIOC0B) Input level detection or SPOER setting MTU2PE1ZE ((POE8F • POE8E) + (MTU2CH0HIZ)) MTU2 channel 0 pin (PE2/TIOC0C) Input level detection or SPOER setting MTU2PE2ZE ((POE8F • POE8E) + (MTU2CH0HIZ)) MTU2 channel 0 pin (PE3/TIOC0D) Input level detection or SPOER setting MTU2PE3ZE ((POE8F • POE8E) + (MTU2CH0HIZ))

Section 13 Port Output Enable (POE) R01UH0198EJ0500 Rev. 5.00 Page 711 of 1560 Mar 18, 2011 SH7080 Group

13.4.1 Input Level Detection Operation

If the input conditions set by ICSR1 to ICSR3 occur on the POE0 to POE8 pins, the high-current pins and the pins for channel 0 of the MTU2 are placed in high-impedance state. Note however, that these high-current and MTU2 pins enter high-impedance state only when general input/output function, MTU2 function, or MTU2S function is selected for these pins. (1) Falling Edge Detection When a change from a high to low level is input to the POE0 to POE8 pins, the high-current pins and the pins for channel 0 of the MTU2 are placed in high-impedance state. Figure 13.2 shows a sample timing after the level changes in input to the POE0 to POE8 pins until the respective pins enter high-impedance state. Pφ POE input PE9/TIOC3B Pφ rising edge Falling edge detection High-impedance state* Note: * The other high-current pins also enter the high-impedance state in the similar timing. Figure 13.2 Falling Edge Detection (2) Low-Level Detection Figure 13.3 shows the low-level detection operation. Sixteen continuous low levels are sampled with the sampling clock selected by ICSR1 to ICSR3. If even one high level is detected during this interval, the low level is not accepted. The timing when the high-current pins enter the high-impedance state after the sampling clock is input is the same in both falling-edge detection and in low-level detection.

Section 13 Port Output Enable (POE) Page 712 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Pφ Sampling clock POE input PE9/ TIOC3B When low level is sampled at all points When high level is sampled at least once Flag set (POE received) Flag not set High-impedance state* Note: * Other high-current pins also go to the high-impedance state at the same timing. 8/16/128 clock cycles Figure 13.3 Low-Level Detection Operation

13.4.2 Output-Level Compare Operation

Figure 13.4 shows an example of the output-level compare operation for the combination of TIOC3B and TIOC3D. The operation is the same for the other pin combinations. Pφ PE11/ TIOC3D PE9/ TIOC3B Low level overlapping detected High impedance state Figure 13.4 Output-Level Compare Operation

Section 13 Port Output Enable (POE) R01UH0198EJ0500 Rev. 5.00 Page 713 of 1560 Mar 18, 2011 SH7080 Group

13.4.3 Release from High-Impedance State

High-current pins that have entered high-impedance state due to input-level detection can be released either by returning them to their initial state with a power-on reset, or by clearing all of the flags in bits 12 to 15 (POE0F to POE8F) of ICSR1 to ICSR3. However, note that when low- level sampling is selected by bits 0 to 7 in ICSR1 to ICSR3, just writing 0 to a flag is ignored (the flag is not cleared); flags can be cleared by writing 0 to it only after a high level is input to the POE pin and is sampled. High-current pins that have entered high-impedance state due to output-level detection can be released either by returning them to their initial state with a power-on reset, or by clearing the flag in bit 15 (OCF1 and OCF2) in OCSR1 and OCSR2. However, note that just writing 0 to a flag is ignored (the flag is not cleared); flags can be cleared only after an inactive level is output from the high-current pins. Inactive-level outputs can be achieved by setting the MTU2 and MTU2S internal registers.

Section 13 Port Output Enable (POE) Page 714 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

13.5 Interrupts

The POE issues a request to generate an interrupt when the specified condition is satisfied during input level detection or output level comparison. Table 13.5 shows the interrupt sources and their conditions. Table 13.5 Interrupt Sources and Conditions Name Interrupt Source Interrupt Flag Condition OEI1 Output enable interrupt 1 POE3F, POE2F, POE1F, POE0F, and OSF1 PIE1 • (POE3F + POE2F + POE1F + POE0F) + OIE1 • OSF1 OEI3 Output enable interrupt 3 POE8F PIE3 • POE8F OEI2 Output enable interrupt 2 POE4F, POE5F, POE6F, POE7F, and OSF2 PIE2 • (POE4F + POE5F + POE6F + POE7F) + OIE2 • OSF2

Section 13 Port Output Enable (POE) R01UH0198EJ0500 Rev. 5.00 Page 715 of 1560 Mar 18, 2011 SH7080 Group

13.6 Usage Note

13.6.1 Pin State when a Power-On Reset Is Issued from the Watchdog Timer

When a power-on reset is issued from the watchdog timer (WDT), initialization of the pin function controller (PFC) sets initial values that select the general input function for the I/O ports. However, when a power-on reset is issued from the WDT while a pin is being handled as high impedance by the port output enable (POE), the pin is placed in the output state for one cycle of the peripheral clock (Pφ), after which the function is switched to general input. This also occurs when a power-on reset is issued from the WDT for pins that are being handled as high impedance due to short-circuit detection by the MTU2 and MTU2S. Figure 13.5 shows the state of a pin for which the POE input has selected high impedance handling with the timer output selected when a power-on reset is issued from the WDT. Timer outputPin state General input Timer output General input High impedance state Timer output 1Pφ cycle POE input Pφ PFC setting value Power-on reset by WDT Figure 13.5 Pin State when a Power-On Reset Is Issued from the Watchdog Timer

Section 13 Port Output Enable (POE) Page 716 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

Section 14 Watchdog Timer (WDT) R01UH0198EJ0500 Rev. 5.00 Page 717 of 1560 Mar 18, 2011 SH7080 Group Section 14 Watchdog Timer (WDT) This LSI includes the watchdog timer (WDT). This LSI can be reset by the overflow of the counter when the value of the counter has not been updated because of a system runaway. The watchdog timer (WDT) is a single-channel timer that uses a peripheral clock as an input and counts the clock settling time when revoking software standby mode. It can also be used as an interval timer.

14.1 Features

• Can be used to ensure the clock settling time: Use the WDT to revoke software standby mode.
• Can switch between watchdog timer mode and interval timer mode.
• Generates internal resets in watchdog timer mode: Internal resets occur after counter overflow.
• An interrupt is generated in interval timer mode An interval timer interrupt is generated when the counter overflows.
• Choice of eight counter input clocks Eight clocks (×1 to ×1/4096) that are obtained by dividing the peripheral clock can be chosen.
• Choice of two resets Power-on reset and manual reset are available. Figure 14.1 shows a block diagram of the WDT.

Section 14 Watchdog Timer (WDT) Page 718 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group WTCSR Standby control Bus interface WTCNT Divider Clock selector Internal bus Clock Standby mode Peripheral clock (Pφ) Standby cancellation Reset control Clock selection WDT Overflow WDTOVF Internal reset request Interrupt control Interrupt request [Legend] WTCSR: WTCNT: Watchdog timer control/status register Watchdog timer counter Figure 14.1 Block Diagram of WDT

Section 14 Watchdog Timer (WDT) R01UH0198EJ0500 Rev. 5.00 Page 719 of 1560 Mar 18, 2011 SH7080 Group

14.2 Input/Output Pin for WDT

Table 14.1 lists the WDT pin configuration. Table 14.1 WDT Pin Configuration Pin Name Symbol I/O Description Watchdog timer overflow WDTOVF Output When an overflow occurs in watchdog timer mode, an internal reset is generated and this pin outputs the low level for one clock cycle specified by the CKS2 to CKS0 bits in WTCSR.

Section 14 Watchdog Timer (WDT) Page 720 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

14.3 Register Descriptions

The WDT has the following two registers. Refer to section 27, List of Registers, for the details of the addresses of these registers and the state of registers in each operating mode. Table 14.2 Register Configuration Register Name Abbrevia- tion R/W Initial Value Address Access Size Watchdog timer counter WTCNT R/W H'00 H'FFFFE810 8, 16 Watchdog timer control/status register WTCSR R/W H'00 H'FFFFE812 8, 16

14.3.1 Watchdog Timer Counter (WTCNT)

WTCNT is an 8-bit readable/writable register that increments on the selected clock. When an overflow occurs, it generates a reset in watchdog timer mode and an interrupt in interval time mode. The WTCNT counter is not initialized by an internal reset due to the WDT overflow. The WTCNT counter is initialized to H'00 only by a power-on reset using the RES pin. Use a word access to write to the WTCNT counter, with H'5A in the upper byte. Use a byte access to read WTCNT. Note: WTCNT differs from other registers in that it is more difficult to write to. See section 14.3.3, Notes on Register Access, for details. Bit: Initial value: R/W: 7654321 0 00000000 R/W R/W R/W R/W R/W R/W R/W R/W

Section 14 Watchdog Timer (WDT) R01UH0198EJ0500 Rev. 5.00 Page 721 of 1560 Mar 18, 2011 SH7080 Group

14.3.2 Watchdog Timer Control/Status Register (WTCSR)

WTCSR is an 8-bit readable/writable register composed of bits to select the clock used for the count, bits to select the timer mode, and overflow flags. WTCSR holds its value in an internal reset due to the WDT overflow. WTCSR is initialized to H'00 only by a power-on reset using the RES pin. When used to count the clock settling time for revoking a software standby, it retains its value after counter overflow. Use a word access to write to WTCSR, with H'A5 in the upper byte. Use a byte access to read WTCSR. Note: WTCSR differs from other registers in that it is more difficult to write to. See section 14.3.3, Notes on Register Access, for details. Bit: Initial value: R/W: 7654321 0 00000000 R/W R/W R/W R/W R/W R/W R/W R/W TME WT/IT RSTS WOVF IOVF CKS[2:0] Bit Bit Name Initial Value R/W Description

7 TME 0 R/W Timer Enable

Starts and stops timer operation. Clear this bit to 0 when using the WDT to revoke software standby mode. 0: Timer disabled: Count-up stops and WTCNT value is retained 1: Timer enabled

6 WT/IT 0 R/W Timer Mode Select

Selects whether to use the WDT as a watchdog timer or an interval timer. 0: Interval timer mode 1: Watchdog timer mode Note: If WT/IT is modified when the WDT is operating, the up-count may not be performed correctly.

Section 14 Watchdog Timer (WDT) Page 722 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description

5 RSTS 0 R/W Reset Select

Selects the type of reset when the WTCNT overflows in watchdog timer mode. In interval timer mode, this setting is ignored. 0: Power-on reset 1: Manual reset

4 WOVF 0 R/W Watchdog Timer Overflow

Indicates that the WTCNT has overflowed in watchdog timer mode. This bit is not set in interval timer mode. 0: No overflow 1: WTCNT has overflowed in watchdog timer mode

3 IOVF 0 R/W Interval Timer Overflow

Indicates that the WTCNT has overflowed in interval timer mode. This bit is not set in watchdog timer mode. 0: No overflow 1: WTCNT has overflowed in interval timer mode 2 to 0 CKS[2:0] 000 R/W Clock Select 2 to 0 These bits select the clock to be used for the WTCNT count from the eight types obtainable by dividing the peripheral clock (Pφ). The overflow period that is shown inside the parenthesis in the table is the value when the peripheral clock (Pφ) is 40 MHz. 000: Pφ (6.4 μs) 001: Pφ /4 (25.6 μs) 010: Pφ /16 (102.4 μs) 011: Pφ /32 (204.8 μs) 100: Pφ /64 (409.6 μs) 101: Pφ /256 (1.64 ms) 110: Pφ /1024 (6.55 ms) 111: Pφ /4096 (26.21 ms) Note: If bits CKS2 to CKS0 are modified when the WDT is operating, the up-count may not be performed correctly. Ensure that these bits are modified only when the WDT is not operating.

Section 14 Watchdog Timer (WDT) R01UH0198EJ0500 Rev. 5.00 Page 723 of 1560 Mar 18, 2011 SH7080 Group

14.3.3 Notes on Register Access

The watchdog timer counter (WTCNT) and watchdog timer control/status register (WTCSR) are more difficult to write to than other registers. The procedure for writing to these registers is given below. Writing to WTCNT and WTCSR: These registers must be written by a word transfer instruction. They cannot be written by a byte or longword transfer instruction. When writing to WTCNT, set the upper byte to H'5A and transfer the lower byte as the write data, as shown in figure 14.2. When writing to WTCSR, set the upper byte to H'A5 and transfer the lower byte as the write data. This transfer procedure writes the lower byte data to WTCNT or WTCSR. 15 8 7 0 H'5A Write dataAddress: H'FFFFE810 WTCNT write 15 8 7 0 H'A5 Write dataAddress: H'FFFFE812 WTCSR write Figure 14.2 Writing to WTCNT and WTCSR

Section 14 Watchdog Timer (WDT) Page 724 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

14.4 Operation

14.4.1 Revoking Software Standbys

The WDT can be used to revoke software standby mode with an NMI interrupt or external interrupt (IRQ). The procedure is described below. (The WDT does not run when resets are used for revoking, so keep the RES pin low until the clock stabilizes.) 1. Before transition to software standby mode, always clear the TME bit in WTCSR to 0. When the TME bit is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows. 2. Set the type of count clock used in the CKS2 to CKS0 bits in WTCSR and the initial values for the counter in the WTCNT counter. These values should ensure that the time till count overflow is longer than the clock oscillation settling time. 3. Transition to software standby mode by ex ecuting a SLEEP instruction to stop the clock. 4. The WDT starts counting by detecting a change in the level input to the NMI or IRQ pin. 5. When the WDT count overflows, the CPG starts supplying the clock and the LSI resumes operation. The WOVF flag in WTCSR is not set when this happens.

14.4.2 Using Watchdog Timer Mode

While operating in watchdog timer mode, the WDT generates an internal reset of the type specified by the RSTS bit in WTCSR and asserts a signal through the WDTOVF pin every time the counter overflows. 1. Set the WT/IT bit in WTCSR to 1, set the reset type in the RSTS bit, set the type of count clock in the CKS2 to CKS0 bits, and set the initial value of the counter in the WTCNT counter. 2. Set the TME bit in WTCSR to 1 to start the count in watchdog timer mode. 3. While operating in watchdog timer mode, rewrite the counter periodically to prevent the counter from overflowing. 4. When the counter overflows, the WDT sets the WOVF flag in WTCSR to 1, asserts a signal through the WDTOVF pin for one cycle of the count clock specified by the CKS2 to CKS0 bits, and generates a reset of the type specified by the RSTS bit. The counter then resumes counting.

Section 14 Watchdog Timer (WDT) R01UH0198EJ0500 Rev. 5.00 Page 725 of 1560 Mar 18, 2011 SH7080 Group WTCNT value H'FF H'00 WDTOVF signal Internal reset signal (power-on reset selected) Overflow occurs H'00 is written to WTCNT WT/IT = 1 TME = 1 H'00 is written to WTCNT Count starts WOVF = 1 WDTOVF is asserted and an internal reset is generated

32 Pφ clock

3 Pφ + one cycle of count clock

(manual reset selected)

18 Pφ clock

Figure 14.3 Operation in Watchdog Timer Mode (When WTCNT Count Clock Is Specified to Pφ/32 by CKS2 to CKS0)

14.4.3 Using Interval Timer Mode

When operating in interval timer mode, interval timer interrupts are generated at every overflow of the counter. This enables interrupts to be generated at set periods. 1. Clear the WT/IT bit in WTCSR to 0, set the type of count clock in the CKS2 to CKS0 bits, and set the initial value of the counter in the WTCNT counter. 2. Set the TME bit in WTCSR to 1 to start the count in interval timer mode. 3. When the counter overflows, the WDT sets the IOVF flag in WTCSR to 1 and an interval timer interrupt request is sent to the INTC. The counter then resumes counting.

Section 14 Watchdog Timer (WDT) Page 726 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

14.5 Interrupt Source

The WDT has one interrupt source: the interval timer interrupt (ITI). Table 14.3 shows this interrupt source. An interval timer interrupt (ITI) is generated when the interval timer overflow flag bit (IOVF) in the watchdog timer control status register (WTSCR) is set to 1. The interrupt request is canceled by clearing the interrupt flag to 0. Table 14.3 Interrupt Source Name Interrupt Source Interrupt Enable Bit Interrupt Flag Bit ITI Interval timer interrupt ⎯ Interval timer overflow flag (IOVF)

14.6 Usage Note

14.6.1 WTCNT Setting Value

If WTCNT is set to H'FF in interval timer mode, overflow does not occur when WTCNT changes from H'FF to H'00 after one cycle of count clock, but overflow occurs when WTCNT changes from H'FF to H'00 after 257 cycles of count clock. If WTCNT is set to H'FF in watchdog timer mode, overflow occurs when WTCNT changes from H'FF to H'00 after one cycle of count clock.

Section 15 Serial Communication Interface (SCI) R01UH0198EJ0500 Rev. 5.00 Page 727 of 1560 Mar 18, 2011 SH7080 Group Section 15 Serial Communication Interface (SCI) This LSI has three independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clock synchronous serial communication. In asynchronous serial communication mode, serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). A function is also provided for serial communication between processors (multiprocessor communication function).

15.1 Features

• Choice of asynchronous or clock synchronous serial communication mode
• Asynchronous mode: ⎯ Serial data communication is performed by start-stop in character units. The SCIF can communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous communication interface adapter (ACIA), or any other communications chip that employs a standard asynchronous serial system. There are twelve selectable serial data communication formats. ⎯ Data length: 7 or 8 bits ⎯ Stop bit length: 1 or 2 bits ⎯ Parity: Even, odd, or none ⎯ Multiprocessor communications ⎯ Receive error detection: Parity, overrun, and framing errors ⎯ Break detection: Break is detected by reading the RXD pin level directly when a framing error occurs.
• Clock synchronous mode: ⎯ Serial data communication is synchronized with a clock signal. The SCIF can communicate with other chips having a clock synchronous communication function. ⎯ Data length: 8 bits ⎯ Receive error detection: Overrun errors
• Full duplex communication: The transmitting and receiving sections are independent, so the SCI can transmit and receive simultaneously. Both sections use double buffering, so high- speed continuous data transfer is possible in both the transmit and receive directions.
• On-chip baud rate generator with selectable bit rates
• Internal or external transmit/receive clock source: From either baud rate generator (internal clock) or SCK pin (external clock)

Section 15 Serial Communication Interface (SCI) R01UH0198EJ0500 Rev. 5.00 Page 729 of 1560 Mar 18, 2011 SH7080 Group

15.2 Input/Output Pins

The SCI has the serial pins summarized in table 15.1. Table 15.1 Pin Configuration Channel Pin Name * I/O Function

0 SCK0 I/O SCI0 clock input/output

RXD0 Input SCI0 receive data input TXD0 Output SCI0 transmit data output

1 SCK1 I/O SCI1 clock input/output

RXD1 Input SCI1 receive data input TXD1 Output SCI1 transmit data output

2 SCK2 I/O SCI2 clock input/output

RXD2 Input SCI2 receive data input TXD2 Output SCI2 transmit data output Note: * Pin names SCK, RXD, and TXD are used in the description for all channels, omitting the channel designation.

Section 15 Serial Communication Interface (SCI) Page 730 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

15.3 Register Descriptions

The SCI has the following registers for each channel. For details on register addresses and register states during each processing, refer to section 27, List of Registers. Table 15.2 Register Configuration Chan- nel Register Name Abbrevia- tion R/W Initial Value Address Access Size

0 Serial mode register_0 SCSMR_0 R/W H'00 H'FFFFC000 8

Bit rate register_0 SCBRR_0 R/W H'FF H'FFFFC002 8 Serial control register_0 SCSCR_0 R/W H'00 H'FFFFC004 8 Transmit data register_0 SCTDR_0 ⎯ ⎯ H'FFFFC006 8 Serial status register_0 SCSSR_0 R/W H'84 H'FFFFC008 8 Receive data register_0 SCRDR_0 ⎯ ⎯ H'FFFFC00A 8 Serial direction control register_0 SCSDCR_0 R/W H'F2 H'FFFFC00C 8 Serial port register_0 SCSPTR_0 R/W H'0x H'FFFFC00E 8

1 Serial mode register_1 SCSMR_1 R/W H'00 H'FFFFC080 8

Bit rate register_1 SCBRR_1 R/W H'FF H'FFFFC082 8 Serial control register_1 SCSCR_1 R/W H'00 H'FFFFC084 8 Transmit data register_1 SCTDR_1 ⎯ ⎯ H'FFFFC086 8 Serial status register_1 SCSSR_1 R/W H'84 H'FFFFC088 8 Receive data register_1 SCRDR_1 ⎯ ⎯ H'FFFFC08A 8 Serial direction control register_1 SCSDCR_1 R/W H'F2 H'FFFFC08C 8 Serial port register_1 SCSPTR_1 R/W H'0x H'FFFFC08E 8

2 Serial mode register_2 SCSMR_2 R/W H'00 H'FFFFC100 8

Bit rate register_2 SCBRR_2 R/W H'FF H'FFFFC102 8 Serial control register_2 SCSCR_2 R/W H'00 H'FFFFC104 8 Transmit data register_2 SCTDR_2 ⎯ ⎯ H'FFFFC106 8 Serial status register_2 SCSSR_2 R/W H'84 H'FFFFC108 8 Receive data register_2 SCRDR_2 ⎯ ⎯ H'FFFFC10A 8 Serial direction control register_2 SCSDCR_2 R/W H'F2 H'FFFFC10C 8 Serial port register_2 SCSPTR_2 R/W H'0x H'FFFFC10E 8

Section 15 Serial Communication Interface (SCI) R01UH0198EJ0500 Rev. 5.00 Page 731 of 1560 Mar 18, 2011 SH7080 Group

15.3.1 Receive Shift Register (SCRSR)

SCRSR receives serial data. Data input at the RXD pin is loaded into SCRSR in the order received, LSB (bit 0) first, converting the data to parallel form. When one byte has been received, it is automatically transferred to SCRDR. The CPU cannot read or write to SCRSR directly. Bit: Initial value: R/W: 7654321 0

15.3.2 Receive Data Register (SCRDR)

SCRDR is a register that stores serial receive data. After receiving one byte of serial data, the SCI transfers the received data from the receive shift register (SCRSR) into SCRDR for storage and completes operation. After that, SCRSR is ready to receive data. Since SCRSR and SCRDR work as a double buffer in this way, data can be received continuously. SCRDR is a read-only register and cannot be written to by the CPU. Bit: Initial value: R/W: 7654321 0

15.3.3 Transmit Shift Register (SCTSR)

SCTSR transmits serial data. The SCI loads transmit data from the transmit data register (SCTDR) into SCTSR, then transmits the data serially from the TXD pin, LSB (bit 0) first. After transmitting one data byte, the SCI automatically loads the next transmit data from SCTDR into SCTSR and starts transmitting again. If the TDRE flag in the serial status register (SCSSR) is set to 1, the SCI does not transfer data from SCTDR to SCTSR. The CPU cannot read or write to SCTSR directly. Bit: Initial value: R/W: 7654321 0

Section 15 Serial Communication Interface (SCI) Page 732 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

15.3.4 Transmit Data Register (SCTDR)

SCTDR is an 8-bit register that stores data for serial transmission. When the SCI detects that the transmit shift register (SCTSR) is empty, it moves transmit data written in the SCTDR into SCTSR and starts serial transmission. If the next transmit data has been written to SCTDR during serial transmission from SCTSR, the SCI can transmit data continuously. SCTDR can always be written or read to by the CPU. Bit: Initial value: R/W: 7654321 0

15.3.5 Serial Mode Register (SCSMR)

SCSMR is an 8-bit register that specifies the SCI serial communication format and selects the clock source for the baud rate generator. The CPU can always read and write to SCSMR. Bit: Initial value: R/W: 7654321 0 00000000 R/W R/W R/W R/W R/W R/W R/W R/W C/A CHR PE O/ E STOP MP CKS[1:0] Bit Bit Name Initial value R/W Description

7 C/ A 0 R/W Communication Mode

Selects whether the SCI operates in asynchronous or clock synchronous mode. 0: Asynchronous mode 1: Clock synchronous mode

6 CHR 0 R/W Character Length

Selects 7-bit or 8-bit data in asynchronous mode. In the clock synchronous mode, the data length is always eight bits, regardless of the CHR setting. When 7-bit data is selected, the MSB (bit 7) of the transmit data register is not transmitted. 0: 8-bit data 1: 7-bit data

Section 15 Serial Communication Interface (SCI) R01UH0198EJ0500 Rev. 5.00 Page 733 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial value R/W Description

5 PE 0 R/W Parity Enable

Selects whether to add a parity bit to transmit data and to check the parity of receive data, in asynchronous mode. In clock synchronous mode, a parity bit is neither added nor checked, regardless of the PE setting. 0: Parity bit not added or checked 1: Parity bit added and checked* Note: * When PE is set to 1, an even or odd parity bit is added to transmit data, depending on the parity mode (O/E) setting. Receive data parity is checked according to the even/odd (O/E) mode setting.

4 O/ E 0 R/W Parity mode

Selects even or odd parity when parity bits are added and checked. The O/E setting is used only in asynchronous mode and only when the parity enable bit (PE) is set to 1 to enable parity addition and checking. The O/E setting is ignored in clock synchronous mode, or in asynchronous mode when parity addition and checking is disabled. 0: Even parity 1: Odd parity If even parity is selected, the parity bit is added to transmit data to make an even number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an even number of 1s in the received character and parity bit combined. If odd parity is selected, the parity bit is added to transmit data to make an odd number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an odd number of 1s in the received character and parity bit combined.

Section 15 Serial Communication Interface (SCI) Page 734 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial value R/W Description

3 STOP 0 R/W Stop Bit Length

Selects one or two bits as the stop bit length in asynchronous mode. This setting is used only in asynchronous mode. It is ignored in clock synchronous mode because no stop bits are added. 0: One stop bit* 1: Two stop bits* When receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of the next incoming character. Notes: 1. When transmitting, a single 1-bit is added at the end of each transmitted character. 2. When transmitting, two 1 bits are added at the end of each transmitted character.

2 MP 0 R/W Multiprocessor Mode (only in asynchronous mode)

Enables or disables multiprocessor mode. The PE and O/E bit settings are ignored in multiprocessor mode. 0: Multiprocessor mode disabled 1: Multiprocessor mode enabled 1, 0 CKS[1:0] 00 R/W Clock Select 1 and 0 Select the internal clock source of the on-chip baud rate generator. Four clock sources are available. Pφ, Pφ/4, Pφ/16 and Pφ/64. For further information on the clock source, bit rate register settings, and baud rate, see section 15.3.10, Bit Rate Register (SCBRR). 00: Pφ 01: Pφ/4 10: Pφ/16 11: Pφ/64 Note: P φ: Peripheral clock

Section 15 Serial Communication Interface (SCI) R01UH0198EJ0500 Rev. 5.00 Page 735 of 1560 Mar 18, 2011 SH7080 Group

15.3.6 Serial Control Register (SCSCR)

SCSCR is an 8-bit register that enables or disables SCI transmission/reception and interrupt requests and selects the transmit/receive clock source. The CPU can always read and write to SCSCR. Bit: Initial value: R/W: 7654321 0 00000000 R/W R/W R/W R/W R/W R/W R/W R/W TIE RIE TE RE MPIE TEIE CKE[1:0] Bit Bit Name Initial value R/W Description

7 TIE 0 R/W Transmit Interrupt Enable

Enables or disables a transmit-data-empty interrupt (TXI) to be issued when the TDRE flag in the serial status register (SCSSR) is set to 1 after serial transmit data is sent from the transmit data register (SCTDR) to the transmit shift register (SCTSR). TXI can be canceled by clearing the TDRE flag to 0 after reading TDRE = 1 or by clearing the TIE bit to 0. 0: Transmit-data-empty interrupt request (TXI) is disabled 1: Transmit-data-empty interrupt request (TXI) is enabled

6 RIE 0 R/W Receive Interrupt Enable

Enables or disables a receive-data-full interrupt (RXI) and a receive error interrupt (ERI) to be issued when the RDRF flag in SCSSR is set to 1 after the serial data received is transferred from the receive shift register (SCRSR) to the receive data register (SCRDR). RXI can be canceled by clearing the RDRF flag after reading RDRF =1. ERI can be canceled by clearing the FER, PER, or ORER flag to 0 after reading 1 from the flag. Both RXI and ERI can also be canceled by clearing the RIE bit to 0. 0: Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are disabled 1: Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are enabled

Section 15 Serial Communication Interface (SCI) Page 736 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial value R/W Description

5 TE 0 R/W Transmit Enable

Enables or disables the SCI serial transmitter. 0: Transmitter disabled* 1: Transmitter enabled* Notes: 1. The TDRE flag in SCSSR is fixed at 1. 2. Serial transmission starts after writing transmit data into SCTDR and clearing the TDRE flag in SCSSR to 0 while the transmitter is enabled. Select the transmit format in the serial mode register (SCSMR) before setting TE to 1.

4 RE 0 R/W Receive Enable

Enables or disables the SCI serial receiver. 0: Receiver disabled* 1: Receiver enabled* Notes: 1. Clearing RE to 0 does not affect the receive flags (RDRF, FER, PER, and ORER). These flags retain their previous values. 2. Serial reception starts when a start bit is detected in asynchronous mode, or synchronous clock input is detected in clock synchronous mode. Select the receive format in SCSMR before setting RE to 1.

3 MPIE 0 R/W Multiprocessor Interrupt Enable (only when MP = 1 in

SCSMR in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped and setting of the RDRF, FER, and ORER status flags in SCSSR is prohibited. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared to 0 and normal receiving operation is resumed. For details, refer to section 15.4.4, Multiprocessor Communication Function.

Section 15 Serial Communication Interface (SCI) R01UH0198EJ0500 Rev. 5.00 Page 737 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial value R/W Description

2 TEIE 0 R/W Transmit End Interrupt Enable

Enables or disables a transmit end interrupt (TEI) to be issued when no valid transmit data is found in SCTDR during MSB data transmission. TEI can be canceled by clearing the TEND flag to 0 (by clearing the TDRE flag in SCSSR to 0 after reading TDRE = 1) or by clearing the TEIE bit to 0. 0: Transmit end interrupt request (TEI) is disabled 1: Transmit end interrupt request (TEI) is enabled 1, 0 CKE[1:0] 00 R/W Clock Enable 1 and 0 Select the SCI clock source and enable or disable clock output from the SCK pin. Depending on the combination of CKE1 and CKE0, the SCK pin can be used for serial clock output or serial clock input. When selecting the clock output in clock synchronous mode, set the C/A bit in SCSMR to 1 and then set bits CKE1 and CKE0. For details on clock source selection, refer to table 15.14.

• Asynchronous mode 00: Internal clock, SCK pin used for input pin (The input signal is ignored.) 01: Internal clock, SCK pin used for clock output* 10: External clock, SCK pin used for clock input* 11: External clock, SCK pin used for clock input*
• Clock synchronous mode 00: Internal clock, SCK pin used for synchronous clock output 01: Internal clock, SCK pin used for synchronous clock output 10: External clock, SCK pin used for synchronous clock input 11: External clock, SCK pin used for synchronous clock input Notes: 1. The output clock frequency is 16 times the bit rate. 2. The input clock frequency is 16 times the bit rate.

Section 15 Serial Communication Interface (SCI) Page 738 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

15.3.7 Serial Status Register (SCSSR)

SCSSR is an 8-bit register that contains status flags to indicate the SCI operating state. The CPU can always read and write to SCSSR, but cannot write 1 to status flags TDRE, RDRF, ORER, PER, and FER. These flags can be cleared to 0 only after 1 is read from the flags. The TEND flag is a read-only bit and cannot be modified. Bit: Initial value: R/W: 7654321 0 10000100 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W TDRE RDRF ORER FER PER TEND MPB MPBT Note: Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.* Bit Bit Name Initial value R/W Description

7 TDRE 1 R/(W) * Transmit Data Register Empty

Indicates whether data has been transferred from the transmit data register (SCTDR) to the transmit shift register (SCTSR) and SCTDR has become ready to be written with next serial transmit data. 0: Indicates that SCTDR holds valid transmit data [Clearing conditions]

• When 0 is written to TDRE after reading TDRE = 1
• When data is written to SCTDR by a TXI interrupt through the DMAC
• When the DTC is activated by a TXI interrupt and transmit data is transferred to SCTDR while the DISEL bit of MRB in the DTC is 0 1: Indicates that SCTDR does not hold valid transmit data [Setting conditions]
• By a power-on reset or in standby mode
• When the TE bit in SCSCR is 0
• When data is transferred from SCTDR to SCTSR and data can be written to SCTDR

Section 15 Serial Communication Interface (SCI) R01UH0198EJ0500 Rev. 5.00 Page 739 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial value R/W Description

6 RDRF 0 R/(W) * Receive Data Register Full

Indicates that the received data is stored in the receive data register (SCRDR). 0: Indicates that valid received data is not stored in SCRDR [Clearing conditions]

• By a power-on reset or in standby mode
• When 0 is written to RDRF after reading RDRF =
• When the SCRDR data is read by an RXI interrupt through the DMAC
• When the DTC is activated by an RXI interrupt and data is transferred from SCRDR while the DISEL bit of MRB in the DTC is 0 1: Indicates that valid received data is stored in SCRDR [Setting condition]
• When serial reception ends normally and receive data is transferred from SCRSR to SCRDR Note: SCRDR and the RDRF flag are not affected and retain their previous states even if an error is detected during data reception or if the RE bit in the serial control register (SCSCR) is cleared to 0. If reception of the next data is completed while the RDRF flag is still set to 1, an overrun error will occur and the received data will be lost.

Section 15 Serial Communication Interface (SCI) Page 740 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial value R/W Description

5 ORER 0 R/(W) * Overrun Error

Indicates that an overrun error occurred during reception, causing abnormal termination. 0: Indicates that reception is in progress or was completed successfully* [Clearing conditions]

• By a power-on reset or in standby mode
• When 0 is written to ORER after reading ORER = 1: Indicates that an overrun error occurred during reception* [Setting condition]
• When the next serial reception is completed while RDRF = 1 Notes: 1. The ORER flag is not affected and retains its previous value when the RE bit in SCSCR is cleared to 0. 2. The receive data prior to the overrun error is retained in SCRDR, and the data received subsequently is lost. Subsequent serial reception cannot be continued while the ORER flag is set to 1.

Section 15 Serial Communication Interface (SCI) R01UH0198EJ0500 Rev. 5.00 Page 741 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial value R/W Description

4 FER 0 R/(W) * Framing Error

Indicates that a framing error occurred during data reception in asynchronous mode, causing abnormal termination. 0: Indicates that reception is in progress or was completed successfully* [Clearing conditions]

• By a power-on reset or in standby mode
• When 0 is written to FER after reading FER = 1 1: Indicates that a framing error occurred during reception [Setting condition]
• When the SCI founds that the stop bit at the end of the received data is 0 after completing reception* Notes: 1. The FER flag is not affected and retains its previous value when the RE bit in SCSCR is cleared to 0. 2. In 2-stop-bit mode, only the first stop bit is checked for a value to 1; the second stop bit is not checked. If a framing error occurs, the receive data is transferred to SCRDR but the RDRF flag is not set. Subsequent serial reception cannot be continued while the FER flag is set to 1.

Section 15 Serial Communication Interface (SCI) Page 742 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial value R/W Description

3 PER 0 R/(W) * Parity Error

Indicates that a parity error occurred during data reception in asynchronous mode, causing abnormal termination. 0: Indicates that reception is in progress or was completed successfully* [Clearing conditions]

• By a power-on reset or in standby mode
• When 0 is written to PER after reading PER = 1 1: Indicates that a parity error occurred during reception* [Setting condition]
• When the number of 1s in the received data and parity does not match the even or odd parity specified by the O/E bit in the serial mode register (SCSMR). Notes: 1. The PER flag is not affected and retains its previous value when the RE bit in SCSCR is cleared to 0. 2. If a parity error occurs, the receive data is transferred to SCRDR but the RDRF flag is not set. Subsequent serial reception cannot be continued while the PER flag is set to 1.

Section 15 Serial Communication Interface (SCI) R01UH0198EJ0500 Rev. 5.00 Page 743 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial value R/W Description

2 TEND 1 R Transmit End

Indicates that no valid data was in SCTDR during transmission of the last bit of the transmit character and transmission has ended. The TEND flag is read-only and cannot be modified. 0: Indicates that transmission is in progress [Clearing condition]

• When 0 is written to TDRE after reading TDRE = 1 1: Indicates that transmission has ended [Setting conditions]
• By a power-on reset or in standby mode
• When the TE bit in SCSCR is 0
• When TDRE = 1 during transmission of the last bit of a 1-byte serial transmit character Note: The TEND flag value becomes undefined if data is written to SCTDR by activating the DMAC or DTC by a TXI interrupt. In this case, do not use the TEND flag as the transmit end flag.

1 MPB 0 R Multiprocessor Bit

Stores the multiprocessor bit found in the receive data. When the RE bit in SCSCR is cleared to 0, its previous state is retained.

0 MPBT 0 R/W Multiprocessor Bit Transfer

Specifies the multiprocessor bit value to be added to the transmit frame. Note: * Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.

Section 15 Serial Communication Interface (SCI) Page 744 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

15.3.8 Serial Port Register (SCSPTR)

SCSPTR is an 8-bit register that controls input/output and data for the ports multiplexed with the SCI function pins. Data to be output through the TXD pin can be specified to control break of serial transfer. Through bits 3 and 2, data reading and writing through the SCK pin can be specified. Bit 7 enables or disables RXI interrupts. The CPU can always read and write to SCSPTR. When reading the value on the SCI pins, use the respective port register. For details, refer to section 22, I/O Ports. Bit: Initial value: R/W: 76543210 00000-01 R/W - - - R/W R/W R/W R/W E I O --- SPB1IO SPB1DT SPB0IO SPB0DT Bit Bit Name Initial value R/W Description

7 EIO 0 R/W Error Interrupt Only

Enables or disables RXI interrupts. While the EIO bit is set to 1, the SCI does not request an RXI interrupt to the CPU even if the RIE bit is set to 1. 0: The RIE bit enables or disables RXI and ERI interrupts. While the RIE bit is 1, RXI and ERI interrupts are sent to the INTC. 1: While the RIE bit is 1, only the ERI interrupt is sent to the INTC. 6 to 4 ⎯ All 0 ⎯ Reserved These bits are always read as 0. The write value should always be 0.

3 SPB1IO 0 R/W Clock Port Input/Output in Serial Port

Specifies the input/output direction of the SCK pin in the serial port. To output the data specified in the SPB1DT bit through the SCK pin as a port output pin, set the C/A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR to 0. 0: Does not output the SPB1DT bit value through the SCK pin. 1: Outputs the SPB1DT bit value through the SCK pin.

Section 15 Serial Communication Interface (SCI) R01UH0198EJ0500 Rev. 5.00 Page 745 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial value R/W Description

2 SPB1DT Undefined R/W Clock Port Data in Serial Port

Specifies the data output through the SCK pin in the serial port. Output should be enabled by the SPB1IO bit (for details, refer to the SPB1IO bit description). When output is enabled, the SPB1DT bit value is output through the SCK pin. 0: Low level is output 1: High level is output

1 SPB0IO 0 R/W Serial Port Break Output

Together with the SPB0DT bit and the TE bit in SCSCR, controls the TXD pin. Serial Port Break Data Together with the SPB0IO bit and TE bit in SCSCR, controls the TXD pin. Note that the TXD pin function needs to have been selected with the pin function controller (PFC). TE bit setting in SCSCR SPB0IO bit setting SPB0DT bit setting State of TXD pin 0 0 * SPB0DT output disabled (initial state) 0 1 0 Output, low level 0 1 1 Output, high level 1 * * Output for transmit data in accord with the serial core logic

0 SPB0DT 1 R/W

Note: * Don't care

Section 15 Serial Communication Interface (SCI) Page 746 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

15.3.9 Serial Direction Control Register (SCSDCR)

The DIR bit in the serial direction control register (SCSDCR) selects LSB-first or MSB-first transfer. With an 8-bit data length, LSB-first/MSB-first selection is available regardless of the communication mode. Bit: Initial value: R/W: 7654321 0 11110010 RRRR R / W RRR ---- D I R --- Bit Bit Name Initial Value R/W Description 7 to 4 ⎯ All 1 R Reserved These bits are always read as 1. The write value should always be 1.

3 DIR 0 R/W Data Transfer Direction

Selects the serial/parallel conversion format. Valid for an 8-bit transmit/receive format. 0: SCTDR contents are transmitted in LSB-first order Receive data is stored in SCRDR in LSB-first 1: SCTDR contents are transmitted in MSB-first order Receive data is stored in SCRDR in MSB-first 2 ⎯ 0 R Reserved This bit is always read as 0. The write value should always be 0. 1 ⎯ 1 R Reserved This bit is always read as 1. The write value should always be 1. 0 ⎯ 0 R Reserved This bit is always read as 0. The write value should always be 0.

Section 15 Serial Communication Interface (SCI) R01UH0198EJ0500 Rev. 5.00 Page 747 of 1560 Mar 18, 2011 SH7080 Group

15.3.10 Bit Rate Register (SCBRR)

SCBRR is an 8-bit register that, together with the baud rate generator clock source selected by the CKS1 and CKS0 bits in the serial mode register (SCSMR), determines the serial transmit/receive bit rate. The CPU can always read and write to SCBRR. The SCBRR setting is calculated as follows: Bit: Initial value: R/W: 7654321 0 11111111 R/W R/W R/W R/W R/W R/W R/W R/W

• Asynchronous mode: N = × 106 - 164 × 22n-1 × B Pφ
• Clock synchronous mode: N = × 106 - 18 × 22n-1 × B Pφ B: Bit rate (bits/s) N: SCBRR setting for baud rate generator (0 ≤ N ≤ 255) (The setting value should satisfy the electrical characteristics.) Pφ: Operating frequency for peripheral modules (MHz) n: Baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of n, see table 15.3.)

Section 15 Serial Communication Interface (SCI) Page 748 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 15.3 SCSMR Settings SCSMR Settings n Clock Source CKS1 CKS0

0 P φ 0 0

1 P φ/4 0 1

2 P φ/16 1 0

3 P φ/64 1 1

Note: The bit rate error in asynchronous is given by the following formula: Pφ × 106

Section 15 Serial Communication Interface (SCI) R01UH0198EJ0500 Rev. 5.00 Page 749 of 1560 Mar 18, 2011 SH7080 Group Tables 15.4 to 15.6 show examples of SCBRR settings in asynchronous mode, and tables 15.7 to 15.9 show examples of SCBRR settings in clock synchronous mode. Table 15.4 Bit Rates and SCBRR Settings in Asynchronous Mode (1) Pφ (MHz) 10 12 14 16 18 20 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) n N Error (%) n N Error (%)

Section 15 Serial Communication Interface (SCI) Page 750 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 15.5 Bit Rates and SCBRR Settings in Asynchronous Mode (2) Pφ (MHz) 22 24 26 28 30 32 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) n N Error (%) n N Error (%)

Section 15 Serial Communication Interface (SCI) R01UH0198EJ0500 Rev. 5.00 Page 751 of 1560 Mar 18, 2011 SH7080 Group Table 15.6 Bit Rates and SCBRR Settings in Asynchronous Mode (3) Pφ (MHz) 34 36 38 40 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 3 150 -0.05 3 159 -0.12 3 168 -0.19 3 177 -0.25 150 3 110 -0.29 3 116 0.16 3 123 -0.24 3 129 0.16 300 2 220 0.16 2 233 0.16 2 246 0.16 3 64 0.16 600 2 110 -0.29 2 116 0.16 2 123 -0.24 2 129 0.16 1200 1 220 0.16 1 233 0.16 1 246 0.16 2 64 0.16 2400 1 110 -0.29 1 116 0.16 1 123 -0.24 1 129 0.16 4800 0 220 0.16 0 233 0.16 0 246 0.16 1 64 0.16 9600 0 110 -0.29 0 116 0.16 0 123 -0.24 0 129 0.16 14400 0 73 -0.29 0 77 0.16 0 81 0.57 0 86 -0.22 19200 0 54 0.62 0 58 -0.69 0 61 -0.24 0 64 0.16 28800 0 36 -0.29 0 38 0.16 0 40 0.57 0 42 0.94 31250 0 33 0.00 0 35 0.00 0 37 0.00 0 39 0.00 38400 0 27 -1.18 0 28 1.02 0 30 -0.24 0 32 -1.36

Section 15 Serial Communication Interface (SCI) Page 752 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 15.7 Bit Rates and SCBRR Settings in Clock Synchronous Mode (1) P φ (MHz) 10 12 14 16 18 20 Bit Rate (bits/s) n N n N n N n N n N n N 250 3 155 3 187 3 218 3 249 500 3 77 3 93 3 108 3 124 3 140 3 155 1000 2 155 2 187 2 218 2 249 3 69 3 77 2500 1 249 2 74 2 87 2 99 2 112 2 124 5000 1 124 1 149 1 174 1 199 1 224 1 249 10000 0 249 1 74 1 87 1 99 1 112 1 124 25000 0 99 0 119 0 139 0 159 0 179 0 199 50000 0 49 0 59 0 69 0 79 0 89 0 99 100000 0 24 0 29 0 34 0 39 0 44 0 49 250000 0 9 0 11 0 13 0 15 0 17 0 19 500000 0 4 0 5 0 6 0 7 0 8 0 9 1000000 ⎯ ⎯ 0 2 ⎯ ⎯ 0 3 ⎯ ⎯ 0 4

Section 15 Serial Communication Interface (SCI) R01UH0198EJ0500 Rev. 5.00 Page 753 of 1560 Mar 18, 2011 SH7080 Group Table 15.8 Bit Rates and SCBRR Settings in Clock Synchronous Mode (2) P φ (MHz) 22 24 26 28 30 32 Bit Rate (bits/s) n N n N n N n N n N n N 250 500 3 171 3 187 3 202 3 218 3 233 3 249 1000 3 85 3 93 3 101 3 108 3 116 3 124 2500 2 137 2 149 2 162 2 174 2 187 2 199 5000 2 68 2 74 2 80 2 87 2 93 2 99 10000 1 137 1 149 1 162 1 174 1 187 1 199 25000 0 219 0 239 1 64 1 69 1 74 1 79 50000 0 109 0 119 0 129 0 139 0 149 0 159 100000 0 54 0 59 0 64 0 69 0 74 0 79 250000 0 21 0 23 0 25 0 27 0 29 0 31 500000 0 10 0 11 0 12 0 13 0 14 0 15 1000000 ⎯ ⎯ 0 5 ⎯ ⎯ 0 6 ⎯ ⎯ 0 7

Section 15 Serial Communication Interface (SCI) Page 754 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 15.9 Bit Rates and SCBRR Settings in Clock Synchronous Mode (3) P φ (MHz) 34 36 38 40 Bit Rate (bits/s) n N n N n N n N 250 500 1000 3 132 3 140 3 147 3 155 2500 2 212 2 224 2 237 2 249 5000 2 105 2 112 2 118 2 124 10000 1 212 1 224 1 237 1 249 25000 1 84 1 89 1 94 1 99 50000 0 169 0 179 0 189 0 199 100000 0 84 0 89 0 94 0 99 250000 0 33 0 35 0 37 0 39 500000 0 16 0 17 0 18 0 19 1000000 ⎯ ⎯ 0 8 ⎯ ⎯ 0 9 [Legend] Blank: No setting possible ⎯: Setting possible, but error occurs *: Continuous transmission/reception is disabled. Note: Settings with an error of 1% or less are recommended.

Section 15 Serial Communication Interface (SCI) R01UH0198EJ0500 Rev. 5.00 Page 755 of 1560 Mar 18, 2011 SH7080 Group Table 15.10 indicates the maximum bit rates in asynchronous mode when the baud rate generator is used. Tables 15.11 and 15.12 list the maximum rates for external clock input. Table 15.10 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode) Settings Pφ (MHz) Maximum Bit Rate (bits/s) n N 10 312500 0 0 12 375000 0 0 14 437500 0 0 16 500000 0 0 18 562500 0 0 20 625000 0 0 22 687500 0 0 24 750000 0 0 26 812500 0 0 28 875000 0 0 30 937500 0 0 32 1000000 0 0 34 1062500 0 0 36 1125000 0 0 38 1187500 0 0 40 1250000 0 0

Section 15 Serial Communication Interface (SCI) Page 756 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 15.11 Maximum Bit Rates with External Clock Input (Asynchronous Mode) Pφ (MHz) External Input Clock (M Hz) Maximum Bit Rate (bits/s) 10 2.5000 156250 12 3.0000 187500 14 3.5000 218750 16 4.0000 250000 18 4.5000 281250 20 5.0000 312500 22 5.5000 343750 24 6.0000 375000 26 6.5000 406250 28 7.0000 437500 30 7.5000 468750 32 8.0000 500000 34 8.5000 531250 36 9.0000 562500 38 9.5000 593750 40 10.0000 625000

Section 15 Serial Communication Interface (SCI) R01UH0198EJ0500 Rev. 5.00 Page 757 of 1560 Mar 18, 2011 SH7080 Group Table 15.12 Maximum Bit Rates with External Clock Input (Clock Synchronous Mode) Pφ (MHz) External Input Clock (M Hz) Maximum Bit Rate (bits/s) 10 1.6667 1666666.7 12 2.0000 2000000.0 14 2.3333 2333333.3 16 2.6667 2666666.7 18 3.0000 3000000.0 20 3.3333 3333333.3 22 3.6667 3666666.7 24 4.0000 4000000.0 26 4.3333 4333333.3 28 4.6667 4666666.7 30 5.0000 5000000.0 32 5.3333 5333333.3 34 5.6667 5666666.7 36 6.0000 6000000.0 38 6.3333 6333333.3 40 6.6667 6666666.7

Section 15 Serial Communication Interface (SCI) Page 758 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

15.4 Operation

15.4.1 Overview

For serial communication, the SCI has an asynchronous mode in which characters are synchronized individually, and a clock synchronous mode in which communication is synchronized with clock pulses. Asynchronous or clock synchronous mode is selected and the transmit format is specified in the serial mode register (SCSMR) as shown in table 15.13. The SCI clock source is selected by the combination of the C/A bit in SCSMR and the CKE1 and CKE0 bits in the serial control register (SCSCR) as shown in table 15.14. (1) Asynchronous Mode

• Data length is selectable: 7 or 8 bits.
• Parity bit is selectable. So is the stop bit length (1 or 2 bits). The combination of the preceding selections constitutes the communication format and character length.
• In receiving, it is possible to detect framing errors, parity errors, overrun errors, and breaks.
• An internal or external clock can be selected as the SCI clock source. ⎯ When an internal clock is selected, the SCI operates using the clock supplied by the on- chip baud rate generator and can output a clock with a frequency 16 times the bit rate. ⎯ When an external clock is selected, the external clock input must have a frequency 16 times the bit rate. (The on-chip baud rate generator is not used.) (2) Clock Synchronous Mode
• The transmission/reception format has a fixed 8-bit data length.
• In receiving, it is possible to detect overrun errors.
• An internal or external clock can be selected as the SCI clock source. ⎯ When an internal clock is selected, the SCI operates using the on-chip baud rate generator, and outputs a serial clock signal to external devices. ⎯ When an external clock is selected, the SCI operates on the input serial clock. The on-chip baud rate generator is not used.

Section 15 Serial Communication Interface (SCI) R01UH0198EJ0500 Rev. 5.00 Page 759 of 1560 Mar 18, 2011 SH7080 Group Table 15.13 SCSMR Settings and SCI Communication Formats SCSMR Settings SCI Communication Format Bit 7 C/A Bit 6 CHR Bit 5 PE Bit 3 STOP Mode Data Length Parity Bit Stop Bit Length 0 0 0 0 8-bit Not set 1 bit 1 2 bits 1 0 Set 1 bit 1 2 bits 1 0 0 7-bit Not set 1 bit 1 2 bits 1 0 Set 1 bit Asynchronous 2 bits 1 x x x Clock synchronous 8-bit Not set None [Legend] x: Don't care Table 15.14 SCSMR and SCSCR Setting s and SCI Clock Source Selection SCSMR SCSCR Settings Bit 7 C/A Bit 1 CKE1 Bit 0 CKE0 Mode Clock Source SCK Pin Function 0 0 0 Asynchronous Internal SCI does not use the SCK pin.

1 Clock with a frequency 16 times the bit rate

is output. 1 0 External Input a clock with frequency 16 times the bit rate. 1 0 0 Internal Serial clock is output. Clock synchronous 1 0 External Input the serial clock.

Section 15 Serial Communication Interface (SCI) Page 760 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

15.4.2 Operation in Asynchronous Mode

In asynchronous mode, each transmitted or received character begins with a start bit and ends with a stop bit. Serial communication is synchronized one character at a time. The transmitting and receiving sections of the SCI are independent, so full duplex communication is possible. Both the transmitter and receiver have a double-buffered structure so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 15.2 shows the general format of asynchronous serial communication. In asynchronous serial communication, the communication line is normally held in the mark (high) state. The SCI monitors the line and starts serial communication when the line goes to the space (low) state, indicating a start bit. One serial character consists of a start bit (low), data (LSB first), parity bit (high or low), and stop bit (high), in that order. When receiving in asynchronous mode, the SCI synchronizes at the falling edge of the start bit. The SCI samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate. Receive data is latched at the center of each bit. LSB Start bit MSB Idle state (mark state) Stop bit Transmit/receive data D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 1 Serial data Parity bit 1 bit 1 or 2 bits 7 or 8 bits 1 bit or none One unit of transfer data (character or frame) Figure 15.2 Example of Data Format in Asynchronous Communication (8-Bit Data with Parity and Two Stop Bits)

Section 15 Serial Communication Interface (SCI) R01UH0198EJ0500 Rev. 5.00 Page 761 of 1560 Mar 18, 2011 SH7080 Group (1) Transmit/Receive Formats Table 15.15 shows the transfer formats that can be selected in asynchronous mode. Any of 12 transfer formats can be selected according to the SCSMR settings. Table 15.15 Serial Transfer Formats (Asynchronous Mode) [Legend] S: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit x: Don't care PE x x x x S 8-bit data STOP S 7-bit data STOP S 8-bit data STOP STOP S 8-bit data P STOP S 7-bit data STOPP S 8-bit data MPB STOP S 8-bit data MPB STOP STOP S 7-bit data STOPMPB S 7-bit data STOPMPB STOP S 7-bit data STOPSTOP CHR MP STOP SCSMR Settings 123456789 1 0 1 1 1 2 Serial Transfer Format and Frame Length STOPS 8-bit data P STOP S 7-bit data STOPP STOP

Section 15 Serial Communication Interface (SCI) Page 762 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group (2) Clock An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in the serial mode register (SCSMR) and bits CKE1 and CKE0 in the serial control register (SCSCR) (table 15.14). When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the desired bit rate. When the SCI operates on an internal clock, it can output a clock signal at the SCK pin. The frequency of this output clock is equal to 16 times the desired bit rate. (3) Transmitting and Receiving Data SCI Initialization (Asynchronous Mode): Before transmitting or receiving, clear the TE and RE bits to 0 in the serial control register (SCSCR), then initialize the SCI as follows. When changing the operation mode or the communication format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing the TE bit to 0 sets the TDRE flag to 1 and initializes the transmit shift register (SCTSR). Clearing the RE bit to 0, however, does not initialize the RDRF, PER, FER, and ORER flags or receive data register (SCRDR), which retain their previous contents. When an external clock is used, the clock should not be stopped during initialization or subsequent operation. SCI operation becomes unreliable if the clock is stopped.

Section 15 Serial Communication Interface (SCI) R01UH0198EJ0500 Rev. 5.00 Page 763 of 1560 Mar 18, 2011 SH7080 Group [4] [5] < Initialization completed> [1] Set the clock selection in SCSCR. [2] Set the data transfer format in SCSMR and SCSDCR. [3] Write a value corresponding to the bit rate to SCBRR. Not necessary if an external clock is used. [4] Set PFC of the external pin used. Set RXD input during receiving and TXD output during transmitting. Set SCK input/output according to contents set by CKE1 and CKE0. When CKE1 and CKE0 are 0 in asynchronous mode, setting the SCK pin is unnecessary. Outputting clocks from the SCK pin starts at synchronous clock output setting. [5] Set the TE bit or RE bit in SCSCR to 1. * Also make settings of the RIE, TIE, TEIE, and MPIE bits. At this time, the TXD, RXD, and SCK pins are ready to be used. The TXD pin is in a mark state during transmitting, and RXD pin is in an idle state for waiting the start bit during receiving. Set the PFC for the external pins to be used (SCK, TXD, RXD) Set TE and RE bits of SCSCR to 1 Set the RIE, TIE, TEIE, and MPIE bits in SCSCR Wait Yes [1] Start initialization Clear RIE, TIE, TEIE, MPIE, TE, and RE bits in SCSCR to 0* [2] No Set value in SCBRR [3] 1-bit interval elapsed? Set data transfer format in SCSMR, SCSDCR Set CKE1 and CKE0 bits in SCSCR (TE and RE bits are 0) Note : * In simultaneous transmit/receive operation, the TE and RE bits must be cleared to 0 or set to 1 simultaneously. Figure 15.3 Sample Flowchart for SCI Initialization

Section 15 Serial Communication Interface (SCI) R01UH0198EJ0500 Rev. 5.00 Page 765 of 1560 Mar 18, 2011 SH7080 Group In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in the serial status register (SCSSR). If it is cleared to 0, the SCI recognizes that data has been written to the transmit data register (SCTDR) and transfers the data from SCTDR to the transmit shift register (SCTSR). 2. After transferring data from SCTDR to SCTSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in the serial control register (SCSCR) is set to 1 at this time, a transmit-data-empty interrupt (TXI) request is generated. The serial transmit data is sent from the TXD pin in the following order. A. Start bit: One-bit 0 is output. B. Transmit data: 8-bit or 7-bit data is output in LSB-first order. C. Parity bit or multiprocessor bit: One parity bit (even or odd parity) or one multiprocessor bit is output. (A format in which neither parity nor multiprocessor bit is output can also be selected.) D. Stop bit(s): One or two 1 bits (stop bits) are output. E. Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. The SCI checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is 0, the data is transferred from SCTDR to SCTSR, the stop bit is sent, and then serial transmission of the next frame is started. If the TDRE flag is 1, the TEND flag in SCSSR is set to 1, the stop bit is sent, and then the "mark state" is entered in which 1 is output. If the TEIE bit in SCSCR is set to 1 at this time, a TEI interrupt request is generated.

Section 15 Serial Communication Interface (SCI) Page 766 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Figure 15.5 shows an example of the operation for transmission.

0 D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 1

(mark state) Data Parity bit Stop bit TXI interrupt request Data written to SCTDR and TDRE flag cleared to 0 by TXI interrupt handler One frame TXI interrupt request TEI interrupt request Figure 15.5 Example of Transmission in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit)

Section 15 Serial Communication Interface (SCI) Page 768 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group <End> Error processing Parity error processing Yes No Clear ORER, PER, and FER flags in SCSSR to 0 No Yes No Yes Framing error processing No Yes Overrun error processing ORER = 1? FER = 1? Break? PER = 1? Clear RE bit in SCSCR to 0 Figure 15.6 Sample Flowchart for Receiving Serial Data (2)

Section 15 Serial Communication Interface (SCI) R01UH0198EJ0500 Rev. 5.00 Page 769 of 1560 Mar 18, 2011 SH7080 Group In serial reception, the SCI operates as described below. 1. The SCI monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR in LSB-to-MSB order. 3. The parity bit and stop bit are received. After receiving these bits, the SCI carries out the following checks. A. Parity check: Th e SCI counts the number of 1s in the received data and checks whether the count matches the even or odd parity specified by the O/E bit in the serial mode register (SCSMR). B. Stop bit check: The SCI checks wh ether the stop bit is 1. If there are two stop bits, only the first is checked. C. Status check: The SCI checks whether the RDRF flag is 0 and the received data can be transferred from the receive shift register (SCRSR) to SCRDR. If all the above checks are passed, the RDRF flag is set to 1 and the received data is stored in SCRDR. If a receive error is detected, the SCI operates as shown in table 15.16 Note: When a receive error occurs, subsequent reception cannot be continued. In addition, the RDRF flag will not be set to 1 after reception; be sure to clear the error flag to 0. 4. If the EIO bit in SCSPTR is cleared to 0 and the RIE bit in SCSCR is set to 1 when the RDRF flag changes to 1, a receive-data-full interrupt (RXI) request is generated. If the RIE bit in SCSCR is set to 1 when the ORER, PER, or FER flag changes to 1, a receive error interrupt (ERI) request is generated. Table 15.16 Receive Errors and Error Conditions Receive Error Abbreviation Error Condition Data Transfer Overrun error ORER When the next data reception is completed while the RDRF flag in SCSSR is set to 1 The received data is not transferred from SCRSR to SCRDR. Framing error FER When the stop bit is 0 The received data is transferred from SCRSR to SCRDR. Parity error PER When the received data does not match the even or odd parity specified in SCSMR The received data is transferred from SCRSR to SCRDR.

Section 15 Serial Communication Interface (SCI) Page 770 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Figure 15.7 shows an example of the operation for reception.

0 D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 0/1 1

Figure 15.7 Example of SCI Receive Operation (8-Bit Data, Parity, One Stop Bit)

15.4.3 Clock Synchronous Mode

In clock synchronous mode, the SCIF transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCI transmitter and receiver are independent, so full-duplex communication is possible while sharing the same clock. Both the transmitter and receiver have a double-buffered structure so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 15.8 shows the general format in clock synchronous serial communication. Don't careDon't care One unit of transfer data (character or frame) Bit 0Serial data Synchronization clock Bit 1 Bit 3 Bit 4 Bit 5 LSB MSB Bit 2 Bit 6 Bit 7 Note: * High level except in continuous transfer Figure 15.8 Data Format in Clock Synchronous Communication

Section 15 Serial Communication Interface (SCI) R01UH0198EJ0500 Rev. 5.00 Page 771 of 1560 Mar 18, 2011 SH7080 Group In clock synchronous serial communication, each data bit is output on the communication line from one falling edge of the serial clock to the next. Data is guaranteed valid at the rising edge of the serial clock. In each character, the serial data bits are transmitted in order from the LSB (first) to the MSB (last). After output of the MSB, the communication line remains in the state of the MSB. In clock synchronous mode, the SCI transmits or receives data by synchronizing with the rising edge of the serial clock. (1) Communication Format The data length is fixed at eight bits. No parity bit can be added. (2) Clock An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. For selection of the SCI clock source, see table 15.14. When the SCI operates on an internal clock, it outputs the clock signal at the SCK pin. Eight clock pulses are output per transmitted or received character. When the SCI does not perform transmission or reception, the clock signal remains in the high state. When only reception is performed, output of the synchronous clock continues until an overrun error occurs or the RE bit is cleared to 0. For the reception of n characters, select the external clock as the clock source. If the internal clock has to be used, set RE and TE to 1, then transmit n characters of dummy data at the same time as receiving the n characters of data. (3) Transmitting and Receiving Data SCI Initialization (Clock Synchronous Mode): Before transmitting, receiving, or changing the mode or communication format, the software must clear the TE and RE bits to 0 in the serial control register (SCSCR), then initialize the SCI. Clearing TE to 0 sets the TDRE flag to 1 and initializes the transmit shift register (SCTSR). Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags and receive data register (SCRDR), which retain their previous contents.

Section 15 Serial Communication Interface (SCI) R01UH0198EJ0500 Rev. 5.00 Page 773 of 1560 Mar 18, 2011 SH7080 Group Transmitting Serial Data (Clock Synchronous Mode): Figure 15.10 shows a sample flowchart for transmitting serial data. Use the following procedure for serial data transmission after enabling the SCI for transmission. Start of transmission Read TDRE flag in SCSSR TDRE = 1? Write transmit data to SCTDR and clear TDRE flag in SCSSR to 0 All data transmitted? Read TEND flag in SCSSR TEND = 1? Clear TE bit in SCSCR to 0 End of transmission No Yes No Yes No Yes [1] SCI status check and transmit data write: Read SCSSR and check that the TDRE flag is set to 1, then write transmit data to SCTDR, and clear the TDRE flag to 0. [2] Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to SCTDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DMAC or DTC is activated by a transmit data empty interrupt (TXI) request, and data is written to SCTDR. Figure 15.10 Sample Flowchart for Transmitting Serial Data

Section 15 Serial Communication Interface (SCI) R01UH0198EJ0500 Rev. 5.00 Page 775 of 1560 Mar 18, 2011 SH7080 Group Receiving Serial Data (Clock Synchronous Mode): Figure 15.12 shows a sample flowchart for receiving serial data. Use the following procedure for serial data reception after enabling the SCIF for reception. When switching from asynchronous mode to clock synchronous mode, make sure that the ORER, PER, and FER flags are all cleared to 0. If the FER or PER flag is set to 1, the RDRF flag will not be set and data reception cannot be started. Start of reception Read ORER flag in SCSSR ORER = 1? Read RDRF flag in SCSSR RDRF = 1? Read receive data in SCRDR, and clear RDRF flag in SCSSR to 0 All data received? Clear RE bit in SCSCR to 0 End of reception Yes No Yes Yes No No Error handling [1] Receive error handling: Read the ORER flag in SCSSR to identify any error, perform the appropriate error handling, then clear the ORER flag to 0. Reception cannot be resumed while the ORER flag is set to 1. [2] SCI status check and receive data read: Read SCSSR and check that RDRF = 1, then read the receive data in SCRDR, and clear the RDRF flag to 0. The transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [3] Serial reception continuation procedure: To continue serial reception, read the receive data register (SCRDR) and clear the RDRF flag to 0 before the MSB (bit 7) of the current frame is received. The RDRF flag is cleared automatically when the direct memory access controller (DMAC) or data transfer controller (DTC) is activated by a receive-data-full interrupt (RXI) request to read the SCRDR value, and this step is not needed. Figure 15.12 Sample Flowchart for Receiving Serial Data (1)

Section 15 Serial Communication Interface (SCI) Page 776 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Error handling Clear ORER flag in SCSSR to 0 End Overrun error handling ORER = 1? Yes No Figure 15.12 Sample Flowchart for Receiving Serial Data (2) In receiving, the SCI operates as follows: 1. The SCI synchronizes with serial clock input or output and initializes internally. 2. Receive data is shifted into SCRSR in orde r from the LSB to the MSB. After receiving the data, the SCI checks whether the RDRF flag is 0 and the receive data can be transferred from SCRSR to SCRDR. If this check is passed, the SCI sets the RDRF flag to 1 and stores the received data in SCRDR. If a receive error is detected, the SCI operates as shown in table 15.16. In this state, subsequent reception cannot be continued. In addition, the RDRF flag will not be set to 1 after reception; be sure to clear the RDRF flag to 0. 3. After setting RDRF to 1, if the receive-data- full interrupt enable bit (RIE) is set to 1 in SCSCR, the SCI requests a receive-data-full interrupt (RXI). If the ORER bit is set to 1 and the RIE bit in SCSCR is also set to 1, the SCI requests a receive error interrupt (ERI).

Section 15 Serial Communication Interface (SCI) Page 778 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Yes No Start of transmission and reception Error processing No Yes ORER = 1? All data received? Read TDRE flag in SCSSR No Yes TDRE = 1? Write transmit data to SCTDR and clear TDRE flag in SCSSR to 0 No Yes RDRF = 1? Read ORER flag in SCSSR Read RDRF flag in SCSSR [1] SCI status check and transmit data write: Read SCSSR and check that the TDRE flag is set to 1, then write transmit data to SCTDR and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. [2] Receive error processing: If a receive error occurs, read the ORER flag in SCSSR, and after performing the appropriate error processing, clear the ORER flag to 0. Reception cannot be resumed if the ORER flag is set to 1. [3] SCI status check and receive data read: Read SCSSR and check that the RDRF flag is set to 1, then read the receive data in SCRDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [4] Serial transmission/reception continuation procedure: To continue serial transmission/reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading SCRDR, and clearing the RDRF flag to 0. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible. Then write data to SCTDR and clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC or DMAC is activated by a transmit data empty interrupt (TXI) request and data is written to SCTDR. Also, the RDRF flag is cleared automatically when the DTC or DMAC is activated by a receive data full interrupt (RXI) request and the SCRDR value is read. Note: When switching from transmit or receive operation to simultaneous transmit and receive operations, first clear the TE bit and RE bit to 0, then set both these bits to 1 simultaneously. Clear TE and RE bits in SCSCR to 0 Read receive data in SCRDR, and clear RDRF flag in SCSSR to 0 End of transmission and reception Figure 15.14 Sample Flowchart for Transmitting/Receiving Serial Data

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15.4.4 Multiprocessor Communication Function

Use of the multiprocessor communication function enables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles: an ID transmission cycle which specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. If the multiprocessor bit is 1, the cycle is an ID transmission cycle, and if the multiprocessor bit is 0, the cycle is a data transmission cycle. Figure 15.15 shows an example of inter-processor communication using the multiprocessor format. The transmitting station first sends the ID code of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. The receiving station skips data until data with a 1 multiprocessor bit is sent. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose ID does not match continue to skip data until data with a 1 multiprocessor bit is again received. The SCI uses the MPIE bit in SCSCR to implement this function. When the MPIE bit is set to 1, transfer of receive data from SCRSR to SCRDR, error flag detection, and setting the SCSSR status flags, RDRF, FER, and OER to 1 are inhibited until data with a 1 multiprocessor bit is received. On reception of receive character with a 1 multiprocessor bit, the MPBR bit in SCSSR is set to 1 and the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCSCR is set to 1 at this time, an RXI interrupt is generated. When the multiprocessor format is selected, the parity bit setting is invalid. All other bit settings are the same as those in normal asynchronous mode. The clock used for multiprocessor communication is the same as that in normal asynchronous mode.

Section 15 Serial Communication Interface (SCI) Page 780 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Transmitting station Receiving station A (ID = 01) Receiving station B (ID = 02) Receiving station C (ID = 03) Receiving station D (ID = 04) Serial transmission line Serial data ID transmission cycle = receiving station specification Data transmission cycle = Data transmission to receiving station specified by ID (MPB = 1) (MPB = 0) H'01 H'AA [Legend] MPB: Multiprocessor bit Figure 15.15 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A)

Section 15 Serial Communication Interface (SCI) R01UH0198EJ0500 Rev. 5.00 Page 781 of 1560 Mar 18, 2011 SH7080 Group

15.4.5 Multiprocessor Serial Data Transmission

Figure 15.16 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SCSSR to 1 before transmission. Maintain the MPBT value at 1 until the ID transmission actually completes. For a data transmission cycle, clear the MPBT bit in SCSSR to 0 before transmission. All other SCI operations are the same as those in asynchronous mode. No <End> [1] Yes Initialization Start transmission Read TDRE flag in SCSSR [2] No Yes No Yes Read TEND flag in SCSSR [3] No Yes [4] Clear DR to 0 Clear TE bit in SCSCR to 0; select the TXD pin as an output port with the PFC TDRE = 1? All data transmitted? TEND = 1? Break output? Clear TDRE flag to 0 [1] SCI initialization: Set the TXD pin using the PFC. After the TE bit is set to 1, 1 is output for one frame, and transmission is enabled. However, data is not transmitted. [2] SCI status check and transmit data write: Read SCSSR and check that the TDRE flag is set to 1, then write transmit data to SCTDR. Set the MPBT bit in SCSSR to 0 or 1. Finally, clear the TDRE flag to 0. To transmit an ID after the SCI is initialized, write the ID to SCTDR. The data is immediately transferred to SCTSR and the TDRE flag is set to 1. At this point the ID has not yet been transmitted from the TXD pin, so it is necessary to maintain the MPBT value at 1. Clear the MPBT bit to 0 after the next data to be transmitted is written to SCTDR and the TDRE flag is set to 1. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to SCTDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DMAC or DTC is activated by a transmit data empty interrupt (TXI) request, and data is written to SCTDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, first clear the port data register (DR) to 0, then clear the TE bit to 0 in SCSCR and use the PFC to select the TXD pin as an output port. Write transmit data to SCTDR and set MPBT bit in SCSSR Figure 15.16 Sample Multiprocessor Serial Transmission Flowchart

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15.4.6 Multiprocessor Serial Data Reception

Figure 15.18 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCSCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to SCRDR. An RXI interrupt request is generated at this time. All other SCI operations are the same as in asynchronous mode. Figure 15.17 shows an example of SCI operation for multiprocessor format reception. MPIE RXD RXD SCRDR value

0 D0 D1 D7 1 1 0 D0 D1 D7 01

Data (ID1)Start bit MPB Stop bit Start bit Data (Data1) MPB Stop bit Data (ID2)Start bit Stop bit Start bit Data (Data2) Stop bit RXI interrupt request (multiprocessor interrupt) generated Idle state (mark state) RDRF SCRDR data read and RDRF flag cleared to 0 in RXI interrupt processing routine If not this station’s ID, MPIE bit is set to 1 again RXI interrupt request is not generated, and SCRDR retains its state ID1 (a) Data does not match station’s ID MPIE SCRDR value (multiprocessor interrupt) generated Idle state (mark state) RDRF SCRDR data read and RDRF flag cleared to 0 in RXI interrupt processing routine Matches this station’s ID, so reception continues, and data is received in RXI interrupt processing routine MPIE bit is set to 1 again ID2 (b) Data matches station’s ID Data2ID1 MPIE = 0 MPIE = 0 Figure 15.17 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)

Section 15 Serial Communication Interface (SCI) R01UH0198EJ0500 Rev. 5.00 Page 783 of 1560 Mar 18, 2011 SH7080 Group Yes <End> [1] No Initialization Start reception No Yes [4] Clear RE bit in SCSCR to 0 Error processing (Continued on next page) [5] No Yes FER = 1? or ORER = 1? RDRF = 1? All data received? Set MPIE bit in SCSCR to 1 [2] Read ORER and FER flags in SCSSR Read RDRF flag in SCSSR [3] Read receive data in SCRDR No Yes This station’s ID? Read ORER and FER flags in SCSSR Yes No Read RDRF flag in SCSSR No Yes FER = 1? or ORER = 1? Read receive data in SCRDR RDRF = 1? [1] SCI initialization: Set the RXD pin using the PFC. [2] ID reception cycle: Set the MPIE bit in SCSCR to 1. [3] SCI status check, ID reception and comparison: Read SCSSR and check that the RDRF flag is set to 1, then read the receive data in SCRDR and compare it with this station’s ID. If the data is not this station’s ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0. If the data is this station’s ID, clear the RDRF flag to 0. [4] SCI status check and data reception: Read SCSSR and check that the RDRF flag is set to 1, then read the data in SCRDR. [5] Receive error processing and break detection: If a receive error occurs, read the ORER and FER flags in SCSSR to identify the error. After performing the appropriate error processing, ensure that the ORER and FER flags are all cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RXD pin value. Figure 15.18 Sample Multiprocessor Serial Reception Flowchart (1)

Section 15 Serial Communication Interface (SCI) Page 784 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group <End> Error processing Yes No Clear ORER and FER flags in SCSSR to 0 No Yes No Yes Framing error processing Overrun error processing ORER = 1 FER = 1 Break? Clear RE bit in SCSCR to 0 [5] Figure 15.18 Sample Multiprocessor Serial Reception Flowchart (2)

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15.5 SCI Interrupt Sources and DMAC/DTC

The SCI has four interrupt sources: transmit end (TEI), receive error (ERI), receive-data-full (RXI), and transmit-data-empty (TXI) interrupt requests. Table 15.17 shows the interrupt sources. The interrupt sources are enabled or disabled by means of the TIE, RIE, and TEIE bits in SCSCR and the EIO bit in SCSPTR. A separate interrupt request is sent to the interrupt controller for each of these interrupt sources. When the TDRE flag in the serial status register (SCSSR) is set to 1, a TDR empty interrupt request is generated. This request can be used to activate the direct memory access controller (DMAC) or data transfer controller (DTC) to transfer data. The TDRE flag is automatically cleared to 0 when data is written to the transmit data register (SCTDR) through the DMAC or DTC. When the RDRF flag in SCSSR is set to 1, an RDR full interrupt request is generated. This request can be used to activate the DMAC or DTC to transfer data. The RDRF flag is automatically cleared to 0 when data is read from the receive data register (SCRDR) through the DMAC or DTC. When the ORER, FER, or PER flag in SCSSR is set to 1, an ERI interrupt request is generated. This request cannot be used to activate the DMAC or DTC. It is possible to disable generation of RXI interrupt requests and allow only ERI interrupt requests to be generated during data reception processing. To accomplish this, set the RIE bit to 1 and the EIO bit in SCSPTR to 1. Note that setting the EIO bit to 1 will prevent the DMAC or DTC from transferring received data because no ERI interrupt requests are generated. When the TEND flag in SCSSR is set to 1, a TEI interrupt request is generated. This request cannot be used to activate the DMAC or DTC. The TXI interrupt indicates that transmit data can be written, and the TEI interrupt indicates that transmission has been completed.

Section 15 Serial Communication Interface (SCI) Page 786 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 15.17 SCI Interrupt Sources Interrupt Source Description DMAC/DTC Activation ERI Interrupt caused by receive error (ORER, FER, or PER) Not possible RXI Interrupt caused by receive data full (RDRF) Possible TXI Interrupt caused by transmit data empty (TDRE) Possible TEI Interrupt caused by transmit end (TENT) Not possible

15.6 Serial Port Register (SCSPTR) and SCI Pins

The relationship between SCSPTR and the SCI pins is shown in figures 15.19 and 15.20. [Legend] SPTRW: SCSPTR write Note: * These signals control the SCK pin according to the settings of the C/A bit in SCSMR and bits CKE1 and CKE0 in SCSCR. Reset Internal data bus Clock output enable signal* Serial clock output signal* Serial clock input signal* Serial input enable signal* Bit 3 Bit 2 Reset QD R SCKIO SCK C QD R SCKDT SPTRW SPTRW C Figure 15.19 SCKIO Bit, SCKDT bit, and SCK Pin

Section 15 Serial Communication Interface (SCI) R01UH0198EJ0500 Rev. 5.00 Page 787 of 1560 Mar 18, 2011 SH7080 Group [Legend] SPTRW: SCSPTR write Reset Internal data bus Transmit enable signal Bit 1 Bit 0 Reset Serial transmit data QD R SPBIO TXD C QD R SPBDT SPTRW SPTRW C Figure 15.20 SPBIO Bit, SPBDT bit, and TXD Pin

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15.7 Usage Notes

15.7.1 SCTDR Writing and TDRE Flag

The TDRE flag in the serial status register (SCSSR) is a status flag indicating transferring of transmit data from SCTDR into SCTSR. The SCI sets the TDRE flag to 1 when it transfers data from SCTDR to SCTSR. Data can be written to SCTDR regardless of the TDRE bit status. If new data is written in SCTDR when TDRE is 0, however, the old data stored in SCTDR will be lost because the data has not yet been transferred to SCTSR. Before writing transmit data to SCTDR, be sure to check that the TDRE flag is set to 1.

15.7.2 Multiple Receive Error Occurrence

If multiple receive errors occur at the same time, the status flags in SCSSR are set as shown in table 15.18. When an overrun error occurs, data is not transferred from the receive shift register (SCRSR) to the receive data register (SCRDR) and the received data will be lost. Table 15.18 SCSSR Status Flag Values and Transfer of Received Data SCSSR Status Flags Receive Errors Generated RDRF ORER FER PER Receive Data Transfer from SCRSR to SCRDR Overrun error 1 1 0 0 Not transferred Framing error 0 0 1 0 Transferred Parity error 0 0 0 1 Transferred Overrun error + framing error 1 1 1 0 Not transferred Overrun error + parity error 1 1 0 1 Not transferred Framing error + parity error 0 0 1 1 Transferred Overrun error + framing error + parity error 1 1 1 1 Not transferred

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15.7.3 Break Detection and Processing

Break signals can be detected by reading the RXD pin directly when a framing error (FER) is detected. In the break state the input from the RXD pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set. Note that, although transfer of receive data to SCRDR is halted in the break state, the SCI receiver continues to operate.

15.7.4 Sending a Break Signal

The I/O condition and level of the TXD pin are determined by the SPB0IO and SPB0DT bits in the serial port register (SCSPTR). This feature can be used to send a break signal. Until TE bit is set to 1 (enabling transmission) after initializing, TXD pin does not work. During the period, mark status is performed by SPB0DT bit. Therefore, the SPB0IO and SPB0DT bits should be set to 1 (high level output). To send a break signal during serial transmission, clear the SPB0DT bit to 0 (low level), then clear the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, and 0 is output from the TXD pin.

15.7.5 Receive Data Sampling Timing and Receive Margin (Asynchronous Mode)

The SCI operates on a base clock with a frequency of 16 times the transfer rate in asynchronous mode. In reception, the SCI synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the eighth base clock pulse. The timing is shown in figure 15.21.

Section 15 Serial Communication Interface (SCI) Page 790 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group 0 1 2 3 4 5 6 7 8 9 10 1112 1314 15 0 1 2 3 4 5 6 7 8 9 10 1112 1314 15 0 1 2 3 4 5 D0 D1 16 clocks 8 clocks Base clock Receive data (RXD) Start bit –7.5 clocks +7.5 clocks Synchronization sampling timing Data sampling timing Figure 15.21 Receive Data Sampling Timing in Asynchronous Mode The receive margin in asynchronous mode can therefore be expressed as shown in equation 1. Equation 1: D - 0.5 N Where: M: Receive margin (%) N: Ratio of bit rate to clock (N = 16) D: Clock duty (D = 0 to 1.0) L: Frame length (L = 9 to 12) F: Absolute deviation of clock frequency From equation 1, if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation 2. Equation 2: When D = 0.5 and F = 0: = 46.875% This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.

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15.7.6 Note on Using DMAC or DTC

When the external clock source is used for the clock for synchronization, input the external clock after waiting for five or more cycles of the peripheral operating clock after SCTDR is modified through the DMAC or DTC. If a transmit clock is input within four cycles after SCTDR is modified, a malfunction may occur (figure 15.22). SCK TDRE TXD D0 D2 D6 D1 D3 D4 D5 D7 t Note: When using the external clock, t must be set to larger than 4 cycles. Figure 15.22 Example of Clock Synchronous Transfer Using DMAC or DTC When data is written to SCTDR by activating the DMAC or DTC by a TXI interrupt, the TEND flag value becomes undefined. In this case, do not use the TEND flag as the transmit end flag.

15.7.7 Note on Using External Clock in Clock Synchronous Mode

TE and RE must be set to 1 after waiting for four or more cycles of the peripheral operating clock after the SCK external clock is changed from 0 to 1. TE and RE must be set to 1 only while the SCK external clock is 1.

15.7.8 Module Standby Mode Setting

SCI operation can be disabled or enabled using the standby control register. The initial setting is for SCI operation to be halted. Register access is enabled by clearing module standby mode. For details, refer to section 26, Power-Down Modes.

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Section 16 Serial Communication Interface with FIFO (SCIF) R01UH0198EJ0500 Rev. 5.00 Page 793 of 1560 Mar 18, 2011 SH7080 Group Section 16 Serial Communication Interface with FIFO (SCIF) This LSI has a channel serial communication interface with FIFO (SCIF) that supports both asynchronous and clock synchronous serial communication. It also has 16-stage FIFO registers for both transmission and reception independently that enable this LSI to perform efficient high-speed continuous communication.

16.1 Features

• Asynchronous serial communication: ⎯ Serial data communication is performed by start-stop in character units. The SCIF can communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous communication interface adapter (ACIA), or any other communications chip that employs a standard asynchronous serial system. There are eight selectable serial data communication formats. ⎯ Data length: 7 or 8 bits ⎯ Stop bit length: 1 or 2 bits ⎯ Parity: Even, odd, or none ⎯ Receive error detection: Parity, framing, and overrun errors ⎯ Break detection: Break is detected when a framing error is followed by at least one frame at the space 0 level (low level). It is also detected by reading the RXD level directly from the serial port data register when a framing error occurs.
• Clock Synchronous mode: ⎯ Serial data communication is synchronized with a clock signal. The SCIF can communicate with other chips having a clock synchronous communication function. There is one serial data communication format. ⎯ Data length: 8 bits ⎯ Receive error detection: Overrun errors
• Full duplex communication: The transmitting and receiving sections are independent, so the SCIF can transmit and receive simultaneously. Both sections use 16-stage FIFO buffering, so high-speed continuous data transfer is possible in both the transmit and receive directions.
• On-chip baud rate generator with selectable bit rates
• Internal or external transmit/receive clock source: From either baud rate generator (internal) or SCK pin (external)

Section 16 Serial Communication Interface with FIFO (SCIF) R01UH0198EJ0500 Rev. 5.00 Page 795 of 1560 Mar 18, 2011 SH7080 Group

16.2 Input/Output Pins

The SCIF has the serial pins summarized in table 16.1. Table 16.1 Pin Configuration Channel Pin Name Abbreviation I/O Function

3 Serial clock pin SCK3 I/O Clock I/O

Receive data pin RXD3 Input Receive data input Transmit data pin TXD3 Output Transmit data output Request to send pin RTS3 Output Request to send Clear to send pin CTS3 Input Clear to send Note: In the following descriptions in this section, the channel number in the abbreviated pin names is omitted as in SCK, RXD, TXD, RTS, and CTS.

Section 16 Serial Communication Interface with FIFO (SCIF) Page 796 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

16.3 Register Descriptions

The SCIF has the following registers. These registers specify the data format and bit rate, and control the transmitter and receiver sections. Table 16.2 Register Configuration Register Name Abbr. R/W Initial Value Address Access Size Serial mode register_3 SCSMR_3 R/W H'0000 H'FFFFC180 16 Bit rate register_3 SCBRR_3 R/W H'FF H'FFFFC182 8 Serial control register_3 SCSCR_3 R/W H'0000 H'FFFFC184 16 Transmit FIFO data register_3 SCFTDR_3 W H'xx H'FFFFC186 8 Serial status register_3 SCFSR_3 R/W H'0060 H'FFFFC188 16 Receive FIFO data register_3 SCFRDR_3 R H'xx H'FFFFC18A 8 FIFO control register_3 SCFCR_3 R/W H'0000 H'FFFFC18C 16 FIFO data count register_3 SCFDR_3 R H'0000 H'FFFFC18E 16 Serial port register_3 SCSPTR_3 R/W H'00xx H'FFFFC190 16 Line status register_3 SCLSR_3 R/W H'0000 H'FFFFC192 16

16.3.1 Receive Shift Register (SCRSR)

SCRSR receives serial data. Data input at the RXD pin is loaded into SCRSR in the order received, LSB (bit 0) first, converting the data to parallel form. When one byte has been received, it is automatically transferred to SCFRDR, the receive FIFO data register. The CPU cannot read or write to SCRSR directly. Bit: Initial value: R/W: 7654321 0

Section 16 Serial Communication Interface with FIFO (SCIF) R01UH0198EJ0500 Rev. 5.00 Page 797 of 1560 Mar 18, 2011 SH7080 Group

16.3.2 Receive FIFO Data Register (SCFRDR)

SCFRDR is a 16-stage 8-bit FIFO register that stores serial receive data. The SCIF completes the reception of one byte of serial data by moving the received data from the receive shift register (SCRSR) into SCFRDR for storage. Continuous reception is possible until 16 bytes are stored. The CPU can read but not write to SCFRDR. If data is read when there is no receive data in the SCFRDR, the value is undefined. When this register is full of receive data, subsequent serial data is lost. Bit: Initial value: R/W: 7654321 0 RRRRRRRR Bit Bit Name Initial value R/W Description 7 to 0 Undefined R FIFO for receive serial data

16.3.3 Transmit Shift Register (SCTSR)

SCTSR transmits serial data. The SCIF loads transmit data from the transmit FIFO data register (SCFTDR) into SCTSR, then transmits the data serially from the TXD pin, LSB (bit 0) first. After transmitting one data byte, the SCIF automatically loads the next transmit data from SCFTDR into SCTSR and starts transmitting again. The CPU cannot read or write to SCTSR directly. Bit: Initial value: R/W: 7654321 0

Section 16 Serial Communication Interface with FIFO (SCIF) Page 798 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

16.3.4 Transmit FIFO Data Register (SCFTDR)

SCFTDR is a 16-stage 8-bit FIFO register that stores data for serial transmission. When the SCIF detects that the transmit shift register (SCTSR) is empty, it moves transmit data written in the SCFTDR into SCTSR and starts serial transmission. Continuous serial transmission is performed until there is no transmit data left in SCFTDR. SCFTDR can always be written to by the CPU. When SCFTDR is full of transmit data (16 bytes), no more data can be written. If writing of new data is attempted, the data is ignored. Bit: Initial value: R/W: 7654321 0 WWWWWWWW Bit Bit Name Initial value R/W Description 7 to 0 Undefined W FIFO for transmits serial data

16.3.5 Serial Mode Register (SCSMR)

SCSMR is a 16-bit register that specifies the SCIF serial communication format and selects the clock source for the baud rate generator. The CPU can always read and write to SCSMR. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRRRRRR R / W R / W R / W R / W R / W R R / W R / W Bit Bit Name Initial value R/W Description 15 to 8 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 16 Serial Communication Interface with FIFO (SCIF) R01UH0198EJ0500 Rev. 5.00 Page 799 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial value R/W Description Selects whether the SCIF operates in asynchronous or clock synchronous mode. 0: Asynchronous mode 1: Clock synchronous mode Selects 7-bit or 8-bit data in asynchronous mode. In the clock synchronous mode, the data length is always eight bits, regardless of the CHR setting. 0: 8-bit data 1: 7-bit data* Note: * When 7-bit data is selected, the MSB (bit 7) of the transmit FIFO data register is not transmitted. Selects whether to add a parity bit to transmit data and to check the parity of receive data, in asynchronous mode. In clock synchronous mode, a parity bit is neither added nor checked, regardless of the PE setting. 0: Parity bit not added or checked 1: Parity bit added and checked* Note: * When PE is set to 1, an even or odd parity bit is added to transmit data, depending on the parity mode (O/E) setting. Receive data parity is checked according to the even/odd (O/E) mode setting.

Section 16 Serial Communication Interface with FIFO (SCIF) Page 800 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial value R/W Description Selects even or odd parity when parity bits are added and checked. The O/E setting is used only in asynchronous mode and only when the parity enable bit (PE) is set to 1 to enable parity addition and checking. The O/E setting is ignored in clock synchronous mode, or in asynchronous mode when parity addition and checking is disabled. 0: Even parity* 1: Odd parity* Notes: 1. If even parity is selected, the parity bit is added to transmit data to make an even number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an even number of 1s in the received character and parity bit combined. 2. If odd parity is selected, the parity bit is added to transmit data to make an odd number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an odd number of 1s in the received character and parity bit combined. Selects one or two bits as the stop bit length in asynchronous mode. This setting is used only in asynchronous mode. It is ignored in clock synchronous mode because no stop bits are added. When receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of the next incoming character. 0: One stop bit When transmitting, a single 1-bit is added at the end of each transmitted character. 1: Two stop bits When transmitting, two 1 bits are added at the end of each transmitted character.

Section 16 Serial Communication Interface with FIFO (SCIF) R01UH0198EJ0500 Rev. 5.00 Page 801 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial value R/W Description 2 ⎯ 0 R Reserved This bit is always read as 0. The write value should always be 0. 1, 0 CKS[1:0] 00 R/W Clock Select 1 and 0 Select the internal clock source of the on-chip baud rate generator. Four clock sources are available. Pφ, Pφ/4, Pφ/16 and Pφ/64. For further information on the clock source, bit rate register settings, and baud rate, see section 16.3.8, Bit Rate Register (SCBRR). 00: Pφ 01: Pφ/4 10: Pφ/16 11: Pφ/64 Note: P φ: Peripheral clock

16.3.6 Serial Control Register (SCSCR)

SCSCR is a 16-bit register that operates the SCIF transmitter/receiver, enables/disables interrupt requests, and selects the transmit/receive clock source. The CPU can always read and write to SCSCR. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRRRRRR R / W R / W R / W R / W R / W R R / W R / W - - - - - - - - TIE RIE TE RE REIE - CKE[1:0]

Section 16 Serial Communication Interface with FIFO (SCIF) Page 802 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial value R/W Description 15 to 8 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. Enables or disables the transmit-FIFO-data-empty interrupt (TXIF). Serial transmit data in the transmit FIFO data register (SCFTDR) is send to the transmit shift register (SCTSR). Then, the TDFE flag in the serial status register (SCFSR) is set to1 when the number of data in SCFTDR becomes less than the number of transmission triggers. At this time, a TXIF is requested. 0: Transmit-FIFO-data-empty interrupt request (TXIF) is disabled* 1: Transmit-FIFO-data-empty interrupt request (TXIF) is enabled Note: * The TXIF interrupt request can be cleared by writing a greater number of transmit data than the specified transmission trigger number to SCFTDR and by clearing the TDFE bit to 0 after reading 1 from the TDFE bit, or can be cleared by clearing this bit to 0.

Section 16 Serial Communication Interface with FIFO (SCIF) R01UH0198EJ0500 Rev. 5.00 Page 803 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial value R/W Description Enables or disables the receive-data-full (RXIF) interrupts requested when the RDF flag or DR flag in serial status register (SCFSR) is set to1, receive-error (ERIF) interrupts requested when the ER flag in SCFSR is set to1, and break (BRIF) interrupts requested when the BRK flag in SCFSR or the ORER flag in line status register (SCLSR) is set to1. 0: Receive-data-full interrupt (RXIF), receive-error interrupt (ERIF), and break interrupt (BRIF) requests are disabled* 1: Receive-data-full interrupt (RXIF), receive-error interrupt (ERIF), and break interrupt (BRIF) requests are enabled Note: * RXIF interrupt requests can be cleared by reading the DR or RDF flag after it has been set to 1, then clearing the flag to 0, or by clearing RIE to 0. ERIF or BRIF interrupt requests can be cleared by reading the ER, BR or ORER flag after it has been set to 1, then clearing the flag to 0, or by clearing RIE and REIE to 0. Enables or disables the SCIF serial transmitter. 0: Transmitter disabled 1: Transmitter enabled* Note: * Serial transmission starts after writing of transmit data into SCFTDR. Select the transmit format in SCSMR and SCFCR and reset the transmit FIFO before setting TE to 1.

Section 16 Serial Communication Interface with FIFO (SCIF) Page 804 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group ⊕⊕Bit Bit Name Initial value R/W Description Enables or disables the SCIF serial receiver. 0:Receiver disabled* 1: Receiver enabled* Notes: 1. Clearing RE to 0 does not affect the receive flags (DR, ER, BRK, RDF, FER, PER, and ORER). These flags retain their previous values. 2. Serial reception starts when a start bit is detected in asynchronous mode, or synchronous clock input is detected in clock synchronous mode. Select the receive format in SCSMR and SCFCR and reset the receive FIFO before setting RE to 1.

3 REIE 0 R/W Receive Error Interrupt Enable

Enables or disables the receive-error (ERIF) interrupts and break (BRIF) interrupts. The setting of REIE bit is valid only when RIE bit is set to 0. 0: Receive-error interrupt (ERIF) and break interrupt (BRIF) requests are disabled* 1: Receive-error interrupt (ERIF) and break interrupt (BRIF) requests are enabled Note: * ERIF or BRIF interrupt requests can be cleared by reading the ER, BR or ORER flag after it has been set to 1, then clearing the flag to 0, or by clearing RIE and REIE to 0. Even if RIE is set to 0, when REIE is set to 1, ERIF or BRIF interrupt requests are enabled.

Section 16 Serial Communication Interface with FIFO (SCIF) R01UH0198EJ0500 Rev. 5.00 Page 805 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial value R/W Description 2 ⎯ 0 R Reserved This bit is always read as 0. The write value should always be 0. 1, 0 CKE[1:0] 00 R/W Clock Enable 1 and 0 Select the SCIF clock source and enable or disable clock output from the SCK pin. Depending on the combination of CKE1 and CKE0, the SCK pin can be used for serial clock output or serial clock input. The CKE0 setting is valid only when the SCIF is operating on the internal clock (CKE1 = 0). The CKE0 setting is ignored when an external clock source is selected (CKE1 = 1). In clock synchronous mode, select the SCIF operating mode in the serial mode register (SCSMR), then set CKE1 and CKE0.

• Asynchronous mode 00: Internal clock, SCK pin used for input pin (The input signal is ignored. The state of the SCK pin depends on both the SCKIO and SCKDT bits.) 01: Internal clock, SCK pin used for clock output (The output clock frequency is 16 times the bit rate.) 10: External clock, SCK pin used for clock input (The input clock frequency is 16 times the bit rate.) 11: Setting prohibited
• Clock synchronous mode 00: Internal clock, SCK pin used for serial clock output 01: Internal clock, SCK pin used for serial clock output 10: External clock, SCK pin used for serial clock input 11: Setting prohibited

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16.3.7 Serial Status Register (SCFSR)

SCFSR is a 16-bit register. The upper 8 bits indicate the number of receives errors in the SCFRDR data, and the lower 8 bits indicate the status flag indicating SCIF operating state. The CPU can always read and write to SCFSR, but cannot write 1 to the status flags (ER, TEND, TDFE, BRK, RDF, and DR). These flags can be cleared to 0 only if they have first been read (after being set to 1). Bits 3 (FER) and 2 (PER) are read-only bits that cannot be written. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000001100000 RRRRRRRR R / ( W ) * R/(W)* R/(W)* R/(W)* R R R/(W) * R/(W)* Note: To clear the flag, only 0 can be written after reading 1.* PER[3:0] FER[3:0] ER TEND TDFE BRK FER PER RDF DR Bit Bit Name Initial value R/W Description 15 to 12 PER[3:0] 0000 R Number of Parity Errors Indicate the number of data including a parity error in the receive data stored in the receive FIFO data register (SCFRDR). After the ER bit in SCFSR is set to 1, the value indicated by bits 15 to 12 indicates the number of parity errors in SCFRDR. When parity errors have occurred in all 16-byte receive data in SCFRDR, PER3 to PER0 show 0. 11 to 8 FER[3:0] 0000 R Number of Framing Errors Indicate the number of data including a framing error in the receive data stored in SCFRDR. After the ER bit in SCFSR is set to 1, the value indicated by bits 11 to 8 indicates the number of framing errors in SCFRDR. When framing errors have occurred in all 16-byte receive data in SCFRDR, FER3 to FER0 show 0.

Section 16 Serial Communication Interface with FIFO (SCIF) R01UH0198EJ0500 Rev. 5.00 Page 807 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial value R/W Description

7 ER 0 R/(W) * Receive Error

Indicates the occurrence of a framing error, or of a parity error when receiving data that includes parity. * 0: Receiving is in progress or has ended normally [Clearing conditions]

• ER is cleared to 0 a power-on reset
• ER is cleared to 0 when the chip is when 0 is written after 1 is read from ER 1: A framing error or parity error has occurred. [Setting conditions]
• ER is set to 1 when the stop bit is 0 after checking whether or not the last stop bit of the received data is 1 at the end of one data receive operation*
• ER is set to 1 when the total number of 1s in the receive data plus parity bit does not match the even/odd parity specified by the O/E bit in SCSMR Notes: 1. Clearing the RE bit to 0 in SCSCR does not affect the ER bit, which retains its previous value. Even if a receive error occurs, the receive data is transferred to SCFRDR and the receive operation is continued. Whether or not the data read from SCFRDR includes a receive error can be detected by the FER and PER bits in SCFSR. 2. In two stop bits mode, only the first stop bit is checked; the second stop bit is not checked.

Section 16 Serial Communication Interface with FIFO (SCIF) Page 808 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial value R/W Description

6 TEND 1 R/(W) * Transmit End

Indicates that when the last bit of a serial character was transmitted, SCFTDR did not contain valid data, so transmission has ended. 0: Transmission is in progress [Clearing condition]

• TEND is cleared to 0 when 0 is written after 1 is read from TEND after transmit data is written in SCFTDR 1: End of transmission [Setting conditions]
• TEND is set to 1 when the chip is a power-on reset
• TEND is set to 1 when TE is cleared to 0 in the serial control register (SCSCR)
• TEND is set to 1 when SCFTDR does not contain receive data when the last bit of a one-byte serial character is transmitted Note: When data is written to SCFTDR by activating the DTC through a TXIF interrupt, the TEND flag value is undefined. In this case, do not use the TEND flag as a transmit end flag.

Section 16 Serial Communication Interface with FIFO (SCIF) R01UH0198EJ0500 Rev. 5.00 Page 809 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial value R/W Description

5 TDFE 1 R/(W) * Transmit FIFO Data Empty

Indicates that data has been transferred from the transmit FIFO data register (SCFTDR) to the transmit shift register (SCTSR), the number of data in SCFTDR has become less than the transmission trigger number specified by the TTRG1 and TTRG0 bits in the FIFO control register (SCFCR), and writing of transmit data to SCFTDR is enabled. 0: The number of transmit data written to SCFTDR is greater than the specified transmission trigger number [Clearing conditions]

• TDFE is cleared to 0 when data exceeding the specified transmission trigger number is written to SCFTDR after 1 is read from the TDFE bit and then 0 is written
• TDFE is cleared to 0 when data exceeding the specified transmission trigger number is written to SCFTDR by using the DTC 1: The number of transmit data in SCFTDR is less than or equal to the specified transmission trigger number* [Setting conditions]
• TDFE is set to 1 by a power-on reset
• TDFE is set to 1 when the number of transmit data in SCFTDR becomes less than or equal to the specified transmission trigger number as a result of transmission Note: * Since SCFTDR is a 16-byte FIFO register, the maximum number of data that can be written when TDFE is 1 is "16 minus the specified transmission trigger number". If an attempt is made to write additional data, the data is ignored. The number of data in SCFTDR is indicated by the upper 8 bits of SCFDR.

Section 16 Serial Communication Interface with FIFO (SCIF) Page 810 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial value R/W Description

4 BRK 0 R/(W) * Break Detection

Indicates that a break signal has been detected in receive data. 0: No break signal received [Clearing conditions]

• BRK is cleared to 0 when the chip is a power-on reset
• BRK is cleared to 0 when software reads BRK after it has been set to 1, then writes 0 to BRK 1: Break signal received* [Setting condition]
• BRK is set to 1 when data including a framing error is received, and a framing error occurs with space 0 in the subsequent receive data Note: * When a break is detected, transfer of the receive data (H'00) to SCFRDR stops after detection. When the break ends and the receive signal becomes mark 1, the transfer of receive data resumes.

3 FER 0 R Framing Error

Indicates a framing error in the data read from the next receive FIFO data register (SCFRDR) in asynchronous mode. 0: No receive framing error occurred in the next data read from SCFRDR [Clearing conditions]

• FER is cleared to 0 when the chip undergoes a power-on reset
• FER is cleared to 0 when no framing error is present in the next data read from SCFRDR 1: A receive framing error occurred in the next data read from SCFRDR. [Setting condition]
• FER is set to 1 when a framing error is present in the next data read from SCFRDR

Section 16 Serial Communication Interface with FIFO (SCIF) R01UH0198EJ0500 Rev. 5.00 Page 811 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial value R/W Description

2 PER 0 R Parity Error

Indicates a parity error in the data read from the next receive FIFO data register (SCFRDR) in asynchronous mode. 0: No receive parity error occurred in the next data read from SCFRDR [Clearing conditions]

• PER is cleared to 0 when the chip undergoes a power-on reset
• PER is cleared to 0 when no parity error is present in the next data read from SCFRDR 1: A receive parity error occurred in the next data read from SCFRDR [Setting condition]
• PER is set to 1 when a parity error is present in the next data read from SCFRDR

Section 16 Serial Communication Interface with FIFO (SCIF) Page 812 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial value R/W Description

1 RDF 0 R/(W) * Receive FIFO Data Full

Indicates that receive data has been transferred to the receive FIFO data register (SCFRDR), and the number of data in SCFRDR has become more than the receive trigger number specified by the RTRG1 and RTRG0 bits in the FIFO control register (SCFCR). 0: The number of transmit data written to SCFRDR is less than the specified receive trigger number [Clearing conditions]

• RDF is cleared to 0 by a power-on reset
• RDF is cleared to 0 when the SCFRDR is read until the number of receive data in SCFRDR becomes less than the specified receive trigger number after 1 is read from RDF and then 0 is written
• RDF is cleared to 0 when the SCFRDR is read by using the DTC until the number of receive data in SCFRDR becomes less than the specified receive trigger number 1: The number of receive data in SCFRDR is more than the specified receive trigger number [Setting condition]
• RDF is set to 1 when a number of receive data more than the specified receive trigger number is stored in SCFRDR* Note: * SCFTDR is a 16-byte FIFO register. When RDF is 1, the specified receive trigger number of data can be read at the maximum. If an attempt is made to read after all the data in SCFRDR has been read, the data is undefined. The number of receive data in SCFRDR is indicated by the lower 8 bits of SCFDR.

Section 16 Serial Communication Interface with FIFO (SCIF) R01UH0198EJ0500 Rev. 5.00 Page 813 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial value R/W Description

0 DR 0 R/(W) * Receive Data Ready

Indicates that the number of data in the receive FIFO data register (SCFRDR) is less than the specified receive trigger number, and that the next data has not yet been received after the elapse of 15 ETU from the last stop bit in asynchronous mode. In clock synchronous mode, this bit is not set to 1. 0: Receiving is in progress, or no receive data remains in SCFRDR after receiving ended normally [Clearing conditions]

• DR is cleared to 0 when the chip undergoes a power-on reset
• DR is cleared to 0 when all receive data are read after 1 is read from DR and then 0 is written
• DR is cleared to 0 when all receive data in SCFRDR are read by the DTC 1: Next receive data has not been received [Setting condition]
• DR is set to 1 when SCFRDR contains less data than the specified receive trigger number, and the next data has not yet been received after the elapse of 15 ETU from the last stop bit.* Note: * This is equivalent to 1.5 frames with the 8-bit, 1-stop-bit format. (ETU: Elementary time unit) Note: * To clear the flag, only 0 can be written after reading 1.

Section 16 Serial Communication Interface with FIFO (SCIF) Page 814 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

16.3.8 Bit Rate Register (SCBRR)

SCBRR is an 8-bit register that, together with the baud rate generator clock source selected by the CKS1 and CKS0 bits in the serial mode register (SCSMR), determines the serial transmit/receive bit rate. The CPU can always read and write to SCBRR. SCBRR is initialized to H'FF by a power-on reset. The SCBRR setting is calculated as follows: Bit: Initial value: R/W: 7654321 0 11111111 R/W R/W R/W R/W R/W R/W R/W R/W

• Asynchronous mode: N = × 106 - 164 × 22n-1 × B Pφ
• Clock synchronous mode: N = × 106 - 18 × 22n-1 × B Pφ B: Bit rate (bits/s) N: SCBRR setting for baud rate generator (0 ≤ N ≤ 255) (The setting value should satisfy the electrical characteristics.) Pφ: Operating frequency for peripheral modules (MHz) n: Baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of n, see table 16.3.)

Section 16 Serial Communication Interface with FIFO (SCIF) R01UH0198EJ0500 Rev. 5.00 Page 815 of 1560 Mar 18, 2011 SH7080 Group Table 16.3 SCSMR Settings SCSMR Settings n Clock Source CKS1 CKS0 Note: The bit rate error in asynchronous is given by the following formula: Pφ × 106

Section 16 Serial Communication Interface with FIFO (SCIF) Page 816 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Tables 16.4 to 16.6 list examples of SCBRR settings in asynchronous mode, and tables 16.7 to 16.9 list examples of SCBRR settings in clock synchronous mode. Table 16.4 Bit Rates and SCBRR Settings in Asynchronous Mode Pφ (MHz) 10 12 14 16 18 20 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) n N Error (%) n N Error (%)

Section 16 Serial Communication Interface with FIFO (SCIF) R01UH0198EJ0500 Rev. 5.00 Page 817 of 1560 Mar 18, 2011 SH7080 Group Table 16.5 Bit Rates and SCBRR Settings in Asynchronous Mode Pφ (MHz) 22 24 26 28 30 32 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) n N Error (%) n N Error (%)

Section 16 Serial Communication Interface with FIFO (SCIF) Page 818 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 16.6 Bit Rates and SCBRR Settings in Asynchronous Mode Pφ (MHz) 34 36 38 40 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 3 150 -0.05 3 159 -0.12 3 168 -0.19 3 177 -0.25 150 3 110 -0.29 3 116 0.16 3 123 -0.24 3 129 0.16 300 2 220 0.16 2 233 0.16 2 246 0.16 3 64 0.16 600 2 110 -0.29 2 116 0.16 2 123 -0.24 2 129 0.16 1200 1 220 0.16 1 233 0.16 1 246 0.16 2 64 0.16 2400 1 110 -0.29 1 116 0.16 1 123 -0.24 1 129 0.16 4800 0 220 0.16 0 233 0.16 0 246 0.16 1 64 0.16 9600 0 110 -0.29 0 116 0.16 0 123 -0.24 0 129 0.16 14400 0 73 -0.29 0 77 0.16 0 81 0.57 0 86 -0.22 19200 0 54 0.62 0 58 -0.69 0 61 -0.24 0 64 0.16 28800 0 36 -0.29 0 38 0.16 0 40 0.57 0 42 0.94 31250 0 33 0.00 0 35 0.00 0 37 0.00 0 39 0.00 38400 0 27 -1.18 0 28 1.02 0 30 -0.24 0 32 -1.36

Section 16 Serial Communication Interface with FIFO (SCIF) R01UH0198EJ0500 Rev. 5.00 Page 819 of 1560 Mar 18, 2011 SH7080 Group Table 16.7 Bit Rates and SCBRR Settings in Clock Synchronous Mode P φ (MHz) 10 12 14 16 18 20 Bit Rate (bits/s) n N n N n N n N n N n N 250 3 155 3 187 3 218 3 249 500 3 77 3 93 3 108 3 124 3 140 3 155 1000 2 155 2 187 2 218 2 249 3 69 3 77 2500 1 249 2 74 2 87 2 99 2 112 2 124 5000 1 124 1 149 1 174 1 199 1 224 1 249 10000 0 249 1 74 1 87 1 99 1 112 1 124 25000 0 99 0 119 0 139 0 159 0 179 0 199 50000 0 49 0 59 0 69 0 79 0 89 0 99 100000 0 24 0 29 0 34 0 39 0 44 0 49 250000 0 9 0 11 0 13 0 15 0 17 0 19 500000 0 4 0 5 0 6 0 7 0 8 0 9 1000000 ⎯ ⎯ 0 2 ⎯ ⎯ 0 3 ⎯ ⎯ 0 4

Section 16 Serial Communication Interface with FIFO (SCIF) Page 820 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 16.8 Bit Rates and SCBRR Settings in Clock Synchronous Mode P φ (MHz) 22 24 26 28 30 32 Bit Rate (bits/s) n N n N n N n N n N n N 250 500 3 171 3 187 3 202 3 218 3 233 3 249 1000 3 85 3 93 3 101 3 108 3 116 3 124 2500 2 137 2 149 2 162 2 174 2 187 2 199 5000 2 68 2 74 2 80 2 87 2 93 2 99 10000 1 137 1 149 1 162 1 174 1 187 1 199 25000 0 219 0 239 1 64 1 69 1 74 1 79 50000 0 109 0 119 0 129 0 139 0 149 0 159 100000 0 54 0 59 0 64 0 69 0 74 0 79 250000 0 21 0 23 0 25 0 27 0 29 0 31 500000 0 10 0 11 0 12 0 13 0 14 0 15 1000000 ⎯ ⎯ 0 5 ⎯ ⎯ 0 6 ⎯ ⎯ 0 7

Section 16 Serial Communication Interface with FIFO (SCIF) R01UH0198EJ0500 Rev. 5.00 Page 821 of 1560 Mar 18, 2011 SH7080 Group Table 16.9 Bit Rates and SCBRR Settings in Clock Synchronous Mode P φ (MHz) 34 36 38 40 Bit Rate (bits/s) n N n N n N n N 250 500 1000 3 132 3 140 3 147 3 155 2500 2 212 2 224 2 237 2 249 5000 2 105 2 112 2 118 2 124 10000 1 212 1 224 1 237 1 249 25000 1 84 1 89 1 94 1 99 50000 0 169 0 179 0 189 0 199 100000 0 84 0 89 0 94 0 99 250000 0 33 0 35 0 37 0 39 500000 0 16 0 17 0 18 0 19 1000000 ⎯ ⎯ 0 8 ⎯ ⎯ 0 9 [Legend] Blank: No setting possible ⎯: Setting possible, but error occurs *: Continuous transmission/reception is disabled. Note: Settings with an error of 1% or less are recommended. Table 16.10 indicates the maximum bit rates in asynchronous mode when the baud rate generator is used. Tables 16.11 and 16.12 list the maximum rates for external clock input.

Section 16 Serial Communication Interface with FIFO (SCIF) Page 822 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 16.10 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode) Settings Pφ (MHz) Maximum Bit Rate (bits/s) n N 10 312500 0 0 12 375000 0 0 14 437500 0 0 16 500000 0 0 18 562500 0 0 20 625000 0 0 22 687500 0 0 24 750000 0 0 26 812500 0 0 28 875000 0 0 30 937500 0 0 32 1000000 0 0 34 1062500 0 0 36 1125000 0 0 38 1187500 0 0 40 1250000 0 0

Section 16 Serial Communication Interface with FIFO (SCIF) R01UH0198EJ0500 Rev. 5.00 Page 823 of 1560 Mar 18, 2011 SH7080 Group Table 16.11 Maximum Bit Rates with External Clock Input (Asynchronous Mode) Pφ (MHz) External Input Clock (M Hz) Maximum Bit Rate (bits/s) 10 2.5000 156250 12 3.0000 187500 14 3.5000 218750 16 4.0000 250000 18 4.5000 281250 20 5.0000 312500 22 5.5000 343750 24 6.0000 375000 26 6.5000 406250 28 7.0000 437500 30 7.5000 468750 32 8.0000 500000 34 8.5000 531250 36 9.0000 562500 38 9.5000 593750 40 10.0000 625000

Section 16 Serial Communication Interface with FIFO (SCIF) Page 824 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 16.12 Maximum Bit Rates with External Clock Input (Clock Synchronous Mode) Pφ (MHz) External Input Clock (M Hz) Maximum Bit Rate (bits/s) 10 1.6667 1666666.7 12 2.0000 2000000.0 14 2.3333 2333333.3 16 2.6667 2666666.7 18 3.0000 3000000.0 20 3.3333 3333333.3 22 3.6667 3666666.7 24 4.0000 4000000.0 26 4.3333 4333333.3 28 4.6667 4666666.7 30 5.0000 5000000.0 32 5.3333 5333333.3 34 5.6667 5666666.7 36 6.0000 6000000.0 38 6.3333 6333333.3 40 6.6667 6666666.7

Section 16 Serial Communication Interface with FIFO (SCIF) R01UH0198EJ0500 Rev. 5.00 Page 825 of 1560 Mar 18, 2011 SH7080 Group

16.3.9 FIFO Control Register (SCFCR)

SCFCR is a 16-bit register that resets the number of data in the transmit and receive FIFO registers, sets the trigger data number, and contains an enable bit for loop-back testing. SCFCR can always be read and written to by the CPU. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRRR R / W R / W R / W R / W R / W R / W R / W R / W R / W R / W R / W - - - - - RSTRG[2:0] RTRG[1:0] TTRG[1:0] MCE TFRST RFRST LOOP Bit Bit Name Initial value R/W Description 15 to 11 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. 10 to 8 RSTRG[2:0] 000 R/W RTS Output Active Trigger When the number of receive data in the receive FIFO register (SCFRDR) becomes more than the number shown below, the RTS signal is set to high. These bits are valid only when modem control signals are enabled in asynchronous mode. 000: 15 001: 1 010: 4 011: 6 100: 8 101: 10 110: 12 111: 14

Section 16 Serial Communication Interface with FIFO (SCIF) Page 826 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial value R/W Description 7, 6 RTRG[1:0] 00 R/W Receive FIFO Data Trigger Set the specified receive trigger number. The receive data full (RDF) flag in the serial status register (SCFSR) is set when the number of receive data stored in the receive FIFO register (SCFRDR) exceeds the specified trigger number shown below.

• Asynchronous mode 00: 1 01: 4 10: 8 11: 14
• Clock synchronous mode 00: 1 01: 2 10: 8 11: 14 5, 4 TTRG[1:0] 00 R/W Transmit FIFO Data Trigger 1 and 0 Set the specified transmit trigger number. The transmit FIFO data register empty (TDFE) flag in the serial status register (SCFSR) is set when the number of transmit data in the transmit FIFO data register (SCFTDR) becomes less than the specified trigger number shown below. 00: 8 (8)* 01: 4 (12)* 10: 2 (14)* 11: 0 (16)* Note: * Values in parentheses mean the number of remaining bytes in SCFTDR when the TDFE flag is set to 1.

Section 16 Serial Communication Interface with FIFO (SCIF) R01UH0198EJ0500 Rev. 5.00 Page 827 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial value R/W Description

3 MCE 0 R/W Modem Control Enable

Enables modem control signals CTS and RTS. In clock synchronous mode, clear this bit to 0. 0: Modem signal disabled* 1: Modem signal enabled Note: * Regardless of the input value, the CTS level has no effect on transmit operation and the RTS level has no effect on receive operation.

2 TFRST 0 R/W Transmit FIFO Data Register Reset

Disables the transmit data in the transmit FIFO data register and resets the data to the empty state. 0: Reset operation disabled* 1: Reset operation enabled Note: * Reset operation is executed by a power-on reset.

1 RFRST 0 R/W Receive FIFO Data Register Reset

Disables the receive data in the receive FIFO data register and resets the data to the empty state. 0: Reset operation disabled* 1: Reset operation enabled Note: * Reset operation is executed by a power-on reset.

0 LOOP 0 R/W Loop-Back Test

Internally connects the transmit output pin (TXD) and receive input pin (RXD) and internally connects the RTS pin and CTS pin and enables loop-back testing. 0: Loop back test disabled 1: Loop back test enabled

Section 16 Serial Communication Interface with FIFO (SCIF) Page 828 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

16.3.10 FIFO Data Count Register (SCFDR)

SCFDR is a 16-bit register which indicates the number of data stored in the transmit FIFO data register (SCFTDR) and the receive FIFO data register (SCFRDR). It indicates the number of transmit data in SCFTDR with the upper eight bits, and the number of receive data in SCFRDR with the lower eight bits. SCFDR can always be read from by the CPU. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRRRRRRRRRRRRRR Bit Bit Name Initial value R/W Description 15 to 13 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. 12 to 8 T[4:0] 00000 R Indicate the number of non-transmitted data stored in SCFTDR. H'00 means no transmit data, and H'10 means that SCFTDR is full of transmit data. 7 to 5 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 to 0 R[4:0] 00000 R Indicate the number of receive data stored in SCFRDR. H'00 means no receive data, and H'10 means that SCFRDR full of receive data.

Section 16 Serial Communication Interface with FIFO (SCIF) R01UH0198EJ0500 Rev. 5.00 Page 829 of 1560 Mar 18, 2011 SH7080 Group

16.3.11 Serial Port Register (SCSPTR)

SCSPTR is a 16-bit register that controls input/output and data for the pins multiplexed to the SCIF function. Bits 7 and 6 can control the RTS pin, bits 5 and 4 can control the CTS pin, and bits 3 and 2 can control the SCK pin. Bits 1 and 0 can be used to output data to the TXD pin, so they control break of serial transfer. In addition to descriptions of individual bits shown below, see section 16.6, Serial Port Register (SCSPTR) and SCIF Pins. SCSPTR can always be read from or written to by the CPU. Note that the respective port registers should be used to read the values on the SCIF pins. For details, refer to section 22, I/O Ports. Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 00000000 0-0-0-0- RRRRRRRR R / W R / W R / W R / W R / W R / W R / W R / W - - - - - - - - RTSIO RTSDT CTSIO CTSDT SCKIO SCKDT SPBIO SPBDT Bit Bit Name Initial value R/W Description 15 to 8 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0.

7 RTSIO 0 R/W RTS Port Input/Output Control

Controls the RTS pin in combination with the RTSDT bit in this register and the MCE bit in SCFCR.

6 RTSDT Undefined R/W RTS Port Data

Controls the RTS pin in combination with the RTSIO bit in this register and the MCE bit in SCFCR. Select the RTS pin function in the PFC (pin function controller) beforehand. MCE RTSIO RTSDT: RTS pin state 0 0 ×: Setting prohibited (initial state) 0 1 0: Low level output 0 1 1: High level output 1 × ×: Sequence output according to modem control logic Note: ×: Don't care

Section 16 Serial Communication Interface with FIFO (SCIF) Page 830 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial value R/W Description

5 CTSIO 0 R/W CTS Port Input/Output Control

Controls the CTS pin in combination with the CTSDT bit in this register and the MCE bit in SCFCR.

4 CTSDT Undefined R/W CTS Port Data

Controls the CTS pin in combination with the CTSIO bit in this register and the MCE bit in SCFCR. Select the CTS pin function in the PFC (pin function controller) beforehand. MCE CTSIO CTSDT: CTS pin state 0 0 ×: Setting prohibited (initial state) 0 1 0: Low level output 0 1 1: High level output 1 × ×: Input to modem control logic Note: ×: Don't care

3 SCKIO 0 R/W SCK Port Input/Output Control

Controls the SCK pin in combination with the SCKDT bit in this register, the C/A bit in SCSMR, and bits CKE1 and CKE0 in SCSCR.

Section 16 Serial Communication Interface with FIFO (SCIF) R01UH0198EJ0500 Rev. 5.00 Page 831 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial value R/W Description

2 SCKDT Undefined R/W SCK Port Data

Controls the SCK pin in combination with the SCKIO bit in this register, the C/A bit in SCSMR, and bits CKE1 and CKE0 in SCSCR. Select the SCK pin function in the PFC (pin function controller) beforehand. C/A CKE1 CKE0 SCKIO SCKDT: SCK pin state 0 0 0 0 ×: Setting prohibited (initial state) 0 0 0 1 0: Low level output 0 0 0 1 1: High level output 0 0 1 × ×: Internal clock output according to serial core logic 0 1 0 × ×: External clock input to serial core logic 0 1 1 × ×: Setting prohibited 1 0 0 × ×: Internal clock output according to serial core logic 1 0 1 × ×: Internal clock output according to serial core logic 1 1 0 × ×: External clock input to serial core logic 1 1 1 × ×: Setting prohibited Note: ×: Don't care

1 SPBIO 0 R/W Serial Port Break Output Control

Controls the TXD pin in combination with the SPBDT bit in this register and the TE bit in SCSCR.

0 SPBDT Undefined R/W Serial Port Break Data

Controls the TXD pin in combination with the SPBIO bit in this register and the TE bit in SCSCR. Select the TXD pin function in the PFC (pin function controller) beforehand. TE SPBIO SPBDT: TXD pin state 0 0 ×: Setting prohibited (initial state) 0 1 0: Low level output 0 1 1: High level output 0 × ×: Transmit data output according to serial core logic Note: ×: Don't care

Section 16 Serial Communication Interface with FIFO (SCIF) Page 832 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group

16.3.12 Line Status Register (SCLSR)

SCLSR is a 16-bit readable/writable register which can always be read from and written to by the CPU. However, a 1 cannot be written to the ORER flag. This flag can be cleared to 0 only if it has first been read (after being set to 1). Bit: Initial value: R/W: 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 0000000000000000 RRRRRRRRRRRRRRR R / ( W ) * Note: To clear the flag, only 0 can be written after reading 1.* Bit Bit Name Initial value R/W Description 15 to 1 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0.

0 ORER 0 R/(W) * Overrun Error

Indicates the occurrence of an overrun error. 0: Receiving is in progress or has ended normally * [Clearing conditions]

• ORER is cleared to 0 when the chip is a power-on reset
• ORER is cleared to 0 when 0 is written after 1 is read from ORER. 1: An overrun error has occurred * [Setting condition]
• ORER is set to 1 when the next serial receiving is finished while receive FIFO data are full. Notes: 1. Clearing the RE bit to 0 in SCSCR does not affect the ORER bit, which retains its previous value. 2. The receive FIFO data register (SCFRDR) hold the data before an overrun error is occurred, and the next receive data is extinguished. When ORER is set to 1, SCIF can not continue the next serial receiving.

Section 16 Serial Communication Interface with FIFO (SCIF) R01UH0198EJ0500 Rev. 5.00 Page 833 of 1560 Mar 18, 2011 SH7080 Group

16.4 Operation

16.4.1 Overview

For serial communication, the SCIF has an asynchronous mode in which characters are synchronized individually, and a clock synchronous mode in which communication is synchronized with clock pulses. The SCIF has a 16-byte FIFO buffer for both transmit and receive operations, reducing the overhead of the CPU, and enabling continuous high-speed communication. Moreover, it has RTS and CTS signals as modem control signals. The transmission format is selected in the serial mode register (SCSMR) as shown in table 16.13. The SCIF clock source is selected by the combination of the CKE1 and CKE0 bits in the serial control register (SCSCR) as shown in table 16.14. (1) Asynchronous Mode

• Data length is selectable: 7 or 8 bits.
• Parity bit is selectable. So is the stop bit length (1 or 2 bits). The combination of the preceding selections constitutes the communication format and character length.
• In receiving, it is possible to detect framing errors, parity errors, receive FIFO data full, overrun errors, receive data ready, and breaks.
• The number of stored data bytes is indicated for both the transmit and receive FIFO registers.
• An internal or external clock can be selected as the SCIF clock source. ⎯ When an internal clock is selected, the SCIF operates using the on-chip baud rate generator. ⎯ When an external clock is selected, the external clock input must have a frequency 16 times the bit rate. (The on-chip baud rate generator is not used.) (2) Clock Synchronous Mode
• The transmission/reception format has a fixed 8-bit data length.
• In receiving, it is possible to detect overrun errors (ORER).
• An internal or external clock can be selected as the SCIF clock source. ⎯ When an internal clock is selected, the SCIF operates using the on-chip baud rate generator, and outputs a serial clock signal to external devices. ⎯ When an external clock is selected, the SCIF operates on the input serial clock. The on- chip baud rate generator is not used.

Section 16 Serial Communication Interface with FIFO (SCIF) Page 834 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Table 16.13 SCSMR Settings and SCIF Communication Formats SCSMR Settings SCIF Communication Format Bit 7 C/A Bit 6 CHR Bit 5 PE Bit 3 STOP Mode Data Length Parity Bit Stop Bit Length 0 0 0 0 8-bit Not set 1 bit 1 2 bits 1 0 Set 1 bit 1 2 bits 1 0 0 7-bit Not set 1 bit 1 2 bits 1 0 Set 1 bit Asynchronous 2 bits 1 x x x Clock synchronous 8-bit Not set None [Legend] x: Don't care Table 16.14 SCSMR and SCSCR Settings and SCIF Clock Source Selection SCSMR SCSCR Settings SCIF Transmit/Receive Clock Bit 7 C/A Bit 1 CKE1 Bit 0 CKE0 Mode Clock Source SCK Pin Function 0 0 0 Asynchronous Internal SCIF does not use the SCK pin. The state of the SCK pin depends on both the SCKIO and SCKDT bits. is output. 1 0 External Input a clock with frequency 16 times the bit rate. 1 ⎯ Setting prohibited. 1 0 x Internal Serial clock is output. 1 0 Clock synchronous External Input the serial clock. 1 ⎯ Setting prohibited. [Legend] x: Don't care

Section 16 Serial Communication Interface with FIFO (SCIF) R01UH0198EJ0500 Rev. 5.00 Page 835 of 1560 Mar 18, 2011 SH7080 Group

16.4.2 Operation in Asynchronous Mode

In asynchronous mode, each transmitted or received character begins with a start bit and ends with a stop bit. Serial communication is synchronized one character at a time. The transmitting and receiving sections of the SCIF are independent, so full duplex communication is possible. The transmitter and receiver are 16-byte FIFO buffered, so data can be written and read while transmitting and receiving are in progress, enabling continuous transmitting and receiving. Figure 16.2 shows the general format of asynchronous serial communication. In asynchronous serial communication, the communication line is normally held in the mark (high) state. The SCIF monitors the line and starts serial communication when the line goes to the space (low) state, indicating a start bit. One serial character consists of a start bit (low), data (LSB first), parity bit (high or low), and stop bit (high), in that order. When receiving in asynchronous mode, the SCIF synchronizes at the falling edge of the start bit. The SCIF samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate. Receive data is latched at the center of each bit. LSB Start bit MSB Idle state (mark state) Stop bit Transmit/receive data D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 1 Serial data Parity bit 1 bit 1 or 2 bits 7 or 8 bits 1 bit or none One unit of transfer data (character or frame) Figure 16.2 Example of Data Format in Asynchronous Communication (8-Bit Data with Parity and Two Stop Bits)

Section 16 Serial Communication Interface with FIFO (SCIF) Page 836 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group (1) Transmit/Receive Formats Table 16.15 lists the eight communication formats that can be selected in asynchronous mode. The format is selected by settings in the serial mode register (SCSMR). Table 16.15 Serial Communication Formats (Asynchronous Mode) SCSMR Bits Serial Transmit/Receive Format and Frame Length CHR PE STOP 1 2 3 4 5 6 7 8 9 10 11 12 0 0 0 START 8-bit data STOP 0 0 1 START 8-bit data STOP STOP 0 1 0 START 8-bit data P STOP 0 1 1 START 8-bit data P STOP STOP 1 0 0 START 7-bit data STOP 1 0 1 START 7-bit data STOP STOP 1 1 0 START 7-bit data P STOP 1 1 1 START 7-bit data P STOP STOP [Legend] START: Start bit STOP: Stop bit P: Parity bit (2) Clock An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCIF transmit/receive clock. The clock source is selected by the C/A bit in the serial mode register (SCSMR) and bits CKE1 and CKE0 in the serial control register (SCSCR). For selection of the SCIF clock source, see table 16.14. When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the desired bit rate. When the SCIF operates on an internal clock, it can output a clock signal at the SCK pin. The frequency of this output clock is equal to 16 times the desired bit rate.

Section 16 Serial Communication Interface with FIFO (SCIF) R01UH0198EJ0500 Rev. 5.00 Page 837 of 1560 Mar 18, 2011 SH7080 Group (3) Transmitting and Receiving Data SCIF Initialization (Asynchronous Mode): Before transmitting or receiving, clear the TE and RE bits to 0 in the serial control register (SCSCR), then initialize the SCIF as follows. When changing the operation mode or the communication format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing TE to 0 initializes the transmit shift register (SCTSR). Clearing TE and RE to 0, however, does not initialize the serial status register (SCFSR), transmit FIFO data register (SCFTDR), or receive FIFO data register (SCFRDR), which retain their previous contents. Clear TE to 0 after all transmit data has been transmitted and the TEND flag in the SCFSR is set. The TE bit can be cleared to 0 during transmission, but the transmit data goes to the Mark state after the bit is cleared to 0. Set the TFRST bit in SCFCR to 1 and reset SCFTDR before TE is set again to start transmission. When an external clock is used, the clock should not be stopped during initialization or subsequent operation. SCIF operation becomes unreliable if the clock is stopped.

Section 16 Serial Communication Interface with FIFO (SCIF) Page 840 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group In serial transmission, the SCIF operates as described below. 1. When data is written into the transmit FIFO data register (SCFTDR), the SCIF transfers the data from SCFTDR to the transmit shift register (SCTSR) and starts transmitting. Confirm that the TDFE flag in the serial status register (SCFSR) is set to 1 before writing transmit data to SCFTDR. The number of data bytes that can be written is (16 – transmit trigger setting). 2. When data is transferred from SCFTDR to SCTSR and transmission is started, consecutive transmit operations are performed until there is no transmit data left in SCFTDR. When the number of transmit data bytes in SCFTDR falls below the transmit trigger number set in the FIFO control register (SCFCR), the TDFE flag is set. If the TIE bit in the serial control register (SCSR) is set to 1 at this time, a transmit-FIFO-data-empty interrupt (TXIF) request is generated. The serial transmit data is sent from the TXD pin in the following order. A. Start bit: One-bit 0 is output. B. Transmit data: 8-bit or 7-bit data is output in LSB-first order. C. Parity bit: One parity bit (even or odd parity) is output. (A format in which a parity bit is not output can also be selected.) D. Stop bit(s): One or two 1 bits (stop bits) are output. E. Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. The SCIF checks the SCFTDR transmit data at the timing for sending the stop bit. If data is present, the data is transferred from SCFTDR to SCTSR, the stop bit is sent, and then serial transmission of the next frame is started. If there is no transmit data, the TEND flag in SCFSR is set to 1, the stop bit is sent, and then the line goes to the mark state in which 1 is output continuously.

Section 16 Serial Communication Interface with FIFO (SCIF) R01UH0198EJ0500 Rev. 5.00 Page 841 of 1560 Mar 18, 2011 SH7080 Group Figure 16.5 shows an example of the operation for transmission. (mark state) Data Parity bit Stop bit TXIF interrupt request Data written to SCFTDR and TDFE flag read as 1 then cleared to 0 by TXIF interrupt handler One frame TXIF interrupt request Figure 16.5 Example of Transmit Operation (8-Bit Data, Parity, One Stop Bit) 4. When modem control is enabled, transmission can be stopped and restarted in accordance with the CTS input value. When CTS is set to 1, if transmission is in progress, the line goes to the mark state after transmission of one frame. When CTS is set to 0, the next transmit data is output starting from the start bit. Figure 16.6 shows an example of the operation when modem control is used. Serial data TXD 0 D0 D1 D7 0/1 0 D0 D1 D7 0/1 CTS Drive high before stop bit Start bit Parity bit Stop bit Start bit Figure 16.6 Example of Operation Using Modem Control (CTS)

Section 16 Serial Communication Interface with FIFO (SCIF) Page 842 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Receiving Serial Data (Asynchronous Mode): Figures 16.7 and 16.8 show a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCIF for reception. Start of reception Read ER, DR, BRK flags in SCFSR and ORER flag in SCLSR ER, DR, BRK or ORER = 1? Read RDF flag in SCFSR RDF = 1? Read receive data in SCFRDR, and clear RDF flag in SCFSR to 0 All data received? Clear RE bit in SCSCR to 0 End of reception Yes No Yes Yes No No Error handling [1] Receive error handling and break detection: Read the DR, ER, and BRK flags in SCFSR, and the ORER flag in SCLSR, to identify any error, perform the appropriate error handling, then clear the DR, ER, BRK, and ORER flags to 0. In the case of a framing error, a break can also be detected by reading the value of the RXD pin. [2] SCIF status check and receive data read: Read SCFSR and check that RDF = 1, then read the receive data in SCFRDR, read 1 from the RDF flag, and then clear the RDF flag to 0. The transition of the RDF flag from 0 to 1 can also be identified by an RXIF interrupt. [3] Serial reception continuation procedure: To continue serial reception, read at least the receive trigger number of receive data bytes from SCFRDR, read 1 from the RDF flag, then clear the RDF flag to 0. The number of receive data bytes in SCFRDR can be ascertained by reading from the lower 8 bits of SCFDR. [1] [2] [3] Figure 16.7 Sample Flowchart for Receiving Serial Data

Section 16 Serial Communication Interface with FIFO (SCIF) R01UH0198EJ0500 Rev. 5.00 Page 843 of 1560 Mar 18, 2011 SH7080 Group Error handling Receive error handling ER = 1? BRK = 1? Break handling DR = 1? Read receive data in SCFRDR Clear DR, ER, BRK flags in SCFSR, and ORER flag in SCLSR, to 0 End Yes Yes Yes No Overrun error handling ORER = 1? Yes No No No [1] Whether a framing error or parity error has occurred in the receive data that is to be read from SCFRDR can be ascertained from the FER and PER bits in SCFSR. [2] When a break signal is received, receive data is not transferred to SCFRDR while the BRK flag is set. However, note that the last data in SCFRDR is H'00, and the break data in which a framing error occurred is stored. Figure 16.8 Sample Flowchart for Receiving Serial Data (cont)

Section 16 Serial Communication Interface with FIFO (SCIF) Page 844 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group In serial reception, the SCIF operates as described below. 1. The SCIF monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR in LSB-to-MSB order. 3. The parity bit and stop bit are received. After receiving these bits, the SCIF carries out the following checks. A. Stop bit check: The SCIF check s whether the stop bit is 1. If there are two stop bits, only the first is checked. B. The SCIF checks whether rece ive data can be transferred from the receive shift register (SCRSR) to SCFRDR. C. Overrun check: The SCIF checks that the ORER flag is 0, indicating that the overrun error has not occurred. D. Break check: The SCIF checks that the BRK flag is 0, indicating that the break state is not set. If all the above checks are passed, the receive data is stored in SCFRDR. Note: When a parity error or a framing error occurs, reception is not suspended. 4. If the RIE bit in SCSCR is se t to 1 when the RDF or DR flag changes to 1, a receive-FIFO- data-full interrupt (RXIF) request is generated. If the RIE bit or the REIE bit in SCSCR is set to 1 when the ER flag changes to 1, a receive-error interrupt (ERIF) request is generated. If the RIE bit or the REIE bit in SCSCR is set to 1 when the BRK or ORER flag changes to 1, a break reception interrupt (BRIF) request is generated. Figure 16.9 shows an example of the operation for reception.

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0 D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 Idle state

(mark state) RDF FER Serial data Start bit Data Parity bit Stop bit Start bit Data Parity bit Stop bit RXIF interrupt request One frame Data read and RDF flag read as 1 then cleared to 0 by RXIF interrupt handler ERIF interrupt request generated by receive error Figure 16.9 Example of SCIF Receive Operation (8-Bit Data, Parity, One Stop Bit) 5. When modem control is enabled, the RTS signal is output depending on the empty status of SCFRDR. When RTS is 0, reception is possible. When RTS is 1, this indicates that the SCFRDR is full and no extra data can be received. Figure 16.10 shows an example of the operation when modem control is used. D0 D1 D2 D7 0/1 D0 D1 D7 0/1100 RTS Serial data RXD Start bit Parity bit Stop bit Start bit Figure 16.10 Example of Operation Using Modem Control (RTS)

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16.4.3 Clock Synchronous Mode

In clock synchronous mode, the SCIF transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCIF transmitter and receiver are independent, so full-duplex communication is possible while sharing the same clock. The transmitter and receiver are also 16-byte FIFO buffered, so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress. Figure 16.11 shows the general format in clock synchronous serial communication. Don't careDon't care One unit of transfer data (character or frame) Bit 0Serial data Synchronization clock Bit 1 Bit 3 Bit 4 Bit 5 LSB MSB Bit 2 Bit 6 Bit 7 Note: * High except in continuous transfer Figure 16.11 Data Format in Clock Synchronous Communication

Section 16 Serial Communication Interface with FIFO (SCIF) R01UH0198EJ0500 Rev. 5.00 Page 847 of 1560 Mar 18, 2011 SH7080 Group In clock synchronous serial communication, each data bit is output on the communication line from one falling edge of the serial clock to the next. Data is guaranteed valid at the rising edge of the serial clock. In each character, the serial data bits are transmitted in order from the LSB (first) to the MSB (last). After output of the MSB, the communication line remains in the state of the MSB. In clock synchronous mode, the SCIF receives data in synchronization with the rising edge of the serial clock. (1) Communication Format The data length is fixed at eight bits. No parity bit can be added. (2) Clock An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCIF transmit/receive clock. When the SCIF operates on an internal clock, it outputs the clock signal at the SCK pin. Eight clock pulses are output per transmitted or received character. When the SCIF is not transmitting or receiving, the clock signal remains in the high state. When only receiving, the clock signal outputs while the RE bit of SCSCR is 1 and the number of data in receive FIFO is more than the receive FIFO data trigger number. In this case, 8 × (16 + 1) = 136 pulses of synchronous clock are output. To perform reception of n characters of data, select an external clock as the clock source. If an internal clock should be used, set RE = 1 and TE = 1 and receive n characters of data simultaneously with the transmission of n characters of dummy data. (3) Transmitting and Receiving Data SCIF Initialization (Clock Synchronous Mode): Before transmitting, receiving, or changing the mode or communication format, the software must clear the TE and RE bits to 0 in the serial control register (SCSCR), then initialize the SCIF. Clearing TE to 0 initializes the transmit shift register (SCTSR). Clearing RE to 0, however, does not initialize the RDF, PER, FER, and ORER flags and receive data register (SCRDR), which retain their previous contents.

Section 16 Serial Communication Interface with FIFO (SCIF) R01UH0198EJ0500 Rev. 5.00 Page 849 of 1560 Mar 18, 2011 SH7080 Group Transmitting Serial Data (Clock Synchronous Mode): Figure 16.13 shows a sample flowchart for transmitting serial data. Start of transmission Read TDFE flag in SCFSR TDFE = 1? Write transmit data to SCFTDR and clear TDFE flag and TEND flag in SCFSR to 0 after reading them as 1 All data transmitted? Read TEND flag in SCFSR TEND = 1? Clear TE bit in SCSCR to 0 End of transmission No Yes No Yes No Yes [1] SCIF status check and transmit data write: Read SCFSR and check that the TDFE flag and the TEND flag are set to 1, then write transmit data to SCFTDR, and clear the TDFE flag and the TEND flag to 0. [2] Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDFE flag to confirm that writing is possible, them write data to SCFTDR, and then clear the TDFE flag to 0. [1] [2] Figure 16.13 Sample Flowchart for Transmitting Serial Data

Section 16 Serial Communication Interface with FIFO (SCIF) R01UH0198EJ0500 Rev. 5.00 Page 853 of 1560 Mar 18, 2011 SH7080 Group Start of transmission and reception Initialization Read TDFE flag in SCFSR TDFE = 1? Write transmit data to SCFTDR, and clear TDFE flag and TEND flag in SCFSR to 0 after reading them as 1 Read ORER flag in SCLSR ORER = 1? Read RDF flag in SCFSR RDF = 1? Clear TE and RE bits in SCSCR to 0 End of transmission and reception Read receive data in SCFRDR, and clear RDF flag in SCFSR to 0 All data received? No No Yes No No Yes Yes [1] SCIF status check and transmit data write: Read SCFSR and check that the TDFE flag and the TEND flag are set to 1, then write transmit data to SCFTDR, and clear the TDFE flag and the TEND flag to 0. The transition of the TDFE flag from 0 to 1 can also be identified by a TXIF interrupt. [2] Receive error handling: Read the ORER flag in SCLSR to identify any error, perform the appropriate error handling, then clear the ORER flag to 0. Transmission/reception cannot be resumed while the ORER flag is set to 1. [3] SCIF status check and receive data read: Read SCFSR and check that RDF = 1, then read the receive data in SCFRDR, and clear the RDF flag to 0. The transition of the RDF flag from 0 to 1 can also be identified by an RXIF interrupt. [4] Serial transmission and reception continuation procedure: To continue serial transmission and reception, read 1 from the RDF flag and the receive data in SCFRDR, and clear the RDF flag to 0 before receiving the last bit in the current frame. Similarly, read 1 from the TDFE flag to confirm that writing is possible before transmitting the MSB in the current frame. Then write data to SCFTDR and clear the TDFE flag to 0. [1] Yes Error handling [4] When switching from a transmit operation or receive operation to simultaneous transmission and reception operations, clear the TE and RE bits to 0, and then set them simultaneously to 1. Note: [3] [2] Figure 16.18 Sample Flowchart for Transmitting/Receiving Serial Data

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16.5 SCIF Interrupt Sources and DTC

The SCIF has four interrupt sources: transmit-FIFO-data-empty (TXIF), receive-error (ERIF), receive-data-full (RXIF), and break (BRIF). Table 16.16 shows the interrupt sources and their order of priority. The interrupt sources are enabled or disabled by means of the TIE, RIE, and REIE bits in SCSCR. A separate interrupt request is sent to the interrupt controller for each of these interrupt sources. When TXIF request is enabled by TIE bit and the TDFE flag in the serial status register (SCFSR) is set to 1, a TXIF interrupt request is generated. When RXIF request is enabled by RIE bit and the RDF or DR flag in SCFSR is set to 1, an RXIF interrupt request is generated. The RXIF interrupt request caused by DR flag is generated only in asynchronous mode. When BRIF request is enabled by RIE bit or REIE bit and the BRK flag in SCFSR or ORER flag in SCLSR is set to 1, a BRIF interrupt request is generated. When ERIF request is enabled by RIE bit or REIE bit and the ER flag in SCFCR is set to 1, an ERIF interrupt request is generated. When the RIE bit is set to 0 and the REIE bit is set to 1, SCIF request ERIF interrupt and BRIF interrupt without requesting RXIF interrupt. The TXIF interrupt indicates that transmit data can be written, and the RXIF interrupt indicates that there is receive data in SCFRDR. Table 16.16 SCIF Interrupt Sources Interrupt Source ERIF Interrupt initiated by receive error (ER) RIE or REIE ⎯ RXIF Interrupt initiated by receive data FIFO full (RDF) or data ready (DR) RIE √ BRIF Interrupt initiated by break (BRK) or overrun error (ORER) RIE or REIE ⎯ TXIF Interrupt initiated by transmit FIFO data empty (TDFE) TIE √

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16.6 Serial Port Register (SCSPTR) and SCIF Pins

The relationship between SCSPTR and the SCIF pins is shown in figures 16.19 to 16.22. [Legend] SPTRW: SCSPTR write Note: * The modem control function is specified for the RTS pin by setting the MCE bit in SCFCR. Reset Internal data bus Modem control enable signal* Bit 7 Bit 6 Reset RTS signal QD R RTSIO RTS C QD R RTSDT SPTRW SPTRW C Figure 16.19 RTSIO Bit, RTSDT Bit, and RTS Pin

Section 16 Serial Communication Interface with FIFO (SCIF) R01UH0198EJ0500 Rev. 5.00 Page 857 of 1560 Mar 18, 2011 SH7080 Group [Legend] SPTRW: SCSPTR write Reset Internal data bus Transmit enable signal Bit 1 Bit 0 Reset Serial transmit data QD R SPBIO TXD C QD R SPBDT SPTRW SPTRW C Figure 16.22 SPBIO Bit, SPBDT bit, and TXD Pin

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16.7 Usage Notes

Note the following when using the SCIF.

16.7.1 SCFTDR Writing and TDFE Flag

The TDFE flag in the serial status register (SCFSR) is set when the number of transmit data bytes written in the transmit FIFO data register (SCFTDR) has fallen below the transmit trigger number set by bits TTRG1 and TTRG0 in the FIFO control register (SCFCR). After TDFE is set, transmit data up to the number of empty bytes in SCFTDR can be written, allowing efficient continuous transmission. However, if the number of data bytes written in SCFTDR is equal to or less than the transmit trigger number, the TDFE flag will be set to 1 again after being read as 1 and cleared to 0. TDFE clearing should therefore be carried out when SCFTDR contains more than the transmit trigger number of transmit data bytes. The number of transmit data bytes in SCFTDR can be found from the upper 8 bits of the FIFO data count register (SCFDR).

16.7.2 SCFRDR Reading and RDF Flag

The RDF flag in the serial status register (SCFSR) is set when the number of receive data bytes in the receive FIFO data register (SCFRDR) has become equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in the FIFO control register (SCFCR). After RDF is set, receive data equivalent to the trigger number can be read from SCFRDR, allowing efficient continuous reception. However, if the number of data bytes in SCFRDR is equal to or greater than the trigger number, the RDF flag will be set to 1 again if it is cleared to 0. RDF should therefore be cleared to 0 after being read as 1 after reading the number of the received data in the receive FIFO data register (SCFRDR) which is less than the trigger number. The number of receive data bytes in SCFRDR can be found from the lower 8 bits of the FIFO data count register (SCFDR).

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16.7.3 Break Detection and Processing

Break signals can be detected by reading the RXD pin directly when a framing error (FER) is detected. In the break state the input from the RXD pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set. Note that, although transfer of receive data to SCFRDR is halted in the break state, the SCIF receiver continues to operate.

16.7.4 Sending a Break Signal

The I/O condition and level of the TXD pin are determined by the SPBIO and SPBDT bits in the serial port register (SCSPTR). This feature can be used to send a break signal. Until TE bit is set to 1 (enabling transmission) after initializing, TXD pin does not work. During the period, mark status is performed by SPBDT bit. Therefore, the SPBIO and SPBDT bits should be set to 1 (high level output). To send a break signal during serial transmission, clear the SPBDT bit to 0 (designating low level), then clear the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, and 0 is output from the TXD pin.

16.7.5 Receive Data Sampling Timing and Receive Margin (Asynchronous Mode)

The SCIF operates on a base clock with a frequency of 16 times the transfer rate. In reception, the SCIF synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the eighth base clock pulse. The timing is shown in figure 16.23.

Section 16 Serial Communication Interface with FIFO (SCIF) Page 860 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group 0 1 2 3 4 5 6 7 8 9 10 1112 1314 15 0 1 2 3 4 5 6 7 8 9 10 1112 1314 15 0 1 2 3 4 5 D0 D1 16 clocks 8 clocks Base clock Receive data (RXD) Start bit –7.5 clocks +7.5 clocks Synchronization sampling timing Data sampling timing Figure 16.23 Receive Data Sampling Timing in Asynchronous Mode The receive margin in asynchronous mode can therefore be expressed as shown in equation 1. Equation 1: D - 0.5 N Where: M: Receive margin (%) N: Ratio of clock frequency to bit rate (N = 16) D: Clock duty (D = 0 to 1.0) L: Frame length (L = 9 to 12) F: Absolute deviation of clock frequency From equation 1, if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation 2. Equation 2: When D = 0.5 and F = 0: = 46.875% This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.

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16.7.6 Module Standby Mode Setting

The SCIF operation can be disabled or enabled using the standby control register. The initial setting is for SCIF operation to be halted. Access to registers is enabled by clearing module standby mode. For details, refer to section 26, Power-Down Modes.

16.7.7 Note on Using DTC

When data is written to SCFTDR by activating the DTC through a TXIF interrupt, the TEND flag value is undefined. In this case, do not use the TEND flag as a transmit end flag.

16.7.8 FER Flag and PER Flag of Serial Status Register (SCFSR)

The FER flag and PER flag in the serial status register (SCFSR) are status flags that apply to next entry to be read from the receive FIFO data register (SCFRDR). After the CPU or DTC reads the receive FIFO data register, the flags of framing errors and parity errors will disappear. To check the received data for the states of framing errors and parity errors, only read the receive FIFO register after reading the serial status register.

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Section 17 Synchronous Serial Communication Unit (SSU) R01UH0198EJ0500 Rev. 5.00 Page 863 of 1560 Mar 18, 2011 SH7080 Group Section 17 Synchronous Serial Communication Unit (SSU) This LSI has an independent synchronous serial communication unit (SSU) channel. The SSU has master mode in which this LSI outputs clocks as a master device for synchronous serial communication and slave mode in which clocks are input from an external device for synchronous serial communication. Synchronous serial communication can be performed with devices having different clock polarity and clock phase.

17.1 Features

• Choice of SSU mode and clock synchronous mode
• Choice of master mode and slave mode
• Choice of standard mode and bidirectional mode
• Synchronous serial communication with devices with different clock polarity and clock phase
• Choice of 8/16/32-bit width of transmit/receive data
• Full-duplex communication capability The shift register is incorporated, enabling transmission and reception to be executed simultaneously.
• Consecutive serial communication
• Choice of LSB-first or MSB-first transfer
• Choice of a clock source Pφ/4, Pφ/8, Pφ/16, Pφ/32, Pφ/64, Pφ/128, Pφ/256, or an external clock
• Five interrupt sources Transmit end, transmit data register empty, receive data full, overrun error, and conflict error. The data transfer controller (DTC) can be activated by a transmit data register empty request or a receive data full request to transfer data.
• Module standby mode can be set

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17.2 Input/Output Pins

Table 17.1 shows the SSU pin configuration. Table 17.1 Pin Configuration Symbol I/O Function SSCK I/O SSU clock input/output SSI I/O SSU data input/output SSO I/O SSU data input/output SCS I/O SSU chip select input/output

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17.3 Register Descriptions

The SSU has the following registers. For details on the addresses of these registers and the states of these registers in each processing state, see section 27, List of Registers. Table 17.2 Register Configuration Register Name Abbrevia- tion R/W Initial value Address Access Size SS control register H SSCRH R/W H'0D H'FFFFCD00 8, 16 SS control register L SSCRL R/W H'00 H'FFFFCD01 8 SS mode register SSMR R/W H'00 H'FFFFCD02 8, 16 SS enable register SSER R/W H'00 H'FFFFCD03 8 SS status register SSSR R/W H'04 H'FFFFCD04 8, 16 SS control register 2 SSCR2 R/W H'00 H'FFFFCD05 8 SS transmit data register 0 SSTDR0 R/W H'00 H'FFFFCD06 8, 16 SS transmit data register 1 SSTDR1 R/W H'00 H'FFFFCD07 8 SS transmit data register 2 SSTDR2 R/W H'00 H'FFFFCD08 8, 16 SS transmit data register 3 SSTDR3 R/W H'00 H'FFFFCD09 8 SS receive data register 0 SSRDR0 R H'00 H'FFFFCD0A 8, 16 SS receive data register 1 SSRDR1 R H'00 H'FFFFCD0B 8 SS receive data register 2 SSRDR2 R H'00 H'FFFFCD0C 8, 16 SS receive data register 3 SSRDR3 R H'00 H'FFFFCD0D 8

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17.3.1 SS Control Register H (SSCRH)

SSCRH specifies master/slave device selection, bidirectional mode enable, SSO pin output value selection, SSCK pin selection, and SCS pin selection. Bit: Initial value: R/W: 7654321 0 00001101 R/W R/W R R/W R/W R R/W R/W MSS BIDE - SOL SOLP - CSS[1:0] Bit Bit Name Initial Value R/W Description

7 MSS 0 R/W Master/Slave Device Select

Selects that this module is used in master mode or slave mode. When master mode is selected, transfer clocks are output from the SSCK pin. When the CE bit in SSSR is set, this bit is automatically cleared. 0: Slave mode is selected. 1: Master mode is selected.

6 BIDE 0 R/W Bidirectional Mode Enable

Selects that both serial data input pin and output pin are used or one of them is used. However, transmission and reception are not performed simultaneously when bidirectional mode is selected. For details, section 17.4.3, Relationship between Data Input/Output Pins and Shift Register. 0: Standard mode (two pins are used for data input and output) 1: Bidirectional mode (one pin is used for data input and output) 5 ⎯ 0 R Reserved This bit is always read as 0. The write value should always be 0.

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4 SOL 0 R/W Serial Data Output Value Select

The serial data output retains its level of the last bit after completion of transmission. The output level before or after transmission can be specified by setting this bit. When specifying the output level, use the MOV instruction after clearing the SOLP bit to 0. Since writing to this bit during data transmission causes malfunctions, this bit should not be changed. 0: Serial data output is changed to low. 1: Serial data output is changed to high.

3 SOLP 1 R/W SOL Bit Write Protect

When changing the output level of serial data, set the SOL bit to 1 or clear the SOL bit to 0 after clearing the SOLP bit to 0 using the MOV instruction. 0: Output level can be changed by the SOL bit 1: Output level cannot be changed by the SOL bit. This bit is always read as 1. 2 ⎯ 1 R Reserved This bit is always read as 1. The write value should always be 1. 1, 0 CSS[1:0] 01 R/W SCS Pin Select Select that the SCS pin functions as SCS input or output. 00: Setting prohibited 01: Setting prohibited 10: Function as SCS automatic input/output (function as SCS input before and after transfer and output a low level during transfer) 11: Function as SCS automatic output (outputs a high level before and after transfer and outputs a low level during transfer)

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17.3.2 SS Control Register L (SSCRL)

SSCRL selects operating mode, software reset, and transmit/receive data length. Bit: Initial value: R/W: 7654321 0 00000000 R/W R/W R/W R R R R/W R/W FCLRM SSUMS SRES - - - DATS[1:0] Bit Bit Name Initial Value R/W Description

7 FCLRM 0 R/W Flag Clear Mode

Selects whether the SSRXI and SSTXI interrupt flags are cleared on writing to SSTDR or reading from SSRDR or on completion of DTC transfer. When using the DTC, set this bit to 0. 0: Flags are cleared when DTC transfer is completed (except when transfer counter value is H'0000) 1: Flags are cleared on SSTDR or SSRDR access

6 SSUMS 0 R/W Selects transfer mode from SSU mode and clock

synchronous mode. 0: SSU mode 1: Clock synchronous mode

5 SRES 0 R/W Software Reset

Setting this bit to 1 forcibly resets the SSU internal sequencer. After that, this bit is automatically cleared. The ORER, TEND, TDRE, RDRF, and CE bits in SSSR and the TE and RE bits in SSER are also initialized. Values of other bits for SSU registers are held. To stop transfer, set this bit to 1 to reset the SSU internal sequencer. 4 to 2 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0.

Section 17 Synchronous Serial Communication Unit (SSU) Page 870 of 1560 R01UH0198EJ0500 Rev. 5.00 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description 1, 0 DATS[1:0] 00 R/W Transmit/Receive Data Length Select Select serial data length. 00: 8 bits 01: 16 bits 10: 32 bits 11: Setting prohibited

17.3.3 SS Mode Register (SSMR)

SSMR selects the MSB first/LSB first, clock polarity, clock phase, and clock rate of synchronous serial communication. Bit: Initial value: R/W: 7654321 0 00000000 R/W R/W R/W R R R/W R/W R/W MLS CPOS CPHS - - CKS[2:0] Bit Bit Name Initial Value R/W Description

7 MLS 0 R/W MSB First/LSB First Select

Selects that the serial data is transmitted in MSB first or LSB first. 0: LSB first 1: MSB first

6 CPOS 0 R/W Clock Polarity Select

Selects the SSCK clock polarity. 0: High output in idle mode, and low output in active mode 1: Low output in idle mode, and high output in active mode

5 CPHS 0 R/W Clock Phase Select (Only for SSU Mode)

Selects the SSCK clock phase. 0: Data changes at the first edge. 1: Data is latched at the first edge.

Section 17 Synchronous Serial Communication Unit (SSU) R01UH0198EJ0500 Rev. 5.00 Page 871 of 1560 Mar 18, 2011 SH7080 Group Bit Bit Name Initial Value R/W Description 4, 3 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. 2 to 0 CKS[2:0] 000 R/W Transfer Clock Rate Select Select the transfer clock rate (prescaler division rate) when an internal clock is selected. 000: Reserved 001: Pφ/4 010: Pφ/8 011: Pφ/16 100: Pφ/32 101: Pφ/64 110: Pφ/128 111: Pφ/256

17.3.4 SS Enable Register (SSER)

SSER performs transfer/receive control of synchronous serial communication and setting of interrupt enable. Bit: Initial value: R/W: 7654321 0 00000000 R/W R/W R R R/W R/W R/W R/W TE RE - - TEIE TIE RIE CEIE Bit Bit Name Initial Value R/W Description

7 TE 0 R/W Transmit Enable

When this bit is set to 1, transmission is enabled.

6 RE 0 R/W Receive Enable

When this bit is set to 1, reception is enabled. 5, 4 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0.

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3 TEIE 0 R/W Transmit End Interrupt Enable

When this bit is set to 1, a SSTEI interrupt request is enabled.

2 TIE 0 R/W Transmit Interrupt Enable

When this bit is set to 1, a SSTXI interrupt request is enabled.

1 RIE 0 R/W Receive Interrupt Enable

When this bit is set to 1, an SSRXI interrupt request and an SSOEI interrupt request are enabled.

0 CEIE 0 R/W Conflict Error Interrupt Enable

When this bit is set to 1, a SSCEI interrupt request is enabled.

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17.3.5 SS Status Register (SSSR)

SSSR is a status flag register for interrupts. Bit: Initial value: R/W: 7654321 0 00000100 R R/W R R R/W R/W R/W R/W - ORER - - TEND TDRE RDRF CE Bit Bit Name Initial Value R/W Description 7 ⎯ 0 R Reserved This bit is always read as 0. The write value should always be 0.

6 ORER 0 R/W Overrun Error

If the next data is received while RDRF = 1, an overrun error occurs, indicating abnormal termination. SSRDR stores 1-frame receive data before an overrun error occurs and loses data to be received later. While ORER = 1, consecutive serial reception cannot be continued. Serial transmission cannot be continued, either. [Setting condition]

• When one byte of the next reception is completed with RDRF = 1 [Clearing condition]
• When writing 0 after reading ORER = 1 5, 4 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0.

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