DF6805

DF6805 DCD | Alldatasheet

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All trademarks mentioned in this document are trademarks of their respective owners. Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved. http://www.DigitalCoreDesign.com http://www.dcd.pl DDFF66880055 8-bit FAST Microcontrollers Family ver 1.04 OVERVIEW Document contains brief description of DF6805 core functionality. The DF6805 is a advanced 8-bit MCU IP Core with highly so- phisticated, on chip peripheral capabilities. DF6805 soft core is binary-compatible with the industry standard 68HC05 8-bit microcontrol- ler and can achieve a performance 45-100 million instructions per second. There are two configurations of DF6805: Harvard where data and program buses are separated, and von Neumann with common program and data bus DF6805 has FAST architecture that is 4.1 times faster compared to original im- plementation. Core in standard configuration has integrated on chip major peripheral func- tion. The DF6805 Microcontroller Core contains full-duplex UART (Asynchronous serial com- munications interface (SCI), and can also be equipped with the Synchronous Serial Periph- eral Interface SPI. The main 16-bit, free-running timer system has implemented two input capture lines and two output-compare lines. Self-monitoring circuitry is included on-chip to protect against system errors. A computer operating properly (COP) watchdog system protects against software failures. An illegal opcode detection circuit provides a non- maskable interrupt if illegal opcode is de- tected. Two software-controlled power-saving modes, WAIT and STOP, are available to conserve additional power. These modes make the DF6805 IP Core especially attractive for automotive and battery-driven applications. DF6805 is fully customizable, which means it is delivered in the exact configuration to meet users requirements. There is no need to pay extra for not used features and wasted silicon. It includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC de- sign flow. CPU FEATURES FAST architecture, 4.1 times faster than the original implementation Software compatible with industry standard 68HC05 Configurable Harvard or Von Neumann architectures 64 bytes of System Function Registers space (SFRs) Up to 64k bytes of Program Memory Up to 64k bytes of Data Memory De-multiplexed Address/Data Bus to allow easy connection to memory Two power saving modes: STOP, WAI Ready pin allows Core to operate with slow program and data memories Fully synthesizable, static synchronous design with no internal tri-states

All trademarks mentioned in this document are trademarks of their respective owners. Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved. http://www.DigitalCoreDesign.com http://www.dcd.pl ONE GLOBAL SYSTEM CLOCK No internal reset generator or gated clock Scan test ready Technology independent HDL source code Core can be fully customized

1 GHz virtual clock frequency compared to

ALL ASYNCHRONOUS INPUT SIGNALS ARE SYNCHRONIZED BEFORE INTERNAL USE

9 D ATA MEMORY:

The DF6805 can address up to 64K bytes of Data Memory. The lowest 64 Bytes is reserved for Special Function Reg- isters area. Data Memory can be imple- mented as synchronous or asynchronous RAM

9 S YSTEM FUNCTION REGISTERS:

Up to 64 System Function Regis- ters(SFRs) may be implemented in the DF6805 design.

9 P ROGRAM MEMORY:

Up to 64kB of Program Memory may be implemented to the DF6805 design. Pro- gram Memory can be implemented as syn- chronous or asynchronous ROM

9 A LL CORE IS DESIGNED AS SYNCHRONOUS LOGIC

WITHOUT ANY MICROCODE. PERIPHERALS The peripherals listed below are implemented in standard configuration of DF6805. DoCDTM on Chip Debugger Processor execution control Read, write all processor contents Hardware execution breakpoints Three wire communication interface Four 8-bit I/O Ports Interrupt Controller 7 interrupt sources 7 priority levels Dedicated Interrupt vect or for each interrupt source Main16-bit timer/counter system 16 bit free running counter Timer clocked by internal source 16-bit Compare/Capture Unit Two independent input-capture functions Two output-compare channels Events capturing Pulses generation Digital signals generation Gated timers Sophisticated comparator Pulse width modulation Pulse width measuring Full-duplex UART - SCI Standard Nonreturn to Zero format (NRZ) 8 or 9 bit data transfer Integrated baud rate generator Noise, Overrun and Framing error detection IDLE and BREAK characters generation Wake-up block to recognize UART wake-up from IDLE condition Three SCI related interrupts DELIVERABLES Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF VHDL & VERILOG test bench environ- ment Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Technical documentation Installation notes HDL core specification Datasheet Synthesis scripts Example application Technical support IP Core implementation support 3 months maintenance

• Delivery the IP Core updates, minor and major versions changes
• Delivery the documentation updates Phone & email support

All trademarks mentioned in this document are trademarks of their respective owners. Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved. http://www.DigitalCoreDesign.com http://www.dcd.pl CONFIGURATION The following parameters of the DF6805 core can be easy adjusted to requirements of dedicated application and technology. Con- figuration of the core can be prepared by ef- fortless changing appropriate constants in package file. There is no need to change any parts of the code. - used • DoCDTM Hardware Debugger - unused - Harvard • Architecture type - Von Neumann - Synchronous • Memories type - Asynchronou - used • Data Memory wait-states - unused - used • Power saving STOP mode - unused - used • WATCHDOG Timer - unused - used • Timer system - unused - used • Compare Capture channels - unused - used • PORTS A, B, C, D - unused - used • SCI – UART Interface - unused - used • Support for MUL Instruction - unused LICENSING Comprehensible and clearly defined licensing methods without royalty fees make using of IP Core easy and simply. Single Design license allows use IP Core in single FPGA bitstream and ASIC implementa- tion. Unlimited Designs , One Year licenses allow use IP Core in unlimited number of FPGA bit- streams and ASIC implementations. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited. There is no time restric- tion except One Year license where time of use is limited to 12 months. Single Design license for VHDL, Verilog source code called HDL Sour- ce ○ Encrypted, or plain text EDIF called Netlist One Year license for Encrypted Netlist only Unlimited Designs license for HDL Source Netlist Upgrade from HDL Source to Netlist Single Design to Unlimited Designs

All trademarks mentioned in this document are trademarks of their respective owners. Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved. http://www.DigitalCoreDesign.com http://www.dcd.pl PINS DESCRIPTION PIN ACTIVE TYPE DESCRIPTION clk - input Global system clock rst Low input Global system reset prgdata[7:0] - input Program memory bus input datai[7:0] - input Memory bus input ufrdatai[7:0] - input UFRs data bus input ready Low input Code and Data memory Ready irq * input Interrupt input portai[7:0] - input Port A input portbi[7:0] - input Port B input portci[7:0] - input Port C input portdi[7:0] - input Port D input cap1,2 Low input Capture inputs rxd Low input SCI receiver data input clkdocd - input DoCD TM clock input docddatai - input DoCD TM serial Data input prgaddr[15:0] - output Program memory address bus prgoe - output Program memory output enable datao[7:0] - output Data memory & UFR bus output addr[15:0] - output Data memory address bus ramwe Low output Data memory write enable ramoe Low output Data memory output enable ufraddr[5:0] - output UFR’s address bus ufrwe Low output UFRs write enable ufroe Low output UFRs output enable halt High output Halt clock system (STOP inst.) portao[7:0] - output Port A output portbo[7:0] - output Port B output portco[7:0] - output Port C output portdo[7:0] - output Port D output ddra[7:0] - output Port A data direction control ddrb[7:0] - output Port B data direction control ddrc[7:0] - output Port C data direction control ddrd[7:0] - output Port D data direction control cmp1,2 * output Compare outputs txd Low output SCI transmitter data output docddatao - output DoCD TM Serial Data Output docdclk - output DoCD TM Serial Clock Output prgwe - output DoCD TM Program Memory Write * Kind of activity is configurable SYMBOL addr(15:0) ramwe ramoe portao(7:0) portdo(7:0) portco(7:0) portbo(7:0) portai(7:0) portbi(7:0) portci(7:0) portdi(7:0) datai(7:0) ufrdatai(7:0) irq cap1 cap2 clk rst rxd datao(7:0) txd halt ddra(7:0) ddrd(7:0) ddrc(7:0) ddrb(7:0) cmp1 cmp2 prgdata(7:0) prgaddr(15:0) prgoe ready ufraddr(5:0) ufrwe ufroe clkdocd docddatai docddatao docdclk prgwe DoCDTM Interface BLOCK DIAGRAM Control Unit - Performs the core synchroniza- tion and data flow control. This module man- ages execution of all instructions. The Control Unit also manages execution of STOP instruc- tion and wakes-up the processor from the STOP mode. Opcode Decoder - Performs an instruction opcode decoding and the control functions for all other blocks. ALU - Arithmetic Logic Unit performs the arithmetic and logic operations during execu- tion of an instruction. It contains accumulator (A), Condition Code Register (CCREG), Index registers (X) and related logic like arithmetic unit, logic unit and multiplier.

All trademarks mentioned in this document are trademarks of their respective owners. Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved. http://www.DigitalCoreDesign.com http://www.dcd.pl Bus Controller – Program Memory, Data Memory & SFR’s (Special Function Register) interface controls access into the program and data memories and special registers. It con- tains Program Counter (PC), Stack Pointer (SP) register, and related logic. portao(7:0) portdo(7:0) portco(7:0) portbo(7:0) datai(7:0) clk rst datao(7:0) cap1 cap2 BUS Controller I/O Ports Opcode Decoder Interrupt Controller Timer with Compare / Capture Unit SCI Unit irq cmp1 cmp2 txd rxd ramoe ramwe addr(23:0) halt portai(7:0) portdi(7:0) portci(7:0) portbi(7:0) ddra(7:0) ddrd(7:0) ddrc(7:0) ddrb(7:0) Watchdog Timer ALU prgdata(7:0) prgaddr(15:0) prgoe ufroe ufrwe ufraddr(5:0) ready Control Unit DoCDTM Debugger docdclk docddatai docddatao prgwe clkdocd Interrupt Controller - DF6805 extended IC has implemented 7-level interrupt priority con- trol. The interrupt requests may come from external pin (IRQ) as well as from particular peripherals. The DF6805 peripheral systems generate maskable interrupts, which are rec- ognized only if the global interrupt mask bit (I) in the CCR is cleared. Maskable interrupts are prioritized according to default arrangement established during reset. When interrupt con- dition occurs, an interrupt status flag is set to indicate the condition. I/O Ports - All ports are 8-bit general-purpose bi-directional I/O system. The PORTA, PORTB, PORTC, PORTD data registers have their corresponding data direction registers DDRA, DDRB, DDRC, DDRD to control ports data flow. It assures that all DF6805’s ports have full I/O selectable registers. Writes to any ports pins cause data to be stored in the data registers. If any port pins are configured as output then data registers are driven out of those pins. Reads from port pins configured as input causes that input pin is read. If port pins is configured as output, during read data register is read. Writes to any ports pins not configured as outputs do not cause data to be driven out of those pins, but the data is stored in the output registers. Thus, if the pins later become outputs, the last data written to port will be driven out the port pins. Timer & Compare - The programmable timer is based on free-running 16-bit counter with a fixed divide by four prescaler. plus input cap- ture/output compare circuitry. The timer can be used for many purposes including measur- ing pulse length of two input signals and gen- erating two output signals. The timer has 16- bit architecture, hence each specific functional segment is represented by two 8-bit registers. These registers contains the high and low byte of that functional block. Accessing the low byte of a specific timer function allows full control of that function, however, an access of the high byte inhibits that specific timer func- tion until the byte is also accessed. Each of the input-capture channel has its own 16-bit time capture latch (input-capture regis- ter) and each of the output-compare channel has its own 16-bit compare register. Additional control bits permit software to control the edge(s) that trigger each input-capture func- tion and the automatic actions that result from output-compare functions. Although hardwired logic is included to automate many timer ac- tivities, this timer architecture is essentially a software-oriented system. This structure is easily adaptable to a very wide range of appli- cations although it is not as efficient as dedi- cated hardware for some specific timing appli- cations. Watchdog Timer - The Watchdog Timer con- sist of a free running Timer CLK/213 , plus con- trol logic. The Watchdog Timer can be en- abled by software by writing ‘1’ to the WDOG bit in MISC register ($000C). Once enabled the WDT Timer cannot be disabled by soft- ware. In addition the WDOG bit acts as a re- set mechanism for the WDT Timer. Writing logic one ‘1’ to the WDOG bit clears Watch- dog counter and inhibits Watchdog timeout

All trademarks mentioned in this document are trademarks of their respective owners. Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved. http://www.DigitalCoreDesign.com http://www.dcd.pl SCI - The SCI is a full-duplex UART type asynchronous system, using standard non return to zero (NRZ) format : 1 start bit, 8 or 9 data bits and a 1 stop bit. The DF6805 resyn- chronizes the receiver bit clock on all one to zero transitions in the bit stream. Therefore differences in baud rate between the sending device and the SCI are not as likely to cause reception errors. Three logic samples are taken near the middle of data bit time, and majority logic decides the sense for the bit. For the start and stop bits seven logic sam- ples are taken. Even if noise causes one of these samples to be incorrect, the bit will still be received correctly. The receiver also has the ability to enter a temporary standby mode (called receiver wakeup) to ignore messages intended for a different receiver. Logic auto- matically wakes up the receiver in time to see the first character of the next message. This wakeup feature greatly reduces CPU over- head in multi-drop SCI networks. The SCI transmitter can produce queued characters of idle (whole characters of all logic 1) and break (whole characters of all logic 0). In addition to the usual transmit data register empty (TDRE) status flag, this SCI also provides a transmit complete (TC) indication that can be used in applications with a modem. DoCDTM - Debug Unit – it’s a real-time hard- ware debugger provides debugging capability of a whole SoC system. In contrast to other on-chip debuggers DoCD™ provides non- intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller in- cluding all registers, internal, external, pro- gram memories, all SFRs including user de- fined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, as well as on SFRs. Hardware breakpoint is executed if any write/read occurred at particular address with certain data pattern or without pattern. The DoCD TM system includes three-wire inter- face and complete set of tools to communi- cate and work with core in real time debug- ging. It is built as scalable unit and some fea- tures can be turned off to save silicon and reduce power consumption. A special care on power consumption has been taken, and when debugger is not used it is automatically switched in power save mode. Finally whole debugger is turned off when debug option is no longer used. OPTIONAL PERIPHERALS There are also available an optional pe- ripherals, not included in presented DF6805 Microcontroller Core. The optional peripherals, can be implemented in microcontroller core upon customer request. SPI – Master and Slave Serial Peripheral Interface Supports speeds up ¼ of system clock Mode fault error Write collision error Software selectable polarity and phase of se- rial clock SCK System errors detection Allows operation from a wide range of system clock frequencies (build-in 5-bit timer) Interrupt generation I2C bus controller - Master 7-bit and 10-bit addressing modes NORMAL, FAST, HIGH speeds Multi-master systems supported Clock arbitration and synchronization User defined timings on I2C lines Wide range of system clock frequencies Interrupt generation I2C bus controller - Slave NORMAL speed 100 kbs FAST speed 400 kbs HIGH speed 3400 kbs Wide range of system clock frequencies User defined data setup time on I2C lines Interrupt generation PWM – Pulse Width Modulation Timer Fixed-Point arithmetic coprocessor Floating-Point arithmetic coprocessor IEEE-754 standard single precision Floating-Point math coprocessor - IEEE- 754 standard single precision real, word and short integers

All trademarks mentioned in this document are trademarks of their respective owners. Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved. http://www.DigitalCoreDesign.com http://www.dcd.pl PERFORMANCE The following table gives a survey about the Core area and performance in the ALTERA® devices after Place & Route: Device Speed grade Logic Cells Fmax CYCLONE -6 1689 79 MHz STRATIX -5 1690 83 MHz MERCURY -5 1671 85 MHz APEX II -7 1850 63 MHz APEX20KC -7 1698 55 MHz APEX20KE -1 1698 47 MHz ACEX1K -1 1739 41 MHz FLEX10KE -1 1739 41 MHz Core performance in ALTERA® devices Area utilized by the each unit of DF6805 core in vendor specific technologies is summarized in table below. Component Area [LC] [FFs] CPU* 1134 153 Main Timer 110 55 COM/CAP 150 60 Watchdog 29 14 UART - SCI 272 124 I/O Ports 161 64 Total area 1856 470 *CPU – consisted of ALU, Control Unit and Instruction Decoder, Bus Controller with support for 64KB RAM, External IRQ pin Interrupt Con- troller Core components area utilization IMPROVEMENT For user the most important is application speed improvement. The most commonly used arithmetic functions and theirs improve- ment are shown in table below. Improvement was computed as {M68HC04 clock periods} divided by {DF6805 clock periods} required to execute an identical function. More details are available in core documentation Function Improve- ment 8-bit addition (immediate data) 4 8-bit addition (direct addressing) 4 8-bit addition (indirect addressing) 3,6 8-bit subtraction (immediate data) 4 8-bit subtraction (direct addressing) 4 8-bit subtraction (indirect addressing) 3,6 16-bit addition (immediate data) 4 16-bit addition (direct addressing) 4 16-bit addition (indirect addressing 3,6 16-bit subtraction (immediate data) 4 16-bit subtraction (direct addressing) 4 16-bit subtraction (indirect addressing 3,6 Multiplication 5 Division 5 DF68XX FAMILY OVERVIEW The main features of each DF68XX family member have been summarized in table below. It gives a briefly member characterization helping user to select the most suitable IP Core for its application. User can specify its own peripheral set (including listed below and the others) and requests the core modifications. Design Physical Linear memory space Paged Data Memory space Motorola Memory Expansion Logic Interrupt sources Interrupt levels Real Time Inter- rupt Data Pointers READY for Pro. and Data mem. Compare\\Capture Main Timer Sys- tem SCI (UART) I\\O Ports SPI M/S Interface Watchdog Timer Pulse accumula- tor Interface for additional SFRs DoCD Debugger Size – ASIC gates DF6805 64k 64k - 7 7 - - * 2/2* 1* * 4 + * - 6 700 DF6808 64k 64k - 7 7 - - * 22* 1* * 4 * - 8 900 DF6811 64k 16M - 20 17 1* * 5/3* 1* * 4 12 000 DF6811CPU 64k 16M - 3 3 + 1* * + + + + + + + 6 500 DF68XX family of High Performance Microcontroller Cores + optional * configurable

All trademarks mentioned in this document are trademarks of their respective owners. Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved. http://www.DigitalCoreDesign.com http://www.dcd.pl CONTACTS For any modification or special request please contact to Digital Core Design or local distributors. Headquarters: Wroclawska 94 41-902 Bytom, POLAND e-mail: info@dcd.pliinnffoo@@ddccdd..ppll tel. : +48 32 282 82 66 fax : +48 32 282 74 37 Distributors: