PCM1760P BURR-BROWN | Alldatasheet
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Technical content
FEATURES
l DUAL 20-BIT MONOLITHIC MODULATOR (PCM1760) AND MONOLITHIC DECIMATING DIGITAL FILTER (DF1760) l HIGH PERFORMANCE: THD+N: –92dB typ, –90dB max Dynamic Range: 108dB typ SNR: 108dB min, 110dB typ Channel Separation: 98dB typ, 94dB min l 64X OVERSAMPLING l CO-PHASE CONVERSION l RUNS ON 256fs OR 384fs SYSTEM CLOCK l VERSATILE INTERFACE CAPABILITY: 16-, 20-Bit Output MSB First or LSB First Format l OPTIONAL FUNCTIONS: Offset Error Calibration Overflow Detection Power Down Mode (DF1760) l RUNS ON ±5V SUPPLIES (PCM1760) AND 5V SUPPLY (DF1760) l COMPACT 28-PIN PACKAGES: 28-Pin DIP and SOIC Multi-Bit Enhanced Noise Shaping 20-Bit ANALOG-TO-DIGITAL CONVERSION SYSTEM
DESCRIPTION
The PCM1760 and DF1760 combine for a low-cost, high-performance dual 20-bit, 48kHz sampling ana- log-to-digital conversion system which is specifically designed for dynamic applications. The PCM1760/DF1760 pair form a 4-bit, 4th order, 64X oversampling analog-to-digital converter. The PCM1760 is a delta-sigma modulator that uses a 4-bit quantizer within the modulation loop to achieve very high dynamic range. The DF1760 is a high-performance decimating digital filter. The DF1760 accepts 4-bit 64fs data from the PCM1760 and decimates to 20-bit 1fs data. The FIR filter of the DF1760 has pass-band ripple of less than ±0.001dB and greater than 100dB of the reject band attenuation.
4 Stage, 4-Bit
Input (L) Analog Input (R) 64fs 256fs 4fs fs Data System Clock 256/384fs 64fs DF1760 International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 PCM1760P/U DF1760P/U © 1993 Burr-Brown Corporation PDS-1174C Printed in U.S.A. July, 1994
At TA = +25°C, ±VCC , ±Vdd = +5V, +VDD = +5V, fS = 48kHz and ext. components = ±2% unless otherwise noted. PCM1760/DF1760 PARAMETER CONDITIONS MIN TYP MAX UNITS RESOLUTION 20 Bits ANALOG INPUT Input Range R IN1 = 2.2kΩ± 2.5 Vp-p Input Impedance R IN1 = 2.2kΩ R IN1 Ω SAMPLING FREQUENCY Cover Range of fs Integrator Constants: Application (1) 30 48 50 kHz ACCURACY Gain Error ±0.5 ±1.0 dB Gain Mismatch ±0.5 dB Bipolar Zero Error V IN = 0 at 20s After Power-On ±0.4 % FSR (2) Gain Drift 0 °C to +70°C ±100 ppmfs/ °C Bipolar Zero Drift 0 °C to +70°C ±20 ppmfs/ °C DYNAMIC CHARACTERISTICS (4) THD+N/(0dBFS) P, U f IN = 1kHz –92 –90 dB P-L, U-L –90 –88 dB THD+N/(–20dBFS) P, U f IN = 1kHz –76 –70 dB P-L, U-L –76 –70 dB THD+N/(–60dBFS) P, U f IN = 1kHz –44 –42 dB P-L, U-L –44 –42 dB Dynamic Range P, U f IN = 1kHz, VIN = –60dBFS, A Filter 104 108 dB P-L, U-L 104 108 dB SNR P, U V IN = 0, A Filter 108 110 dB P-L, U-L 106 110 dB Frequency Response f IN = 20kHz ±0.1 dB Channel Separation f IN = 1kHz, A Filter 94 98 dB DIGITAL FILTER Over Sample Rate 64 fs Ripple in Band 0 - 0.04535fs ±0.0001 dB Stopband Attenuation –1 0.5465fs - 63.4535fs –94 dB Stopband Attenuation –2 0.5465fs - 3.4535fs –100 dB LOGIC INPUTS AND OUTPUTS Logic Family Input TTL Level Compatible CMOS Frequency (System Clock 1) 256fs 12.288 MHz Frequency (System Clock 2) 384fs 18.432 MHz Duty Cycle (System Clock 1) 256fs 40 50 60 % Duty Cycle (System Clock 2) 384fs 45 50 55 % Data Clock Input 32 48 64 fs Logic Family Output CMOS Data Clock Output 64 fs Data Coding Two's Complement Data Bit Length 16 20 Bits Data Format Selectable Output Data Delay fs = 48kHz 1.5 ms POWER SUPPLY REQUIREMENTS Supply Voltage CC PCM1760 ±4.75 ±5.0 ±5.25 V ±Vdd PCM1760 ±4.75 ±5.0 ±5.25 V +VDD DF1760 4.75 5.0 5.25 V Supply Current +ICC PCM1760 24 36 mA –ICC PCM1760 –30 –45 mA +Idd PCM1760 12 18 mA –IDD PCM1760 –8 –12 mA +IDD –1 DF1760, Normal Mode 40 55 mA +IDD –2 DF1760, Power-Down Mode 4 6.6 mA Power Consumption PCM1760 370 500 mW DF1760, Normal Mode 200 275 mW DF1760, Power-Down Mode 20 33 mW TEMPERATURE RANGE Operating PCM1760/DF1760 0 +25 +70 °C Storage PCM1760/DF1760 –50 +125 °C NOTES: (1) Integrator Constants are determined by the external components shown in the block diagram. (2) FSR means Full Scale Range, digital output code is from 90000H to 70000H, FSR = 5.0V. (3) Use 20-bit DAC, 20kHz LPF, 400Hz HPF, average response. (4) Average response using a 20-bit reconstruction DAC with 20kHz low-pass filter and 400Hz high-pass filter.
3 PCM1760P/U DF1760P/U
MODEL PACKAGE THD +N (fs) SNR PCM1760P PDIP –90dB 108dB PCM1760U SOIC –90dB 108dB PCM1760P-L PDIP –88dB 106dB PCM1760U-L SOIC –88dB 106dB DF1760P PDIP NA NA DF1760U SOIC NA NA DD +0.5V VSS –0.5V Input Current ±20mA CC GND –0.3V ABSOLUTE MAXIMUM RATINGS—PCM1760 ABSOLUTE MAXIMUM RATINGS—DF1760 The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ORDERING INFORMATION PACKAGE INFORMATION PACKAGE DRAWING MODEL PACKAGE NUMBER (1) PCM1760P 28-Pin PDIP 800 PCM1760U 28-Pin SOIC 804 PCM1760P-L 28-Pin PDIP 800 PCM1760U-L 28-Pin SOIC 804 DF1760P 28-Pin PDIP 801 DF1760U 28-Pin SOIC 805 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. PIN ASSIGNMENTS PCM1760 PIN I/O (1) NAME DESCRIPTION
1 O Out-2R Right Channel Second Integrator Output
2 I In-2R Right Channel Second Integrator Input
3 O Out-1R Right Channel First Integrator Output
4 I In-1R Right Channel First Integrator Input
5 – SERVO DC Servo Amp Decoupling Capacitor 6–+ V CC +5V Analog Supply Voltage 7 – AGND Analog Common 8– – V CC –5V Analog Supply Voltage 9 – BGDC Band Gap Reference Decoupling Capacitor 10 – NC No Connection
11 I In-1L Left Channel First Integrator Input
12 O Out-1L Left Channel First Integrator Output
13 I In-2L Left Channel Second Integrator Input
14 O Out-2L Left Channel Second Integrator Output
15 – NC No Connection 16 – BPODC-L Left Channel Bipolar Offset Decoupling Capacitor
17 O L/RCK LR Clock Output (64fs)
18 O Strobe Data Strobe Output (128fs)
19 I 256fs 256fs Clock Input
20 – –V DD –5V Digital Supply Voltage 21 – DGND Digital Common 22 – +V DD +5V Digital Supply Voltage
23 O D 0 D 0 Data Output (LSB)
24 O D 1 D 1 Data Output
25 O D 2 D 2 Data Output
26 O D 3 D 3 Data Output (MSB)
27 – BPODC-R Right Channel Bipolar Offset Decoupling Capacitor 28 – NC No Connection Top View SOIC/DIP PCM1760 Out-2R In-2R Out-1R In-1R SERVO DC CC AGND –VCC BGDC NC In-1L Out-1L In-2L Out-2L NC BPODC-R D D 2 D 1 D 0 +VDD DGND DD 256fs Strobe L/RCK BPODC-L NC NOTE: (1) O = Output terminal; I = Input terminal.
D D 2 D 1 D 0 TP1 VSS1 VDD1 256fs Strobe LRCK CALD CAL V SS2 VDD2 TP2 CLKSEL S/M Mode 1 Mode 2 /PD LRSC FSYNC SDATA L/R SCLK SYSCLK PIN ASSIGNMENTS DF1760 NOTE: (1) O = Output terminal; I = Input terminal. PIN I/O (1) NAME DESCRIPTION
1 O OVL Left Channel Overflow Output (Active High)
2 O OVR Right Channel Overflow Output (Active High)
3 D3 Data Input (MSB)
6I D 0 D0 Data Input (LSB) 7 – TP1 Test Pin (No Connection) 8– V SS1 Common Channel 1 9– V DD1 +5V Channel 1
10 O 256fs 256fs Clock Output
11 I Strobe Data Strobe Clock Input (128fs)
12 I LRCK LR Clock Input
13 I ↑ CALD Calibration Function Enable (Active Low)
14 O CAL Calibration Output (High During Calibration)
15 I SYSCLK System Clock Input (256fs or 384fs)
16 I ↑ /O SCLK Data Clock
17 I ↑ /O L/R LR Channel Phase Clock
18 O SDATA Serial Data Output (1fs)
19 I ↑ /O FSYNC Frame Clock (2fs)
20 I ↑ LRSC Phase Control of LR Channel Phase Clock
21 I ↑ /PD Power Down Mode Enable Input (Active Low)
22 I ↑ Mode2 Output Format Selection Input 2
23 I ↑ Mode1 Output Format Selection Input 1
24 I ↑ S/M Slave/Master Mode Selection Input (High Makes
25 I ↑ CLKSEL System Clock Selection Input (High Makes 256fs)
26 – TP2 Test Pin (No Connection) 27 – V DD2 +5V Channel 2 28 – V SS2 Common Channel 2 Boost Filter Input LAT Decimation Filter Input RAM Multiplier ALU Calib- ration Output Control P/S Coefficient Overflow DET Main Timing Control Temporary RAM Test SYSCLK CLKSEL /PD TP1 TP2 VSS2 VDD2 VSS1 VDD1 256fs OVL OVR S/M MODE 1 MODE 2 LRSC FSYNC L/R SCLK SDATA (16-, 20-Bit) CALD CAL D D 2 D 1 D 0 Strobe LRCK
5 PCM1760P/U DF1760P/U
+VCC C 2R R T1R R IN2R C 1R R IN1R C 4R R Z1R R T2R C 3R C 2L R T1L R IN2L C 1L C 4L R T2L C 3L R IN1L R Z1L 3 2 1 28 27 11 12 13 14 15 16 NC In-1L In-2LOut-1L Out-2L NC BPODC-L In-1R In-2R Out-2R BPODC-R 1R 2R 1L 2L RCH S/H LCH S/HS/HINL LCH BPO RCH BPO S/HINR RCH DAC RCH ADC LCH DAC LCH ADCIOUT L IOUT L IOUT R IOUT R Band Gap Bias Servo Amp 21 DGND +VDD D 0 D 1 D 2 D 3 –VDD 256fs Strobe L/R CK +5V –5V D e c o d e r T i m i n g C T L AGND –VCC +5V –5V Sub SERVO DC BGDC NC External Components Condition R IN 1R/L 2.2kΩ C 1, C2 R/L 2200pF R TIR/L 470Ω R IN 2R/L 1.3kΩ C 3, C4 R/L 1800pF R T2 R/L 560Ω R Z1 R/L 1.2kΩ RCH, VIN Out-1R LCH, VIN
TYPICAL PERFORMANCE CURVES OVERALL PASS-BAND CHARACTERISTICS OF THE DF1760 –1.0 0 fs ÷ 2fs ÷ 4 1.0 0.5 –0.5 (dB) OVERALL CHARACTERISTICS OF THE DF1760 (fs) –150 06 4 16 32 46 –50 –100 (dB) PASS-BAND CHARACTERISTICS OF THE FIR PORTION OF THE DF1760 –0.0010 0 fs ÷ 2 fs ÷ 4 0.0010 0.0005 –0.0005(dB) TOTAL PASS-BAND FREQUENCY RESPONSE, COMBINATION OF PCM1760 AND DF1760 –0.3 0.3 0.2 0.1 –0.1 –0.2 Amplitude (dB) Frequency (kHz) 0.1 1 10 100 TYPICAL FFT ANALYSIS OF THE 1kHz fs INPUT SIGNAL –200 02 4 –20 –40 –60 –80 –100 –120 –140 –160 –180 Amplitude (dB) 61 2 1 8 Frequency (kHz) fs = 48.000000kHz F C1 = 1.171876kHz
7 PCM1760P/U DF1760P/U
BASIC CONNECTION DIAGRAM OF PCM1760 AND DF1760 R IN 2.2kΩ 3.3µF PCM1760 Out-2R In-2R Out-1R In-1R Servo DC CC BPO DCR D D 2 D 1 D 0 +VDD –VCC BG DC In-1L Out-1L In-2L Out-2L DD 256fs STB L/R CLK BPO DCL 21DGND AGND7 DF1760 D 3 D 2 D 1 D 0 VSS1 V SS2 VDD2 CLKSEL S/M Mode 1 Mode 2 V DD1 256fs STB LRCK FSYNC SDATA L/R SCLK SYSCLK Digital I/O 3.3µF+ 0.1µF0.1µF 3.3µF 0.1µF 3.3µF –5V VDD +5V VDD +5V VDD 10µF 0.1µF + 3.3µF +5V VDD 0.1µF +5V VDD SYS CLK 0.1µF 3.3µF 0.1µF 3.3µF 10µF 10µF +5V VCC –5V VCC R IN 2.2kΩ 2200pF 2200pF 1.3kΩ 470Ω 560Ω 1800pF 1800pF 1.2kΩ LCH In RCH In 560Ω 1800pF 1.2kΩ 2200pF 1.3kΩ 470Ω 10µF 1800pF 2200pF 10kΩ 47µF +5V VDD Power on Reset PD
The DF1760 can accept a system clock of either 256fs or 384fs. If a 384fs system clock is used, the DF1760 divides by 2/3 to create the 256fs system clock required for the PCM1760. The system clock is applied to pin 15 (SYSCLK input). The actual clock selection is done by setting pin 25 (CLKSEL input) “high” for 256fs clock and “LOW” for 384fs clock. The detailed timing requirements for the system clock are shown in Figure 3c. CLKSEL SYSCLK H 256fs L 384fs MASTER/SLAVE MODE The DF1760 can be used in both the master mode and slave mode. In the master mode, the DF1760 outputs L/R (left/ right channel phase clock), SCLK (data clock) and FSYNC (frame clock 2fs) signals. In the slave mode, the DF1760 accepts L/R, SCLK and FSYNC signals. The mode selection is done by taking pin 24 (S/M INPUT) “HIGH” for slave mode and “LOW” for master mode. S/M MODE H Slave L Master OUTPUT DATA FORMAT The serial output data has four possible formats. The selec- tion of the formats can be done by the Mode 1 and Mode 2 inputs. CALD CALIBRATION H Disable L Enable MODE 1 MODE 2 FORMATS H H MSB First, 16 Bits, Falling Edge L H MSB First, 20 Bits, Falling Edge H L MSB First, 20 Bits, Rising Edge L L LSB First, 20 Bits, Falling Edge LRSC L/R CLOCK AND CHANNEL H H = LCH, L = RCH L L = LCH, H = RCH OVERFLOW DETECTION When a near-to-clipping input condition is detected, OVL output (Pin 1), or OVR output (Pin 2), becomes “HIGH” for a duration of 4096/fs (about 85ms) depending upon on the channel detected. The OVL and OVR output return to “LOW” after 4096/fs duration automatically. OFFSET CALIBRATION MODE The offset error is calibrated by storing the digital data when the input is zero in registers and subtracting it from the future data with actual signal input. To enable the calibration mode, set the CALD input (Pin 13) “LOW”. The calibration mode is disabled by setting the CALD input (Pin 13) “HIGH”. The calibration cycle is initiated by setting the /PD input (Pin 21) “LOW” for more than 2 system clock periods and then setting it “HIGH”. During the calibration cycle, the CAL output (Pin 14) becomes “HIGH”, all the serial data is forced to “LOW”, and the L/R (Pin 17), SCLK (Pin 16) and FSYNC (Pin 19) pins become input terminals after the completion of the calibration cycle. The CAL output is “LOW”. POWER DOWN MODE/RESET The /PD input (Pin 21) has two functions. First, it should be set at “HIGH” after application or restoration of power (VSS and/or VDD ) to accomplish the power-on/mode reset func- tion. The detail timing requirements for this function are shown in Figure 3f. Second, the DF1760 is placed in the power down mode by setting the /PD input (Pin 21) “LOW”. Set the /PD input (Pin 21) “HIGH” for normal operation mode. LR CHANNEL PHASE CLOCK The status of the LR channel phase clock can be set by the LRSC input. /PD OPERATION H Normal L Power Down DESCRIPTION NAME MIN TYP MAX UNITS Delay from Overflow Detection to OVL (OVR) Output T OR ––0n s OVL (OVR) Output Pulse Width T OF – 4096 – 1/fs FIGURE 3a. DF1760 Overflow Detection. TOF TOR TOF TOR OVL (OVR) –Detect Level +Detect Level The power dissipation of the DF1760 in the power down mode is about 1/10 of the normal operation mode. During the power down mode, the L/R, SCLK, and FSYNC pins become input pins and all the serial data is forced “LOW”. The 256fs output is enabled even in the power down mode. The detailed timing of the power down mode operation and the offset calibration is shown in Figure 3b.
9 PCM1760P/U DF1760P/U
/PD TPSF TPDW TPCR DESCRIPTION NAME MIN TYP MAX UNITS Pulse Width of /PD Input T PDW 2 – – 1/Fclk Delay from /PD Input to CAL Output T PCR – – 6 1/Fclk Calibration Cycle Duration TPCF – 4096 – 1/fs Delay from /PD Input to SDATA LT PSF – – 6 1/Fclk Delay from Completion of Calibration to SDATA Valid TCSV – 1 – 1/fs FIGURE 3b. DF1760 Power Down and Offset Calibration. SYSTEM CLOCK: 256fs DESCRIPTION NAME MIN TYP MAX UNITS Low Level Duration T CLKL 31 – – ns High Level Duration T CLKH 31 – – ns TCLKH TCLKL 2.0V 1.4V 0.8V TLH THL DESCRIPTION NAME MIN TYP MAX UNITS SCLK Frequency F SLK 32fs 48fs 64fs – Low Duration of FSCLK T SLKL 100 – – ns High Duration of FSCLK T SLKH 100 – – ns Delay from SCLK to L/R Edge TSLR –70 – 70 ns Delay from Falling Edge of SCLK to SDATA Valid T DSS –– 5 0 n s Delay from SCLK to FSYNC Edge T SF –70 – 0 ns Delay from Rising Edge of SCLK to SDATA Valid T DSV 100 – – ns Delay from SDATA Valid to Rising Edge of SCLK T SDR 100 – – ns SCKL SDATA L/R FSYNC TSLR TSDR TSF TDSS TDSV TSLKH TSLKL FIGURE 3e. Timing of Slave Mode, DF1760. FIGURE 3f. Power On and Mode Reset Timing. APPLIES TO DESCRIPTION NAME MIN TYP MAX UNITS (1) MODE Power on to PD ↑ TPDW 2 1/fs Master/Slave PD ↑ to L/R ↑ TSP –1 +1 1/Fclk Slave (LRSC = “H”) PD ↑ to L/R ↓ TSP –1 +1 1/Fclk Slave (LRSC = “L”) NOTE: (1) fs: sampling rate. Fclk: system clock frequency. TPDW TPDW TSP TSP Power L/R PD <LRSC = “H” TPDW TPDW TSP TSP Power L/R PD <LRSC = “L” SYSTEM CLOCK: 384fs DESCRIPTION NAME MIN TYP MAX UNITS Low Level Duration T CLKL 24 – – ns High Level Duration T CLKH 24 – – ns Rise Time T LH –– 6 n s Fall Time T HL –– 6 n s FIGURE 3c. System Clock Timing Requirements of DF1760. TSDR TSF TDSS SCLK SDATA L/R FSYNC TSLR TDSV TDSS TDSV TSF DESCRIPTION NAME MIN TYP MAX UNITS SCLK Frequency F SLK – 64fs – SCLK Frequency Duty Cycle – 50 – % FSYNC Frequency F SYNC – 2fs – FSYNC Frequency Duty Cycle – 50 – % Delay from SCLK to L/R Edge TSLR –20 – 50 ns Delay from Falling Edge of SCLK to SDATA Valid T DSS –– 5 0 n s Delay from SCLK to FSYNC Edge T SF –20 – 50 ns Delay from Rising Edge of SCLK to SDATA Valid T SDR 100 – – ns Delay from SDATA Valid to Rising Edge of SCLK T DSV 100 – – ns FIGURE 3d. Output Timing of Master Mode, DF1760.
11 PCM1760P/U DF1760P/U
tone never occurs when the sampling frequency (fs) is 32kHz. greater than 0.05% of full scale range. value which are shown in Basic Connection Diagram. page five are recommended for optimized performance. mended for integration capacitors. The tolerance of external components should be better than ±2%. FIGURE 8. Application Example to Eliminate the Tone
- An optional analog switch is driven by a CAL output of
8000H (–Full Scale) to 7FFFFH (+Full Scale). FIGURE 9. Application Example to Eliminate the Tone (alternative modulator's integrator circuit. Only for fs = 48kHz).
70000H or under 82FFFH of digital output code. applied first followed by –VCC and –VDD . FIGURE 10. Illustration of Offset Calibration.
13 PCM1760P/U DF1760P/U
FIGURE 11. Master Mode Reset Circuit. FIGURE 12. Slave Mode Reset Circuit, (LRSC = H). FIGURE 13. Slave Mode Reset Circuit, (LRSC = L). NOTE: (1) External /PD input: Time "L" > 2/fs. NOTE: (1) External /PD input: Time "L" > 2/fs. NOTE: (1) External /PD input: Time "L" > 2/fs.
15 PCM1760P/U DF1760P/U
FIGURE 15c. Slave Mode and SCLK = 64fs. FIGURE 15d. Master Mode. L/R (0) SCLK (0)
- MSB First 20 Bit (1) FSYNC (0) SDATA (0)
- MSB First 20 Bit (2) FSYNC (0) SDATA (0)
- MSB First 16 Bit FSYNC (0) SDATA (0)
- LSB First 20 Bit FSYNC (0) SDATA (0) L/R (1) SCLK (1) FSYNC (1)
- MSB First 20-Bit (1) SDATA (0)
- MSB First 20-Bit (2) SDATA (0)
- MSB First 16-Bit SDATA (0)
- LSB First 20-Bit SDATA (0)