DF1750 BURR-BROWN | Alldatasheet
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Technical content
FEATURES
l USER SELECTABLE FOR 1/4 OR 1/2 DECIMATING RATIOS l USER SELECTABLE FOR 16- OR 18-BIT INPUT DATA l SERIAL DATA INPUT IS COMPATIBLE WITH THE BURR-BROWN PCM1750 ADC l FILTERS OUT-OF-BAND NOISE WITH STOPBAND ATTENUATION > 95dB l PASSBAND RIPPLE < 0.0005dB l SINGLE +5V SUPPLY OPERATION WITH LOW POWER DISSIPATION OF ONLY 250mW
DESCRIPTION
The DF1750 is a high performance 1/4 or 1/2 decimat- ing digital filter that is designed for digital audio appli- cations. This device decimates and filters 2x or 4x (2fs or 4fs) oversampled data from the output of an ADC to a data frequency of fs. The technique of oversampling and decimating allows the input to an oversampling ADC to be processed by a much lower order, linear phase, analog low-pass filter. This simultaneously im- proves system performance while reducing circuit com- plexity and cost. The DF1750 provides output data word rates (fs) up to 50.5kHz and it is compatible with the Burr-Brown PCM1750, dual 18-bit analog-to-digital converter. Input Interface CircuitSystem Clock Timing Control FIR Filter Circuit Output Interface Circuit XTI XTO CKEN CKO CC BBC IBO TEST SCSL2 IBCK DINRDINLSCSL1 LRCK WDCK BCK DOUT MUTE LRPOL OBPOL FSEN OW20 IMOD 2DS Dual Channel DIGITAL DECIMATION FILTER International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1990 Burr-Brown Corporation PDS-1092 Printed in U.S.A. October, 1993
PIN NO. PIN NO. DIP SOIC NAME I/O* DESCRIPTION DIP SOIC NAME I/O* DESCRIPTION 1 1 CKO o Clock output (the same as XTI 15 21 OW20 ip Output data bit select frequency), CKO = L when CKEN = H (16bit: OW20 = H, 20 bit: OW20 = L) – 2 (NC) – 22 (NC) 2 3 SCSL1 ip XTI Frequency select 16 23 FSEN ip I/O pin select (FSEN = H: BCK, WDCK, LRCK pin=Input (FSEN = L: BCK, WDCK, LRCK pin=Output) 3 4 SCSL2 ip (Refer to XTI pin description) 17 24 LRCK ip fs clock 4 5 TEST ip Test, (Test = L; test mode) 18 25 LRPOL ip LRCK polarity select (LRPOL = H: Lch/Rch=Low/High) (LRPOL = L: Lch/Rch=High/Low) – 6 (NC) – 26 (NC) 5 7 2DS ip 1/4 or 1/2 decimating select 2DS = H: 1/4 decimating, ip 2DS = L: 1/2 decimating 19 27 OBPOL ip BCK polarity select 6 8 IMOD ip A/D converter interface mode select 20 28 WDCK ip/o 2fs clock – 9 (NC) 21 29 V SS1 – GND 1 71 0V SS2 – GND 2 – 30 (NC) 8 11 DINR ip Rch input data – 31 (NC) – 12 (NC) 22 32 BCK ip/o Output data bit clock 9 13 CC o A/D converter control signal 23 33 DOUT o Data output (Lch or Rch serial data output). 10 14 BBC o A/D converter control signal – 34 (NC) – 15 (NC) 24 35 MUTE ip Data output mute, (MUTE = L: DOUT = L) 25 36 XTI i Oscillator Input (512fs: SCSL1 = H, SCSL2 = H) 11 16 IBCK ip Input data bit clock input (256fs: SCSL1 = H, SCSL2 = L) (768fs: SCSL1 = L, SCSL2 = H) (384fs: SCSL1 = L, SCSL2 = L) 12 17 IBO o Input data bit clock output 26 37 XTO o Oscillator Output 13 18 DINL ip Lch input data – 38 (NC) 14 19 V DD2 – +5V 27 39 CKEN ip CKO output select, (CKEN = H, CKO = L) – 20 (NC) 28 40 V DD1 – +5V *i = Input pin ip = Input with pull-up resistor o = Output pin ip/o = Input with pull-up resistor when FSEN = H, output with FSEN = L. PIN CONFIGURATION CKO NC SCSL1 SCSL2 TEST (NC) 2DS IMOD (NC) V DINR (NC) CC BBC (NC) IBCK IBO DINL V (NC) V CKEN (NC) XTO XTI MUTE (NC) DOUT BCK (NC) (NC) V WDCK OBPOL (NC) LRPOL LRCK FSEN (NC) OW20 DD1 DD2 SS2 SS1 Top View SOIC Top View DIP CKO SCSL1 SCSL2 TEST 2DS IMOD V DINR CC BBC IBCK IBO DINL V V CKEN XTO XTI MUTE DOUT BCK V WDCK OBPOL LRPOL LRCK FSEN OW20 SS2 DD1 SS1 DD2 PIN DESCRIPTION
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. Electrostatic discharge can cause damage ranging from per- formance degradation to complete device failure. Burr-Brown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. ABSOLUTE MAXIMUM RATINGS
PACKAGE INFORMATION
MODEL PACKAGE NUMBER (1) DF1750P 28-Pin Plastic DIP 215 DF1750U 40-Pin Plastic SOIC 252 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. DC SPECIFICATIONS ELECTRICAL VDD = 4.5V to 5.5V, VSS = 0V, TA = –20°C to +80°C unless otherwise specified. PARAMETER PIN SYMBOL CONDITION MIN TYP MAX UNIT INPUTS Logic Family CMOS Logic Voltages XTI V IL1 For Clock Input 0.3V DD V XTI V IH1 For Clock Input 0.7V DD V XTI V CLK For AC Coupling 1.8 V P-P (1),(2) VIL2 FSEN = H 0.5 V (1),(2) VIH2 FSEN = H 2.4 V Logic Currents XTI I IL1 VIN = 0V 5 10 µA XTI I IH1 VIN = VDD 51 0 µA (1),(2) IIL2 VIN = 0V, FSEN = H 10 20 µA Input Leakage Current (1),(2) ILH1 VIN = VDD , FSEN = H 1.0 µA OUTPUTS Logic Family CMOS Logic Voltages (2),(3) VOL IOL = 1.6mA, FSEN = L 0.4 V (2),(3) VOH IOH = –0.4mA, FSEN = L 2.5 POWER SUPPLY REQUIREMENTS Supply Voltage V DD1 , V DD2 +5 V Supply Current I DD VDD = 5V(4), FSEN = H 30 mA Power Dissipation P D Nominal VDD 250 mW TEMPERATURE RANGE (AMBIENT, T A ) Specification –20 +80 °C Operating –20 +80 °C DF1750P/U NOTES: (1) Refers to pins SCSL1, SCSL2, TEST, 2DS, IMOD, DINR, IBCK, DINL, OW20, MUTE, OBPOL, LRPOL, FSEN, CKEN. (2) Refers to pins BCK, WDCK, LRCK. (3) Refers to pins CKO, CC, BBC, IBO, DOUT. (4) Test Condition; SCSL1 = H, SCSL2 = H, TEST = H, 2DS = H, IMOD = H, OW20 = H, MUTE = H, OBPOL = H, LRPOL = H, FSEN = L, CKEN = L. TCY = 38ns (XTI Clock Period), CL= 0pF (Capacitive Load), DINL, DINR (Applicable Input Data). ELECTROSTATIC DISCHARGE SENSITIVITY
VDD = 4.5V to 5.5V, VSS = 0V, TA = –20°C to +80°C unless otherwise specified. XTI Clock CONDITION SYS DF1750P/U PARAMETER SYMBOL SCSL1 SCSL2 FREQ MIN TYP MAX UNIT Crystal Oscillator F OSC H H 512fs (1) 8 26 MHz Frequency H L 256fs 4 13 MHz L H 768fs 12 26 MHz L L 384fs 6 20 MHz H H 512fs 15 70 ns External Clock H L 256fs 38 140 ns Pulse Width t CW L H 768fs 15 50 ns L L 384fs 25 100 ns H H 512fs 38 125 ns External Clock H L 256fs 77 250 ns Pulse Period t CY L H 768fs 38 84 ns L L 384fs 50 167 ns VIH1 1/2VDD IL1V XTI t CW t CY t CW AC Coupling is required with an external clock. NOTE: (1) fs = Sampling frequency. ADC CONTROL SIGNAL TIMING (CC, BBC, AND IBO) WITH IMOD = H PARAMETER SYMBOL MIN TYP MAX UNIT 2DS = H CC Pulse Width (H) T1 65 1/256fs ns S/H Acquisition Time T2 670 9/256fs ns CC-BBC Time T3 285 4/256fs ns BBC Pulse Period T4 228 3/256fs ns BBC Pulse Width (H) T5 65 1/256fs ns BBC Pulse Width (L) T6 140 2/256fs ns BBC-IBO Time T7 140 2/256fs ns IBO Pulse Period T8 228 3/256fs ns IBO Pulse Width (H) T9 140 2/256fs ns IBO Pulse Width (L) T10 65 1/256fs ns 2DS = L CC Pulse Width (H) T1 130 1/256fs ns S/H Acquisition Time T2 1350 9/256fs ns CC-BBC Time T3 570 4/256fs ns BBC Pulse Period T4 456 3/256fs ns BBC Pulse Width (H) T5 130 1/256fs ns BBC Pulse Width (L) T6 280 2/256fs ns BBC-IBO Time T7 280 2/256fs ns IBO Pulse Period T8 456 3/256fs ns IBO Pulse Width (H) T9 280 2/256fs ns IBO Pulse Width (L) T10 130 1/256fs ns DF1750P/U 1.5V BBC 1.5V 1.5V CC IBO T2 T3 T5 T10
1.5V 1.5V 1.5V CC IBCK DINL DINR SLt SDt IBYt t HL IBWt IBWt HDt DF1750P/U PARAMETER SYMBOL MIN TYP MAX UNIT 2DS = H IBCK Pulse Width t IBW 50 1/256fs ns IBCK Pulse Period t IBY 3/12.928MHz(1) 3/256fs ns Data Word Latch t SL 50 ns Set-up Time Data Word Latch t HL 50 ns Hold Time DINL, DINR t SD 25 ns Set-up Time DINL, DINR t HD 25 ns Hold Time 2DS = L IBCK Pulse Width t IBW 50 1/128fs ns IBCK Pulse Period t IBY 3/12.928MHz(1) 3/128fs ns Data Word Latch t SL 50 ns Set-up Time Data Word Latch t HL 50 ns Hold Time DINL, DINR t SD 25 ns Set-up Time DINL, DINR t HD 25 ns Hold Time SERIAL INPUT TIMING (IBCK, DINL, DINR) WITH IMOD=H Normally, IBO output is connected to IBCK (Refer to the applications diagram). ADC CONTROL SIGNAL TIMING (CC, BBC, AND IBO) WITH IMOD = L DF1750P/U PARAMETER SYMBOL MIN TYP MAX UNIT 2DS = H CC Pulse Width (H) t CCW 1/8fs ns BBC Pulse Width t BBW 130 1/128fs ns BBC Pulse Period t BBY 1/64fs ns IBO Pulse Width t BOW 130 1/128fs ns IBO Pulse Period t BOY 1/64fs ns CC-BBC Time t CCBB -5 0 20 ns CC-IBO Time t CCBO 130 1/128fs ns BBC-IBO Time t BBBO 130 1/128fs ns 2DS = L CC Pulse Width (H) t CCW 1/4fs ns BBC Pulse Width t BBW 280 1/64fs ns BBC Pulse Period t BBY 1/32fs ns IBO Pulse Width t BOW 280 1/64fs ns IBO Pulse Period t BOY 1/32fs ns CC-BBC Time t CCBB –5 0 20 ns CC-IBO Time t CCBO 280 1/64fs ns BBC-IBOTime t BBBO 280 1/64fs ns 1.5V 1.5V 1.5VIBO CC BBC t BBW t BBW t BBY t CCW t CCW CCBBt BOWt BOYt t BBBO CCBOt BOWt NOTE: (1) 12.928MHz = 256 x 50.5kHz (max sampling frequency).
PARAMETER SYMBOL MIN TYP MAX UNIT REMARKS BCK Pulse Width t BCW 100 1/128fs ns BCK Pulse Period t BCY 1/3.232MHz(1) 1/64fs ns LRCK Pulse Width t LCW 1/2fs µs Duty = 50% LRCK Pulse Period t LCY 1/50.5kHz 1/fs µs LRCK Set-up Time t BL 50 ns LRCK Hold Time t LB 50 ns Output Data t H 0n s C L = 0pF Hold Time Output Data t D 100 ns C L = 15pF Delay Time SERIAL OUTPUT TIMING WITH FSEN = H NOTE: (1) 3.232MHz = 64 x 50.5kHz (max sampling frequency). 1.5V 1.5V 1.5V LRCK BCK DOUT (OBPOL = H) t LB t BL t BCW t BCW t , H t D t BCY DF1750P/U PARAMETER SYMBOL MIN TYP MAX UNIT 2DS = H IBCK Pulse Width t IBW 100 1/128fs ns IBCK Pulse Period t IBY 1/3.232MHz(1) 1/64fs ns Data Word Latch t SL 50 ns Set-up Time Data Word Latch t HL 50 ns Hold Time DINL, DINR t SD 25 ns Set-up Time DINL, DINR t HD 25 ns Hold Time 2DS = L IBCK Pulse Width t IBW 100 1/64fs ns IBCK Pulse Period t IBY 1/3.232MHz(1) 1/32fs ns Data Word Latch t SL 50 ns Set-up Time Data Word Latch t HL 50 ns Hold Time DINL, DINR t SD 25 ns Set-up Time DINL, DINR t HD 25 ns Hold Time SERIAL INPUT TIMING (IBCK, DINL, DINR) WITH IMOD = L Normally, IBO output is connected to IBCK. (Refer to the application diagram). 1.5V 1.5V 1.5V CC IBCK DINL DINR t HL SLt IBWt t IBY SDt HDt IBWt DF1750P/U PARAMETER SYMBOL MIN TYP MAX UNIT BCK Pulse Width t OBCW 140 1/128fs ns BCK Pulse Period t OBCY 1/64fs ns WDCK Pulse Width t WDCW 1/4fs µs WDCK Pulse Period t WDCY 1/2fs µs LRCK Pulse Width t LRCW 1/2fs µs LRCK Pulse Period t LRCY 1/fs µs Output Data t DHL –10 30 ns Delay Time t DLH –10 30 ns SERIAL OUTPUT TIMING WITH FSEN = L 1.5V 1.5V (OBPOL =H) LRCK WDCK DOUT BCK OBCWt OBCWt t DLHt DHL OBCYt NOTE: (1) 3.232MHz = 64 x 50.5kHz (max sampling frequency).
(x fs) 0.5 0.55 0.6 100 Attenuation (dB) 100 Attenuation (dB) —0.001 0.0005 —0.0005 0.001 (x fs) Attenuation (dB) 0.001 0.0005 —0.001 —0.0005Attenuation (dB) (x fs) 0 . 5 1234 100 Attenuation (dB) (x fs) 100 0.5 1 1.5 2 (x fs) Attenuation (dB) THEORETICAL FILTER CHARACTERISTICS 1/4 DECIMATING, INPUT DATA FREQUENCY = 4fs 1/2 DECIMATING, INPUT DATA FREQUENCY = 2fs PARAMETER CHARACTERISTICS Passband DC to 0.4583fs Stopband 0.5417fs and above Passband Ripple ±0.0002dB Stopband Attenuation 95dB min, 0.5417fs to 1.4583fs Group Delay Time Constant, Linear Phase PARAMETER CHARACTERISTICS Passband DC to 0.4583fs Stopband 0.5417fs and Above Passband Ripple ±0.0005 dB Stopband Attenuation 95dB min, 0.5417fs to 1.4583fs 88dB min, 1.4583fs to 2.5417fs 95dB min, 2.5417fs to 3.4583fs Group Delay Time Constant, Linear Phase DF1750 1/4 Decimating Filter Tranfer Characteristics. DF1750 1/2 Decimating Filter Transfer Characteristics. DF1750 1/2 Decimating Passband Frequency Response.DF1750 1/4 Decimating Passband Frequency Response. DF1750 1/4 Decimating Transitionband Frequency Response. DF1750 1/2 Decimating Transitionband Frequency Response.
pling is required for an external clock. when CKEN = L. CKO stays low when CKEN = H. data are loaded into the DF1750 simultaneously. FIGURE 3. Filter Arithmetic Structure algorithm. 2DS is used to select 1/4 or 1/2 decimating. finite impulse response (FIR) filters as shown in Figure 3. FIGURE 5. Input Data Latch/Loading Timing. FIGURE 4. SIPO Input Data Loading Timing.
1 WORD
applicable to the 18-bit input mode.
clock is available at pin LRCK. derived from the system clock. When FSEN = H, apply a 64fs clock to pin BCK. clock is available at pin BCK. (Regardless of LRCK’s I/O mode). (Regardless of BCK’s I/O mode). phase differences (between XTI and BCK, LRCK clocks). FIGURE 6. ADC Control Signals With IMOD = H. (Applicable for use with the Burr-Brown PCM1750 ADC). FIGURE 7. ADC Control Signals with IMOD = L.
2 LSB153
2 LSB 153
(SOUTL) (SOUTR) are outputs of the PCM1750.
FIGURE 8. Output Timing. with OW20 = L a 20-bit output is selected. at the end of the LRCK pulse as shown in Figure 8. MUTE pin. When MUTE = L, the output stays low (muted). Under normal operation MUTE = H. NOTE: Bit 1 is the most significant bit. NOTE: Bit 1 is the most significant bit.
1/2 decimating (2DS = L) IMOD = H 1/2 decimating (2DS = L) IMOD = L OUTPUT
APPLICATIONS
A typical circuit configuration for digital audio recording is shown in Figure 9. Each of the stereo input channels passes through a six pole Generalized Immittance Converter (GIC) low pass analog filter. This filter features extremely low distortion and negligible phase shift. The band limited signals are 4x oversampled by the dual-channel PCM1750 A/D converter. Clock and convert signals are provided to the PCM1750 by the DF1750. The 4fs oversampled data of the PCM1750 is filtered by the DF1750 to provide a data stream of fs. A PCM1750/DF1750 evaluation board, DEM1133, is available from Burr-Brown. This board incorporates the fea- tures mentioned above as well as an AES/EBU interface, test points for monitoring both the serial and parallel data outputs, and a breadboard area for user experimentation. DINL DINR BBC (32fs) IBCK (32fs) CC 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1/2fs NOTE: Bit 1 is the most significant bit. NOTE: Bit 1 is the most significant bit. 1 8 24 32 40 48 56 64 LSBRch MSB Rch LSB MSB Lch LSB LSBLchMSB LSB LSB 20 1 MSB LRCK (LRPOL = H) (LRPOL = L) WDCK BCK (64fs) (OBPOL = H) (OBPOL = L) DOUT (OW20 = L) (OW20 = H) CC BBC IBCK INTERNAL CLOCK (64fs) INVALID 12 13 14 INVALID 1/2fs DINL DINR 64 1 8 16 24 32 123 5 67 89 1110 15 16 17 184
FIGURE 9. Circuit diagram for a typical digital audio application using the DF1750 for decimating oversampled data from the output of the PCM1750 dual channel ADC. The OPA2604s are configured in a generalized immittance converter (GIC) filter arrangement to avoid aliasing in the PCM1750.