DF1706

DF1706 TI | Alldatasheet

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Stereo, 24-Bit, 192kHz 8x Oversampling Digital Interpolation Filter 49% FPO DF1706

DESCRIPTION

The DF1706 is a high performance, stereo, 8X oversampling digital interpolation filter designed for high-end consumer and professional audio applica- tions. The DF1706 supports 24-bit, 192kHz operation and features user-programmable functions, including

FEATURES

G COMPANION DIGITAL FILTER FOR THE PCM1704 24-BIT AUDIO DAC G HIGH PERFORMANCE FILTER: Stopband Attenuation: –115dB Passband Ripple: ±0.00005dB G AUDIO INTERFACE: Input Data Formats: Standard, Left- Justified, and I Input Word Length: 16, 20, or 24 Bits Output Word Length: 16, 18, 20, or 24 Bits Sampling Frequency: 32kHz to 192kHz Serial Input I/F Mode Control I/F 8X Oversampling Digital Filter with Function Controller Crystal/OSC XTI SCK XTO CLKO(SF0) (SF1) (SRO) V DD DGND Output I/F BCKO (I2S) (IW1) (IW0) (OW1) (OW0) WCKO DOL DOR MC/LRIP MD/CKO LRCIN DIN BCKIN MODE ML/RESV (MUTE) RST (DEM) Power Supply Copyright © 2001, Texas Instruments Incorporated SBAS182 Printed in U.S.A. January, 2001 www.ti.com DF1706 G SYSTEM CLOCK: 128f S, 192fS, 256fS, 384fS, 512fS, 768fS G ON-CHIP CRYSTAL OSCILLATOR G PROGRAMMABLE FUNCTIONS: Hardware or Software Control Modes Sharp or Slow Roll-Off Filter Response Soft Mute Digital De-Emphasis Independent Left/Right Digital Attenuation G +3.3V SINGLE-SUPPLY OPERATION G SMALL SSOP-28 PACKAGE selectable filter response, de-emphasis, attenuation, and input/output data formats. The DF1706 is the ideal companion for Texas Instruments’s PCM1704 24-bit audio Digital-to-Ana- log (D/A) converter. This combination allows for the construction of very high-performance audio systems and components.

All specifications at TA = +25°C, VDD = 3.3V, fS = 44.1kHz, system clock = 256fS/384fS, 16-bit data, unless otherwise noted. DF1706E PARAMETER CONDITIONS MIN TYP MAX UNITS RESOLUTION 24 Bits INPUT DATA FORMAT Audio Data Interface Format Standard, Left-Justified , I2S Audio Data Bit Length 16, 20, 24 Selectable Audio Data Format MSB First, Binary Two’s Complement Sampling Frequency f S 32 192 kHz System Clock Frequency(1) 128/192/256/384/512/768 f S OUTPUT DATA FORMAT Audio Data Interface Format Right-Justified Audio Data Bit Length 16, 20, 24 Selectable Audio Data Format MSB First, Binary Two’s Complement DIGITAL INPUT/OUTPUT CMOS Compatible Input Logic Level: V IH 0.7VDD V VIL 0.3VDD V Output Logic Level: VOH IOH = 2mA 2.4 V VOL IOL = 4mA 1.0 V CLKO AC CHARACTERISTICS (2) Rise Time t R 20% to 80% VDD , 20pF 4 ns Fall Time t F 80% to 20% VDD , 20pF 3 ns Duty Cycle(2) 20pF Load 50 % DIGITAL FILTER PERFORMANCE Filter Characteristics 1 (Sharp Roll-Off) Passband ±0.00005dB 0.454 f S –3dB 0.493 f S Stopband 0.546 f S Passband Ripple ±0.00005 dB Stopband Attenuation Stopband = 0.546f S –115 dB Filter Characteristics 2 (Slow Roll-Off) Passband Ripple ±0.0001dB 0.254 f S –3dB 0.460 f S Stopband 0.732 f S Passband Ripple ±0.0001 dB Stopband Attenuation Stopband = 0.748f S –100 dB Delay Time 45.125/fS sec De-Emphasis Error ±0.004 dB POWER-SUPPLY REQUIREMENTS Voltage Range V DD 3.0 3.3 3.6 VDC Supply Current I DD VDD = 3.3V 30 45 mA Power Dissipation V DD = 3.3V 99 149 mW TEMPERATURE RANGE Operation –25 +85 °C Storage –55 +125 °C Thermal Resistance, θJA SSOP-28 100 °C NOTES: (1) Refer to Table I. (2) Crystal resonator used.

1D IN IN Serial Audio Data Input(1)

2 BCKIN IN Bit Clock Input for Serial Audio Data (1)

3I 2S IN Input Audio Data Format Select (2, 4)

4 IW0 IN Input Audio Data Word Select (2, 4)

5 IW1 IN Input Audio Data Word Select (2, 4)

6 XTI IN Oscillator Input /External Clock Input

7 XTO OUT Oscillator Output

8 DGND — Digital Ground

9 CLKO OUT Buffered System Clock Output

10 MODE IN Mode Control Select (HIGH: Software Mode,

LOW: Hardware Mode)(3)

11 MD/CKO IN Mode Control, Data/Half External Clock Fre-

quency Select(3, 5)

12 MC/LRIP IN Mode Control, Clock/Polarity of LRCIN Select(3, 5)

13 ML/RESV IN Mode Control, Latch Clock/Reserve(3, 5)

14 RST IN Reset, Active LOW. When this pin is LOW the DF and modulators are held in reset.(3)

15 MUTE IN Mute Control, Active LOW (4)

16 DEM IN De-Emphasis Control (2, 4)

17 SF0 IN Sampling Rate Select for De-emphasis (2, 4)

18 SF1 IN Sampling Rate Select for De-emphasis (2, 4)

19 OW0 IN Output Audio Data Word Select (2, 4)

20 OW1 IN Output Audio Data Word Select (2, 4)

21 x4 IN Oversampling Ratio Control. When this pin is set HIGH, the ratio is 4 times. 22 V DD — Digital Power, +3.3V

23 DOR OUT R-Channel, Serial Audio Data Output

24 DOL OUT L-Channel, Serial Audio Data Output

25 WCKO OUT Word Clock Output for Serial Audio Data Output

26 BCKO OUT Bit Clock Output for Serial Audio Data Output

27 SRO IN Filter Response Select

(2, 4)

28 LRCIN IN L/R Clock Input (f S)(1)

NOTES: (1) Pins 1, 2, 28—Schmitt-Trigger input without pull-up and -down resistor. (2) Pins 3-5, 16-21, 27—Schmitt-Trigger input without pull-up and -down resistor. (3) Pins 10-15—Schmitt-Trigger input without pull-up and -down resistor. (4) Pins 3-5, 15-20, 27—these pins are invalid when MODE (pin 10) is HIGH. (5) Pins 11-13—these pins have different functions corre- sponding to MODE (pin 10) HIGH/LOW. PIN ASSIGNMENTSPIN CONFIGURATION ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS D IN BCKIN I2S IW0 IW1 XTI XTO DGND CLKO MODE MD/CKO MC/LRIP ML/RSV RST LRCIN SRO BCKO WCKO DOL DOR V DD OW1 OW0 SF1 SF0 DEM MUTE DF1706E PACKAGE SPECIFIED DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE NUMBER RANGE MARKING NUMBER (1) MEDIA DF1706E SSOP-28 324 –25°C to +85°C DF1706E DF1706E Rails "" " " " DF1706E/2K Tape and Reel NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces of “DF1706E/2K ” will get a single 2000-piece Tape and Reel. PACKAGE/ORDERING INFORMATION Top View SSOP

TYPICAL PERFORMANCE CURVES At TA = +25°C, VDD = ±3.3V, fS = 44.1kHz, System Clock = 256fS/384fS, 16-bit data, unless otherwise noted. DIGITAL FILTER (DE-EMPHASIS OFF, fS = 44.1kHz) DE-EMPHASIS AND DE-EMPHASIS ERROR 04 321 Frequency (fS) –20 –40 –60 –80 –100 –120 –140 –160 –180 –200 FREQUENCY RESPONSE (Sharp Roll-Off) Attenuation (dB) Frequency (fS) 0.00010 0.00008 0.00006 0.00004 0.00002 –0.00002 –0.00004 –0.00006 –0.00008 –0.00010 PASSBAND RIPPLE (Sharp Roll-Off) Attenuation (dB) 04 321 Frequency (fS) –20 –40 –60 –80 –100 –120 –140 –160 –180 –200 FREQUENCY RESPONSE (Slow Roll Off) Attenuation (dB) Frequency (fS) TRANSITION CHARACTERISTIC (Slow Roll Off) –10 –15 Attenuation (dB) 01 4 12108642 Frequency (kHz) –10 DE-EMPHASIS (fS = 32kHz) Level (dB) 01 4 1281 0642 Frequency (kHz) 0.010 0.008 0.006 0.004 0.002 –0.002 –0.004 –0.006 –0.008 –0.010 DE-EMPHASIS ERROR (f S = 32kHz) Error (dB)

TYPICAL PERFORMANCE CURVES (Cont.) At TA = +25°C, VDD = ±3.3V, fS = 44.1kHz, System Clock = 256fS/384fS, 16-bit data, unless otherwise noted. 02 0 181610 14128642 Frequency (kHz) –10 DE-EMPHASIS (fS = 44.1kHz) Level (dB) 02 0 181610 14128642 Frequency (kHz) DE-EMPHASIS ERROR (f S = 44.1kHz) 0.010 0.008 0.006 0.004 0.002 –0.002 –0.004 –0.006 –0.008 –0.010 Error (dB) 02 2 20181610 14128642 Frequency (kHz) –10 DE-EMPHASIS (fS = 48kHz) Level (dB) 02 2 20181610 14128642 Frequency (kHz) DE-EMPHASIS ERROR (f S = 48kHz) 0.010 0.008 0.006 0.004 0.002 –0.002 –0.004 –0.006 –0.008 –0.010 Error (dB)

input (pin 10). See Table II for MODE selection. (Cont.) FIGURE 6. Audio Output Data Format. NOTE: (1) Rising and falling time is measured from 10% to 90% of IN/OUT signal swing. (2) Load capacitance of all signals are 20pF. FIGURE 7. Audio Data Output Timing.

RSV 13 Reserved, Not Used LRIP 12 LRCIN Polarity LRIP = H: LRCIN= H = Left Channel, LRCIN= L = Right Channel LRIP = L: LRCIN= L = Left Channel, LRCIN = H = Right Channel CKO 11 CLKO Output Frequency CKO = H: CLKO Frequency = XTI/2 CKO = L: CLKO Frequency = XTI MUTE 15 Soft Mute Control: H = Mute Off, L = Mute On I 2S 3 Input Data Format Controls IW0 4 IW1 5 I 2S IW1 IW0 INPUT FORMAT L L L 16-Bit, Standard, MSB-First, Right-Justified L L H 20-Bit, Standard, MSB-First, Right-Justified L H L 24-Bit, Standard, MSB-First, Right-Justified L H H 24-Bit, MSB-First, Left-Justified H L L 16-Bit, I H L H 24-Bit, I 2S SRO 27 Digital Filter Roll-Off: H = Slow, L = Sharp OW0 19 Output Data Word Length Controls OW1 20 OW1 OW0 OUTPUT FORMAT L L 16-Bit, MSB-First L H 18-Bit, MSB-First H L 20-Bit, MSB-First H H 24-Bit, MSB-First SF0 17 Sample Rate Selection for the Digital De-Emphasis Control SF1 18 SF1 SF0 SAMPLING RATE L L 44.1kHz L H Reserved, Not Used H L 48kHz H H 32kHz DEM 16 Digital De-Emphasis: H = On, L = Off x4 21 Oversampling Rate Control: H = 4f S, L = 8fS TABLE IV. Hardware Mode Controls. RESET SOFTWARE HARDWARE DEFAULT FUNCTION (MODE = H) (MODE = L) (Software Mode) Input Data Format Selection O O Standard Format Input Word Length Selection O O 16 Bits Output Word Length Selection O O 16 Bits LRCIN Polarity Selection O O Left/Right = High/Low Digital De-Emphasis O O OFF Over Sample Ratio Control O O 8x Soft Mute O O OFF Digital Attenuation O X 0dB, Independent L/R Sample Rate for De-Emphasis Function O O 44.1 kHz Filter Roll-Off Selection O O Sharp Roll-Off Selected CLKO Output-Frequency Selection O O Same As XTI Input Legend: O = User Programmable, X = Not Available. TABLE III. User-Programmable Functions for Software and Hardware Mode. Programmable Functions The DF1706 includes a number of programmable features, with most being accessible from either Hardware or Soft- ware mode. Table III summarizes the user-programmable functions for both modes of operation. Hardware Mode Controls With MODE = L, the DF1706 may be configured by utilizing several user-programmable pins. The following is a brief summary of the pin functions. Table IV provides more details on setting the hardware mode controls. Pins I 2S, IW0, and IW1 are used to select the audio data input format and word length. Pins OW0 and OW1 are used to select the output data word length. The DEM pin is used to enable and disable the digital de- emphasis function. De-emphasis is only available for 32kHz, 44.1kHz, and 48kHz sample rates. Pins SF0 and SF1 are used to select the sample rate for the de-emphasis function. The SRO pin is used to select the digital filter response, either sharp or slow roll-off. Generally, sharp roll-off filter is used. The MUTE pin is used to enable or disable the soft mute function. The CKO pin is used to select the clock frequency seen at the CLKO pin, either XTI or XTI ÷ 2. The LRIP pin is used to select the polarity used for the audio input left/right clock, LRCIN. The x4 pin is used to control the over sampling ratio of the internal digital filter, either a 8x or 4x. For instance, when fs is 192kHz or 176.4kHz, the over sampling ratio should be 4x. Finally, the RESV pin is not used by the current DF1706 design, but is reserved for future use. Software Mode Controls With MODE = H, the DF1706 may be configured by programming four internal registers in software mode. ML (pin 13), MC (pin 12), and MD (pin 11) make up the 3-wire software control port, and may be controlled using DSP or microcontroller general purpose I/O pins, or a serial port. Table V provides an overview of the internal registers, labeled MODE0 through MODE3 (see Table V). See Figures 8 through 10 for more details regarding the control port data format and timing requirements. The data format for the control port is 16-bit, MSB-first, with Bit B15 being the MSB. Register Addressing A[1:0], bits B10 and B9 of the 16-bit control data word, are used to indicate the register address to be written to by the current control port write cycle. See Table VI for how to address the internal registers using bits A[1:0] of registers MODE0 through MODE3.

The MODE0 register is used to set the attenuation data for the left output channel, or DOL (pin 24). When ATC = 1 (Bit B2 of Register MODE3 = 1), the left channel attenuation data AL[7:0] is used for both the left and right channel attenuators. When ATC = 0, (Bit B2 of Register MODE3 = 0), left channel attenuation data is taken from AL[7:0] of register MODE0, and right channel attenuation data is taken from AR[7:0] of register MODE1. AL[7:0] Left Channel Attenuator Data, where AL7 is the MSB and AL0 is the LSB. Attenuation Level is given by: ATTEN = 0.5 • (DATA – 255)dB For DATA = FF H , ATTEN = –0dB For DATA = FE H , ATTEN = –0.5dB For DATA = 01 H , ATTEN = –127.5dB For DATA = 00 H , ATTEN = infinity = Mute LDL Left Channel Attenuation Data Load Control. This bit is used to simultaneously set attenua- tion levels of both the left and right channels. When LDL = 1, the left channel output level is set by the data in AL[7:0]. The right channel output level is set by the data in AL[7:0], or the most recently programmed data in bits AR[7:0] of register MODE1. When LDL = 0, the left channel output data remains at its previously programmed level. MODE1 Register The MODE1 register is used to set the attenuation data for the right output channel, or DOR (pin 23). When ATC = 1 (Bit B2 of Register MODE3 = 1), the left channel attenuation data AL[7:0] of register MODE0 is used for both the left and right channel attenuators. When ATC = 0, (Bit B2 of Register MODE3 = 0), left channel attenuation data is taken from AL[7:0] of register MODE0, and right channel attenuation data is taken from AR[7:0] of register MODE1. AR[7:0] Right Channel Attenuator Data, where AR7 is the MSB and AR0 is the LSB. Attenuation Level is given by: ATTEN = 0.5 • (DATA – 255)dB For DATA = FF H , ATTEN = –0dB For DATA = FE H , ATTEN = –0.5dB For DATA = 01 H , ATTEN = –127.5dB For DATA = 00 H , ATTEN = infinity = Mute LDR Right Channel Attenuation Data Load Control. This bit is used to simultaneously set attenua- tion levels of both the left and right channels. When LDR = 1, the right channel output level is set by the data in AR[7:0], or by the data in bits AL[7:0] of register MODE0. The left chan- nel output level is set to the most recently programmed data in bits AL[7:0] of register MODE0. When LDR = 0, the right channel output data remains at its previously programmed level. MODE2 Register The MODE2 register is used to program various functions: MUT Soft Mute Function. When MUT = 0, Soft Mute is ON for both left and right channels. When MUT = 1, Soft Mute is OFF for both left and right channels. DEM Digital De-Emphasis Function. When DEM = 0, de-emphasis is OFF. When DEM = 1, de-emphasis is ON. x4 Oversampling Rate Selection When x4 = 0, 8f S Sampling Rate Operation When x4 = 1, 4fS Sampling Rate Operation IW[1:0] Input Data Format and Word Length. I2S IW1 IW0 Description 0 0 0 16-Bit Data, Standard Format (MSB-First, Right-Justified) 0 0 1 20-Bit Data, Standard Format 0 1 0 24-Bit Data, Standard Format 0 1 1 24-Bit Data, MSB-First, Left-Justified 1 0 0 16-Bit Data, I 2S Format 1 0 1 24-Bit Data, I 2S format 1 1 0 Reserved 1 1 1 Reserved OW[1:0] Output Data Word Length. OW1 OW0 Description 0 0 16-Bit Data, MSB-First 0 1 18-Bit Data, MSB-First 1 0 20-Bit Data, MSB-First 1 1 24-Bit Data, MSB-First MODE3 Register The MODE3 register is used to program various functions. I 2S Input Data Format. When I2S = 0, standard or left-justified formats are enabled. When I2S = 1, the I2S formats are enabled. LRP LRCIN Polarity Selection. When LRP = 0, left channel is HIGH and right channel is LOW. When LRP = 1, left channel is LOW and right channel is HIGH.

FIGURE 11. PCB Layout Model.

FIGURE 14. DF1706 Typical Application Circuit.

ORDERABLE DEVICE STATUS(1) PACKAGE TYPE PACKAGE DRAWING PINS PACKAGE QTY DF1706E ACTIVE SSOP DB 28 47 DF1706E/2K ACTIVE SSOP DB 28 2000 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. PACKAGE OPTION ADDENDUM www.ti.com 3-Oct-2003

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