DF1704E

DF1704 TI | Alldatasheet

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Technical content

Stereo, 24-Bit, 96kHz 8X Oversampling Digital Interpolation Filter 49% FPO DF1704 TM

DESCRIPTION

The DF1704 is a high-performance, stereo, 8X oversampling digital interpolation filter designed for high-end consumer and professional audio applications. The DF1704 supports 24-bit, 96kHz operation and features user-programmable functions, including selectable filter response, de-emphasis, attenuation, and input/output data formats. The DF1704 is the ideal companion for Texas Instruments’ PCM1704 24-bit audio digital-to-analog converter. This combination allows for construction of very high-perfor- mance audio systems and components.

FEATURES

G COMPANION DIGITAL FILTER FOR THE PCM1704 24-BIT AUDIO DAC G HIGH PERFORMANCE FILTER: Stopband Attenuation: –115dB Passband Ripple: ±0.00005dB G AUDIO INTERFACE: Input Data Formats: Standard, Left- Justified, and I Input Word Length: 16, 20, or 24 Bits Output Word Length: 16, 18, 20, or 24 Bits Sampling Frequency: 32kHz to 96kHz G PROGRAMMABLE FUNCTIONS: Hardware or Software Control Modes Sharp or Slow Roll-Off Filter Response Soft Mute Digital De-Emphasis Independent Left/Right Digital Attenuation DF1704 Serial Input I/F Mode Control I/F 8X Oversampling Digital Filter with Function Controller Crystal/OSC XTI SCK XTO CLKO(SF0) (SF1) (SRO) V DD VSS Output I/F BCKO (I2S) (IW1) (IW0) (OW1) (OW0) WCKO DOL DOR MC/LRIP MD/CKO LRCIN DIN BCKIN MODE ML/RESV (MUTE) RST (DEM) Power Supply SBAS099A – MARCH 2001 www.ti.com PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1998, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. G SYSTEM CLOCK: 256f S, 384fS, 512fS, 768fS G ON-CHIP CRYSTAL OSCILLATOR G +5V SINGLE-SUPPLY OPERATION G SMALL SSOP-28 PACKAGE

1 DIN IN Serial Audio Data Input (3)

2 BCKIN IN Bit Clock Input for Serial Audio Data (3)

3I 2S IN Input Audio Data Format Selection (2, 4)

4 IW0 IN Input Audio Data Word Selection (2, 4)

5 IW1 IN Input Audio Data Word Selection (2, 4)

6 XTI IN Oscillator Input /External Clock Input

7 XTO OUT Oscillator Output

8V SS — Digital Ground

9 CLKO OUT Buffered System Clock Output

10 MODE IN Mode Control Selection (H: Software, L: Hardware) (1)

11 MD/CKO IN Control Data Input/Clock Output Frequency

Select(1, 5)

12 MC/LRIP IN Control Data Clock/Polarity of LRCK Select(1, 5)

13 ML/RESV IN Control Data Latch/Reserved(1, 5)

14 RST IN Reset. When this pin is LOW, the digital filter is held in reset.(1)

15 MUTE IN Mute Control (1, 4)

16 DEM IN De-Emphasis Control (2, 4)

17 SF0 IN Sampling Rate Select for De-emphasis (2, 4)

18 SF1 IN Sampling Rate Select for De-emphasis (2, 4)

19 OW0 IN Output Audio Data Word and Format Select (2, 4)

20 OW1 IN Output Audio Data Word and Format Select (2, 4)

21 NC — No Connection

22 V DD — Digital Power, +5V

23 DOR OUT Rch, Serial Audio Data Output

24 DOL OUT Lch, Serial Audio Data Output

25 WCKO OUT Word Clock for Serial Audio Data Output

26 BCKO OUT Bit Clock for Serial Audio Data Output

27 SRO IN Filter Response Select

(2, 4)

28 LRCIN IN L/R Clock Input (f S) for Serial Audio Data(3)

NOTES: (1) Pins 10-15; Schmitt-Trigger input with pull-up resistor. (2) Pins 3-5, 16-20, 27; Schmitt-Trigger input with pull-down resister. (3) Pins 1, 2, 28; Schmitt-Trigger input. (4) Pins 3-5, 15-20, 27; these pins are invalid when MODE (pin 10) is HIGH. (5) Pins 11-13; these pins have different functions corresponding to MODE (pin 10), (HIGH/LOW). PIN ASSIGNMENTSPIN CONFIGURATION ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instru- ments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS DIN BCKIN I2S IW0 IW1 XTI XTO V SS CLKO MODE MD/CKO MC/LRIP ML/RESV RST LRCIN SRO BCKO WCKO DOL DOR V DD NC OW1 OW0 SF1 SF0 DEM MUTE DF1704E NC: No Connection TOP VIEW SSOP PACKAGE SPECIFIED DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE NUMBER RANGE MARKING NUMBER MEDIA DF1704E SSOP-28 324 –25°C to +85°C DF1704E DF1704E Rails PACKAGE/ORDERING INFORMATION

ELECTRICAL CHARACTERISTICS

All specifications at +25°C, VDD = +5V, unless otherwise noted. DF1704E PARAMETER CONDITIONS MIN TYP MAX UNITS RESOLUTION 24 Bits INPUT DATA FORMAT Audio Data Interface Format Standard/Left-Justified /I2S Audio Data Bit Length 16/20/24 Selectable Audio Data Format MSB-First, Two’s Binary Comp Sampling Frequency (fS) 32 96 kHz System Clock Frequency 256/384/512/768fS OUTPUT DATA FORMAT Audio Data Interface Format Right-Justified Audio Data Bit Length 16/20/24 Selectable Audio Data Format MSB-First, Binary Two’s Complement DIGITAL INPUT/OUTPUT Input Logic Level: VIH 2.0 V VIL 0.8 V Output Logic Level: VOH IOH = 2mA 4.5 V VOL IOL = 4mA 0.5 V CLKO AC CHARACTERISTICS Rise Time (tR ) 20% to 80% V DD , 10pF 4 ns Fall Time (tF) 80% to 20% V DD , 10pF 3 ns Duty Cycle 10pF Load 37 % DIGITAL FILTER PERFORMANCE Filter Characteristics 1 (Sharp Roll-Off) Passband ±0.00005dB 0.454f S –3dB 0.493f S Stopband 0.546fS Passband Ripple ±0.00005 dB Stopband Attenuation Stopband = 0.546f S –115 dB Filter Characteristics 2 (Sharp Roll-Off) Passband Ripple ±0.0001dB 0.254f S –3dB 0.460f S Stopband 0.732fS Passband Ripple ±0.0001 dB Stopband Attenuation Stopband = 0.748f S –100 dB Delay Time 45.125/fS sec De-Emphasis Error ±0.003 dB POWER SUPPLY REQUIREMENTS Voltage Range V DD 4.5 5 5.5 VDC Supply Current: IDD 20 30 mA Power Dissipation 100 150 mW TEMPERATURE RANGE Operation –25 +85 °C Storage –55 +100 °C

TYPICAL CHARACTERISTICS OF INTERNAL FILTER DIGITAL FILTER (DE-EMPHASIS OFF, fS = 44.1kHz) DE-EMPHASIS AND DE-EMPHASIS ERROR 04 3.532.521.510.5 Frequency (fS) –20 –40 –60 –80 –100 –120 –140 –160 –180 –200 FREQUENCY RESPONSE (Sharp Roll Off) Attenuation (dB) Frequency (fS) 0.0001 0.00008 0.00006 0.00004 0.00002 –0.00002 –0.00004 –0.00006 –0.00008 –0.0001 PASSBAND RIPPLE (Sharp Roll Off) Attenuation (dB) 04 3.532.521.510.5 Frequency (fS) –20 –40 –60 –80 –100 –120 –140 –160 –180 –200 FREQUENCY RESPONSE (Slow Roll Off) Attenuation (dB) Frequency (fS) TRANSITION CHARACTERISTIC (Slow Roll Off) –10 –15 Attenuation (dB) 01 4 12108642 Frequency ( fS) –10 DE-EMPHASIS (fS = 32kHz) Level (dB) 01 4 1281 0642 Frequency (fS) 0.01 0.008 0.006 0.004 0.002 –0.002 –0.004 –0.006 –0.008 –0.01 DE-EMPHASIS ERROR (f S = 32kHz) Error (dB)

TYPICAL CHARACTERISTICS OF INTERNAL FILTER (Cont.) 02 0 181610 14128642 Frequency (fS) –10 DE-EMPHASIS (fS = 44.1kHz) Level (dB) 02 0 181610 14128642 Frequency (fS) DE-EMPHASIS ERROR (f S = 44.1kHz) 0.01 0.008 0.006 0.004 0.002 –0.002 –0.004 –0.006 –0.008 –0.01 Error (dB) 02 2 20181610 14128642 Frequency (fS) –10 DE-EMPHASIS (fS = 48kHz) Level (dB) 02 2 20181610 14128642 Frequency (fS) DE-EMPHASIS ERROR (f S = 48kHz) 0.01 0.008 0.006 0.004 0.002 –0.002 –0.004 –0.006 –0.008 –0.01 Error (dB)

latch audio data words into an audio DAC. FIGURE 6. Audio Output Data Format.

Legend: O = User Programmable, X = Not Available. functions for both modes of operation. details on setting the hardware mode controls. input format and word length. 44.1kHz, and 48kHz sample rates. either sharp or slow roll-off. the CLKO pin, either XTI or XTI ÷ 2. input left/right clock, LRCIN. design, but is reserved for future use. microcontroller general purpose I/O pins, or a serial port. labeled MODE0 through MODE3. FIGURE 7. Audio Output Data Format.

FIGURE 10. Software Interface Timing Requirements. NOTES: (1) ML rising edge to the next MC rising edge. (2) MC rising edge for LSB to ML rising edge. (3) SYSCK: System Clock Cycle. the Left output channel, or DOL (pin 24). and Right channel attenuators. LDL Left Channel Attenuation Data Load Control. tion levels of both the Left and Right channels. remains at its previously programmed level. the Right output channel, or DOR (pin 23). for both the Left and Right channel attenuators. LDR Right Channel Attenuation Data Load Control. levels of both the Left and Right channels. remains at its previously programmed level.

The MODE2 register is used to program various functions: MUT Soft Mute Function. When MUT = 0, Soft Mute is ON for both Left and Right channels. When MUT = 1, Soft Mute is OFF for both Left and Right channels. DEM Digital De-Emphasis Function. When DEM = 0, de-emphasis is OFF. When DEM = 1, de-emphasis is ON. IW[1:0] Input Data Format and Word Length. I 2S IW1 IW0 Description 0 0 0 16-Bit Data, Standard Format (MSB-First, Right-Justified) 0 0 1 20-Bit Data, Standard Format 0 1 0 24-Bit Data, Standard Format 0 1 1 24-Bit Data, MSB-First, Left-Justified 1 0 0 16-Bit Data, I 2S Format 1 0 1 24-Bit Data, I 2S format 1 1 0 Reserved 1 1 1 Reserved OW[1:0] Output Data Word Length. OW1 OW0 Description 0 0 16-Bit Data, MSB-First 0 1 18-Bit Data, MSB-First 1 0 20-Bit Data, MSB-First 1 1 24-Bit Data, MSB-First MODE3 Register The MODE3 register is used to program various functions. I 2S Input Data Format. When I2S = 0, standard or left-justified formats are enabled. When I2S = 1, the I2S formats are enabled. LRP LRCIN Polarity Selection. When LRP = 0, Left channel is HIGH and Right channel is LOW. When LRP = 1, Left channel is LOW and Right channel is HIGH. ATC Attenuator Control. This bit is used to determine whether the Left and Right channel attenuators operate with inde- pendent data, or use common data (the Left channel data in bits AL[7:0] of register MODE0). When ATC = 0, the Left and Right channel attenuator data is independent. When ATC = 1, the Left and Right channel attenuators use common data. SRO Digital Filter Roll-Off Selection. When SRO = 0, sharp roll-off is selected. When SRO = 1, slow roll-off is selected. CKO CLKO Output Frequency Selection. When CKO = 0, the CLKO frequency is the same as the clock at the XTI input. When CKO =1, the CLKO frequency is half of the XTI input clock frequency. SF[1:0] Sampling Frequency Selection for the De-Em- phasis Function. SF1 SF0 Description 0 0 44.1 kHz 0 1 Reserved 1 0 48 kHz 1 1 32 kHz

FIGURE 11. PCB Layout Model.

FIGURE 14. DF1704 Typical Application Circuit.

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DF1704E NRND Production SSOP (DB) | 28 47 | TUBE Yes NIPDAU Level-1-260C-UNLIM - DF1704E DF1704E.B NRND Production SSOP (DB) | 28 47 | TUBE Yes NIPDAU Level-1-260C-UNLIM See DF1704E DF1704E (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) DF1704E DB SSOP 28 47 500 10.6 500 9.6 DF1704E.B DB SSOP 28 47 500 10.6 500 9.6 Pack Materials-Page 1

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