DF1704E

DF1704 BURR-BROWN | Alldatasheet

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Technical content

Stereo, 24-Bit, 96kHz 8X Oversampling Digital Interpolation Filter DIGITAL-TO-ANALOG CONVERTER 49% FPO DF1704 TM

DESCRIPTION

The DF1704 is a high performance, stereo, 8X oversampling digital interpolation filter designed for high-end consumer and professional audio applica- tions. The DF1704 supports 24-bit, 96kHz operation and features user-programmable functions, including selectable filter response, de-emphasis, attenuation, and input/output data formats. The DF1704 is the ideal companion for Burr-Brown’s PCM1704 24-bit audio digital-to-analog converter. This combination allows for construction of very high performance audio systems and components.

FEATURES

l COMPANION DIGITAL FILTER FOR THE PCM1704 24-BIT AUDIO DAC l HIGH PERFORMANCE FILTER: Stopband Attenuation: –115dB Passband Ripple: –0.00005dB l AUDIO INTERFACE: Input Data Formats: Standard, Left- Justified, and I Input Word Length: 16, 20, or 24 Bits Output Word Length: 16, 18, 20, or 24 Bits Sampling Frequency: 32kHz to 96kHz l SYSTEM CLOCK: 256f S, 384fS, 512fS, 768fS l ON-CHIP CRYSTAL OSCILLATOR l PROGRAMMABLE FUNCTIONS: Hardware or Software Control Modes Sharp or Slow Roll-Off Filter Response Soft Mute Digital De-Emphasis Independent Left/Right Digital Attenuation l +5V SINGLE-SUPPLY OPERATION l SMALL 28-LEAD SSOP PACKAGE © 1998 Burr-Brown Corporation PDS-1458B Printed in U.S.A. December, 1998 DF1704 Serial Input I/F Mode Control I/F 8X Oversampling Digital Filter with Function Controller Crystal/OSC XTI SCK XTO CLKO(SF0) (SF1) (SRO) V DD VSS Output I/F BCKO (I2S) (IW1) (IW0) (OW1) (OW0) WCKO DOL DOR MC/LRIP MD/CKO LRCIN DIN BCKIN MODE ML/RESV (MUTE) RST (DEM) Power Supply International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132

All specifications at +25°C, VDD = +5V, unless otherwise noted. DF1704E PARAMETER CONDITIONS MIN TYP MAX UNITS RESOLUTION 24 Bits INPUT DATA FORMAT Audio Data Interface Format Standard/Left-Justified /I2S Audio Data Bit Length 16/20/24 Selectable Audio Data Format MSB-First, Two’s Binary Comp Sampling Frequency (fS) 32 96 kHz System Clock Frequency 256/384/512/768fS OUTPUT DATA FORMAT Audio Data Interface Format Right-Justified Audio Data Bit Length 16/20/24 Selectable Audio Data Format MSB-First, Binary Two’s Complement DIGITAL INPUT/OUTPUT Input Logic Level: VIH 2.0 V VIL 0.8 V Output Logic Level: VOH IOH = 2mA 4.5 V VOL IOL = 4mA 0.5 V CLKO AC CHARACTERISTICS Rise Time (tR ) 20% to 80% V DD , 10pF 4 ns Fall Time (tF) 80% to 20% V DD , 10pF 3 ns Duty Cycle 10pF Load 37 % DIGITAL FILTER PERFORMANCE Filter Characteristics 1 (Sharp Roll-Off) Passband –0.00005dB 0.454f S –3dB 0.493f S Stopband 0.546fS Passband Ripple –0.00005 dB Stopband Attenuation Stopband = 0.546f S –115 dB Filter Characteristics 2 (Sharp Roll-Off) Passband Ripple –0.0001dB 0.254f S –3dB 0.460f S Stopband 0.732fS Passband Ripple –0.0001 dB Stopband Attenuation Stopband = 0.748f S –100 dB Delay Time 45.125/fS sec De-Emphasis Error –0.003 dB POWER SUPPLY REQUIREMENTS Voltage Range V DD 4.5 5 5.5 VDC Supply Current: IDD 20 30 mA Power Dissipation 100 150 mW TEMPERATURE RANGE Operation –25 +85 °C Storage –55 +100 °C

3 DF1704

1 DIN IN Serial Audio Data Input (3)

2 BCKIN IN Bit Clock Input for Serial Audio Data (3)

3I 2S IN Input Audio Data Format Selection (2, 4)

4 IW0 IN Input Audio Data Word Selection (2, 4)

5 IW1 IN Input Audio Data Word Selection (2, 4)

6 XTI IN Oscillator Input /External Clock Input

7 XTO OUT Oscillator Output

SS — Digital Ground

9 CLKO OUT Buffered System Clock Output

10 MODE IN Mode Control Selection (H: Software, L: Hardware) (1)

11 MD/CKO IN Control Data Input/Clock Output Frequency

Select(1, 5)

12 MC/LRIP IN Control Data Clock/Polarity of LRCK Select(1, 5)

13 ML/RESV IN Control Data Latch/Reserved(1, 5)

14 RST IN Reset. When this pin is LOW, the digital filter is held in reset.(1)

15 MUTE IN Mute Control (1, 4)

16 DEM IN De-Emphasis Control (2, 4)

17 SF0 IN Sampling Rate Select for De-emphasis (2, 4)

18 SF1 IN Sampling Rate Select for De-emphasis (2, 4)

19 OW0 IN Output Audio Data Word and Format Select (2, 4)

20 OW1 IN Output Audio Data Word and Format Select (2, 4)

21 NC — No Connection

22 V DD — Digital Power, +5V

23 DOR OUT Rch, Serial Audio Data Output

24 DOL OUT Lch, Serial Audio Data Output

25 WCKO OUT Word Clock for Serial Audio Data Output

26 BCKO OUT Bit Clock for Serial Audio Data Output

27 SRO IN Filter Response Select

(2, 4)

28 LRCIN IN L/R Clock Input (f S) for Serial Audio Data(3)

NOTES: (1) Pins 10-15; Schmitt-Trigger input with pull-up resistor. (2) Pins 3-5, 16-20, 27; Schmitt-Trigger input with pull-down resister. (3) Pins 1, 2, 28; Schmitt-Trigger input. (4) Pins 3-5, 15-20, 27; these pins are invalid when MODE (pin 10) is HIGH. (5) Pins 11-13; these pins have different functions corresponding to MODE (pin 10), (HIGH/LOW). PIN ASSIGNMENTSPIN CONFIGURATION PACKAGE DRAWING PRODUCT PACKAGE NUMBER (1) DF1704E 28-Lead SSOP 324 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book.

PACKAGE INFORMATION

This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ABSOLUTE MAXIMUM RATINGS DIN BCKIN I2S IW0 IW1 XTI XTO V SS CLKO MODE MD/CKO MC/LRIP ML/RESV RST LRCIN SRO BCKO WCKO DOL DOR V DD NC OW1 OW0 SF1 SF0 DEM MUTE DF1704E NC: No Connection

TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER DIGITAL FILTER (DE-EMPHASIS OFF, fS = 44.1kHz) DE-EMPHASIS AND DE-EMPHASIS ERROR 04 3.532.521.510.5 Frequency (fS) –20 –40 –60 –80 –100 –120 –140 –160 –180 –200 FREQUENCY RESPONSE (Sharp Roll Off) Attenuation (dB) Frequency (fS) 0.0001 0.00008 0.00006 0.00004 0.00002 –0.00002 –0.00004 –0.00006 –0.00008 –0.0001 PASSBAND RIPPLE (Sharp Roll Off) Attenuation (dB) 04 3.532.521.510.5 Frequency (fS) –20 –40 –60 –80 –100 –120 –140 –160 –180 –200 FREQUENCY RESPONSE (Slow Roll Off) Attenuation (dB) Frequency (fS) TRANSITION CHARACTERISTIC (Slow Roll Off) –10 –15 Attenuation (dB) 01 4 12108642 Frequency ( fS) –10 DE-EMPHASIS (f S = 32kHz) Level (dB) 01 4 1281 0642 Frequency (fS) 0.01 0.008 0.006 0.004 0.002 –0.002 –0.004 –0.006 –0.008 –0.01 DE-EMPHASIS ERROR (f S = 32kHz) Error (dB)

5 DF1704

TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER 02 0 181610 14128642 Frequency (fS) –10 DE-EMPHASIS (f S = 44.1kHz) Level (dB) 02 0 181610 14128642 Frequency (fS) DE-EMPHASIS ERROR (f S = 44.1kHz) 0.01 0.008 0.006 0.004 0.002 –0.002 –0.004 –0.006 –0.008 –0.01 Error (dB) 02 2 20181610 14128642 Frequency (fS) –10 DE-EMPHASIS (f S = 48kHz) Level (dB) 02 2 20181610 14128642 Frequency (fS) DE-EMPHASIS ERROR (f S = 48kHz) 0.01 0.008 0.006 0.004 0.002 –0.002 –0.004 –0.006 –0.008 –0.01 Error (dB)

7 DF1704

FIGURE 5. Audio Input Interface Timing. FIGURE 4. Audio Data Input Formats.

FIGURE 6. Audio Output Data Format.

9 DF1704

Legend: O = User Programmable, X = Not Available. functions for both modes of operation. details on setting the hardware mode controls. input format and word length. 44.1kHz, and 48kHz sample rates. either sharp or slow roll-off. CLKO pin, either XTI or XTI ‚ 2. input left/right clock, LRCIN. design, but is reserved for future use. microcontroller general purpose I/O pins, or a serial port. labeled MODE0 through MODE3. FIGURE 7. Audio Output Data Format.

11 DF1704

FIGURE 10. Software Interface Timing Requirements. NOTES: (1) ML rising edge to the next MC rising edge. (2) MC rising edge for LSB to ML rising edge. (3) SYSCK: System Clock Cycle. the Left output channel, or DOL (pin 24). and Right channel attenuators. LDL Left Channel Attenuation Data Load Control. tion levels of both the Left and Right channels. remains at its previously programmed level. the Right output channel, or DOR (pin 23). for both the Left and Right channel attenuators. LDR Right Channel Attenuation Data Load Control. levels of both the Left and Right channels. remains at its previously programmed level.

The MODE2 register is used to program various functions: MUT Soft Mute Function. When MUT = 0, Soft Mute is ON for both Left and Right channels. When MUT = 1, Soft Mute is OFF for both Left and Right channels. DEM Digital De-Emphasis Function. When DEM = 0, de-emphasis is OFF. When DEM = 1, de-emphasis is ON. IW[1:0] Input Data Format and Word Length. I 2S IW1 IW0 Description 0 0 0 16-Bit Data, Standard Format (MSB-First, Right-Justified) 0 0 1 20-Bit Data, Standard Format 0 1 0 24-Bit Data, Standard Format 0 1 1 24-Bit Data, MSB-First, Left-Justified 1 0 0 16-Bit Data, I 2S Format 1 0 1 24-Bit Data, I 2S format 1 1 0 Reserved 1 1 1 Reserved OW[1:0] Output Data Word Length. OW1 OW0 Description 0 0 16-Bit Data, MSB-First 0 1 18-Bit Data, MSB-First 1 0 20-Bit Data, MSB-First 1 1 24-Bit Data, MSB-First MODE3 Register The MODE3 register is used to program various functions. I 2S Input Data Format. When I2S = 0, standard or left-justified formats are enabled. When I2S = 1, the I2S formats are enabled. LRP LRCIN Polarity Selection. When LRP = 0, Left channel is HIGH and Right channel is LOW. When LRP = 1, Left channel is LOW and Right channel is HIGH. ATC Attenuator Control. This bit is used to determine whether the Left and Right channel attenuators operate with inde- pendent data, or use common data (the Left channel data in bits AL[7:0] of register MODE0). When ATC = 0, the Left and Right channel attenuator data is independent. When ATC = 1, the Left and Right channel attenuators use common data. SRO Digital Filter Roll-Off Selection. When SRO = 0, sharp roll-off is selected. When SRO = 1, slow roll-off is selected. CKO CLKO Output Frequency Selection. When CKO = 0, the CLKO frequency is the same as the clock at the XTI input. When CKO =1, the CLKO frequency is half of the XTI input clock frequency. SF[1:0] Sampling Frequency Selection for the De-Em- phasis Function. SF1 SF0 Description 0 0 44.1 kHz 0 1 Reserved 1 0 48 kHz 1 1 32 kHz APPLICATIONS INFORMATION PCB LAYOUT GUIDELINES In order to obtain the specified performance from the DF1704 and its associated D/A converters, proper printed circuit board layout is essential. Figure 11 shows two approaches for obtaining the best audio performance. Figure 11(a) shows a standard, mixed signal layout scheme. The board is divided into digital and analog sections, each with its own ground. The ground areas should be put on a split-plane, separate from the routing and power layers. The DF1704 and all digital circuitry should be placed over the digital section, while the audio DACs and analog circuitry should be located over the analog section of the board. A common connection between the digital and analog grounds is required and is done at a single point as shown. For Figure 11(a), digital signals should be routed from the DF1704 to the audio DACs using short, direct connections to reduce the amount of radiated high-frequency energy. If necessary, series resistors may be placed in the clock and data signal paths to reduce or eliminate any overshoot or undershoot present on these signals. A value of 50W to 100W is recommended as a starting point, but the designer should experiment with the resistor values in order to obtain the best results.

13 DF1704

Figure 11(b) shows an improved method for high perfor- mance, mixed signal board layout. This method adds digital isolation between the DF1704 and the audio DACs, and provides complete isolation between the digital and analog sections of the board. The Burr-Brown ISO150 dual digital coupler provides excellent isolation, and operates at speeds up to 80Mbps. POWER SUPPLIES AND BYPASSING The DF1704 requires a single +5V power supply for opera- tion. The power supply should be bypassed by a 10mF and 0.1mF parallel capacitor combination. The capacitors should be placed as close as possible to V DD (pin 22). Aluminum electrolytics or tantalum capacitors can be used for the 10mF value, while ceramics may be used for the 0.1mF value. BASIC CIRCUIT CONNECTIONS Figures 12 and 13 show basic circuit connections for the DF1704. Figure 12 shows connections for Hardware mode controls, while Figure 13 shows connections for Software mode controls. Notice the placement of C 1 and C2 in both figures, as they are physically close to the DF1704. TYPICAL APPLICATIONS The DF1704 will typically be used in high performance audio equipment, in conjunction with high performance audio D/A converters. Figure 14 shows a typical application circuit example, employing the DF1704, a digital audio receiver, and two PCM1704 24-bit, 96kHz audio DACs.

FIGURE 11. PCB Layout Model.

15 DF1704

FIGURE 12. Basic Circuit Connections, Hardware Control. FIGURE 13. Basic Circuit Connection, Software Control. DD or DGND (hardwired, switch, jumper) or actively driven by logic.

FIGURE 14. DF1704 Typical Application Circuit.