DEVICE

CS5171_06 ONSEMI | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 21

Technical content

Features

• Integrated Power Switch: 1.5 A Guaranteed
• Wide Input Range: 2.7 V to 30 V
• High Frequency Allows for Small Components
• Minimum External Components
• Easy External Synchronization
• Built in Overcurrent Protection
• Frequency Foldback Reduces Component Stress During an Overcurrent Condition
• Thermal Shutdown with Hysteresis
• Regulates Either Positive or Negative Output V oltages
• Shut Down Current: 50 /C0109A Maximum
• Pin−to−Pin Compatible with LT1372/1373
• Wide Temperature Range ♦ Industrial Grade: −40°C to 125°C ♦ Commercial Grade: 0°C to 125°C
• Pb−Free Packages are Available 517xy = Device Code x= 1, 2, 3, or 4 y= E, G A = Assembly Location L = Wafer Lot Y = Year W = Work Week /C0071 = Pb−Free Package

ORDERING INFORMATION

SOIC−8 D SUFFIX CASE 751 VCCSS 517xy ALYW /C0071 AGNDTest PGNDFB VSWVC MARKING DIAGRAM AND PIN CONNECTIONS VCCSS 517xy ALYW /C0071 AGNDNFB PGNDTest VSWVC http://onsemi.com See detailed ordering and shipping information in the package dimensions section on page 20 of this data sheet.

8 VOUT

Figure 1. Applications Diagram

1. 60 second maximum above 183 °C.

CS5171, CS5172, CS5173, CS5174 http://onsemi.com ELECTRICAL CHARACTERISTICS (2.7 V< VCC < 30 V; Industrial Grade: −40°C < TJ < 125°C; Commercial Grade: 0°C < TJ < 125°C; For all CS5171/2/3/4 specifications unless otherwise stated.) Characteristic Test Conditions Min Typ Max Unit Positive and Negative Error Amplifiers FB Reference Voltage (CS5171/3 only) VC tied to FB; measure at FB 1.246 1.276 1.300 V NFB Reference Voltage (CS5172/4 only) VC = 1.25 V −2.55 −2.45 −2.35 V FB Input Current (CS5171/3 only) FB = VREF −1.0 0.1 1.0 /C0109A NFB Input Current (CS5172/4 only) NFB = NVREF −16 −10 −5.0 /C0109A FB Reference Voltage Line Regulation (CS5171/3 only) NFB Reference Voltage Line Regulation (CS5172/4 only) Positive Error Amp Transconductance IVC = ± 25 /C0109A 300 550 800 /C0109Mho Negative Error Amp Transconductance IVC = ± 5 /C0109A 115 160 225 /C0109Mho Positive Error Amp Gain (Note 2) 200 500 − V/V Negative Error Amp Gain (Note 2) 100 180 320 V/V VC Source Current FB = 1.0 V or NFB = −1.9 V, VC = 1.25 V 25 50 90 /C0109A VC Sink Current FB = 1.5 V or NFB = −3.1 V, VC = 1.25 V 200 625 1500 /C0109A VC High Clamp Voltage FB = 1.0 V or NFB = −1.9 V; VC sources 25 /C0109A 1.5 1.7 1.9 V VC Threshold Reduce VC from 1.5 V until switching stops 0.75 1.05 1.30 V Oscillator Base Operating Frequency CS5171/2, FB = 1 V or NFB = −1.9 V 230 280 310 kHz Reduced Operating Frequency CS5171/2, FB = 0 V or NFB = 0 V 30 52 120 kHz Maximum Duty Cycle CS5171/2 90 94 − % Base Operating Frequency CS5173/4, FB = 1 V or NFB = −1.9 V 460 560 620 kHz Reduced Operating Frequency CS5173/4, FB = 0 V or NFB = 0 V 60 104 160 kHz Maximum Duty Cycle CS5173/4 82 90 − % NFB Frequency Shift Threshold Frequency drops to reduced operating frequency −0.80 −0.65 −0.50 V FB Frequency Shift Threshold Frequency drops to reduced operating frequency 0.36 0.40 0.44 V Sync/ Shutdown Sync Range CS5171/2 320 − 500 kHz Sync Range CS5173/4 640 − 1000 kHz Sync Pulse Transition Threshold Rise time = 20 ns 2.5 − − V SS Bias Current SS = 0 V SS = 3.0 V −15 −3.0 3.0 8.0 /C0109A /C0109A Shutdown Threshold − 0.50 0.85 1.20 V Shutdown Delay 2.7 V ≤ VCC ≤ 12 V

12 V < VCC ≤ 30 V

/C0109s /C0109s 2. Guaranteed by design, not 100% tested in production.

CS5171, CS5172, CS5173, CS5174 http://onsemi.com ELECTRICAL CHARACTERISTICS (2.7 V< VCC < 30 V; Industrial Grade: −40°C < TJ < 125°C; Commercial Grade: 0°C < TJ < 125°C; For all CS5171/2/3/4 specifications unless otherwise stated.) Characteristic UnitMaxTypMinTest Conditions Power Switch Switch Saturation Voltage ISWITCH = 1.5 A, (Note 3) ISWITCH = 1.0 A, 0°C ≤ TJ ≤ 85°C ISWITCH = 1.0 A, −40°C ≤ TJ ≤ 0°C ISWITCH = 10 mA 0.8 0.55 0.75 0.09 1.4 0.45 V V V V Switch Current Limit 50% duty cycle, (Note 3) 80% duty cycle, (Note 3) 1.6 1.5 1.9 1.7 2.4 2.2 A A Minimum Pulse Width FB = 0 V or NFB = 0 V, ISW = 4.0 A, (Note 3) 200 250 300 ns /C0068ICC/ /C0068IVSW 2.7 V ≤ VCC ≤ 12 V, 10 mA ≤ ISW ≤ 1.0 A 12 V < VCC ≤ 30 V, 10 mA ≤ ISW ≤ 1.0 A 2.7 V ≤ VCC ≤ 12 V, 10 mA ≤ ISW ≤ 1.5 A, (Note 3) 12 V < VCC ≤ 30 V, 10 mA ≤ ISW ≤ 1.5 A, (Note 3) 100 100 mA/A mA/A mA/A mA/A Switch Leakage VSW = 40 V, VCC = 0V − 2.0 100 /C0109A General Operating Current ISW = 0 − 5.5 8.0 mA Shutdown Mode Current VC < 0.8 V, SS = 0 V, 2.7 V ≤ VCC ≤ 12 V VC < 0.8 V, SS = 0 V, 12 V ≤ VCC ≤ 30 V 100 /C0109A Minimum Operation Input Voltage VSW switching, maximum ISW = 10 mA − 2.45 2.70 V Thermal Shutdown (Note 3) 150 180 210 °C Thermal Hysteresis (Note 3) − 25 − °C 3. Guaranteed by design, not 100% tested in production. PACKAGE PIN DESCRIPTION Package Pin # Pin Symbol Function 1 VC Loop compensation pin. The VC pin is the output of the error amplifier and is used for loop compensation, current limit and soft start. Loop compensation can be implemented by a simple RC network as shown in the application diagram on page 2 as R1 and C1. (CS5171/3 only) FB Positive regulator feedback pin. This pin senses a positive output voltage and is referenced to 1.276 V. When the voltage at this pin falls below 0.4 V, chip switching frequency reduces to 20% of the nominal frequency. (CS5172/4) CS5171/3) Test These pins are connected to internal test logic and should either be left floating or tied to ground. Connection to a voltage between 2 V and 6 V shuts down the internal oscillator and leaves the power switch running. (CS5172/4) NFB Negative feedback pin. This pin senses a negative output voltage and is referenced to −2.5 V. When the voltage at this pin goes above −0.65 V, chip switching frequency reduces to 20% of the nominal frequency. 4 SS Synchronization and shutdown pin. This pin may be used to synchronize the part to nearly twice the base frequency. A TTL low will shut the part down and put it into low current mode. If synchronization is not used, this pin should be either tied high or left floating for normal operation. 5 VCC Input power supply pin. This pin supplies power to the part and should have a bypass capacitor connected to AGND. 6 AGND Analog ground. This pin provides a clean ground for the controller circuitry and should not be in the path of large currents. The output voltage sensing resistors should be connected to this ground pin. This pin is connected to the IC substrate. 7 PGND Power ground. This pin is the ground connection for the emitter of the power switching transistor. Connection to a good ground plane is essential. 8 VSW High current switch pin. This pin connects internally to the collector of the power switch. The open voltage across the power switch can be as high as 40 V. To minimize radiation, use a trace as short as practical.

0.4 V Detector

Figure 2. Block Diagram

Figure 27. Current Mode Control Scheme gain−bandwidth over a comparable voltage mode circuit. sacrificing the advantages of current mode control. Figure 28. Timing Diagram of Sync and Shutdown turned off by the output of the PWM Comparator. supplies to operate at the same frequency. and reduce the supply current. external components and the IC itself. for the slope compensation to improve regulator stability. Figure 29. Error Amplifier Equivalent Circuit

2.0 V200 k

reduced from its nominal value.

AV = 5 V/V , the gain of the current sense amplifier.

1.5 A is to clamp the V

equation above, the desired clamp voltage will result. C voltage to a diode drop above the voltage on resistor R3. acceptable if VIN is loosely regulated. Figure 37. Current Limiting using a Diode Clamp sense resistor. Such a circuit is illustrated in Figure 38. Figure 38. Current Limiting using a Current Sense

form a low−pass filter to remove noise. switching regulators with a continuous inductor current. high−frequency audible noise. on−time, typically in the amount of 180 mA//C0109s. Figure 39. Technique for Increasing Slope circuitry to limit the bandwidth of the error amplifier. AV = 5 V/V , the gain of the current sense amplifier. inductor current from rising at a high slope.

activate any time the SS pin is used to restart the converter. Figure 40. Soft Start typically 1.05 V (refer to graphs for detail over temperature). but simple task. First, the power losses must be quantified.

• biasing of internal control circuitry, PBIAS
• switch driver, PDRIVER
• switch saturation, PSAT The internal control circuitry, including the oscillator and linear regulator, requires a small amount of power even when the switch is turned off. The specifications section of this datasheet reveals that the typical operating current, IQ, due to this circuitry is 5.5 mA. Additional guidance can be found in the graph of operating current vs. temperature. This graph shows that IQ is strongly dependent on input voltage, V IN, and temperature. Then PBIAS /C0043VINIQ Since the onboard switch is an NPN transistor, the base drive current must be factored in as well. This current is drawn from the V IN pin, in addition to the control circuitry current. The base drive current is listed in the specifications as /C0068ICC//C0068ISW, or switch transconductance. As before, the designer will find additional guidance in the graphs. With that information, the designer can calculate PDRIVER /C0043VINISW /C0032ICC /C0068ISW /C0032D where: ISW = the current through the switch; D = the duty cycle or percentage of switch on−time. I SW and D are dependent on the type of converter. In a boost converter, ISW(AVG) /C0094ILOAD /C0032D /C00321 Efficiency D /C0094VOUT /C0042VIN VOUT In a flyback converter, ISW(AVG) /C0094VOUTILOAD VIN /C00321 Efficiency D /C0094VOUT VOUT /C0041 NS NP VIN The switch saturation voltage, V(CE)SAT, is the last major source of on−chip power loss. V (CE)SAT is the collector−emitter voltage of the internal NPN transistor when it is driven into saturation by its base drive current. The value for V (CE)SAT can be obtained from the specifications or from the graphs, as “Switch Saturation V oltage.” Thus, PSAT /C0094V(CE)SATISW /C0032D Finally, the total on−chip power losses are PD /C0043PBIAS/C0041PDRIVER/C0041PSAT Power dissipation in a semiconductor device results in the generation of heat in the junctions at the surface of the chip. This heat is transferred to the surface of the IC package, but a thermal gradient exists due to the resistive properties of the package molding compound. The magnitude of the thermal gradient is expressed in manufacturers’ data sheets as /C0113 JA, or junction−to−ambient thermal resistance. The on−chip junction temperature can be calculated if /C0113JA, the air temperature near the surface of the IC, and the on−chip power dissipation are known.

/C0113JA = junction−to−ambient thermal resistance (°C/W). whether the CS517x can be used in an application is settled. possible means of reducing the junction temperature. guidelines should be followed in the layout.

1. In boost circuits, high AC current circulates within the
2. Separate the low current signal grounds from the

plane construction for the best results.

1. Locate th e voltage feedback resistors as near the IC as

possible to keep the sensitive feedback wiring short. Figure 41. Additional Application Diagram, 5.0 V to −12 V/ 75 mA Inverting Converter

3.3 VIN

Figure 42. Additional Application Diagram, 3.3 V Input, 5.0 V/ 400 mA Output Boost Converter Figure 43. Additional Application Diagram, 2.7 to 13 V Input, /C004312 V/ 200 mA Output Flyback Converter Figure 44. Additional Application Diagram, −9.0 V to −28 V Input, −5.0 V/700 mA Output Inverted Buck Converter

Figure 45. Additional Application Diagram, 2.7 V to 28 V Input, 5.0 V Output SEPIC Converter Figure 46. Additional Application Diagram, 4.0 V Input, 100 V/ 10 mA Output Boost Converter with

50 V 50 V 50 V

Figure 47. Additional Application Diagram, 5.0 V Input, ± 12 V Output Dual Boost Converter

CS5171, CS5172, CS5173, CS5174 http://onsemi.com Temperature Range Package Shipping† CS5171ED8 −40°C < TJ < 125°C SOIC−8 98 Units/Rail CS5171ED8G SOIC−8 (Pb−Free)

98 Units/Rail

CS5171EDR8 SOIC−8 2500 Tape & Reel CS5171EDR8G SOIC−8 (Pb−Free)

2500 Tape & Reel

CS5172ED8 SOIC−8 98 Units/Rail CS5172ED8G SOIC−8 (Pb−Free) CS5172EDR8 SOIC−8 2500 Tape & Reel CS5172EDR8G SOIC−8 (Pb−Free) CS5173ED8 SOIC−8 98 Units/Rail CS5173ED8G SOIC−8 (Pb−Free) CS5173EDR8 SOIC−8 2500 Tape & Reel CS5173EDR8G SOIC−8 (Pb−Free) CS5174ED8 SOIC−8 98 Units/Rail CS5174ED8G SOIC−8 (Pb−Free) CS5174EDR8 SOIC−8 2500 Tape & Reel CS5174EDR8G SOIC−8 (Pb−Free) 0°C < TJ < 125°C SOIC−8 98 Units/Rail CS5171GD8G SOIC−8 (Pb−Free) CS5171GDR8 SOIC−8 2500 Tape & Reel CS5171GDR8G SOIC−8 (Pb−Free) CS5172GD8 SOIC−8 98 Units/Rail CS5172GD8G SOIC−8 (Pb−Free) CS5172GDR8 SOIC−8 2500 Tape & Reel CS5172GDR8G SOIC−8 (Pb−Free) CS5173GD8 SOIC−8 98 Units/Rail CS5173GD8G SOIC−8 (Pb−Free) CS5173GDR8 SOIC−8 2500 Tape & Reel CS5173GDR8G SOIC−8 (Pb−Free) CS5174GD8 SOIC−8 98 Units/Rail CS5174GD8G SOIC−8 (Pb−Free) CS5174GDR8 SOIC−8 2500 Tape & Reel CS5174GDR8G SOIC−8 (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.

CS5171, CS5172, CS5173, CS5174 http://onsemi.com PACKAGE DIMENSIONS SOIC−8 D SUFFIX CASE 751−07 ISSUE AH SEATING PLANE N J X 45/C0095 K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A B S DH C 0.10 (0.004) DIM A MIN MAX MIN MAX INCHES 4.80 5.00 0.189 0.197 MILLIMETERS B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.053 0.069 D 0.33 0.51 0.013 0.020 G 1.27 BSC 0.050 BSC H 0.10 0.25 0.004 0.010 J 0.19 0.25 0.007 0.010 K 0.40 1.27 0.016 0.050 M 0 8 0 8 N 0.25 0.50 0.010 0.020 S 5.80 6.20 0.228 0.244 −X− −Y− G MYM0.25 (0.010) −Z− YM0.25 (0.010) Z S X S M /C0095/C0095/C0095/C0095 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 /C0466mm inches/C0467SCALE 6:1 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SOLDERING FOOTPRINT* ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. CS5171/D PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative