DEM-VSP2262Y

VSP2262 BURR-BROWN | Alldatasheet

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Technical content

FEATURES

G CCD SIGNAL PROCESSING: Correlated Double Sampling (CDS) Programmable Black Level Clamping G PROGRAMMABLE GAIN AMPLIFIER (PGA): –6dB to +42dB Gain Ranging G 12-BIT DIGITAL DATA OUTPUT: Up to 20MHz Conversion Rate No Missing Codes G 79dB SIGNAL-TO-NOISE RATIO G PORTABLE OPERATION: Low Voltage: 2.7V to 3.6V Low Power: 83mW (typ) at 3.0V Stand-By Mode: 6mW VSP2262 Copyright © 2000, Texas Instruments Incorporated SBMS011 Printed in U.S.A. November, 2000 CCD SIGNAL PROCESSOR for DIGITAL CAMERAS

DESCRIPTION

The VSP2262 is a complete mixed-signal processing IC for digital cameras, providing signal conditioning and Analog-to-Digital (A/D) conversion for the output of a CCD array. The primary CCD channel provides Correlated Double Sampling (CDS) to extract video information from the pixels, –6dB to +42dB gain range with digital control for varying illumination conditions, and black level clamping for an accurate black level reference. Input signal clamping and offset correction of the input CDS are also performed. The stable gain control is linear in dB. Additionally, the black level is quickly recovered after gain change. The VSP2262Y is available in an LQFP-48 package and operates from a single +3V/+3.3V supply. www.ti.com Programmable Gain Amplifier (PGA) Input Clamp Reference Voltage GeneratorPreblanking Timing Control Serial Interface Output Latch Correlated Double Sampling (CDS) Analog- to- Digital Converter 12-Bit Digital Output –6dB to +42dB CCDIN CCD Output Signal PBLK Optical Black (OB) Level Clamping COB CLPOB SHPCLPDM SHD SLOAD SCLK SDATA VCCRESET DRV DDADCCK BYPP2 BYP BYPM REFN CM REFP DRVGND GNDA B[11:0] VSP2262

At TA = +25°C, VCC = +3.0V, DRVDD = +3.0V, Conversion Rate (fADCCK ) = 20MHz, unless otherwise noted. VSP2262Y PARAMETER CONDITIONS MIN TYP MAX UNITS RESOLUTION 12 Bits CONVERSION RATE 20 MHz DIGITAL INPUT Logic Family TTL Input Voltage LOW to HIGH Threshold Voltage (VT+) 1.7 V HIGH to LOW Threshold Voltage (VT–) 1.0 V Input Current Logic HIGH (I IH) VIN = +3V ±20 µA Logic LOW (IIL) VIN = 0V ±20 µA DIGITAL OUTPUT Logic Family CMOS Logic Coding Straight Binary Output Voltage Logic HIGH (V OH ) IOH = –2mA 2.4 V Logic LOW (VOL ) IOL = 2mA 0.4 V ADCCK Clock Duty Cycle 50 % Input Capacitance 5p F Maximum Input Voltage –0.3 5.3 V ANALOG INPUT (CCDIN) Input Signal Level for Full-Scale Out PGA Gain = 0dB 900 mV Input Capitance 15 pF Input Limit –0.3 3.3 V TRANSFER CHARACTERISTICS Differential Non-Linearity (DNL) PGA Gain = 0dB ±0.5 LSB Integral Non-Linearity (INL) PGA Gain = 0dB ±1 LSB No Missing Codes Guaranteed Step Response Settling Time Full-Scale Step Input 1 Pixel Overload Recovery Time Step Input from 1.8V to 0V 2 Pixels Data Latency 9 (Fixed) Clock Cycles Signal-to-Noise Ratio (1) Grounded Input Cap, PGA Gain = 0dB 79 dB Grounded Input Cap, Gain = +24dB 55 dB CCD Offset Correction Range –180 200 mV CDS Reference Sample Settling Time Within 1LSB, Driver Impedance = 50Ω 11 ns Data Sample Settling Time Within 1LSB, Driver Impedance = 50 Ω 11 ns INPUT CLAMP Clamp-On Resistance 400 Ω Clamp Level 1.5 V PROGRAMMABLE GAIN AMP (PGA) Gain-Control Resolution 10 Bits Maximum Gain Gain Code = 1111111111 42 dB High Gain Gain Code = 1101001000 34 dB Medium Gain Gain Code = 1000100000 20 dB Low Gain Gain Code = 0010000000 0 dB Minimum Gain Gain Code = 0000000000 –6d B Gain Control Error ±0.5 dB OPTICAL BLACK CLAMP LOOP Control DAC Resolution 10 Bits Optical Black Clamp Level Programmable Range of Clamp Level 2 60 LSB OBCLP Level at CODE = 1000 130 LSB Min Output Current for Control DAC COB Pin ±0.15 µA Max Output Current for Control DAC COB Pin ±153 µA Loop Time Constant C COB = 0.1µF µs Slew Rate C COB = 0.1µF, Output Current from Control DAC is Saturated 1530 V/s REFERENCE Positive Reference Voltage 1.75 V Negative Reference Voltage 1.25 V POWER SUPPLY Supply Voltage V CC , DRVDD 2.7 3.0 3.6 V Power Dissipation Normal Operation Mode: No Load, DAC0 and DAC1 are Suspended 86 mW Stand-By Mode: fADCCK = Not Apply 6 mW TEMPERATURE RANGE Operating Temperature –25 +85 °C Thermal Resistance θJA LQFP-48 100 °C/W NOTE: (1) SNR = 20 log(full-scale voltage/rms noise).

DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE NUMBER RANGE MARKING NUMBER (1) MEDIA VSP2262Y LQFP-48 340 0 to +85 °C VSP2262Y VSP2262Y 250-Piece Tray "" " " " VSP2262Y/2K Tape and Reel PACKAGE/ORDERING INFORMATION ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degrada- tion to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS (1) PRODUCT ORDERING NUMBER VSP2262Y DEM-VSP2262Y DEMO BOARD ORDERING INFORMATION NOTE: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces of “VSP2262Y/2K ” will get a single 2000 piece Tape and Reel.

24 V CC P Analog Power Supply

25 GNDA P Analog Ground

26 GNDA P Analog Ground

28 COB AO Optical Black Clamp Loop Reference (2)

29 BYPP2 AO Internal Reference P (3)

30 CCDIN AI CCD Signal Input

31 BYP AO Internal Reference C

(4)

32 BYPM AO Internal Reference N (3)

33 V CC P Analog Power Supply

34 V CC P Analog Power Supply

35 GNDA P Analog Ground

36 GNDA P Analog Ground

37 CM AO A/D Converter Common-Mode Voltage (4)

38 REFP AO A/D Converter Positive Reference (4)

39 REFN AO A/D Converter Negative Reference (4)

40 V CC P Analog Power Supply

41 GNDA P Analog Ground

42 GNDA P Analog Ground

43 NC – Should be Left OPEN

44 NC – Should be Left OPEN

45 RESET DI Asynchronous System Reset (Active LOW)

46 SLOAD DI Serial Data Latch Signal (Triggered at the Rising Edge)

47 SDATA DI Serial Data Input

48 SCLK DI Clock for Serial Data Shift (Triggered at the Rising Edge)

(1) DESCRIPTION

1 B0 (LSB) DO Bit 0 (LSB), A/D Converter Output

2 B1 DO Bit 1, A/D Converter Output

3 B2 DO Bit 2, A/D Converter Output

4 B3 DO Bit 3, A/D Converter Output

5 B4 DO Bit 4, A/D Converter Output

6 B5 DO Bit 5, A/D Converter Output

7 B6 DO Bit 6, A/D Converter Output

8 B7 DO Bit 7, A/D Converter Output

9 B8 DO Bit 8, A/D Converter Output

10 B9 DO Bit 9, A/D Converter Output

11 B10 DO Bit 10, A/D Converter Output

B11 (MSB) DO Bit 11 (MSB), A/D Converter Output

13 DRV DD P Power Supply, Exclusively for Digital Output

14 DRVGND P Digital Ground, Exclusively for Digital Output

15 GNDA P Analog Ground

16 ADCCK DI Clock for Digital Output Buffer

17 GNDA P Analog Ground

19 PBLK DI Preblanking:

HIGH = Normal Operation Mode LOW = Preblanking Mode: Digital Output “All Zero”

20 CLPOB DI Optical Black Clamp Pulse (Default = Active LOW)

(5)

21 SHP DI CDS Reference Level Sampling Pulse (Default = Active LOW)(5)

22 SHD DI CDS Data Level Sampling Pulse (Default = Active LOW) (5)

23 CLPDM DI Dummy Pixel Clamp Pulse (Default = Active LOW) (5)

PIN NAME TYPE (1) DESCRIPTION PIN DESCRIPTIONS NOTES: (1) Type designators: P = Power Supply and Ground; DI = Digital Input; DO = Digital Output; AI = Analog Input; AO = Analog Output. (2) Should be connected to ground with a bypass capacitor. We recommend the value of 0.1µF to 0.22 µF, however, it depends on the application environment. Refer to the “Optical Black Level Clamp Loop” section for more detail. (3) Should be connected to ground with a bypass capacitor. We recommend the value of 400pF to 9000pF, however, it depends on the application environment. Refer to the “Voltage Reference” section for more detail. (4) Should be connected to ground with a bypass capacitor (0.1µF). Refer to the “Voltage Reference” section for more detail. (5) Refer to “Serial Interface” section for more detail. Top View LQFP VCC CLPDM SHD SHP CLPOB PBLK V CC GNDA ADCCK GNDA DRVGND DRV DD GNDA GNDA V CC VCC BYPM BYP CCDIN BYPP2 COB V CC GNDA GNDA B0 (LSB) B10 B11 (MSB) CM REFP REFN VCC GNDA GNDA NC NC RESET SLOAD SDATA SCLK 36 35 34 33 32 31 30 29 28 27 26 123456789 1 0 1 1 VSP2262

SYMBOL PARAMETER MIN TYP MAX UNITS tCKP Clock Period 48 ns tADC ADCCK HIGH/LOW Pulse Width 20 ns tWP SHP Pulse Width 14 ns tWD SHD Pulse Width 11 ns tPD SHP Trailing Edge to SHD Leading Edge(1) 8n s tDP SHD Trailing Edge to SHP Leading Edge(1) 12 ns tS Sampling Delay 5 ns tINHIBIT Inhibited Clock Period 20 ns tHOLD Output Hold Time 7 ns tOD Output Delay 38 ns DL Data Latency, Normal Operation Mode 9 (fixed) Clock Cycles N N – 9N – 8N – 7N – 11 N – 10 CCD Output Signal SHP (1) SHD (1) ADCCK B[11:0] tWP N + 1 N + 2 N + 3 tDP tODtHOLD tADCtINHIBIT tADC tCKP tCKP tCKP tS tWD tPD tS NOTE: (1) The description and timing diagrams in this data sheet are all based on the polarity of Active LOW (default value). The user can select the active polarity (Active LOW or Active HIGH) through the serial interface. Refer to the “Serial Interface” section for more detail.

SERIAL INTERFACE TIMING SPECIFICATIONS SYMBOL PARAMETER MIN TYP MAX UNITS tCKP Clock Period 100 ns tCKH Clock HIGH Pulse Width 40 ns tCKL Clcok LOW Pulse Width 40 ns tDS Data Setup Time 30 ns tDH Data Hold TIme 30 ns tXS SLOAD to SCLK Setup Time 30 ns tXH SCLK to SLOAD Hold Time 30 ns SLOAD SCLK MSB LSBSDATA tCKP tXS tCKH tDH tDS

2 Bytes

NOTES: (1) Data shift operation should occur at the rising edge of SCLK while SLOAD is LOW. Two bytes of input data are loaded to the parallel latch in the VSP2260 at the rising edge of SLOAD. (2) When the input serial data is longer than two bytes (16 bits), the last two bytes become effective and the former bits are lost.

between the CCD output and the VSP2262 CCDIN input. LOW asynchronously from the clocks. diagram of the CDS and input clamp. FIGURE 1. Simplified Block Diagram of CDS and Input too high for the CDS to work properly. common-mode voltage for the CDS is around 0.5V to 1.5V. based on the polarity of Active LOW (default value). (refer to the “Serial Interface” section for more detail). The default value of CLPDM and SHP is “Active LOW”.

different from the preblanking mode in which the digital output data comes out on the rising edge of ADCCK with a delay of nine clock cycles (data latency is nine). If the input voltage is higher than the supply rail by 0.3V or lower than the ground rail by 0.3V, the protection diodes will be turned on to prevent the input voltage from going any further. Such a high swing signal may cause device damage to the VSP2262 and should be avoided. STAND-BY MODE For the purpose of saving power, the VSP2262 can be set to Stand-by mode (or Power-Down mode) through the serial interface when the VSP2262 is not in use. Refer to the “Serial Interface” section for more detail. In this mode, all the function blocks are disabled and the digital outputs will go to all ZEROs, causing the current consumption to drop to 1mA. Since all the bypass capacitors will discharge during this mode, a substantial time (usually of the order of 200ms to 300ms) is required to power up from Stand-by mode. VOLTAGE REFERENCE All the reference voltages and bias currents needed in the VSP2262 are generated by its internal bandgap circuitry. The CDS and the ADC use mainly three reference voltages: REFP (Positive Reference, pin 38), REFN (Negative Refer- ence, pin 39) and CM (Common-Mode Voltage, pin 37). REFP, REFN and CM should be heavily decoupled with appropriate capacitors (e.g., 0.1µF ceramic capacitor). Do not use these voltages elsewhere in the system as they affect the stability of the reference level, and cause ADC perfor- mance degradation. Note that these are analog output pins and do not apply external voltage. BYPP2 (pin 29), BYP (pin 31), and BYPM (pin 32) are also reference voltages to be used in the analog circuit. BYP should be connected to ground with a 0.1µF ceramic capaci- tor. Since the capacitor value for BYPP2 and BYPM affects the step response, we consider 400pF to 9000pF to be a reasonable value. However, as it depends on the application environment, we recommend making careful adjustments using trial-and-error. BYPP2, BYP and BYPM should all be heavily decoupled with appropriate capacitors, and not used elsewhere in the system. They affect the stability of the reference levels, and cause performance degradation. Note that these are analog output pins and do not apply external voltage. SERIAL INTERFACE The serial interface has a 2-byte shift register and various parallel registers to control all the digitally programmable features of the VSP2262. Writing to these registers is con- trolled by four signals (SLOAD, SCLK, SDATA, and RE- SET). To enable the shift register, SLOAD must be pulled LOW. SDATA is the serial data input and the SCLK is the shift clock. The data at SDATA is taken into the shift register at the rising edge of SCLK; the data length should be two bytes. After the 2-byte shift operation, the data in the shift register is transferred to the parallel latch at the rising edge of SLOAD. In addition to the parallel latch, there are several registers dedicated to the specific features of the device and are synchronized with ADCCK. It takes five or six clock cycles for the data in the parallel latch to be written to those registers. Therefore, to complete the data updates, it requires five or six clock cycles after parallel latching by the rising edge of SLOAD. See Table II for the serial interface data format. TEST is the flag for the test mode (Texas Instruments proprietary only), A0 to A2 is the address for the various registers, and D0 to D11 is the data (or operand) field.

REGISTERS TEST A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Configuration 000000000000 00 0 C 0 PGA Gain 000100 G 9 G 8 G 7 G 6 G 5 G 4 G 3 G 2 G 1 G 0 OB Clamp Level 001000000000O 3 O 2 O 1 O 0 Clock Polarity 001100000000 0 P 2 P 1 P 0 Reserved 0100 xxxxxxxx xx x x Reserved 0101 xxxxxxxx xx x x Reserved 0110 xxxxxxxx xx x x Reserved 0111 xxxxxxxx xx x x Reserved 1 xxxxxxxxxxx xx x x x = Don’t Care. TABLE II. Serial Interface Data Format. MSB LSB REGISTER DEFINITIONS C[0] Operation Mode, Normal/Stand-By Serial Interface and Registers are always active, independently from the operation mode. C0 = Operation Mode for the entire chip except the serial interface and registers. (C0 = 0 “Active”; C0 = 1 “Stand-by”) G[9:0] The Characteristics of PGA Gain (refer to Figure 2) O[3:0] Programmable OB Clamp Level (refer to Table I) P[2:0] Clock Polarity P0 = Polarity for CLPDM (P0 = 0 “Active LOW”; P0 = 1 “Active HIGH”) P1 = for CLPOB (P0 = 0 “Active LOW”; P0 = 1 “Active HIGH”) P2 = for SHP/SHD (P0 = 0 “Active LOW”; P0 = 1 “Active HIGH”) Immediately after power ON, these values are Unknown. The appropriate value must be set by using the serial interface, or reset to the default value by strobing the RESET pin. Default values are: C[2:0] = 0 Normal Operation Mode G[9:0] = 0010000000 PGA Gain = 0dB O[3:0] = 1000 OB Clamp Level = 32LSB P[2:0] = 000 CLPDM, CLPOB, SHP/SHD are all “Active LOW” (1) NOTE: (1) The descriptions and the timing diagrams in this data sheet are all based on the polarity of Active LOW (default value).

The CDS and the ADC are operated by SHP/SHD and their derivative timing clocks generated by the on-chip timing generator. The digital output data is synchronized with ADCCK. See the VSP2262 “CDS Timing Specifications” for the timing relationship among the CCD signal, SHP/SHD, ADCCK and the output data. CLPOB is used to activate the black level clamp loop during the OB pixel interval, and CLPDM is used to activate the input clamping during the dummy pixel interval. If the CLPDM pulse is not available in your system, the CLPOB pulse can be used in place of CLPDM as long as the clamping takes place during black pixels (refer to the “Input Clamp and Dummy Pixel Clamp” section for more detail). The clock polarities of SHP/SHD, CLPOB and CLPDM can be independently set through the serial interface (refer to the “Serial Interface” section for more detail). The descriptions and the timing diagrams in this data sheet are all based on the polarity of Active LOW (default value). In order to keep a stable and accurate OB clamp level, we recommend CLPOB should not be activated during PBLK active period. Refer to the “Preblanking and Data Latency” section for more detail. In Stand-by mode, ADCCK, SHP, SHD, CLPOB and CLPDM are internally masked and pulled HIGH. POWER SUPPLY, GROUNDING AND DEVICE DECOUPLING RECOMMENDATIONS The VSP2262 incorporates analog circuitry and a very high-precision, high-speed ADC that are vulnerable to any extraneous noise from the rails or elsewhere. For this reason, it should be treated as an analog component and all supply pins except for DRV DD should be powered by the only analog supply of the system. This will ensure the most consistent results, since digital power lines often carry high levels of wideband noise that would otherwise be coupled into the device and degrade the achievable performance. Proper grounding, short lead length, and the use of ground planes are also very important for high-frequency designs. Multi-layer PC boards are recommended for the best perfor- mance, since they offer distinct advantages like minimizing ground impedance, separation of signal layers by ground layers, etc. It is highly recommended that analog and digital ground pins of the VSP2262 be joined together at the IC and be connected only to the analog ground of the system. The driver stage of the digital outputs (B[11:0]) is supplied through a dedicated supply pin (DRV DD ) and it should be separated from the other supply pins completely, or at least with a ferrite bead. It is also recommended to keep the capacitive loading on the output data lines as low as possible (typically less than 15pF). Larger capacitive loads demand higher charging current surges that can feed back into the analog portion of the VSP2262 and affect the performance. If possible, exter- nal buffers or latches should be used, providing the added benefit of isolating the VSP2262 from any digital noise activities on the data lines. In addition, resistors in series with each data line may help minimize the surge current. Values in the range of 100Ω to 200Ω will limit the instan- taneous current the output stage has to provide for recharg- ing the parasitic capacitances as the output levels change from LOW to HIGH, or HIGH to LOW. Due to high operation speed, the converter also generates high-frequency current transients and noises that are fed back into the supply and reference lines. This requires the supply and reference pins to be sufficiently bypassed. In most cases, 0.1µF ce- ramic chip capacitors are adequate to decouple the reference pins. Supply pins should be decoupled to the ground plane with a parallel combination of tantalum (1µF to 22µF) and ceramic (0.1µF) capacitors. The effectiveness of the decou- pling largely depends on the proximity to the individual pin. DRV DD should be decoupled to the proximity of DRVGND. Special attention must be paid to the bypassing of COB, BYPP2 and BYPM, since these capacitor values determine important analog performances of the device.

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) VSP2262Y ACTIVE LQFP PT 48 250 TBD CU SNPB Level-1-235C-UNLIM VSP2262Y/2K ACTIVE LQFP PT 48 2000 TBD CU SNPB Level-1-235C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2005 Addendum-Page 1

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