DEM-OPA-SOT-1A

OPA890 BURR-BROWN | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 32

Technical content

/C0066/C0117/C0114/C0114/C0262/C0066/C0114/C0111/C0119/C0110 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0102/C0114/C0111/C0109 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 OP A890

FEATURES

DESCRIPTION

APPLICATIONS

5.56k/c87 DAC7822 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 V R R I I R R R REF FB OUT1 OUT2 2_3 GNDVDD +5V 2.5pF +7.5V /c45 2.5V VOUT 0V V 5V/c163 /c163 OUT

0.1 F/c109

/c45 5V OPA890 SBOS369 MAY 2007 Low-Power, Wideband, Voltage-Feedback OPERATIONAL AMPLIFIER with Disable FLEXIBLE SUPPLY RANGE: The OPA890 represents a major step forward in +3V to +12V Single Supply unity-gain stable, voltage-feedback op amps. A new 1.5V to Dual Supplies internal architecture provides slew rate and UNITY-GAIN STABLE full-power bandwidth previously found only in WIDEBAND +5V OPERATION: 115MHz wideband, current-feedback op amps. These +2V/V) capabilities provide exceptional full power bandwidth. Using a single +5V supply, the OPA890 can deliver a OUTPUT VOLTAGE SWING: to output swing with over 35mA drive current HIGH SLEW RATE: 500V/ µ s and 220MHz bandwidth. This combination of LOW QUIESCENT CURRENT: 1.1mA (ADC) LOW DISABLE CURRENT: µ A input driver. The low 1.1mA supply current of the OPA890 is VIDEO LINE DRIVING precisely trimmed at +25 This trim, along with low temperature drift, ensures lower maximum supply xDSL LINE DRIVERS/RECEIVERS current than competing products. System power may HIGH-SPEED IMAGING CHANNELS be reduced further using the optional disable control ADC BUFFERS pin. Leaving this disable pin open, or holding it PORTABLE INSTRUMENTS HIGH, operates the OPA890 normally. If pulled LOW, the OPA890 supply current drops to less than TRANSIMPEDANCE AMPLIFIERS µ A while the output goes into a high-impedance ACTIVE FILTERS state. RELATED OPERATIONAL AMPLIFIER Multiplying DAC Transimpedance Amplifier PRODUCTS (1800V/ µ Current-Feedback Amplifier OPA691 OPA2691 OPA3691 with Disable (2100V/ µ Fixed Gain OPA692 OPA3692 Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright 2007, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com ABSOLUTE MAXIMUM RATINGS (1) PIN CONFIGURATIONS DIS +VS Output NC NC Inverting□Input Noninverting□Input /c45V S TOP□VIEW SO TOP□VIEW SOT23 +VS DIS Inverting□Input Output /c45VS Noninverting□Input 1 2 3 6 5 4 NC□=□No□Connection Pin□Orientation/Package□Marking BRI OPA890 SBOS369 MAY 2007 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) SPECIFIED PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE-LEAD DESIGNATOR RANGE MARKING NUMBER MEDIA, QUANTITY OPA890ID Rail, OPA890 SO-8 D C to +85 C OPA890 OPA890IDR Tape and Reel, 2500 OPA890IDBVT Tape and Reel, 250 OPA890 SOT23-6 DBV C to +85 C BRI OPA890IDBVR Tape and Reel, 3000 (1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com Over operating free-air temperature range (unless otherwise noted). OPA890 UNIT Power Supply 6.5 V Internal Power Dissipation See Thermal Characteristics Input Voltage Range V S V Storage Temperature Range to +125 C Lead Temperature (soldering, 10s) +260 C Maximum Junction Temperature J +150 C Maximum Junction Temperature, Continuous Operation, Long-Term Reliability +140 C Human Body Model (HBM) 2000 V ESD Rating: Charge Device Model (CDM) 1500 V Machine Model (MM) 200 V (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. Submit Documentation Feedback

www.ti.com ELECTRICAL CHARACTERISTICS: V S OPA890 SBOS369 MAY 2007 Boldface limits are tested at +25 At R F 750 Ω G +2V/V, and R L 100 Ω unless otherwise noted. OPA890ID, IDBV TYP MIN/MAX OVER TEMPERATURE C to C to MIN/ TEST PARAMETER CONDITIONS +25 C +25 C (2) +70 C (3) +85 C (3) UNITS MAX LEVEL (1) AC PERFORMANCE Small-Signal Bandwidth G +1V/V, V O 100mV PP R F Ω 260 MHz typ C G +2V/V, V O 100mV PP 115 MHz min B G +10V/V, V O 100mV PP 7.5 MHz min B Gain Bandwidth Product G +20V/V 130 100 MHz min B Bandwidth for 0.1dB Flatness G +2V/V, V O 100mV PP MHz typ C Peaking at a Gain of +1V/V V O 100mV PP dB typ C Large-Signal Bandwidth G +2V/V, V O PP 170 MHz typ C Slew Rate G +2V/V, V O Step 500 325 300 275 µ s min B Rise-and-Fall Time 0.2V Step 3.5 ns typ C Settling Time to 0.02% G +1V/V, V O Step ns typ C Settling Time to 0.1% ns typ C Harmonic Distortion G +2V/V, f 1MHz, V O PP 2nd-Harmonic R L 200 Ω -88 -78 -76 -75 dBc max B R L 500 Ω -102 -84 -82 -80 dBc max B 3rd-Harmonic R L 200 Ω -89 -84 -81 -80 dBc max B R L 500 Ω -94 -90 -87 -86 dBc max B Input Voltage Noise f 100kHz nV/ Hz max B Input Current Noise f 100kHz 1.3 1.7 1.9 pA/ Hz max B Differential Gain G +2V/V, V O 1.4V PP R L 150 Ω 0.05 typ C Differential Phase G +2V/V, V O 1.4V PP R L 150 Ω 0.03 typ C Channel-to-Channel Crosstalk f 5MHz, Input-Referred dB typ C DC PERFORMANCE (4) Open-Loop Voltage Gain OL V O 0V, R L 100 Ω dB min A Input Offset Voltage V CM 5.7 mV max A Average Offset Voltage Drift V CM µ C max B Input Bias Current V CM 0.1 1.6 1.8 µ A max A Average Input Bias Current Drift V CM nA/ C max B Input Offset Current V CM 350 450 500 nA max A Average Input Offset Current Drift V CM 2.5 2.5 nA/ C max B INPUT Common-Mode Input Range (CMIR) (5) 3.9 3.8 3.7 3.6 V min A Common-Mode Rejection Ratio (CMRR) V CM 0V, Input-Referred dB min A Input Impedance Differential V CM 190 0.6 k Ω pF typ C Common-Mode V CM 3.2 0.9 M Ω pF typ C OUTPUT Output Voltage Swing No Load 4.0 3.9 3.8 3.7 V min A R L 100 Ω 3.5 3.1 3.05 2.9 V min A Output Current, Sourcing, Sinking V O mA min A Peak Output Current Output Shorted to Ground mA typ C Closed-Loop Output Impedance G +2V/V, f 100kHz 0.04 Ω typ C (1) Test levels: (A) 100% tested at +25 Over temperature limits set by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (2) Junction temperature ambient for +25 C tested specifications. (3) Junction temperature ambient at low temperature limit; junction temperature ambient C at high temperature limit for over temperature specifications. (4) Current is considered positive out-of-node. V CM is the input common-mode voltage. (5) Tested 3dB below minimum specified CMRR at CMIR limits Submit Documentation Feedback

www.ti.com OPA890 SBOS369 MAY 2007 ELECTRICAL CHARACTERISTICS: V S (continued) Boldface limits are tested at +25 At R F 750 Ω G +2V/V, and R L 100 Ω unless otherwise noted. OPA890ID, IDBV TYP MIN/MAX OVER TEMPERATURE C to C to MIN/ TEST PARAMETER CONDITIONS +25 C +25 C (2) +70 C (3) +85 C (3) UNITS MAX LEVEL (1) DISABLE Disable LOW Power-Down Supply Current (+V S V DIS µ A max A Disable Time V IN DC µ s typ C Enable Time V IN DC 200 ns typ C Off Isolation G +2V/V, f 5MHz dB typ C Output Capacitance in Disable pF typ C Enable Voltage 3.0 3.2 3.4 3.8 V min A Disable Voltage 1.4 1.1 1.0 0.8 V max A Control Pin Input Bias Current DIS V DIS 0V, Each Channel µ A max A POWER SUPPLY Specified Operating Voltage V typ C Minimum Operating Voltage 1.5 V typ C Maximum Operating Voltage 6.0 6.0 6.0 V max A Maximum Quiescent Current V S 1.1 1.2 1.22 1.25 mA max A Minimum Quiescent Current V S 1.1 1.05 1.02 mA min A Power-Supply Rejection Ratio (+PSRR) S 4.5V to 5.5V dB min A THERMAL CHARACTERISTICS Specified Operating Range to +85 C typ C Thermal Resistance θ JA Junction-to-Ambient D SO-8 105 C/W typ C DBV SOT23-6 110 C/W typ C Submit Documentation Feedback

www.ti.com ELECTRICAL CHARACTERISTICS: V S +5V OPA890 SBOS369 MAY 2007 Boldface limits are tested at +25 At R F 750 Ω G +2V/V, and R L 100 Ω unless otherwise noted. OPA890ID, IDBV TYP MIN/MAX OVER TEMPERATURE C to C to MIN/ TEST PARAMETER CONDITIONS +25 C +25 C (2) +70 C (3) +85 C (3) UNITS MAX LEVEL (1) AC PERFORMANCE Small-Signal Bandwidth G +1V/V, V O 100mV PP R F Ω 220 MHz typ C G +2V/V, V O 100mV PP 105 MHz min B G +10V/V, V O 100mV PP 6.8 6.3 MHz min B Gain Bandwidth Product G +20V/V 125 MHz min B Bandwidth for 0.1dB Flatness G +2V/V, V O 100mV PP MHz typ C Peaking at a Gain of +1V/V V O 100mV PP dB typ C Large-Signal Bandwidth G +2V/V, V O PP 130 MHz typ C Slew Rate G +2V/V, V O Step 350 250 200 175 µ s min B Rise-and-Fall Time 0.2V Step 3.8 ns typ C Settling Time to 0.02% G +1V/V, V O Step ns typ C Settling Time to 0.1% ns typ C Harmonic Distortion G +2V/V, f 1MHz, V O PP 2nd-Harmonic R L 200 Ω -85 -76 -73 -72 dBc max B R L 500 Ω -90 -78 -74 -73 dBc max B 3rd-Harmonic R L 200 Ω -85 -81 -79 -78 dBc max B R L 500 Ω -87 -84 -82 -81 dBc max B Input Voltage Noise f 100kHz 8.1 9.1 10.1 11.1 nV/ Hz max B Input Current Noise f 100kHz 1.1 1.4 1.7 2.0 pA/ Hz max B Differential Gain G +2V/V, V O 1.4V PP R L 150 Ω 0.06 typ C Differential Phase G +2V/V, V O 1.4V PP R L 150 Ω 0.04 typ C Channel-to-Channel Crosstalk f 5MHz, Input-Referred -68 dB typ C DC PERFORMANCE (4) Open-Loop Voltage Gain OL V O V S /2, R L 100 Ω dB min A Input Offset Voltage V CM V S 5.7 mV max A Average Offset Voltage Drift V CM V S µ C max B Input Bias Current V CM V S 0.1 1.7 1.9 2.1 µ A max A Average Input Bias Current Drift V CM V S nA/ C max B Input Offset Current V CM V S 400 500 550 nA max A Average Input Offset Current Drift V CM V S 2.5 2.5 nA/ C max B INPUT Most Positive Input Voltage (5) +3.8 +3.75 +3.7 V min A Least Positive Input Voltage (5) +1.2 +1.2 +1.3 V max A Common-Mode Rejection Ratio (CMRR) V CM V S /2, Input-Referred dB min A Input Impedance Differential V CM V S 190 0.6 k Ω pF typ C Common-Mode V CM V S 3.2 0.9 M Ω pF typ C OUTPUT Most Positive Output Voltage No Load +4.0 +3.9 +3.85 +3.8 V min A R L 100 Ω +3.9 +3.75 +3.7 +3.65 V min A Least Positive Output Voltage No Load +1.0 +1.1 +1.15 +1.2 V max A R L 100 Ω +1.1 +1.35 +1.4 +1.45 V max A Output Current: Sourcing, Sinking V O V S mA min A Short-Circuit Output Current Output Shorted to Ground mA typ C Closed-Loop Output Impedance G +2V/V, f 100kHz 0.04 Ω typ C (1) Test levels: (A) 100% tested at +25 Over temperature limits set by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (2) Junction temperature ambient for +25 C tested specifications. (3) Junction temperature ambient at low temperature limit; junction temperature ambient C at high temperature limit for over temperature specifications. (4) Current is considered positive out-of-node. V CM is the input common-mode voltage. (5) Tested 3dB below minimum specified CMRR at CMIR limits Submit Documentation Feedback

www.ti.com OPA890 SBOS369 MAY 2007 ELECTRICAL CHARACTERISTICS: V S +5V (continued) Boldface limits are tested at +25 At R F 750 Ω G +2V/V, and R L 100 Ω unless otherwise noted. OPA890ID, IDBV TYP MIN/MAX OVER TEMPERATURE C to C to MIN/ TEST PARAMETER CONDITIONS +25 C +25 C (2) +70 C (3) +85 C (3) UNITS MAX LEVEL (1) DISABLE Disable LOW Power-Down Supply Current (+V S V DIS 0V, both channels µ A max A Disable Time V OUT DC ns typ C Enable Time V OUT DC 200 ns typ C Off Isolation G +2V/V, f 5MHz dB typ C Output Capacitance in Disable pF typ C Enable Voltage 3.0 3.2 3.4 3.8 V min A Disable Voltage 1.4 1.1 1.0 0.8 V max A Control Pin Input Bias Current DIS V DIS 0V, Each Channel µ A max A POWER SUPPLY Specified Operating Voltage V typ C Minimum Operating Voltage V typ C Maximum Operating Voltage +12 +12 +12 V max A Maximum Quiescent Current V S +5V 1.06 1.18 1.20 1.25 mA max A Minimum Quiescent Current V S +5V 1.06 0.92 0.90 0.87 mA min A Power-Supply Rejection Ratio (+PSRR) S 4.5V to 5.5V dB typ C THERMAL CHARACTERISTICS Specified Operating Range to +85 C typ C Thermal Resistance θ JA Junction-to-Ambient D SO-8 105 C/W typ C DBV SOT23-6 110 C/W typ C Submit Documentation Feedback

www.ti.com TYPICAL CHARACTERISTICS: V S /c45 3 /c45 6 /c45 9 Frequency□(MHz) Gain□(dB) 1 10 100 400 RL =□200/c87 G□=□+2V/V 4VPP 7VPP 1VPP 2VPP /c45 3 /c45 6 /c45 9 /c45 12 /c45 15 /c45 18 Frequency□(MHz) Normalized□Gain□(dB) 1 10 100 600 V =□0.1VO PP G□=□+1V/V R =□0F /c87 G□=□+2V/V G□=□+5V/V G□=□+10V/V 400 300 200 100 /c45100 /c45200 /c45300 /c45400 Time□(10ns/div) Output□Voltage□(mV) VO PP=□0.5V G□=□+2V/V /c451 /c452 /c453 Time□(10ns/div) Output□Voltage□(V) VO PP=□5V G□=□+2V/V 0.20 0.18 0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 Number□of□150 Loads/c87 Differential□Gain□(%) 0.40 0.36 0.32 0.28 0.24 0.20 0.16 0.12 0.08 0.04 Differential□Phase□( ) /c176 1 2 3 4 /c45 dP /c45 dG +dP +dG /c4545 /c4550 /c4555 /c4560 /c4565 /c4570 /c4575 /c4580 /c4585 /c4590 Frequency□(MHz) Disable□Feedthrough□(dB) 1 10 100 V =□0V Input□Referred DIS OPA890 SBOS369 MAY 2007 At T A +25 G +2V/V, R F 750 Ω and R L 200 Ω unless otherwise noted. SMALL-SIGNAL FREQUENCY RESPONSE LARGE-SIGNAL FREQUENCY RESPONSE Figure Figure SMALL-SIGNAL PULSE RESPONSE LARGE-SIGNAL PULSE RESPONSE Figure Figure VIDEO DIFFERENTIAL GAIN/DIFFERENTIAL PHASE DISABLE FEEDTHROUGH Figure Figure Submit Documentation Feedback

www.ti.com /c45 80 /c45 85 /c45 90 /c45 95 /c45 100 /c45 105 /c45 110 Load□Resistance□( )/c87 Harmonic□Distortion□(dBc) 100 1k V =□2VO PP f□=□1MHz G□=□+2V/V 3rd□Harmonic 2nd□Harmonic /c45 80 /c45 85 /c45 90 /c45 95 /c45 100 Supply□Voltage□(/c177 V )S Harmonic□Distortion□(dBc) V =□2VO PP R =□200 /c87L G□=□+2V/V 2nd□Harmonic 3rd□Harmonic /c45 50 /c45 60 /c45 70 /c45 80 /c45 90 /c45 100 /c45 110 Frequency□(MHz) Harmonic□Distortion□(dBc) 0.1 1 10 V =□2VO PP R =□200 /c87L G□=□+2V/V 2nd□Harmonic 3rd□Harmonic /c45 70 /c45 75 /c45 80 /c45 85 /c45 90 /c45 95 /c45 100 Output□Voltage□Swing□(V )PP Harmonic□Distortion□(dBc) 0.1 1 10 R =□200 /c87L f□=□1MHz G□=□+2V/V 2nd□Harmonic 3rd□Harmonic /c45 70 /c45 75 /c45 80 /c45 85 /c45 90 /c45 95 /c45 100 /c45 105 Gain□(V/V) Harmonic□Distortion□(dBc) 1 10 20 V =□2VO PP R =□200 /c87L f□=□1MHz 2nd□Harmonic 3rd□Harmonic /c45 70 /c45 75 /c45 80 /c45 85 /c45 90 Gain□(V/V) Harmonic□Distortion□(dBc) /c45 1 /c45 10 /c45 20 V =□2VO PP R =□200 /c87L f□=□1MHz 2nd□Harmonic 3rd□Harmonic OPA890 SBOS369 MAY 2007 TYPICAL CHARACTERISTICS: V S (continued) At T A +25 G +2V/V, R F 750 Ω and R L 200 Ω unless otherwise noted. HARMONIC DISTORTION vs LOAD RESISTANCE 1MHz HARMONIC DISTORTION vs SUPPLY VOLTAGE Figure Figure HARMONIC DISTORTION vs FREQUENCY HARMONIC DISTORTION vs OUTPUT VOLTAGE Figure Figure 10. HARMONIC DISTORTION vs NONINVERTING GAIN HARMONIC DISTORTION vs INVERTING GAIN Figure 11. Figure 12. Submit Documentation Feedback

www.ti.com /c45 40 /c45 50 /c45 60 /c45 70 /c45 80 /c45 90 /c45 100 /c45 110 Single-T one□Load□Power□(dBm) Spurious□P oint□(dBc) /c45 8 /c45 6 /c45 4 /c45 2 0 2 4 6 8 Load□Power□at□Matched□50 Load/c87 10MHz 5MHz 1MHz /c45 90 /c45 95 /c45 100 /c45 105 /c45 110 /c45 115 /c45 120 Frequency□(Hz) Harmonic□Distortion□(dBc) 1k 10k 100k 1M V =□2VO PP R =□500 /c87L G□= 1V/V/c45 2nd□Harmonic 3rd□Harmonic 100 Capacitive□Load□(pF) R ( ) /c87 S 1 10 100 1000 /c45 3 /c45 6 /c45 9 Frequency□(MHz) Gain□(dB) 0 20 40 60 80 100 120 140 160 180 200 G□=□+2V/V 750/c87 RSVIN VOUT 1k/c87 (1)CL 750/c87 NOTE:□(1)□1k is□optional./c87 C =□100pFL C =□47pFL C =□22pFL C =□10pFL OPA890 Frequency□(Hz) CMRR□and□PSRR□(dB) 1k 10k 100k 1M 10M 100M /c45PSRR CMRR +PSRR 100 0.1 Frequency□(Hz) Voltage□Noise□Density□(nV/ ) Hz/c214 Current□Noise□Density□(pA/ Hz/c214 10 100 1k 10k 100k 1M 10M Voltage□Noise□Density□(8nV/ )/c214Hz Current□Noise□Density□(1pA/ )/c214Hz OPA890 SBOS369 MAY 2007 TYPICAL CHARACTERISTICS: V S (continued) At T A +25 G +2V/V, R F 750 Ω and R L 200 Ω unless otherwise noted. LOW-FREQUENCY INVERTING HARMONIC DISTORTION TWO-TONE, 3RD-ORDER INTERMODULATION SPURIOUS Figure 13. Figure 14. RECOMMENDED R S vs CAPACITIVE LOAD FREQUENCY RESPONSE vs CAPACITIVE LOAD Figure 15. Figure 16. COMMON-MODE REJECTION RATIO AND POWER-SUPPLY REJECTION RATIO vs FREQUENCY INPUT VOLTAGE AND CURRENT NOISE Figure 17. Figure 18. Submit Documentation Feedback

www.ti.com 2.10 2.05 2.00 1.95 1.90 1.85 1.80 1.75 250 200 150 100 /c45 50 /c45 100 Ambient□T emperature□( C)/c176 Input□Offset□Voltage□(V) Input□Bias□and□Input□Offset□Currents□(nA) /c45 50 /c45 25 0 25 50 75 100 125 Input□Offset□Voltage□(V )OS Input□Offset□Current□(I )OS Input□Bias□Current□(I )B 1.15 1.14 1.13 1.12 1.11 1.10 1.09 1.08 1.07 1.06 1.05 Ambient□T emperature□( C)/c176 Supply□Current□(mA) Output□Current□(mA) /c45 50 /c45 25 0 25 50 75 100 125 Output□Current,Sinking Output□Current, Sourcing Supply□Current /c451 /c452 Time□(5ns/div) Output□Voltage□(V) V (V) DIS /c452 /c454 /c456 /c458 Time□(10ns/div) Output□Voltage□(V) /c451 /c453 /c453 /c454 Input□Voltage□(V) Input□Voltage Right□Scale Output□Voltage Left□Scale 100 0.1 0.01 0.001 Frequency□(Hz) Output□Impedance□( ) /c87 1k 10k 100k 1M 10M 100M 750/c87 ZO324/c87 750/c87 OPA890 /c45 10 Frequency□(Hz) Open-Loop□Gain□(dB) 180 160 140 120 100 Open-Loop□Phase□( )/c176 100 1k 10k 100k 1M 10M 100M 1G Open-Loop□Gain Open-Loop□Phase OPA890 SBOS369 MAY 2007 TYPICAL CHARACTERISTICS: V S (continued) At T A +25 G +2V/V, R F 750 Ω and R L 200 Ω unless otherwise noted. SUPPLY AND OUTPUT CURRENT vs TEMPERATURE TYPICAL DC DRIFT vs TEMPERATURE Figure 19. Figure 20. LARGE-SIGNAL DISABLE/ENABLE RESPONSE NONINVERTING OVERDRIVE RECOVERY Figure 21. Figure 22. CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY OPEN-LOOP GAIN AND PHASE Figure 23. Figure 24. Submit Documentation Feedback

www.ti.com TYPICAL CHARACTERISTICS: V S 5V, Differential /c45 3 /c45 6 /c45 9 /c45 12 /c45 15 /c45 18 Frequency□(MHz) Normalized□Gain□(dB) 1 10 100 300 R =□750F /c87 R =□400L /c87 G =□10V/VD G =□1V/VD G =□2V/VD G =□5V/VD /c453 /c456 /c459 Frequency□(MHz) Gain□(dB) 1 10 100 300 G =□5VD PP G =□14VD PP G =□8VD PP /c45 30 /c45 40 /c45 50 /c45 60 /c45 70 /c45 80 /c45 90 /c45 100 /c45 110 /c45 120 Frequency□(MHz) Harmonic□Distortion□(dBc) 1 10 20 R =□400 /c87L G =□2V/VD 2nd□Harmonic 3rd□Harmonic /c45 70 /c45 75 /c45 80 /c45 85 /c45 90 /c45 95 /c45 100 /c45 105 /c45 110 /c45 115 /c45 120 Load□Resistance□( )/c87 Harmonic□Distortion□(dBc) 100 1k V =□4VO PP f□=□1MHz G =□2V/VD 3rd□Harmonic 2nd□Harmonic /c45 75 /c45 80 /c45 85 /c45 90 /c45 95 /c45 100 /c45 105 /c45 110 Output□Voltage□(V )PP Harmonic□Distortion□(dBc) 0.1 1 10 R /c87L =□400 f□=□1MHz G =□2V/VD 2nd□Harmonic 3rd□Harmonic OPA890 SBOS369 MAY 2007 At T A +25 Differential Gain +2V/V, R F 750 Ω and R L 400 Ω unless otherwise noted. DIFFERENTIAL SMALL-SIGNAL FREQUENCY RESPONSE DIFFERENTIAL LARGE-SIGNAL FREQUENCY RESPONSE Figure 25. Figure 26. DIFFERENTIAL DISTORTION vs LOAD RESISTANCE DIFFERENTIAL DISTORTION vs FREQUENCY Figure 27. Figure 28. DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE Figure 29. Submit Documentation Feedback

www.ti.com TYPICAL CHARACTERISTICS: V S +5V /c45 3 /c45 6 /c45 9 Frequency□(MHz) Gain□(dB) 1 10 100 300 R =□200 /c87L G□=□+2V/V 3VPP 1VPP 2VPP /c45 3 /c45 6 /c45 9 /c45 12 /c45 15 /c45 18 Frequency□(MHz) Normalized□Gain□(dB) 1 10 100 500 G□=□+2V/V G□=□+5V/V G□=□+10V/VV =□100mVO PP G□=□+1V/V R =□0F /c87 2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 Time□(10ns/div) Output□Voltage□(V) VO PP=□0.5V G□=□+2V/V 4.1 3.7 3.3 2.9 2.5 2.1 1.7 1.3 0.9 Time□(10ns/div) Output□Voltage□(V) V =□0.5VO PP G□=□+2V/V 200 100 Capacitive□Load□(pF) R ( ) /c87 S 1 10 100 1000 /c45 3 /c45 6 /c45 9 Frequency□(MHz) Gain□(dB) 0 20 40 60 80 100 120 140 160 180 200 750/c87 OPA890 RSVIN VOUT 1k/c87 (1)CL 750/c87 NOTE:□(1)□1k is□optional./c87 C =□100pFL C =□47pFL C =□10pFLC =□22pFL OPA890 SBOS369 MAY 2007 At T A +25 G +2V/V, R F 750 Ω and R L 200 Ω unless otherwise noted. SMALL-SIGNAL FREQUENCY RESPONSE LARGE-SIGNAL FREQUENCY RESPONSE Figure 30. Figure 31. SMALL-SIGNAL PULSE RESPONSE LARGE-SIGNAL PULSE RESPONSE Figure 32. Figure 33. RECOMMENDED R S vs CAPACITIVE LOAD FREQUENCY RESPONSE vs CAPACITIVE LOAD Figure 34. Figure 35. Submit Documentation Feedback

www.ti.com 6.5 5.5 4.5 3.5 2.5 1.5 0.5 /c450.5 /c451.5 Time□(10ns/div) Output□Voltage□(1V/div) 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 Input□Voltage□(1V/div) Input□Voltage Right□Scale Output□Voltage Left□Scale /c45 75 /c45 /c45 /c45 /c45 100 1k Harmonic□Distortion□(dBc) Load□Resistance□( )/c87 2nd□Harmonic 3rd□Harmonic V =□2V f□=□1MHz G =□+2V/V O PP D /c45 /c45 /c45 /c45 /c45 100/c45 0.1 1 10 Harmonic□Distortion□(dBc) Frequency□(MHz) 3rd□Harmonic 2nd□Harmonic V =□2V R =□200 to□V /2 G□=□+2V/V O PP L S /c87 /c45 /c45 /c45 /c45 /c45 95/c45 0.1 1 10 Harmonic□Distortion□(dBc) Output□Voltage□Swing□(V )PP 2nd□Harmonic 3rd□Harmonic f□=□1MHz G□=□+2V/V R =□200 to□V /2 L S /c87 /c45 /c45 /c45 /c45 /c45 /c45 100/c45 /c45 8 /c45 7 /c45 6 /c45 5 /c45 4 /c45 3 /c45 2 /c45 1 0 1 2 Single-T one□Load□Power□(dBm) Spurious□Point□(dBc) Load□Power□at□Matched□50 Load/c87 5MHz 10MHz 1MHz OPA890 SBOS369 MAY 2007 TYPICAL CHARACTERISTICS: V S +5V (continued) At T A +25 G +2V/V, R F 750 Ω and R L 200 Ω unless otherwise noted. NONINVERTING OVERDRIVE RECOVERY HARMONIC DISTORTION vs LOAD RESISTANCE Figure 36. Figure 37. HARMONIC DISTORTION vs FREQUENCY HARMONIC DISTORTION vs OUTPUT VOLTAGE Figure 38. Figure 39. TWO-TONE, 3RD-ORDER INTERMODULATION SPURIOUS Figure 40. Submit Documentation Feedback

www.ti.com TYPICAL CHARACTERISTICS: V S +5V, Differential /c45 /c45 /c45 /c45 /c45 /c45 1 10 100 200 Frequency□(MHz) Normalized□Gain□(dB) R =□750 R =□400 /c87 /c87 F L G =□5V/VD G =□2V/VD G =□1V/V R =□0 D F /c87 G =□10V/VD /c45 /c45 /c45 1 10 100 300 Frequency□(MHz) Gain□(dB) 1VPP 4VPP /c45 70 100 105 110 115 120 125 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 100 1k Load□Resistance□( )/c87 Harmonic□Distortion□(dBc)2nd□Harmonic 3rd□Harmonic V =□4V f□=□1MHz G =□2V/V O PP D /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 100 110 120/c45 Harmonic□Distortion□(dBc) 1 10 Frequency□(MHz) 2nd□Harmonic 3rd□Harmonic R =□400 f□=□1MHz G =□2V/V /c87 L D /c45 /c45 /c45 /c45 /c45 /c45 /c45 100 110 120 130/c45 Harmonic□Distortion□(dBc) 0.1 1 10 Output□Voltage□Swing□(V )PP 2nd□Harmonic 3rd□Harmonic OPA890 SBOS369 MAY 2007 At T A +25 Differential Gain +2V/V, R F 750 Ω and R L 400 Ω unless otherwise noted. DIFFERENTIAL SMALL-SIGNAL FREQUENCY RESPONSE DIFFERENTIAL LARGE-SIGNAL FREQUENCY RESPONSE Figure 41. Figure 42. DIFFERENTIAL DISTORTION vs LOAD RESISTANCE DIFFERENTIAL DISTORTION vs FREQUENCY Figure 43. Figure 44. DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE Figure 45. Submit Documentation Feedback

www.ti.com APPLICATION INFORMATION WIDEBAND VOLTAGE-FEEDBACK OPA890 +5V DIS /c45 5V

50 Load/c87

50 Source/c87

+6.8 F/c109 0.1 F/c109 6.8 F/c109 a wideband, unity-gain stable, voltage-feedback op amp using a new high slew rate input stage. Typical differential input stages used for voltage-feedback op amps are designed to steer a fixed-bias current to the compensation capacitor, setting a limit to the achievable slew rate. The OPA890 uses an input stage that places the transconductance element between two input buffers, using the combined output currents as the forward signal. As the error voltage increases across the two inputs, an increasing current is delivered to the compensation capacitor. This increasing current provides very high slew rate (500V/ µ while consuming relatively low quiescent current (1.1mA). This exceptional full-power performance comes at the price of a slightly higher input noise voltage than alternative architectures. The 8nV/ Hz input voltage noise for the OPA890 is low for this combination of Figure 46. DC-Coupled, G +2, Bipolar Supply, input stage and low quiescent current. Specification and Test Circuit Figure shows the dc-coupled, gain of +2, dual power-supply circuit configuration used as the basis Figure shows the ac-coupled, gain of +2, of the Electrical Characteristics and Typical single-supply circuit configuration used as the basis Characteristics For test purposes, the input of the +5V Electrical Characteristics and Typical impedance is set to Ω with a resistor to ground Characteristics Though not a rail-to-rail design, the and the output impedance is set to Ω with a series OPA890 requires minimal input and output voltage output resistor. Voltage swings reported in the headroom compared to other very wideband Typical Characteristics are taken directly at the input voltage-feedback op amps. It delivers a PP output and output pins, while output powers (dBm) are at swing on a single +5V supply with 100MHz the matched Ω load. For the circuit of Figure bandwidth. The key requirement of broadband the total effective load will be 100 Ω 1.5k Ω The single-supply operation is to maintain input and disable control line is typically left open to ensure output signal swings within the usable voltage ranges normal amplifier operation. Two optional components at both the input and the output. The circuit of are included in Figure An additional resistor Figure establishes an input midpoint bias using a (324 Ω is included in series with the noninverting simple resistive divider from the +5V supply (two input. Combined with the Ω dc source resistance 698 Ω resistors). The input signal is then ac-coupled looking back towards the signal generator, this into the midpoint voltage bias. The input voltage can configuration gives an input bias current cancelling swing to within 1.5V of either supply pin, giving a resistance that matches the 375 Ω source resistance PP input signal range centered between the supply seen at the inverting input (see the DC Accuracy and pins. The input impedance matching resistor (59 Ω Offset Control section). In addition to the usual used for testing is adjusted to give a Ω input load power-supply decoupling capacitors to ground, a when the parallel combination of the biasing divider 0.1 µ F capacitor is included between the two network is included. power-supply pins. In practical printed circuit board (PCB) layouts, this optional-added capacitor typically improves the 2nd-harmonic distortion performance by 3dB to 6dB. Submit Documentation Feedback

www.ti.com MULTIPLYING DAC SINGLE-ENDED OUTPUT OPA890 +5V +VS DIS V /2S 698/c87 100/c87VOVI 50/c87 59/c87 698/c87 +6.8 F/c1090.1 F/c109 RG 750/c87 RF 750/c87 5.56k/c87 DAC7822 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 V R R I I R R R REF FB OUT1 OUT2 2_3 GNDVDD +5V 2.5pF +7.5V /c45 2.5V VOUT 0V V 5V/c163 /c163 OUT /c45 5V Frequency□(Hz) Gain□(dB) 100k 1M 10M 100M OPA890 SBOS369 MAY 2007 TRANSIMPEDANCE AMPLIFIER Multiplyings digital-to-analog converters (DACs), such as the DAC7822 can make good use of the low-power, high slew rate amplifier, OPA890. The frequency response of the schematic shown in Figure is shown in Figure Figure 47. AC-Coupled, G +2, Single-Supply, Specification and Test Circuit Again, an additional resistor (50 Ω in this case) is Figure 48. DAC Transimpedance Amplifier included directly in series with the noninverting input. This minimum recommended value provides part of the dc source resistance matching for the noninverting input bias current. It is also used to form a simple parasitic pole to roll off the frequency response at very high frequencies 500MHz) using the input parasitic capacitance to form a bandlimiting pole. The gain resistor G is ac-coupled, giving the circuit a dc gain of +1, which puts the input dc bias voltage (2.5V) at the output as well. The voltage can swing to within 1.35V of either supply pin. Driving a demanding 100 Ω load to a midpoint bias is used in this characterization circuit. Higher swings are possible using a lighter load. Figure 49. OPA2890 (as DAC Transimpedance Amplifier) Frequency Response Submit Documentation Feedback

www.ti.com 2/C0112R FC F /C0043GBP 4/C0112R FC D /C0504 (2) f/C00423dB /C0043GBP 2/C0112R FC D /C0504 (3) OPA890 SBOS369 MAY 2007 Driving a light load, the OPA890 can output over Notice that most of the error occurs mainly at the first supplies. Setting the reference voltage to codes (0, 2); excluding these codes from the results in an output voltage swing from to 5V. In analysis yields the following results, shown in order to optimize the OPA2890 operation for this Table application, the supply voltages have been adjusted so that the output voltage swing is balanced around Table DC Accuracy vs Code mid-supply of the amplifier. Note that as a result of TOTAL ERROR DUE TO the internal architecture of the multiplying DAC, the CODES V OS and I B I OUT1 output is not high impedance. The I OUT1 output All codes 3.9LSB resistance is between 4.5k Ω and 22.1k Ω (excluding Excluding code 2.5LSB code 000h) for a 10k Ω nominal V REF input Excluding codes and 2LSB resistance. I OUT1 output resistance changes are directly related to the code change. This low Excluding codes and 1.83LSB impedance has multiple effects when a bipolar Note that 1LSB 1.221mV in the example shown in technology amplifier is used. Figure Some of these effects are: If more precision is required while maintaining the ac The noise gain of the amplifier changes for each performance, a FET-input amplifier (such as the code. OPA656 or the THS4631 is a good alternative. The output offset voltage of the amplifier changes for each code, because of the input offset Figure shows a single-ended output drive voltage. implementation. In this circuit, only one side of the complementary output drive signal is used. A dual The input bias current cannot be cancelled. The amplifier, such as the OPA2890 provides both effects of the input bias current can be reduced, output drivers for the DAC7822 If even lower but not eliminated, thereby affecting the total quiescent current is needed, the OPA2889 can be output offset voltage of the amplifier with each used instead, with minor modifications. The diagram code. shows the signal output current connected into the The noninverting pin of the amplifier must be tied virtual ground summing junction of the OPA890, to ground and cannot be used to create a dc which is set up as a transimpedance stage or I-V offset on the output amplifier, as is the case for converter The unused current output of the DAC is the transimpedance amplifier. connected to ground. The dc gain for this circuit is The following analysis excludes the input offset equal to R F At high frequencies, the DAC output current. capacitance produces a zero in the noise gain for the OPA890 that may cause peaking in the closed-loop The total output offset voltage variations because of frequency response. C F is added across R F to code changing in the DAC can be expressed as: compensate for this noise gain peaking. To achieve Δ V OSO Δ NG {[(R F R OUT1 R S V O a flat transimpedance frequency response, the pole in the feedback network should be set to: Where: 4.5k Ω R OUT1 22.1k Ω R F 10k Ω Using the previous values, the variation of the which gives a closed-loop transimpedance parallel combination of R F and R OUT1 can be bandwidth, f 3dB of approximately: constrained to: 4.19k Ω F R OUT1 6.88k Ω In order to optimize the bias current cancellation, we select R S to be the average of those limiting numbers, or R S (6.88k Ω 4.19k Ω )/2 5.56k Ω Using the DAC7822 internal output capacitance of Looking at the variation for each code, the total error 25pF gives a feedback capacitance F of 2.5pF (when including all codes) is ~3.9LSB for the and an 8.8MHz bandwidth. OPA890. Submit Documentation Feedback

www.ti.com SINGLE-SUPPLY ACTIVE FILTERS OPA890 1.5k/c87 432/c87137/c87 500/c87 1.87k/c87 1.87k/c87 VI +5V DIS 5MHz, 2nd-Order, Butterworth Filter /c45 3 /c45 6 Frequency□(Hz) Gain□(dB) 100k 1M 10M OPA890 SBOS369 MAY 2007 The capacitor to ground on the noninverting input is intentionally set larger to dominate input parasitic The high bandwidth provided by the OPA890, while terms. At a gain of +4, the OPA890 on a single operating on a single +5V supply, lends itself well to supply shows ~30MHz small- and large-signal high-frequency active filter designs. Again, the key bandwidth. The resistor values have been slightly additional requirement is to establish the dc adjusted to account for this limited bandwidth in the operating point of the signal near the supply midpoint amplifier stage. Tests of this circuit show a precise for highest dynamic range. See Figure for an 5MHz, 3dB point with a maximally flat passband example design of a 5MHz low-pass Butterworth (above the 32kHz ac-coupling corner), and a filter using the Sallen-Key topology. maximum stop band attenuation of 24dB at the amplifier 3dB bandwidth of 30MHz. Both the input signal and the gain setting resistor are ac-coupled using 0.1 µ F blocking capacitors (actually Note that the dc impedance looking out of each input giving band pass response with the low-frequency for this circuit has been set to 1.5k Ω to reduce the pole set to 32kHz for the component values shown). output offset voltage retaining maximum signal swing As discussed for Figure this configuration allows for a mid supply nominal operating voltage at the the midpoint bias formed by the two 1.87k Ω resistors output. to appear at both the input and output pins. The midband signal gain is set to (12dB) in this case. Figure 50. Single-Supply, High-Frequency Active Filter Submit Documentation Feedback

www.ti.com DESIGN-IN TOOLS DEMONSTRATION FIXTURES MACROMODELS AND (PCBs) are available to assist in the initial evaluation of circuit performance Computer simulation of circuit performance using using the OPA890 in its two package options. Both SPICE is often useful when analyzing the of these are offered free of charge as unpopulated performance of analog circuits and systems. This PCBs, delivered with a user's guide. The summary practice is particularly true for video and RF amplifier information for these fixtures is shown in Table circuits where parasitic capacitance and inductance can have a major effect on circuit performance. A Table Demonstration Board Summary SPICE model for the OPA890 is available through the Texas Instruments web page www.ti.com ORDERING LITERATURE These models do a good job of predicting PRODUCT PACKAGE NUMBER NUMBER small-signal ac and transient performance under a OPA890ID SO-8 DEM-OPA-SO-1A SBOU009 wide variety of operating conditions. They do not do OPA890IDBV SOT23-6 DEM-OPA-SOT-1A SBOU010 as well in predicting the harmonic distortion or dG/dP characteristics. These models do not attempt to The demonstration fixtures can be requested at the distinguish between package types in the Texas Instruments web site www.ti.com through the small-signal ac performance. OPA890 product folder. Submit Documentation Feedback

www.ti.com OPERATING SUGGESTIONS OPTIMIZING RESISTOR VALUES Inverting Amplifier Operation BANDWIDTH VERSUS GAIN Noninverting Amplifier Operation OPA890 SBOS369 MAY 2007 approach the predicted value of (GBP/NG). At a gain of +10V/V, the 13MHz bandwidth shown in the Because the OPA890 is a unity-gain stable, Electrical Characteristics agrees with that predicted voltage-feedback op amp, a wide range of resistor using the simple formula and the typical GBP of values can be used for the feedback and gain setting 130MHz. resistors. The primary limits on these values are set by dynamic range (noise and distortion) and parasitic The OPA890 exhibits minimal bandwidth reduction capacitance considerations. Usually, for G going to single-supply (+5V) operation as compared applications, the feedback resistor value should be with 5V. This difference in performance occurs between 200 Ω and 1.5k Ω Below 200 Ω the because the internal bias control circuitry retains feedback network presents additional output loading nearly constant quiescent current as the total supply that can degrade the harmonic distortion voltage between the supply pins is changed. performance of the OPA890. Above 1.5k Ω the typical parasitic capacitance (approximately 0.2pF) across the feedback resistor may cause unintentional The OPA890 is a general-purpose, wideband band-limiting in the amplifier response. voltage-feedback op amp; therefore, all of the The combined impedance of R F R G interacts with familiar op amp application circuits are available to the inverting input capacitance, placing an additional the designer. Inverting operation is one of the more pole in the feedback network and thus, a zero in the common requirements and offers several forward response. Assuming a 2pF total parasitic on performance benefits. Figure shows a typical the inverting node, having R F R G 400 Ω keeps inverting configuration where the I/O impedances this pole above 250MHz. By itself, this constraint and signal gain from Figure are retained in an implies that the feedback resistor R F can increase to inverting circuit configuration. several k Ω at high gains. This increase is In the inverting configuration, three key design acceptable, as long as the pole formed by R F and considerations must be noted. First, the gain resistor any parasitic capacitance appearing in parallel is G becomes part of the signal channel input kept out of the frequency range of interest. impedance. If input impedance matching is desired (which is beneficial whenever the signal is coupled through a cable, twisted-pair, long PCB trace, or other transmission line conductor), R G may be set equal to the required termination value and R F adjusted to give the desired gain. This approach is Voltage-feedback op amps exhibit decreasing the simplest, and results in optimum bandwidth and closed-loop bandwidth as the signal gain is noise performance. However, at low inverting gains, increased. In theory, this relationship is described by the resultant feedback resistor value can present a the gain bandwidth product (GBP) shown in the significant load to the amplifier output. For an Electrical Characteristics Ideally, dividing GBP by inverting gain of 2V/V, setting R G to Ω for input the noninverting signal gain (also called the noise matching eliminates the need for R M but requires a gain, or NG) predicts the closed-loop bandwidth. In 100 Ω feedback resistor. This option has the practice, this relationship only holds true when the interesting advantage that the noise gain becomes phase margin approaches as it does in equal to 2V/V for a Ω source impedance the high-gain configurations. At low gains (increased same as the noninverting circuits considered in the feedback factors), most amplifiers exhibit a more previous section. The amplifier output, however, now complex response with lower phase margin. The sees the 100 Ω feedback resistor in parallel with the OPA890 is compensated to give a slightly peaked external load. In general, the feedback resistor response in a noninverting gain of 2V/V (see should be limited to a range of 200 Ω to 1.5k Ω In this Figure This compensation results in a typical case, it is preferable to increase both the R F and R G gain of +2V/V bandwidth of 115MHz, far exceeding values, as shown in Figure and then achieve the that predicted by dividing the 130MHz GBP by input matching impedance with a third resistor M Increasing the gain causes the phase margin to to ground. The total input impedance becomes the approach and the bandwidth to more closely parallel combination of R G and R M Submit Documentation Feedback

www.ti.com DRIVING CAPACITIVE LOADS OPA890 50/c87 RF 750/c87 RG 324/c87 RB 240/c87 RM 59/c87 Source DIS +5V /c45 5V RO 50/c87 0.1 F/c109 6.8 F/c109+

6.8 F/c109

loading. Often, the capacitive load is the input of an ADC including additional external capacitance that may be recommended to improve ADC linearity. A high-speed, high open-loop gain amplifier such as the OPA890 can be very susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. When the amplifier open-loop output resistance is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. Several external solutions to this problem have been suggested. When the primary considerations are frequency response flatness, pulse response fidelity, and/or distortion, the simplest and most effective solution is to isolate the capacitive Figure 51. Gain of 2V/V Example Circuit load from the feedback loop by inserting a series-isolation resistor between the amplifier output The second major consideration, touched on in the and the capacitive load. This solution does not previous paragraph, is that the signal source eliminate the pole from the loop response, but rather impedance becomes part of the noise gain equation shifts it and adds a zero at a higher frequency. The and influences the bandwidth. For the example in additional zero acts to reduce the phase lag from the Figure the R M value combines in parallel with the capacitive load pole, thus increasing the phase external Ω source impedance, yielding an effective margin and improving stability. driving impedance of Ω Ω Ω This The Typical Characteristics show the recommended impedance is added in series with R G for calculating R S versus capacitive load and the resulting the noise gain (NG). The resulting NG is 3.14V/V for frequency response at the load. Parasitic capacitive Figure as opposed to only if R M could be loads greater than 2pF can begin to degrade the eliminated as discussed previously. The bandwidth is performance of the OPA890. Long PCB traces, therefore slightly lower for the gain of 2V/V circuit of unmatched cables, and connections to multiple Figure than for the gain of +2V/V circuit of devices can easily exceed this value. Always Figure consider this effect carefully, and add the The third important consideration in inverting recommended series resistor as close as possible to amplifier design is setting the bias current the OPA890 output pin (see the Board Layout cancellation resistor on the noninverting input B If Guidelines section). this resistor is set equal to the total dc resistance looking out of the inverting node, the output dc error (because of the input bias currents) is reduced to The input-referred voltage noise, and the two (Input Offset Current) R F If the Ω source input-referred current noise terms, combine to give impedance is dc-coupled in Figure the total low output noise under a wide variety of operating resistance to ground on the inverting input is 351 Ω conditions. Figure shows the op amp noise Combining this resistance in parallel with the analysis model with all the noise terms included. In feedback resistor gives the value of R B 240 Ω used this model, all noise terms are taken to be noise in this example. To reduce the additional voltage or current density terms in either nV/ Hz or high-frequency noise introduced by this resistor, it is pA/ Hz sometimes bypassed with a capacitor. As long as R B 350 Ω a capacitor is not required because the total noise contribution of all other terms is less than that of the op amp input noise voltage. As a minimum, the OPA890 requires an R B value of Ω to damp out parasitic-induced peaking a direct short to ground on the noninverting input runs the risk of a very high-frequency instability in the input stage. Submit Documentation Feedback

www.ti.com DC ACCURACY AND OFFSET CONTROL 4kT RG RG RF RS OPA890 IBI EOIBN 4kT□=□1.6E 20J/c45 at□290 K/c176 ERS ENI 4kTRS/c214 4kTRF/c214 E O /C0043/C0466E 2 NI /C0041/C0466IBN R S/C0467 /C00414kTR S/C0467NG 2 /C0041(IBIR F) /C00414kTR FNG/C0504 E N /C0043E 2 NI /C0041/C0466IBN R S/C0467 /C00414kTR S /C0041/C0466IBIR F NG /C0467 /C00414kTR F NG /C0504 OPA890 SBOS369 MAY 2007 The balanced input stage of a wideband voltage-feedback op amp allows good output dc accuracy in a wide variety of applications. The power-supply current trim for the OPA890 gives even tighter control than comparable amplifiers. Although the high-speed input stage does require relatively high input bias current (+25 C worst case, 1.6 µ A at each input terminal), the close matching between them may be used to reduce the output dc error caused by this current. The total output offset voltage may be considerably reduced by matching the dc Figure 52. Op Amp Noise Analysis Model source resistances appearing at the two inputs. This matching reduces the output dc error resulting from The total output spot noise voltage can be computed the input bias currents to the offset current times the as the square root of the sum of all squared output feedback resistor. Evaluating the configuration of noise voltage contributors. Equation shows the Figure and using worst-case +25 C input offset general form for the output noise voltage using the voltage and current specifications, gives a terms shown in Figure worst-case output offset voltage equal to: (NG V OS(MAX) F I OS(MAX) 5mV) (750 Ω 0.35 µ (4) 11.3mV Dividing this expression by the noise gain [NG R F G gives the equivalent input-referred spot noise with NG noninverting signal gain voltage at the noninverting input, as shown in A fine-scale output offset null or dc operating point Equation adjustment is often required. Numerous techniques are available for introducing dc offset control into an op amp circuit. Most of these techniques eventually reduce to adding a dc current through the feedback (5) resistor. In selecting an offset trim method, one key consideration is the impact on the desired signal Evaluating these two equations for the OPA890 path frequency response. If the signal path is circuit and component values (see Figure gives a intended to be noninverting, the offset control is best total output spot noise voltage of 17.4nV/ Hz and a applied as an inverting summing signal to avoid total equivalent input spot noise voltage of interaction with the signal source. If the signal path is 8.7nV/ Hz This total includes the noise added by intended to be inverting, applying the offset control to the bias current cancellation resistor (175 Ω on the the noninverting input may be considered. However, noninverting input. This total input-referred spot the dc offset voltage on the summing junction will set noise voltage is only slightly higher than the 8nV/ Hz up a dc current back into the source that must be specification for the op amp voltage noise alone. considered. Applying an offset adjustment to the This result will be the case, as long as the inverting op amp input can change the noise gain impedances appearing at each op amp input are and frequency response flatness. For a dc-coupled limited to the previously recommend maximum value inverting amplifier, see Figure for one example of of 350 Ω Keeping both F R G and the an offset adjustment technique that has minimal noninverting input source impedance less than 350 Ω impact on the signal frequency response. In this satisfies both noise and frequency response flatness case, the dc offsetting current is brought into the considerations. Because the resistor-induced noise is inverting input node through resistor values that are relatively negligible, additional capacitive decoupling much larger than the signal path resistors. This across the bias current cancellation resistor B for configuration ensures that the adjustment circuit has the inverting op amp configuration of Figure is not minimal effect on the loop gain and thus, the required. frequency response. Submit Documentation Feedback

www.ti.com RF 750/c87 /c177 150mV□Output□Adjustment = = 2/c45 /c45 Power-supply□decoupling not□shown. 5k/c87 5k/c87 226/c870.1 F/c109 RG 324/c87 VI 20k/c87 10k/c87 /c45 5V +5V OPA890 +5V /c45 5V VO VO VI RF RG THERMAL ANALYSIS DISABLE OPERATION 200k/c87 2M/c87 80k/c87 IS Control /c45 SV +VS VDIS OPA890 SBOS369 MAY 2007 collector current out of Q1, turning the amplifier off. The supply current in the disable mode is only that required to operate the circuit of Figure Additional circuitry ensures that turn-on time occurs faster than turn-off time make-before-break When disabled, the output and input nodes go to a high-impedance state. If the OPA890 is operating at a gain of +1V/V, it shows a very high impedance at the output and exceptional signal isolation. If operating at a gain greater than +1V/V, the total feedback network resistance F R G appears as the impedance looking back into the output, but the circuit still shows very-high forward and reverse isolation. If configured as an inverting amplifier, the input and output are connected through the feedback network resistance F R G and the isolation is Figure 53. DC-Coupled, Inverting Gain of -2V/V, very poor, as a result. with Offset Adjustment Maximum desired junction temperature sets the maximum allowed internal power dissipation, as The OPA890 provides an optional disable feature described below. In no case should the maximum that may be used either to reduce system power or junction temperature be allowed to exceed +150 to implement a simple channel multiplexing operation. If the DIS control pin is left unconnected, Operating junction temperature J is given by T A the OPA890 operates normally. To disable the P D θ JA The total internal power dissipation D is OPA890, the control pin must be asserted low. the sum of quiescent power DQ and additional Figure shows a simplified internal circuit for the power dissipated in the output stage DL to deliver disable control feature. load power. Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. P DL depends on the required output signal and load, but for a grounded resistive load is at a maximum when the output is fixed at a voltage equal to of either supply voltage (for equal bipolar supplies). Under this condition, P DL V S /(4 R L where R L includes feedback network loading. Note that it is the power in the output stage and not into the load that determines internal power dissipation. As a worst-case example, compute the maximum T J using an OPA890IDBV (SOT23-6 package) in the circuit of Figure operating at the maximum specified ambient temperature of +85 C and driving a grounded 100 Ω load. Figure 54. Simplified Disable Control Circuit P D 10V 1.25mA /(4 (100 Ω 1.5k Ω 79mW In normal operation, base current to is provided through the Ω resistor, while the emitter current Maximum T J +85 C (79W 150 C/W) +97 through the 80k Ω resistor sets up a voltage drop that Although this result is still well below the specified is inadequate to turn on the two diodes in the maximum junction temperature, system reliability emitter. As V DIS is pulled low, additional current is considerations may require lower operating junction pulled through the 80k Ω resistor, eventually turning temperatures. The highest possible internal on those two diodes µ A). At this point, any dissipation occurs if the load requires current to be further current pulled out of V DIS goes through those forced into the output for positive output voltages, or diodes, holding the emitter-base voltage of at sourced from the output for negative output voltages. approximately 0V. This process shuts off the This configuration puts a high current through a large internal voltage drop in the output transistors. Submit Documentation Feedback

www.ti.com BOARD LAYOUT GUIDELINES Achieving optimum performance with a OPA890 SBOS369 MAY 2007 allowed, place the feedback resistor directly under the package on the other side of the board between the output and inverting input high-frequency amplifier such as the OPA890 pins. Even with a low parasitic capacitance requires careful attention to board layout parasitics shunting the external resistors, excessively and external component types. Recommendations high resistor values can create significant time that optimize performance include the following: constants that can degrade performance. Minimize parasitic capacitance to any ac Good axial metal film or surface-mount ground for all of the signal I/O pins. Parasitic resistors have approximately 0.2pF in shunt capacitance on the output and inverting input with the resistor. For resistor values 1.5k Ω pins can cause instability; on the noninverting this parasitic capacitance can add a pole input, it can react with the source impedance and/or zero below 500MHz that can effect to cause unintentional bandlimiting. To reduce circuit operation. Keep resistor values as low unwanted capacitance, a window around the as possible consistent with load driving signal I/O pins should be opened in all of the considerations. The 750 Ω feedback used in ground and power planes around those pins. the Typical Characteristics is a good starting Otherwise, ground and power planes should point for design. Note that a direct short is be unbroken elsewhere on the board. suggested for the unity-gain follower application. Minimize the distance 0.25") from the power-supply pins to high-frequency 0.1 µ F Connections to other wideband devices on decoupling capacitors. At the device pins, the the board may be made with short, direct ground and power-plane layout should not be traces or through onboard transmission lines. in close proximity to the signal I/O pins. Avoid For short connections, consider the trace and narrow power and ground traces to minimize the input to the next device as a lumped inductance between the pins and the capacitive load. Relatively wide traces (50mils decoupling capacitors. The power-supply to 100mils) should be used, preferably with connections should always be decoupled with ground and power planes opened up around these capacitors. An optional supply them. Estimate the total capacitive load and decoupling capacitor (0.1 µ across the two set R S from the plot of Recommended R S vs power supplies (for bipolar operation) will Capacitive Load Low parasitic capacitive improve 2nd-harmonic distortion performance. loads 5pF) may not need an R S because Larger (2.2 µ F to 6.8 µ decoupling capacitors, the OPA890 is nominally compensated to effective at lower frequencies, should also be operate with a 2pF parasitic load. Higher used on the main supply pins. These parasitic capacitive loads without an R S are capacitors may be placed somewhat farther allowed as the signal gain increases from the device and may be shared among (increasing the unloaded phase margin). If a several devices in the same area of the PCB. long trace is required, and the 6dB signal loss intrinsic to a doubly-terminated transmission Careful selection and placement of line is acceptable, implement a matched external components preserves the impedance transmission line using microstrip high-frequency performance of the or stripline techniques (consult an ECL design OPA890 Resistors should be a very low handbook for microstrip and stripline layout reactance type. Surface-mount resistors work techniques). A Ω environment is normally best and allow a tighter overall layout. Metal not necessary on the board, and in fact, a film or carbon composition axially-leaded higher impedance environment will improve resistors can also provide good distortion as shown in the distortion versus high-frequency performance. Again, keep the load plots. With a characteristic board trace leads and PCB traces as short as possible. impedance defined (based on board material Never use wirewound type resistors in a and trace dimensions), a matching series high-frequency application. Because the resistor into the trace from the output of the output pin and inverting input pin are the most OPA890 is used as well as a terminating sensitive to parasitic capacitance, always shunt resistor at the input of the destination position the feedback and series output device. Remember also that the terminating resistor, if any, as close as possible to the impedance is the parallel combination of the output pin. Other network components, such shunt resistor and the input impedance of the as noninverting input termination resistors, destination device; this total effective should also be placed close to the package. impedance should be set to match the trace Where double-side component mounting is Submit Documentation Feedback

www.ti.com INPUT AND ESD PROTECTION External Pin +VCC /c45VCC Internal Circuitry OPA890 SBOS369 MAY 2007 impedance. The high output voltage and current capability of the OPA890 allows The OPA890 is built using a very high-speed, multiple destination devices to be handled as complementary, bipolar process. The internal separate transmission lines, each with its junction breakdown voltages are relatively low for respective series and shunt terminations. If these very small geometry devices. These the 6dB attenuation of a doubly-terminated breakdowns are reflected in the Absolute Maximum transmission line is unacceptable, a long trace Ratings table. All device pins are protected with can be series-terminated at the source end internal ESD protection diodes to the power supplies, only. Treat the trace as a capacitive load in as shown in Figure this case, and set the series resistor value as shown in the plot of Recommended R S vs Capacitive Load This configuration does not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there will be some signal attenuation because of the voltage divider formed by the series output into the terminating impedance. Socketing a high-speed part such as the Figure 55. Internal ESD Protection OPA890 is not recommended The additional lead length and pin-to-pin capacitance introduced by the socket can These diodes provide moderate protection to input create an extremely troublesome parasitic overdrive voltages above the supplies as well. The network that can make it almost impossible to protection diodes can typically support 30mA achieve a smooth, stable frequency response. continuous current. Where higher currents are Best results are obtained by soldering the possible (for example, in systems with 15V supply OPA890 directly onto the board. parts driving into the OPA890), current-limiting series resistors should be added into the two inputs. Keep these resistor values as low as possible, because high values degrade both noise performance and frequency response. Submit Documentation Feedback

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) OPA890ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA890IDBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA890IDBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR OPA890IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 8-Jun-2007 Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 6-Jun-2007 Pack Materials-Page 1

Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant OPA890IDBVR DBV 6 MLA 180 8 6.83 7.42 1.88 8 12 Q3 OPA890IDBVT DBV 6 MLA 180 8 6.83 7.42 1.88 8 12 Q3 OPA890IDR D 8 MLA 330 12 6.9 5.4 2.0 8 12 Q1 TAPE AND REEL BOX INFORMATION Device Package Pins Site Length (mm) Width (mm) Height (mm) OPA890IDBVR DBV 6 MLA 0.0 0.0 0.0 OPA890IDBVT DBV 6 MLA 190.0 212.7 31.75 OPA890IDR D 8 MLA 342.9 336.6 28.58 PACKAGE MATERIALS INFORMATION www.ti.com 6-Jun-2007 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 6-Jun-2007 Pack Materials-Page 3

(TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for design. Customers are responsible for their products and components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. TI products are not authorized for use in safety-critical (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications. TI products are neither designed nor intended for use in military/aerospace "enhanced plastic." Only products designated by TI as military-grade meet military specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security RFID www.ti-rfid.com Telephony www.ti.com/telephony Low Power www.ti.com/lpw Video Imaging www.ti.com/video Wireless Wireless www.ti.com/wireless Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright 2007, Texas Instruments Incorporated