DDU8F-5006

DDU8F DATADELAY | Alldatasheet

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Doc #97012 DATA DELAY DEVICES, INC. 1/28/97 3 Mt. Prospect Ave. Clifton, NJ 07013 5-TAP, TTL-INTERFACED FIXED DELAY LINE (SERIES DDU8F)

FEATURES

Five equally spaced outputs Fits standard 8-pin DIP socket Low profile Auto-insertable Input & outputs fully TTL interfaced & buffered

10 T2L fan-out capability

The DDU8F-series device is a 5-tap digitally buffered delay line. The signal input (IN) is reproduced at the outputs (T1-T5), shifted in time by an amount determined by the device dash number (See Table). For dash numbers less than 5025, the total delay of the line is measured from T1 to T5. The nominal tap-to-tap delay increment is given by one-fourth of the total delay, and the inherent delay from IN to T1 is nominally 3.5ns. For dash numbers greater than or equal to 5025, the total delay of the line is measured from IN to T5. The nominal tap-to-tap delay increment is given by one-fifth of this number. SERIES SPECIFICATIONS Minimum input pulse width: 40% of total delay Output rise time: 2ns typical Supply voltage: 5VDC ± 5% Supply current: ICCL = 32ma typical ICCH = 7ma typical Operating temperature: 0° to 70° C Temp. coefficient of total delay: 100 PPM/°C 25% 25% 25% 25% VCC GND IN Functional diagram for dash numbers < 5025 3.5ns 20% 20% 20% 20% 20% VCC GND IN Functional diagram for dash numbers >= 5025 1997 Data Delay Devices data delay devices, inc. IN N/C N/C N/C GND VDD N/C N/C N/C IN GND VCC DDU8F-xx DIP DDU8F-xxA1 Gull-Wing DDU8F-xxB1 J-Lead DDU8F-xxM Military DIP Military SMD DDU8F-xxMD1 DDU8F-xxMD4 PIN DESCRIPTIONS IN Signal Input T1-T5 Tap Outputs VCC +5 Volts GND Ground DASH NUMBER SPECIFICATIONS Part Number Total Delay (ns) Delay Per Tap (ns) DDU8F-5004 4 ± 1.0 * 1.0 ± 0.5 DDU8F-5006 6 ± 1.0 * 1.5 ± 0.5 DDU8F-5008 8 ± 2.0 * 2.0 ± 1.0 DDU8F-5010 10 ± 2.0 * 2.5 ± 1.0 DDU8F-5012 12 ± 2.0 * 3.0 ± 1.0 DDU8F-5016 16 ± 2.0 * 4.0 ± 1.5 DDU8F-5020 20 ± 3.0 * 5.0 ± 2.0 DDU8F-5025 25 ± 3.0 5.0 ± 2.0 DDU8F-5030 30 ± 3.0 6.0 ± 2.0 DDU8F-5035 35 ± 3.0 7.0 ± 2.0 DDU8F-5040 40 ± 3.0 8.0 ± 2.0 DDU8F-5045 45 ± 3.0 9.0 ± 3.0 DDU8F-5050 50 ± 3.0 10.0 ± 3.0 DDU8F-5060 60 ± 3.0 12.0 ± 3.0 DDU8F-5075 75 ± 4.0 15.0 ± 3.0 DDU8F-5100 100 ± 5.0 20.0 ± 3.0 DDU8F-5125 125 ± 6.5 25.0 ± 3.0 DDU8F-5150 150 ± 7.5 30.0 ± 3.0 DDU8F-5175 175 ± 8.0 35.0 ± 4.0 DDU8F-5200 200 ± 10.0 40.0 ± 4.0 DDU8F-5250 250 ± 12.5 50.0 ± 5.0 * Total delay is referenced to first tap output Input to first tap = 3.5ns ±± 1ns NOTE: Any dash number between 5004 and 5250 not shown is also available.

Doc #97012 DATA DELAY DEVICES, INC. 1/28/97 Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com APPLICATION NOTES HIGH FREQUENCY RESPONSE The DDU8F tolerances are guaranteed for input pulse widths and periods greater than those specified in the test conditions. Although the device will function properly for pulse widths as small as 40% of the total delay and periods as small as 80% of the total delay (for a symmetric input), the delays may deviate from their values at low frequency. However, for a given input condition, the deviation will be repeatable from pulse to pulse. Contact technical support at Data Delay Devices if your application requires device testing at a specific input condition. POWER SUPPLY BYPASSING The DDU8F relies on a stable power supply to produce repeatable delays within the stated tolerances. A 0.1uf capacitor from VCC to GND, located as close as possible to the VCC pin, is recommended. A wide VCC trace and a clean ground plane should be used. DEVICE SPECIFICATIONS TABLE 1: ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL MIN MAX UNITS NOTES DC Supply Voltage VCC -0.3 7.0 V Input Pin Voltage VIN -0.3 VDD+0.3 V Storage Temperature TSTRG -55 150 C Lead Temperature TLEAD 300 C 10 sec TABLE 2: DC ELECTRICAL CHARACTERISTICS (0C to 70C, 4.75V to 5.25V) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES High Level Output Voltage VOH 2.5 3.4 V VCC = MIN, IOH = MAX VIH = MIN, VIL = MAX Low Level Output Voltage VOL 0.35 0.5 V VCC = MIN, IOL = MAX VIH = MIN, VIL = MAX High Level Output Current IOH -1.0 mA Low Level Output Current IOL 20.0 mA High Level Input Voltage VIH 2.0 V Low Level Input Voltage VIL 0.8 V Input Clamp Voltage VIK -1.2 V VCC = MIN, II = IIK Input Current at Maximum Input Voltage IIHH 0.1 mA VCC = MAX, VI = 7.0V High Level Input Current IIH µA VCC = MAX, VI = 2.7V Low Level Input Current IIL -0.6 mA VCC = MAX, VI = 0.5V Short-circuit Output Current IOS -60 -150 mA VCC = MAX Output High Fan-out Unit Output Low Fan-out 12.5 Load

Doc #97012 DATA DELAY DEVICES, INC. 1/28/97 3 Mt. Prospect Ave. Clifton, NJ 07013 PACKAGE DIMENSIONS .500 MAX. .290 MAX. .015 TYP. .070 MAX. .018 TYP. .300±.010

3 Equal spaces

each .100±.010 Non-Accumulative .280 MAX. .350 MAX. .010±.002 Lead Material: Nickel-Iron alloy 42 TIN PLATE DDU8F-xx (Commercial DIP) .180 TYP. .500 MAX. .290 MAX. .020 TYP. .440 MAX. .300 TYP. .010 TYP. .300 TYP. .020 TYP. DDU8F-xxM (Military DIP) .520 MAX. .430 TYP. .020 TYP. .040 TYP. .100 .110 .300 .300 MAX. .270 TYP. .010 TYP. .050 TYP. DDU8F-xxA1 (Commercial Gull-Wing) .520 MAX. .320 TYP. .020 TYP. .040 TYP. .100 .110 .300 .350 MAX. .270 TYP. .050 TYP. .110 TYP. DDU8F-xxB1 (Commercial J-Lead) .510 MAX. .510 MAX. .300 TYP. .017 .050 .100 .100 .300 .300 .008 .045 .025 .360 TYP. .065 TYP. .065 TYP. .200 MAX. (Com) .225 MAX. (Mil) DDU8F-xxD1 (Commercial SMD) DDU8F-xxMD1 (Military SMD) .080 .080 .510 MAX. .510 MAX. .017 .050 .300 TYP. .100 .100 .650 .008 .005 .065 TYP. .360 TYP. .065 TYP. DDU8F-xxD4 (Commercial SMD) DDU8F-xxMD4 (Military SMD) .200 MAX. (Com) .225 MAX. (Mil)

Doc #97012 DATA DELAY DEVICES, INC. 1/28/97 Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com DELAY LINE AUTOMATED TESTING TEST CONDITIONS INPUT: OUTPUT: Ambient Temperature: 25oC ± 3oC Load:

1 FAST-TTL Gate

Supply Voltage (Vcc): 5.0V ± 0.1V Cload: 5pf ± 10% Input Pulse: High = 3.0V ± 0.1V Threshold: 1.5V (Rising & Falling) Low = 0.0V ± 0.1V Source Impedance: 50Ω Max. Rise/Fall Time: 3.0 ns Max. (measured between 0.6V and 2.4V ) Pulse Width: PWIN = 1.5 x Total Delay Period: PERIN = 10 x Total Delay NOTE: The above conditions are for test only and do not in any way restrict the operation of the device. OUT TRIG IN REF TRIG Test Setup DEVICE UNDER TEST (DUT) TIME INTERVAL COUNTER PULSE GENERATOR COMPUTER SYSTEM PRINTER IN Timing Diagram For Testing TRISE TFALL PERIN PWIN TRISE TFALL 0.6V 0.6V 1.5V 1.5V 2.4V 2.4V 1.5V 1.5V VIH VIL VOH VOL INPUT SIGNAL OUTPUT SIGNAL