DDU222C DATADELAY | Alldatasheet

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Doc #97014 DATA DELAY DEVICES, INC. 1/28/97 3 Mt. Prospect Ave. Clifton, NJ 07013 5-TAP, HCMOS-INTERFACED FIXED DELAY LINE (SERIES DDU222C)

FEATURES

Five equally spaced outputs Very narrow device (SIP package) Stackable for PC board economy Input & outputs fully CMOS interfaced & buffered

10 T2L fan-out capability

The DDU222C-series device is a 5-tap digitally buffered delay line. The signal input (IN) is reproduced at the outputs (T1-T5), shifted in time by an amount given by the device dash number. For dash numbers less than 40, the total delay of the line is measured from T1 to T5, with the nominal value given by the dash number. The nominal tap-to-tap delay increment is given by 1/4 of this number. The inherent delay from IN to T1 is nominally 8.0ns. For dash numbers greater than or equal to 40, the total delay of the line is measured from IN to T5, with the nominal value given by the dash number. The nominal tap-to-tap delay increment is given by 1/5 of this number. SERIES SPECIFICATIONS Minimum input pulse width: 40% of total delay Output rise time: 8ns typical Supply voltage: 5VDC ± 5% Supply current: ICCL = 40µa typical ICCH = 10ma typical Operating temperature: 0° to 70° C Temp. coefficient of total delay: 300 PPM/°C 25% 25% 25% 25% VCC GND IN Functional diagram for dash numbers < 40 8.0ns 20% 20% 20% 20% 20% VCC GND IN Functional diagram for dash numbers >= 40 1997 Data Delay Devices data delay devices, inc. VCC IN T1 T2 T3 T4 T5 GND DDU222F-xx Commercial DDU222F-xxM Military PIN DESCRIPTIONS IN Signal Input T1-T5 Tap Outputs VDD +5 Volts GND Ground DASH NUMBER SPECIFICATIONS Part Number Total Delay (ns) Delay Per Tap (ns) DDU222C-10 10 ± 2.0 * 2.5 ± 1.0 DDU222C-20 20 ± 2.0 * 5.0 ± 2.0 DDU222C-50 50 ± 3.0 10.0 ± 3.0 DDU222C-60 60 ± 3.0 12.0 ± 3.0 DDU222C-75 75 ± 4.0 15.0 ± 3.0 DDU222C-100 100 ± 5.0 20.0 ± 3.0 DDU222C-125 125 ± 6.5 25.0 ± 3.0 DDU222C-150 150 ± 7.5 30.0 ± 3.0 DDU222C-175 175 ± 8.0 35.0 ± 4.0 DDU222C-200 200 ± 10.0 40.0 ± 4.0 DDU222C-250 250 ± 12.5 50.0 ± 5.0 * Total delay is referenced to first tap output Input to first tap = 8.0ns ±± 2ns NOTE: Any dash number between 10 and 250 not shown is also available.

Doc #97014 DATA DELAY DEVICES, INC. 1/28/97 Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com APPLICATION NOTES HIGH FREQUENCY RESPONSE The DDU222C tolerances are guaranteed for input pulse widths and periods greater than those specified in the test conditions. Although the device will function properly for pulse widths as small as 40% of the total delay and periods as small as 80% of the total delay (for a symmetric input), the delays may deviate from their values at low frequency. However, for a given input condition, the deviation will be repeatable from pulse to pulse. Contact technical support at Data Delay Devices if your application requires device testing at a specific input condition. POWER SUPPLY BYPASSING The DDU222C relies on a stable power supply to produce repeatable delays within the stated tolerances. A 0.1uf capacitor from VDD to GND, located as close as possible to the VDD pin, is recommended. A wide VDD trace and a clean ground plane should be used. DEVICE SPECIFICATIONS TABLE 1: ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL MIN MAX UNITS NOTES DC Supply Voltage VDD -0.3 7.0 V Input Pin Voltage VIN -0.3 VDD+0.3 V Storage Temperature TSTRG -55 150 C Lead Temperature TLEAD 300 C 10 sec TABLE 2: DC ELECTRICAL CHARACTERISTICS (0C to 70C, 4.75V to 5.25V) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES High Level Output Voltage VOH 3.98 4.4 V VDD = 5.0, IOH = MAX VIH = MIN, VIL = MAX Low Level Output Voltage VOL 0.15 0.26 V VDD = 5.0, IOL = MAX VIH = MIN, VIL = MAX High Level Output Current IOH -4.0 mA Low Level Output Current IOL 4.0 mA High Level Input Voltage VIH 3.15 V Low Level Input Voltage VIL 1.35 V Input Current IIH 0.10 µA VDD = 5.0

Doc #97014 DATA DELAY DEVICES, INC. 1/28/97 3 Mt. Prospect Ave. Clifton, NJ 07013 PACKAGE DIMENSIONS .300 MAX. .100 MIN. .900 MAX. .200 MAX. .020 TYP. .020 TYP. .700 TYP. .100 TYP. .010 TYP. DDU222C-xx (Commercial) .375 MAX. .150 ±.030 .005 MIN. .018 TYP. .700 TYP. .100 TYP. .010 TYP. .900 MAX. .200 MAX. DDU222C-xxM (Military)

Doc #97014 DATA DELAY DEVICES, INC. 1/28/97 Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com DELAY LINE AUTOMATED TESTING TEST CONDITIONS INPUT: OUTPUT: Ambient Temperature: 25oC ± 3oC Load:

1 FAST-TTL Gate

Supply Voltage (VDD): 5.0V ± 0.1V Cload: 5pf ± 10% Input Pulse: High = 5.0V ± 0.1V Threshold: 2.5V (Rising & Falling) Low = 0.0V ± 0.1V Source Impedance: 50Ω Max. Rise/Fall Time: 5.0 ns Max. (measured between 0.5V and 4.5V ) Pulse Width: PWIN = 1.5 x Total Delay Period: PERIN = 10 x Total Delay NOTE: The above conditions are for test only and do not in any way restrict the operation of the device. OUT TRIG IN REF TRIG Test Setup DEVICE UNDER TEST (DUT) TIME INTERVAL COUNTER PULSE GENERATOR COMPUTER SYSTEM PRINTER IN 0.5V 0.5V Timing Diagram For Testing TRISE TFALL PERIN PWIN TRISE TFALL 2.5V 2.5V 4.5V 4.5V 2.5V 2.5V VIH VIL VOH VOL INPUT SIGNAL OUTPUT SIGNAL