DDU-7J DATADELAY | Alldatasheet
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Digital Delay Units ata \\73 | delay \\~ series DDU-7J 10 Taps (14 pins DIP) | GeVICESY inc. T’L Interfaced i 19 i e HAA oo" , (Commercial Type) Features: } | = Completely interfaced for TTL and DTL \\ | application ; = No external components required . = P.C. board space economy achieved = Fits standard 14 pins DIP socket Test Conditions: = Operates over commercial temperature = Input Pulse Width: = 150% of total delay. range = Time delay measured @ 1.5 V on rising edge. ag: = Unless otherwise specified all time-delays are Specifications: referenced to input of delay line. ' IB No. Taps: 10 equally spaced taps : Rise-time is measured from .75 V to 2.4 V of ™@ Total Delay Tolerance: +5% or better, or BAT ing edge. ts made @ V » <5V:Ta = #25°C. 2 ns whichever is greater. measurements made @ V ce =SV; Ta = . lf Rise-time: 4 ns typically @ Temperature coefficient: 100 PPM/°C. li Temperature range: 0° to +70°C i Supply voltage: 4.5 to 5.5 Vde. 1 Logic 1 input current: 100 ja max. —| le 180 @ Logic 0 input current: — 4 ma. max. Mi Logic 1 V out: 2.5 V min. + - i Logic 0 V out: 0.5 V max. ane 300 @ Logic 1 Fan-out: 20/tap max. 4. + @ Logic 0 Fan-out: 10/tap max. i ‘290 010 f ™@ Power Dissipation: 740 mw max. Le 890 MAX —*) =| i ovo Total Delay 020 Delay Per Tap ioe (ns) (ns) soo sttoo Fo *DDU-75-10 9 1:4 *DDU-7J-20 18 2465 Tow 1 2 3 4 5 6 7 8 39 10 *DDU-7J-25 22.5 254.7 Poe 19 3 12 4 1 5 1 6 8 8 *DDU-7-50 45 5.0215 DDU-75-100 100 10.02 2 ve prot - oo --45 DDU-7J-150 150 150+ 2 o———_o I DDU-7J-250 250 25.0 + 2 | { DDU-7J-300 300 30.04 3 rol ag! DDU-7J-400 400 400+ 4 Ao | [ ' DDU-7J-500 500 50.0+ 5 a aaa +. ! * Time delay referenced to 1st tap. Two (2) gates in parallel for input | buffer. | 3 Mt. Prospect Avenue, Clifton, New Jersey 07013 = (201) 773-2299 = FAX (201) 773-9672 = TWX 710-989-7008