DDC114 BURR-BROWN | Alldatasheet
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Technical content
FEATURES
/C0068SINGLE-CHIP SOLUTION TO DIRECTLY MEASURE FOUR LOW-LEVEL CURRENTS /C0068HIGH PRECISION, TRUE INTEGRATING FUNCTION /C0068INTEGRAL LINEARITY: ±0.01% of Reading ±0.5ppm of FSR /C0068VERY LOW NOISE: 5.2ppm of FSR /C0068LOW POWER: 13.5mW/channel /C0068ADJUSTABLE DATA RATE: Up to 3.125kSPS /C0068PROGRAMMABLE FULL SCALE /C0068DAISY-CHAINABLE SERIAL INTERFACE
APPLICATIONS
/C0068CT SCANNER DAS /C0068PHOTODIODE SENSORS /C0068INFRARED PYROMETER /C0068LIQUID/GAS CHROMATOGRAPHY Protected by US Patent #5841310 Dual Switched Integrator Dual Switched Integrator Modulator Digital Filter Digital Input/Output FORMAT DCLK DCLK DVALID DOUT DOUT DIN DIN Control IN3 IN1 VREF DVDDAVDD DGNDAGND Dual Switched Integrator Dual Switched Integrator Modulator Digital Filter IN4 IN2 CLK CONV RANGE0 RANGE1 RANGE2 TEST CLK_4X HISPD/LOPWR RESET
DESCRIPTION
The DDC114 is a 20-bit quad channel, current-input analog-to-digital (A/D) converter. It combines both current-to-voltage and A/D conversion so that four low-level current output devices, such as photodiodes, can be directly connected to its inputs and digitized. For each of the four inputs, the DDC114 provides a dual-switched integrator front-end. This allows for continuous current integration: while one integrator is being digitized by the onboard A/D converter, the other is integrating the input current. Adjustable full-scale ranges from 12pC to 350pC and adjustable integration times from 50µs to 1s allow currents from fAs to µAs to be measured with outstanding precision. Low-level linearity is ±0.5ppm of the full-scale range and noise is 5.2ppm of the full-scale range. Two modes of operation are provided. In Low-Power mode, total power dissipation is only 13.5mW per channel with a maximum data rate of 2.5kSPS. The High-Speed mode supports data rates up to 3.125kSPS with a corresponding dissipation of 18mW per channel. The DDC114 has a serial interface designed for daisy-chaining in multi-device systems. Simply connect the output of one device to the input of the next to create the chain. Common clocking feeds all the devices in the chain so that the digital overhead in a multi-DDC114 system is minimal. The DDC114 is a single-supply device using a +5V analog supply and supporting a +2.7V to +5.25V digital supply. Operating over the industrial temperature range of −40°C to 85°C, the DDC114 is offered in a QFN-48 package. DDC114 SBAS255A − JUNE 2004 − REVISED NOVEMBER 2004 Quad Current Input 20-Bit ANALOG-TO-DIGITAL CONVERTER www.ti.com Copyright 2004, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046
/C0068/C0068/C0067/C0049/C0049/C0052 SBAS255A − JUNE 2004 − REVISED NOVEMBER 2004 www.ti.com PACKAGE/ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet. ABSOLUTE MAXIMUM RATINGS (1) (1)Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
/C0068/C0068/C0067/C0049/C0049/C0052 SBAS255A − JUNE 2004 − REVISED NOVEMBER 2004 www.ti.com
ELECTRICAL CHARACTERISTICS
At TA = +25°C, AVDD = +5V, DVDD = 3V, VREF = +4.096V, Range 5 (250pC), and continuous mode operation, unless otherwise noted. Low-Power Mode: TINT = 400µs and CLK = 4MHz; High-Speed Mode: TINT = 320µs and CLK = 4.8MHz. Low-Power Mode High-Speed Mode PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNITS ANALOG INPUT RANGE Range 0 10.2 12 13.8 ∗(1) ∗ ∗ pC Range 1 47.5 50 52.5 ∗ ∗ ∗ pC Range 2 95 100 105 ∗ ∗ ∗ pC Range 3 142.5 150 157.5 ∗ ∗ ∗ pC Range 4 190 200 210 ∗ ∗ ∗ pC Range 5 237.5 250 262.5 ∗ ∗ ∗ pC Range 6 285 300 315 ∗ ∗ ∗ pC Range 7 332.5 350 367.5 ∗ ∗ ∗ pC Negative Full-Scale Range −0.4% of Positive Full-Scale Range ∗ pC Input Current(2) 750 ∗ 1µΑ DYNAMIC CHARACTERISTICS Data Rate 2.5 3.125 kSPS Integration Time, TINT Continuous Mode 400 1,000,000 320 ∗ µS Integration Time, TINT Noncontinuous Mode, Range 1 to 7 50 ∗ µS System Clock Input (CLK) CLK_4X = 0 4 4.8 MHz CLK_4X = 1 16 19.2 MHz Data Clock (DCLK) 16 ∗ MHz ACCURACY Noise, Low-Level Input(3) C SENSOR (4) = 50pF, Range 5 (250pC) 5.2 6.5 5.5 7 ppm of FSR (5), rms Integral Linearity Error(6) ±0.01% Reading ± 0.5ppm FSR, typ ∗ Integral Linearity Error(6) ±0.025% Reading ± 1.0ppm FSR, max ∗ Resolution FORMA T = 1 20 ∗ BitsResolution FORMA T = 0 16 ∗ Bits Input Bias Current 0.1 10 ∗ ∗ pA Range Error Match(7) All Ranges 0.1 0.5 ∗ ∗ % of FSR Range Sensitivity to VREF VREF = 4.096 ± 0.1V 1:1 ∗ Offset Error ±400 ±1000 ∗ ∗ ppm of FSR Offset Error Match(7) ±100 ∗ ppm of FSR DC Bias Voltage(9) ±0.05 ±2 ∗ ∗ mV Power-Supply Rejection Ratio at dc ±25 ±200 ∗ ∗ ppm of FSR/V Internal Test Signal 11 ∗ pC Internal Test Accuracy ±10 ∗ % PERFORMANCE OVER TEMPERA TURE Offset Drift ±0.5 ±3(8) ∗ ∗ ppm of FSR/°C Offset Drift Stability ±0.2 ±1(8) ∗ ∗ ppm of FSR/ minute DC Bias Voltage Drift(9) 3 ∗ µV/°C Input Bias Current Drift TA = +25°C to +45°C 0.01 1(8) ∗ ∗ pA/°C Range Drift(10) 25 ∗ ppm/°C Range Drift Match(7) ±0.05 ∗ ppm/°C REFERENCE Voltage 4.000 4.096 4.200 ∗ ∗ ∗ V Input Current(11) Average Value 75 95 µA (1)∗ indicates specification is the same as Low-Power Mode. (2)Exceeding maximum input current specification may damage device. (3)Input is less than 1% of full scale. (4)C SENSOR is the capacitance seen at the DDC114 inputs from wiring, photodiode, etc. (5)FSR is Full-Scale Range. (6)A best-fit line is used in measuring nonlinearity. (7)Matching between side A and side B of the same input. (8)Ensured by design, not production tested. (9)Voltage produced by the DDC114 at its input which is applied to the sensor. (10)Range drift does not include external reference drift. (11)Input reference current decreases with increasing TINT (see the Voltage Reference section, page 11).
/C0068/C0068/C0067/C0049/C0049/C0052 SBAS255A − JUNE 2004 − REVISED NOVEMBER 2004 www.ti.com ELECTRICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = +5V, DVDD = 3V, VREF = +4.096V, Range 5 (250pC), and continuous mode operation, unless otherwise noted. Low-Power Mode: TINT = 400µs and CLK = 4MHz; High-Speed Mode: TINT = 320µs and CLK = 4.8MHz. High-Speed ModeLow-Power Mode PARAMETER UNITSMAXTYPMINMAXTYPMINTEST CONDITIONS DIGITAL INPUT/OUTPUT Logic Levels VIH 0.8DVDD DVDD + 0.1 ∗ ∗ V VIL − 0.1 0.2DVDD ∗ ∗ V VOH IOH = −500µA DVDD − 0.4 V VOL IOL = 500µA 0.4 ∗ V Input Current (IIN) 0 < VIN < DVDD ±10 ∗ µA Data Format(12) Straight Binary ∗ POWER-SUPPL Y REQUIREMENTS Analog Power-Supply Voltage (AVDD) 4.75 5.25 ∗ ∗ V Digital Power-Supply Voltage (DVDD) 2.7 5.25 ∗ ∗ V Supply Current Total Analog Current 10.5 14.0 mA Total Digital Current DVDD = +3V 0.5 0.67 mA Total Power Dissipation DVDD = +3V 54 75 72 100 mW Total Power Dissipation per Channel DVDD = +3V 13.5 18.75 18 25 mW (12)Data format is Straight Binary with a small offset. The number of bits in the output word is controlled by the FORMAT pin (see text).
/C0068/C0068/C0067/C0049/C0049/C0052 SBAS255A − JUNE 2004 − REVISED NOVEMBER 2004 www.ti.com PIN CONFIGURATIONS Top View QFN DIN DIN NC NC RESET TEST DGND DGND AGND AVDD AGND AGND DGND DGND CONV DGND DVALID DGND CLK DGND DCLK DCLK DGND DVDD AGND AGND AIN4 AGND AIN3 AGND AGND AGND AIN2 AGND AIN1 AGND DOUT DOUT CLK_4X FORMAT HISPD/LOPWR RANGE0 RANGE1 RANGE2 AGND VREF AGND AGND 48 47 46 45 44 43 42 41 40 39 38 13 14 15 16 17 18 19 20 21 22 23 DDC114 PIN DESCRIPTIONS PIN NUMBER FUNCTION DESCRIPTION DOUT 1 Digital Output Serial Data Output DOUT 2 Digital Output Serial Data Output: Complementary Signal CLK_4X 3 Digital Input Master Clock Divider Control: 0 = divide by 1, 1 = divide by 4 FORMAT 4 Digital Input Digital Output Word Format: 0 = 16 Bits, 1 = 20 Bits HISPD/LOPWR 5 Digital Input Mode Control: 0 = Low Power, 1 = High Speed RANGE0 6 Digital Input Range Control 0 (least significant bit) RANGE1 7 Digital Input Range Control 1 RANGE2 8 Digital Input Range Control 2 (most significant bit) AGND 9, 11-14, 16, 18-20, 22, 24-26, 28 Analog Analog Ground VREF 10 Analog Input External Voltage Reference Input, 4.096V Nominal AIN4 15 Analog Input Analog Input 4 AIN3 17 Analog Input Analog Input 3 AIN2 21 Analog Input Analog Input 2 AIN1 23 Analog Input Analog Input 1 AVDD 27 Analog Analog Power Supply, 5V Nominal DGND 29, 30, 38, 41, 43, 45, 47, 48 Digital Digital Ground TEST 31 Digital Input Test Mode Control RESET 32 Digital Input Resets the Digital Circuitry, Active Low NC 33, 34 — No Connection DIN 35 Digital Input Serial Data Input: Complementary Signal (optional, see text on page 13) DIN 36 Digital Input Serial Data Input DVDD 37 Digital Digital Power Supply, 3V Nominal DCLK 39 Digital Input Serial Data Clock Input: Complementary Signal (optional, see text on page 13) DCLK 40 Digital Input Serial Data Clock Input CLK 42 Digital Input Master Clock Input DVALID 44 Digital Output Data Valid Output, Active Low CONV 46 Digital Input Conversion Control Input: 0 = Integrate on Side B, 1 = Integrate on Side A
/C0068/C0068/C0067/C0049/C0049/C0052 SBAS255A − JUNE 2004 − REVISED NOVEMBER 2004 www.ti.com TYPICAL CHARACTERISTICS At TA = +25°C, characterization done with Range 5 (250pC), AVDD = +5V, DVDD = 3V, VREF = +4.096V, Low Power Mode: TINT = 400µs and CLK = 4MHz, unless otherwise noted. NOISE vs CSENSOR 100 40005 0 0 300200 C SENSOR (pF) N o i s e( p p mo fF S R ,r m s ) Range 1 Range 2 Range 7 NOISE vs TINT 1 10000.1 100 10 TINT (µs) Noise (ppm of FSR, rms) C SENSOR = 50pF C SENSOR =0 p F Range 5 NOISE vs TEMPERATURE −40 −15 10 35 60 85 Temperature (/C0095C) Noise (ppm of FSR, rms) C SENSOR =5 0 p F Range 1 Range 3Range 2 Range 7 NOISE vs CSENSOR C SENSOR (pF) 100 150 200 300 500 Range 23.6 30.8 36.3 41.3 46.1 57.0 68.1 89.3 134.0 Range 7.3 10.4 12.3 14.4 16.0 18.8 21.7 27.7 38.9 Range 5.2 6.7 8.2 8.9 10.0 11.9 13.5 16.3 22.4 Range 4.4 5.5 6.5 7.2 8.0 9.2 10.2 12.5 16.6 Range 4.2 4.9 5.6 6.0 6.7 7.8 8.6 10.6 13.5 Range 4.0 4.5 5.1 5.4 5.9 6.8 7.6 9.0 11.7 Range 3.8 4.3 4.8 5.1 5.4 6.1 6.8 8.1 10.4 Range 3.7 4.1 4.4 4.7 5.0 5.7 6.4 7.4 9.5 NOISE vs INPUT LEVEL 20 3010 800 100 60 70 9040 50 Input Level (% of Full−Scale) Noise (ppm of FSR, rms) C SENSOR = 50pF C SENSOR = 0pF Range 5 RANGE DRIFT vs TEMPERATURE −40 −15 10 35 60 85 Temperature (/C0095C) Range Drift (ppm) 2000 1500 1000 500 −500 −1000 −1500 −2000 All Ranges
/C0068/C0068/C0067/C0049/C0049/C0052 SBAS255A − JUNE 2004 − REVISED NOVEMBER 2004 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, characterization done with Range 5 (250pC), AVDD = +5V, DVDD = 3V, VREF = +4.096V, Low Power Mode: TINT = 400µs and CLK = 4MHz, unless otherwise noted. IB vs TEMPERATURE 25 35 45 55 65 75 85 Temperature (/C0095C) IB (pA) 0.1 0.01 All Ranges ANALOG SUPPLY CURRENT vs TEMPERATURE −40 −15 10 35 60 85 Temperature (/C0095C)Temperature (/C0095C) Current (mA) Low−Power Mode POWER CONSUMPTION HISTOGRAM 12.00 12.25 12.50 12.75 13.00 13.25 13.50 13.75 14.00 14.25 14.50 14.75 15.00 15.25 15.50 15.75 16.00 Power per Channel (mW) Occurences (%) Low−Power ModeData collected from multiple lots. OFFSET DRIFT vs TEMPERATURE 25 35 45 55 65 75 85 Temperature (/C0095C) Offset Drift (ppm of FSR) 100 −50 −100 DIGITAL SUPPLY CURRENT vs TEMPERATURE 1.2 1.0 0.8 0.6 0.4 0.2 −40 −15 10 35 60 85 Temperature (/C0095C) Current (mA) DVDD = 3V DVDD = 5V Low Power− Mode OFFSET DRIFT OVER TIME HISTOGRAM 600 500 400 300 200 100 Offset Drift (ppm of FSR/minute) Occurences Range 5Repeated measurement of offset drift over a one minute interval.
and should not be used as an exact timing tool for design. SREF2 , and SRESET are set (see Figure 4). Figure 3. Basic Integration Configuration for Input 1, Shown with a 250pC (CF = 62.5pF) Input Range
cases where a large number of converters are needed. designed to drive DIN. If not using DOUT, leave it floating. shifted out or while CONV is transitioning. Table 3. CLK_4X Pin Operation sponding typical power of 18.0mW/channel. Table 4. HISPD/LOPWR Pin Operation internal clock divided down from the system clock CLK. signal will have a random phase relationship with CONV. Figure 9. Reset Timing INT to be adjusted in steps of 62.5ns.
of the two sides of each input. Table 5. State Descriptions
1 Ncont Complete m/r/az of side A, then side B (if previous
2 Ncont Prepare side A for integration. 4 Cont Integrate on side B; m/r/az on side A. 5 Cont Integrate on side A; m/r/az on side B. 7 Ncont Prepare side B for integration.
8 Ncont Complete m/r/az of side B, then side A (if previous
6 CONV
Figure 10. State Diagram integrating when the other side finishes its integration. and 6, only perform an integration (no m/r/az cycle). the integrations always alternate between sides A and B. relationship during the ncont mode. state is either 1 or 8, depending on the initial level of CONV. For CONV held high at power-up, the beginning state is 1.
Figure 12. Timing Diagram of the Internal Operation in Continuous Mode of the DDC114 Table 7. Timing for the Internal Operation in the Continuous Mode
- When the m/r/az cycles are
Figure 13. Non-Continuous Mode Timing
0.4% of the positive full−scale. Table 9. Ideal Output Code(1) vs Input Signal (1)Excludes the effects of noise, INL, offset, and gain errors. multichannel systems requiring only 16 bits of resolution.
Figure 22. Timing Diagram When Using the DIN Function of the DDC114 Table 11. Timing for the DDC114 Data Retrieval Using DIN and finishes before CONV toggles; as shown in Figure 23. NOTE: 64τDCLK is for FORMAT = low. NOTE: 64τDCLK is for FORMAT = low.
- (or 52 for FORMAT = low)
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) DDC114IRTCR ACTIVE QFN RTC 48 2500 Pb-Free (RoHS) CU SN Level-3-260C-168 HR DDC114IRTCT ACTIVE QFN RTC 48 250 Pb-Free (RoHS) CU SN Level-3-260C-168 HR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - May not be currently available - please checkhttp://www.ti.com/productcontentfor the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 14-Dec-2004 Addendum-Page 1
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