DDC112U/1K

DDC112_V01 TI | Alldatasheet

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ANALOG-TO-DIGITAL CONVERTER

FEATURES

G MONOLITHIC CHARGE MEASUREMENT A/D CONVERTER G DIGITAL FILTER NOISE REDUCTION: 3.2ppm, rms G INTEGRAL LINEARITY: ±0.005% Reading ±0.5ppm FSR G HIGH PRECISION, TRUE INTEGRATING FUNC- TION G PROGRAMMABLE FULL-SCALE G SINGLE SUPPLY G CASCADABLE OUTPUT

APPLICATIONS

G DIRECT PHOTOSENSOR DIGITIZATION G CT SCANNER DAS G INFRARED PYROMETER G PRECISION PROCESS CONTROL G LIQUID/GAS CHROMATOGRAPHY G BLOOD ANALYSIS

DESCRIPTION

The DDC112 is a dual input, wide dynamic range, charge- digitizing analog-to-digital (A/D) converter with 20-bit resolu- tion. Low-level current output devices, such as photosensors, can be directly connected to its inputs. Charge integration is continuous as each input uses two integrators; while one is being digitized, the other is integrating. For each of its two inputs, the DDC112 combines current-to- voltage conversion, continuous integration, programmable full-scale range, A/D conversion, and digital filtering to achieve a precision, wide dynamic range digital result. In addition to the internal programmable full-scale ranges, external integrat- ing capacitors allow an additional user-settable full-scale range of up to 1000pC. To provide single-supply operation, the internal A/D converter utilizes a differential input, with the positive input tied to V REF . When the integration capacitor is reset at the beginning of each integration cycle, the capacitor charges to V REF . This charge is removed in proportion to the input current. At the end of the integration cycle, the remaining voltage is com- pared to V REF . The high-speed serial shift register which holds the result of the last conversion can be configured to allow multiple DDC112 units to be cascaded, minimizing interconnections. The DDC112 is available in an SO-28 or TQFP-32 package and is offered in two performance grades. Protected by US Patent #5841310 Dual Switched Integrator Dual Switched Integrator Modulator Digital Filter Control Digital Input/Output DVALID DXMIT DOUT DIN DCLK RANGE2 RANGE1 RANGE0 TEST CONV CLK CAP1A CAP1A CAP1B CAP1B CAP2A CAP2ACAP2B CAP2B IN2 IN1 VREF DGNDDV DDAGNDAV DD CHANNEL 1 CHANNEL 2 SBAS085B – JANUARY 2000 – REVISED OCTOBER 2004 DDC112 DDC112 www.ti.com PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2000-2004, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners.

SBAS085Bwww.ti.com NOTE: (1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. ABSOLUTE MAXIMUM RATINGS (1) PACKAGE/ORDERING INFORMATION (1) MAXIMUM SPECIFICATION INTEGRAL TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT LINEARITY ERROR RANGE PACKAGE-LEAD DESIGNATOR NUMBER (2) MEDIA DDC112U ±0.025% Reading ±1.0ppm FSR –40°C to +85°C SO-28 DW DDC112U Rails """ " " DDC112U/1K Tape and Reel DDC112UK ±0.025% Reading ±1.0ppm FSR 0°C to +70°C SO-28 DW DDC112UK Rails """ " " DDC112UK/1K Tape and Reel DDC112Y ±0.025% Reading ±1.0ppm FSR –40°C to +85°C TQFP-32 PJT DDC112Y/250 Tape and Reel """ " " DDC112Y/2K Tape and Reel DDC112YK ±0.025% Reading ±1.0ppm FSR 0 °C to +70°C TQFP-32 PJT DDC112YK/250 Tape and Reel """ " " DDC112YK/2K Tape and Reel NOTES: (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet. (2) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (/1K indicates 1000 devices per reel). Ordering 1000 pieces of DDC112U/1K will get a single 1000- piece Tape and Reel. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instru- ments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

SBAS085B www.ti.com

ELECTRICAL CHARACTERISTICS

At TA = +25°C, AVDD = DVDD = +5V, DDC112U, Y: TINT = 500µs, CLK = 10MHz, DDC112UK, YK: TINT = 333.3µs, CLK = 15MHz, VREF = +4.096V, continuous mode operation, and internal integration capacitors, unless otherwise noted. ✻ Specifications same as DDC112U, Y. NOTES: (1) Input is less than 1% of full scale. (2) CSENSOR is the capacitance seen at the DDC112 inputs from wiring, photodiode, etc. (3) FSR is Full-Scale Range. (4) A best-fit line is used in measuring linearity. (5) Matching between side A and side B, not input 1 to input 2. (6) Voltage produced by the DDC112 at its input which is applied to the sensor. (7) Range drift does not include external reference drift. (8) Input reference current decreases with increasing TINT (see the Voltage Reference section). (9) Data format is Straight Binary with a small offset (see the Data Retrieval section). (10) Ensured by design but not production tested. DDC112U, Y DDC112UK, YK PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS ANALOG INPUTS External, Positive Full-Scale Range 0 C EXT = 250pF 1000 ✻ pC Internal, Positive Full-Scale Range 1 47.5 50 52.5 ✻✻ ✻ pC Range 2 95 100 105 ✻✻ ✻ pC Range 3 142.5 150 157.5 ✻✻ ✻ pC Range 4 190 200 210 ✻✻ ✻ pC Range 5 237.5 250 262.5 ✻✻ ✻ pC Range 6 285 300 315 ✻✻ ✻ pC Range 7 332.5 350 367.5 ✻✻ ✻ pC Negative Full-Scale Input –0.4% of Positive FS ✻ pC DYNAMIC CHARACTERISTICS Conversion Rate 2 3 kHz Integration Time, TINT Continuous Mode 500 1,000,000 333.3 ✻ µs Integration Time, TINT Non-Continuous Mode 50 ✻ µs System Clock Input (CLK) 1 10 12 ✻✻ 15 MHz Data Clock (DCLK) 12 15 MHz ACCURACY Noise, Low-Level Current Input(1) CSENSOR (2) = 0pF, Range 5 (250pC) 3.2 ✻ ppm of FSR(3), rms C SENSOR = 25pF, Range 5 (250pC) 3.8 ✻ ppm of FSR, rms C SENSOR = 50pF, Range 5 (250pC) 4.2 6.0 ✻ 7 ppm of FSR, rms Differential Linearity Error ±0.005% Reading ±0.5ppm FSR (max) ✻ Integral Linearity Error(4) ±0.005% Reading ±0.5ppm FSR (typ) ✻ ±0.025% Reading ±1.0ppm FSR (max) ✻ No Missing Codes 20 ✻ Bits Input Bias Current T A = +25°C 0.1 10 ✻✻ pA Range Error Range 5 (250pC) 5 ✻ % of FSR Range Error Match(5) All Ranges 0.1 0.5 ✻✻ % of FSR Range Sensitivity to VREF VREF = 4.096 ±0.1V 1:1 ✻ Offset Error Range 5, (250pC) ±200 ✻ ±600 ppm of FSR Offset Error Match(5) ±100 ✻ ppm of FSR DC Bias Voltage(6) (Input VOS ) ±0.05 ±2 ✻✻ mV Power-Supply Rejection Ratio ±25 ±200 ✻✻ ppm of FSR/V Internal Test Signal 13 ✻ pC Internal Test Accuracy ±10 ✻ % PERFORMANCE OVER TEMPERATURE Offset Drift ±0.5 ±3(10) ppm of FSR/°C Offset Drift Stability ±0.2 ✻ ±0.7(10) ppm of FSR/minute DC Bias Voltage Drift Applied to Sensor Input 3 ±1 µV/°C Input Bias Current Drift +25 °C to +45°C 0.01 1 (10) ✻✻ pA/°C Input Bias Current T A = +75°C2 5 0 (10) ✻✻ pA Range Drift(7) Range 5 (250pC) 25 0 25 50 (10) ppm/°C Range Drift Match(5) Range 5 (250pC) ±0.05 ✻ ppm/°C REFERENCE Voltage 4.000 4.096 4.200 ✻✻ ✻ V Input Current(8) TINT = 500µs 150 225 275 µA DIGITAL INPUT/OUTPUT Logic Levels VIH 4.0 DV DD + 0.3 ✻✻ V VIL –0.3 +0.8 ✻✻ V VOH IOH = –500µA 4.5 ✻ V VOL IOL = 500µA 0.4 ✻ V Input Current, IIN –10 +10 ✻✻ µA Data Format(9) Straight Binary ✻ POWER-SUPPLY REQUIREMENTS Power-Supply Voltage AV DD and DVDD 4.75 5.25 ✻✻ V Supply Current Analog Current AV DD = +5V 14.8 15.2 mA Digital Current DV DD = +5V 1.2 1.8 mA Total Power Dissipation 80 100 85 130 mW TEMPERATURE RANGE Specified Performance –40 +85 0 +70 °C Storage –60 +100 ✻✻ °C

SBAS085Bwww.ti.com PIN DESCRIPTIONS PIN LABEL DESCRIPTION 1 IN1 Input 1: analog input for Integrators 1A and 1B. The integrator that is active is set by the CONV input.

2 AGND Analog Ground

3 CAP1B External Capacitor for Integrator 1B

4 CAP1B External Capacitor for Integrator 1B

5 CAP1A External Capacitor for Integrator 1A

6 CAP1A External Capacitor for Integrator 1A

DD Analog Supply, +5V Nominal 8 TEST Test Control Input. When HIGH, a test charge is applied to the A or B integrators on the next CONV transition.

9 CONV Controls which side of the integrator is connected to

input. In continuous mode; CONV HIGH → side A is integrating, CONV LOW → side B is integrating. CONV must be synchronized with CLK (see Figure 2).

10 CLK System Clock Input, 10MHz Nominal

11 DCLK Serial Data Clock Input. This input operates the serial I/ O shift register. 12 DXMIT Serial Data Transmit Enable Input. When LOW, this input enables the internal serial shift register. 13 DIN Serial Digital Input. Used to cascade multiple DDC112s. 14 DV DD Digital Supply, +5V Nominal

15 DGND Digital Ground

16 DOUT Serial Data Output, Hi-Z when DXMIT is HIGH

17 DVALID Data Valid Output. A LOW value indicates valid data is available in the serial I/O register.

18 RANGE0 Range Control Input 0 (least significant bit)

19 RANGE1 Range Control Input 1

20 RANGE2 Range Control Input 2 (most significant bit)

21 AGND Analog Ground

REF External Reference Input, +4.096V Nominal

23 CAP2A External Capacitor for Integrator 2A

24 CAP2A External Capacitor for Integrator 2A

25 CAP2B External Capacitor for Integrator 2B

26 CAP2B External Capacitor for Integrator 2B

27 AGND Analog Ground

28 IN2 Input 2: analog input for Integrators 2A and 2B. The integrator that is active is set by the CONV input. PIN CONFIGURATION Top View SO IN2 AGND CAP2B CAP2B CAP2A CAP2A V REF AGND RANGE2 (MSB) RANGE1 RANGE0 (LSB) DVALID DOUT DGND IN1 AGND CAP1B CAP1B CAP1A CAP1A AV DD TEST CONV CLK DCLK DXMIT DIN DV DD DDC112U

SBAS085B www.ti.com CAP1A CAP1A AV DD NC NC TEST CONV CLK CAP2A CAP2A V REF AGND NC NC RANGE2 (MSB) RANGE1 DDC112Y CAP1B CAP1B AGND IN1 IN2 AGND CAP2B CAP2B DCLK DXMIT DIN DV DD DGND DOUT DVALID RANGE0 (LSB) PIN CONFIGURATION Top View TQFP PIN DESCRIPTIONS PIN LABEL DESCRIPTION

1 CAP1A External Capacitor for Integrator 1A

2 CAP1A External Capacitor for Integrator 1A

DD Analog Supply, +5V Nominal

4 NC No Connection

5 NC No Connection

6 TEST Test Control Input. When HIGH, a test charge is applied to the A or B integrators on the next CONV transition.

7 CONV Controls which side of the integrator is connected to

input. In continuous mode; CONV HIGH side A is integrating, CONV LOW side B is integrating CONV must be synchronized with CLK (see text).

8 CLK System Clock Input, 10MHz Nominal

9 DCLK Serial Data Clock Input. This input operates the serial I/O shift register. 10 DXMIT Serial Data Transmit Enable Input. When LOW, this input enables the internal serial shift register. 11 DIN Serial Digital Input. Used to cascade multiple DDC112s. 12 DV DD Digital Supply, +5V Nominal

13 DGND Digital Ground

14 DOUT Serial Data Output, Hi-Z when DXMIT is HIGH

15 DVALID Data Valid Output. A LOW value indicates valid data is available in the serial I/O register.

16 RANGE0 Range Control Input 0 (least significant bit)

17 RANGE1 Range Control Input 1

18 RANGE2 Range Control Input 2. (most significant bit)

19 NC No Connection

20 NC No Connection

REF External Reference Input, +4.096V Nominal 28 IN2 Input 2: analog input for Integrators 2A and 2B. The integrator that is active is set by the CONV input. 29 IN1 Input 1: analog input for Integrators 1A and 1B. The integrator that is active is set by the CONV input.

30 AGND Analog Ground

31 CAP1B External Capacitor for Integrator 1B

32 CAP1B External Capacitor for Integrator 1B

SBAS085Bwww.ti.com NOISE vs TINT 1 10000.1 100 10 TINT (ms) Noise (ppm of FSR, rms) C SENSOR = 50pF C SENSOR = 0pF Range 5 TYPICAL CHARACTERISTICS At TA = +25°C, characterization done with Range 5 (250pC), TINT = 500µs, VREF = +4.096, AVDD = DVDD = +5V, and CLK = 10MHz, unless otherwise noted. NOISE vs CSENSOR 200 8000 1000 600400 C SENSOR (pF) Noise (ppm of FSR, rms) Range 7 Range 2 Range 1 Range 0 (CEXT = 250pF) NOISE vs INPUT LEVEL 30 4020 9010 100 70 80 1050 60 Input Level (% of Full-Scale) Noise (ppm of FSR, rms) 4.5 3.5 2.5 1.5 0.5 C SENSOR = 50pF C SENSOR = 0pF Range 5 NOISE vs TEMPERATURE –40 –15 10 35 60 85 Temperature (°C) Noise (ppm of FSR, rms) Range 1 Range 2 Range 7 Range 3 C SENSOR = 0pF RANGE DRIFT vs TEMPERATURE –40 –15 10 35 60 85 Temperature (°C) Range Drift (ppm) Ranges 1 - 7 (Internal Integration Capacitor) 2000 1500 1000 500 –500 –1000 –1500 IB vs TEMPERATURE 25 35 45 55 65 75 85 Temperature (°C) IB (pA) All Ranges 0.1 0.01

SBAS085B www.ti.com TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, characterization done with Range 5 (250pC), TINT = 500µs, VREF = +4.096, AVDD = DVDD = +5V, and CLK = 10MHz, unless otherwise noted. 600 POWER-SUPPLY REJECTION RATIO vs FREQUENCY 0 100 25 75 50 Frequency (KHz) PSRR (ppm of FSR/V) 100 200 300 400 500 INPUT VOS vs RANGE 1234567 Range VOS (µV) DIGITAL SUPPLY CURRENT vs TEMPERATURE 1.4 1.2 1.0 0.8 0.6 0.4 0.2 –40 –15 10 35 60 85 Temperature (°C) Current (mA) ANALOG SUPPLY CURRENT vs TEMPERATURE –40 –15 10 35 60 85 Temperature (°C) Current (mA) OFFSET DRIFT vs TEMPERATURE 25 35 45 55 65 75 85 Temperature (°C) Offset Drift (ppm of FSR) 100 –50 –100 All Ranges CROSSTALK vs FREQUENCY –20 –40 –60 –80 –100 –120 –140 0 100 200 300 400 500 Frequency (Hz) Separation (dB) Separation Measured Between Inputs 1 and 2

SBAS085B www.ti.com Determining the Integration Capacitor (CF) Value The value of the integrator’s feedback capacitor, the integra- tion period, and the reference voltage determine the positive full-scale (+FS) value of the DDC112. The approximate positive full-scale value of the DDC112 is given by the following equations: QIT QV C I VC T or C IT V IN IN INT FS REF F FS REF F INT F FS INT REF = ( ) × = ( ) × = × 09 6 09 6 09 6 (. ) The 0.96 factor allows the front end integrators to reach full- scale without having to completely swing to ground. The negative full-scale (–FS) range is approximately 0.4% of the positive full-scale range. For example, Range 5 has a nomi- nal +FS range of 250pC. The –FS range is then approxi- mately –1pC. This relationship holds for external capacitors as well and is independent of V REF (for VREF within the allowable range, see the Electrical Characteristics table). Integration Capacitors There are seven different capacitors available on-chip for each side of each channel in the DDC112. These internal capacitors are trimmed in production to achieve the specified performance for range error of the DDC112. The range control pins (RANGE0-RANGE2) change the capacitor value for all four integrators. Consequently, both inputs and both sides of each input will always have the same full-scale range unless external capacitors are used. External integration capacitors may be used instead of the internal capacitors values by setting [RANGE2-RANGE0 = 000]. The external capacitor pin connections are summa- rized in Table II. Usually, all four external capacitors are equal in value; however, it is possible to have differing pairs of external capacitors between Input 1 and Input 2 of the DDC112. Regardless of the selected value of the capacitor, it is strongly recommended that the capacitors for sides A and B be the same. INTEGRATOR DDC112U, UK DDC112Y, YK Channel Side 5 and 6 1 and 2 1 A 3 and 4 31 and 32 1 B 23 and 24 23 and 24 2 A 25 and 26 25 and 26 2 B TABLE II. External Capacitor Connections with Range Con- figuration of RANGE2-RANGE0 = 000. Since the range accuracy depends on the characteristics of the integration capacitor, they must be carefully selected. An external integration capacitor should have low-voltage coef- ficient, temperature coefficient, memory, and leakage cur- rent. The optimum selection depends on the requirements of the specific application. Suitable types include chip-on-glass (COG) ceramic, polycarbonate, polystyrene, and silver mica. Voltage Reference The external voltage reference is used to reset the integra- tion capacitors before an integration cycle begins. It is also used by the ∆Σ converter while the converter is measuring the voltage stored on the integrators after an integration cycle ends. During this sampling, the external reference must supply charge needed by the ∆Σ converter. For an integration time of 500µs, this charge translates to an average V REF current of approximately 150µA. The amount of charge needed by the ∆Σ converter is independent of the integration time; therefore, increasing the integration time lowers the average current. For example, an integration time of 1000µs lowers to average V REF current to 75µA. It is critical that VREF be stable during the different modes of operation in Figure 5. The ∆Σ converter measures the volt- age on the integrator with respect to VREF . Since the integrator’s capacitors are initially reset to VREF , any droop in VREF from the time the capacitors are reset to the time when the converter measures the integrator’s output will introduce an offset. It is also important that VREF be stable over longer periods of time as changes in VREF correspond directly to changes in the full-scale range. Finally, VREF should intro- duce as little additional noise as possible. For reasons mentioned above, it is strongly recommended that the external reference source be buffered with an operational amplifier, as shown in Figure 6. In this circuit, the voltage reference is generated by a 4.096V reference.FIGURE 6. Recommended External Voltage Reference Circuit for Best Low-Noise Operation with the DDC112. 0.10µF +5V 10kΩ 10µF 4 0.10µF 0.1µF10µF OPA350 To VREF Pin 22 of the DDC112REF3040 +5V 0.47µF EXTERNAL CAPACITOR PINS

TEST and CONV work together to implement this feature. TEST to the existing charge on the integrator capacitors. the TEST pin is not LOW when CONV toggles. is fundamentally independent of the data retrieval process. by one of the two sides of each input. able to keep pace with the speed of the integration process. Noncontinuous Operational Modes section of this data sheet.

6 CONV

FIGURE 9. State Diagram. measurement/reset/auto-zero (m/r/az) cycle is in progress.

1 Ncont Complete m/r/az of side A, then side B (if previous

2 Ncont Prepare side A for integration. 4 Cont Integrate on side B; m/r/az on side A. 5 Cont Integrate on side A; m/r/az on side B. 7 Ncont Prepare side B for integration.

8 Ncont Complete m/r/az of side B, then side A (if previous

TABLE IV. State Descriptions.

SBAS085Bwww.ti.com SPECIAL CONSIDERATIONS NCONT MODE INTEGRATION TIME The DDC112 uses a relatively fast clock. For CLK = 10MHz, this allows TINT to be adjusted in steps of 100ns since CONV should be synchronized to CLK. However, for the internal measurement, reset and auto-zero operations, a slower clock is more efficient. The DDC112 divides CLK by six and uses this slower clock with a period of 600ns to run the m/r/ az cycle and data ready logic. Because of the divider, it is possible for the integration time to be a non-integer number of slow clock periods. For example, if TINT = 5000 CLK periods (500µs for CLK = 10MHz), there will be 833 1/3 slow clocks in an integration period. This non-integer relationship between TINT and the slow clock period causes the number of rising and falling slow clock edges within an integration period to change from integration to integration. The digital coupling of these edges to the integrators will in turn change from integration to integration which produces noise. The change in the clock edges is not random, but will repeat every 3 integrations. The coupling noise on the integrators appears as a tone with a frequency equal to the rate at which the coupling repeats. To avoid this problem in cont mode, the internal slow clock is shut down after the m/r/az cycle is complete when it is no longer needed. It starts up again just after the next integra- tion begins. Since the slow clock is always off when CONV toggles, the same number of slow clock edges fall within an integration period regardless of its length. Therefore, T INT ≥ 4794 CLK periods will not produce the coupling problem described above. For the ncont mode however, the slow clock must always be left running. The m/r/az cycle is not completed before an integration ends. It is then possible to have digital coupling to the integrators. The digital coupling noise depends heavily on the layout of the printed circuit board used for the DDC112. For solid grounds and power supplies with good bypassing, it is possible to greatly reduce the coupling. However, for ensuring the best performance in the ncont mode, the inte- gration time should be chosen to be an integer multiple of 1/(2f SLOWCLOCK ). For CLK = 10MHz, the integration time should be an integer multiple of 300ns— TINT = 100µs is not. A better choice would be TINT = 99µs. DATA READY The DVALID signal which indicates that data is ready is generated using the internal slow clock. The phase relation- ship between this clock and CLK is set when power is first applied and is random. Since CONV is synchronized with CLK, it will have a random phase relationship with respect to the slow clock. When T INT > t6, the slow clock will temporarily shut down as described above. This shutdown process synchronizes the internal clock with CONV so that the time between when CONV toggles to when DVALID goes LOW (t7 and t8) is fixed. For TINT ≤ t6, the internal slow clock, is not allowed to shut down and the synchronization never occurs. Therefore, the time between CONV toggling and DVALID indicating data is ready has uncertainty due to the random phase relationship between CONV and the slow clock. This variation is ±1/(2f SLOWCLOCK ) or ±3/fCLK . The timing to the second DVALID in the ncont mode will not have a variation since it is triggered off the first data ready (t9) and both are derived from the slow clock. Polling DVALID to determine when data is ready eliminates any concern about the variation in timing since the readback is automatically adjusted as needed. If the data readback is triggered off the toggling of CONV directly (instead of poll- ing), then waiting the maximum value of t 7 or t8 insures that data will always be ready before readback occurs. Data Retrieval In the continuous and noncontinuous modes of operation, the data from the last conversion is available for retrieval with the falling edge of DVALID (see Figure 22). The falling edge of DXMIT in combination with the data clock (DCLK) will initiate the serial transmission of the data from the DDC112. Typically, data is retrieved from the DDC112 as soon as DVALID falls and completed before the next CONV transition from HIGH to LOW or LOW to HIGH occurs. If this is not the case, care should be taken to stop activity on DCLK and consequently DOUT by at least 10µs around a CONV tran- sition. If this caution is ignored it is possible that the integra- tion that is being initiated by CONV will have additional noise introduced. The serial output data at DOUT is transmitted in Straight Binary Code per Table VIII. An output offset has been built into the DDC112 to allow for the measurement of input signals near and below zero. Board leakage up to ≈ –0.4% of the positive full-scale can be tolerated before the digital output clips to all zeroes. Cascading Multiple Converters Multiple DDC112 units can be connected in serial or parallel configurations, as illustrated in Figures 20 and 21. DOUT can be used with DIN to daisy-chain several DDC112 devices together to minimize wiring. In this mode of opera- tion, the serial data output is shifted through multiple DDC112s, as illustrated in Figure 20. R PULLUP prevents DIN from floating when DXMIT is HIGH. Care should be taken to keep the capacitive load on DOUT as low as possible when running CLK=15MHz. CODE INPUT SIGNAL 1111 1111 1111 1111 1111 FS 1111 1111 1111 1111 1110 FS – 1LSB 0000 0001 0000 0000 0001 +1LSB 0000 0001 0000 0000 0000 Zero 0000 0000 0000 0000 0000 –0.4% FS TABLE VIII. Straight Binary Code Table.

FIGURE 20. Daisy-Chained DDC112s.

40 Bits 40 Bits 40 Bits

FIGURE 21. DDC112 in Parallel Operation. to DDC112U, Y only, with a maximum load of one DDC112U,Y DIN (4pF typical) with an additional load of (5pF 100kΩ). FIGURE 22. Digital Interface Timing Diagram for Data Retrieval From a Single DDC112. TABLE IX. Timing for the DDC112 Data Retrieval. NOTE: (1) Disable DCLK (preferably hold LOW) when DXMIT is HIGH.

(421.2µs – 10µs – 2µs for CLK = 10MHz), regardless of TINT. FIGURE 23. Timing Diagram When Using the DIN Function of the DDC112. NOTE: (1) Disable DCLK (preferably LOW) when DXMIT is HIGH. TABLE X. Timing for the DDC112 Data Retrieval Using DIN.

integration completes leaving less time available for retrieval. completed before new data is ready (t26). FIGURE 26. Readback Before and After CONV Toggles.

www.ti.com 7-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DDC112U Active Production SOIC (DW) | 28 20 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 DDC112U DDC112U.B Active Production SOIC (DW) | 28 20 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 85 DDC112U DDC112U/1K Active Production SOIC (DW) | 28 1000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 DDC112U DDC112U/1K.B Active Production SOIC (DW) | 28 1000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 DDC112U DDC112U/1KG4 Active Production SOIC (DW) | 28 1000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 DDC112U DDC112U/1KG4.B Active Production SOIC (DW) | 28 1000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 DDC112U DDC112UK Active Production SOIC (DW) | 28 20 | TUBE Yes NIPDAU Level-1-260C-UNLIM 0 to 70 DDC112UK DDC112UK.B Active Production SOIC (DW) | 28 20 | TUBE Yes NIPDAU Level-1-260C-UNLIM 0 to 70 DDC112UK DDC112Y/250 Active Production TQFP (PJT) | 32 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 DDC112Y DDC112Y/250.B Active Production TQFP (PJT) | 32 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 DDC112Y DDC112Y/2K Active Production TQFP (PJT) | 32 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 DDC112Y DDC112Y/2K.B Active Production TQFP (PJT) | 32 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 DDC112Y DDC112YK/250 Active Production TQFP (PJT) | 32 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR 0 to 70 DDC112YK DDC112YK/250.B Active Production TQFP (PJT) | 32 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR 0 to 70 DDC112YK (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Addendum-Page 1

www.ti.com 7-Oct-2025 Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DDC112U/1K SOIC DW 28 1000 350.0 350.0 66.0 DDC112U/1KG4 SOIC DW 28 1000 350.0 350.0 66.0 DDC112Y/2K TQFP PJT 32 2000 350.0 350.0 43.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) DDC112U DW SOIC 28 20 506.98 12.7 4826 6.6 DDC112U.B DW SOIC 28 20 506.98 12.7 4826 6.6 DDC112UK DW SOIC 28 20 506.98 12.7 4826 6.6 DDC112UK.B DW SOIC 28 20 506.98 12.7 4826 6.6 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C 32X 0.45 0.30

0.2 C A B

28X 0.8 PIN 1 ID 0.09-0.20 TYP 0.15 0.05 0 -7 4X 5.6 9.2

8.8 TYP

0.75 0.45 0.1 C 1.2 1.0 B7.2 6.8 A 7.2 6.8 0.25 GAGE PLANE (1) PLASTIC QUAD FLATPACK TQFP - 1.2 mm max heightPJT0032A PLASTIC QUAD FLATPACK 4220861/A 07/2023 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Reference JEDEC registration MS-026. 9 16 2532 0.1 C DETAIL A SCALE: 15 DETAIL A TYPICAL SCALE 1.700

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

(8.4) (8.4) 28X (0.8) 32X (1.5) 32X (0.55) (R0.05) TYP TQFP - 1.2 mm max heightPJT0032A PLASTIC QUAD FLATPACK 4220861/A 07/2023 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM SYMM 32 25 9 16 SEE DETAILS METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (8.4) 28X (0.8) 32X (1.5) 32X (0.55) (8.4) (R0.05) TYP TQFP - 1.2 mm max heightPJT0032A PLASTIC QUAD FLATPACK 4220861/A 07/2023 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:8X SYMM SYMM 32 25 9 16

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