DDC112 BURR-BROWN | Alldatasheet
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International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 DDC112 Dual Current Input 20-Bit ANALOG-TO-DIGITAL CONVERTER
FEATURES
l MONOLITHIC CHARGE MEASUREMENT ADC l DIGITAL FILTER NOISE REDUCTION: 3.2ppm, rms l INTEGRAL LINEARITY: ±0.005% Reading ±0.5ppm FSR l HIGH PRECISION, TRUE INTEGRATING FUNCTION l PROGRAMMABLE FULL SCALE l SINGLE SUPPLY l CASCADABLE OUTPUT
APPLICATIONS
l DIRECT PHOTOSENSOR DIGITIZATION l CT SCANNER DAS l INFRARED PYROMETER l PRECISION PROCESS CONTROL l LIQUID/GAS CHROMATOGRAPHY l BLOOD ANALYSIS
DESCRIPTION
The DDC112 is a dual input, wide dynamic range, charge-digitizing analog-to-digital converter (ADC) with 20-bit resolution. Low level current output devices, such as photosensors, can be directly connected to its inputs. Charge integration is continuous as each input uses two integrators; while one is being digitized, the other is integrating. For each of its two inputs, the DDC112 combines current-to-voltage conversion, continuous integration, programmable full-scale range, A/D conversion, and digital filtering to achieve a precision, wide dynamic range digital result. In addition to the internal program- mable full-scale ranges, external integrating capacitors allow an additional user-settable full-scale range of up to 1000pC. To provide single-supply operation, the internal ADC utilizes a differential input, with the positive input tied to V REF . When the integration capacitor is reset at the beginning of each integration cycle, the capacitor charges to VREF . This charge is removed in proportion to the input current. At the end of the integration cycle, the remaining voltage is compared to VREF . The high-speed serial shift register which holds the result of the last conversion can be configured to allow multiple DDC112 units to be cascaded, minimizing interconnections. The DDC112 is available in a SO-28 package and is offered in two performance grades. Protected by US Patent #5841310 Dual Switched Integrator Dual Switched Integrator ΔΣ Modulator Digital Filter Control Digital Input/Output DVALID DXMIT DOUT DIN DCLK RANGE2 RANGE1 RANGE0 TEST CONV CLK CAP1A CAP1A CAP1B CAP1B CAP2A CAP2ACAP2B CAP2B IN2 IN1 VREF DGNDDV DDAGNDAV DD CHANNEL 1 CHANNEL 2 © 1997 Burr-Brown Corporation PDS-1421D Printed in U.S.A. January, 2000 For most current data sheet and other product information, visit www.burr-brown.com
At TA = +25°C, AVDD = DVDD = +5V, DDC112U: TINT = 500µs, CLK = 10MHz, DDC112UK: TINT = 333.3µs, CLK = 15MHz, VREF = +4.096V, continuous mode operation, and internal integration capacitors, unless otherwise noted. NOTES: (1) Input is less than 1% of full scale. (2) CSENSOR is the capacitance seen at the DDC112 inputs from wiring, photodiode, etc. (3) FSR is Full-Scale Range. (4) A best-fit line is used in measuring linearity. (5) Matching between side A and side B, not input 1 to input 2. (6) Voltage produced by the DDC112 at its input which is applied to the sensor. (7) Range drift does not include external reference drift. (8) Input reference current decreases with increasing TINT (see text). (9) Data format is Straight Binary with a small offset (see text). (10) Guaranteed but not tested. DDC112U DDC112UK PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS ANALOG INPUTS External, Positive Full-Scale Range 0 C EXT = 250pF 1000 [ pC Internal, Positive Full-Scale Range 1 47.5 50 52.5 [[ [ pC Range 2 95 100 105 [[ [ pC Range 3 142.5 150 157.5 [[ [ pC Range 4 190 200 210 [[ [ pC Range 5 237.5 250 262.5 [[ [ pC Range 6 285 300 315 [[ [ pC Range 7 332.5 350 367.5 [[ [ pC Negative Full-Scale Input –0.4% of Positive FS [ pC DYNAMIC CHARACTERISTICS Conversion Rate 2 3 kHz Integration Time, TINT Continuous Mode 500 1,000,000 333.3 [ µs Integration Time, TINT Non-continuous Mode 50 [ µs System Clock Input (CLK) 1 10 12 [[ 15 MHz Data Clock (DCLK) 12 15 MHz ACCURACY Noise, Low Level Current Input(1) CSENSOR (2) = 0pF, Range 5 (250pC) 3.2 [ ppm of FSR(3), rms C SENSOR = 25pF, Range 5 (250pC) 3.8 [ ppm of FSR, rms C SENSOR = 50pF, Range 5 (250pC) 4.2 6.0 [ 7 ppm of FSR, rms Differential Linearity Error ±0.005% Reading ±0.5ppm FSR, max [ Integral Linearity Error(4) ±0.005% Reading ±0.5ppm FSR, typ [ ±0.025% Reading ±1.0ppm FSR, max [ No Missing Codes 20 [ Bits Input Bias Current T A = +25°C 0.1 10 [[ pA Range Error Range 5 (250pC) 5 [ % of FSR Range Error Match(5) All Ranges 0.1 0.5 [[ % of FSR Range Sensitivity to VREF VREF = 4.096 ±0.1V 1:1 [ Offset Error Range 5, (250pC) ±200 [ ±600 ppm of FSR Offset Error Match(5) ±100 [ ppm of FSR DC Bias Voltage(6) (Input VOS ) ±0.05 ±2 [[ mV Power Supply Rejection Ratio ±25 ±200 [[ ppm of FSR/V Internal Test Signal 13 [ pC Internal Test Accuracy ±10 [ % PERFORMANCE OVER TEMPERATURE Offset Drift ±0.5 ±3(10) ppm of FSR/°C Offset Drift Stability ±0.2 [ ±0.7(10) ppm of FSR/minute DC Bias Voltage Drift Applied to Sensor Input 3 ±1 µV/°C Input Bias Current Drift +25 °C to +45°C 0.01 1 (10) [[ pA/°C Input Bias Current T A = +75°C2 5 0 (10) [[ pA Range Drift(7) Range 5 (250pC) 25 0 25 50 (10) ppm/°C Range Drift Match(5) Range 5 (250pC) ±0.05 [ ppm/°C REFERENCE Voltage 4.000 4.096 4.200 [[ [ V Input Current(8) TINT = 500µs 150 225 275 µA DIGITAL INPUT/OUTPUT Logic Levels VIH 4.0 DV DD + 0.3 [[ V VIL –0.3 +0.8 [[ V VOH IOH = –500µA 4.5 [ V VOL IOL = 500µA 0.4 [ V Input Current, IIN –10 +10 [[ µA Data Format(9) Straight Binary [ POWER SUPPLY REQUIREMENTS Power Supply Voltage AV DD and DVDD 4.75 5.25 [[ V Supply Current Analog Current AV DD = +5V 14.8 15.2 mA Digital Current DV DD = +5V 1.2 1.8 mA Total Power Dissipation 80 100 85 130 mW TEMPERATURE RANGE Specified Performance –40 +85 0 +70 °C Storage –60 +100 [[ °C
1 IN1 Input 1: analog input for Integrators 1A and 1B. The integrator that is active is set by the CONV input. 2 AGND Analog Ground. 3 CAP1B External Capacitor for Integrator 1B. 4 CAP1B External Capacitor for Integrator 1B. 5 CAP1A External Capacitor for Integrator 1A. 6 CAP1A External Capacitor for Integrator 1A. 7A V DD Analog Supply, +5V nominal. 8 TEST Test Control Input. When HIGH, a test charge is applied to the A or B integrators on the next CONV transition.
9 CONV Controls which side of the integrator is connected to
input. In continuous mode; CONV HIGH → side A is integrating, CONV LOW → side B is integrating. CONV must be synchronized with CLK (see text). 10 CLK System Clock Input, 10MHz nominal. 11 DCLK Serial Data Clock Input. This input operates the serial I/O shift register. 12 DXMIT Serial Data Transmit Enable Input. When LOW, this input enables the internal serial shift register. 13 DIN Serial Digital Input. Used to cascade multiple DDC112s. 14 DV DD Digital Supply, +5V nominal. 15 DGND Digital Ground. 16 DOUT Serial Data Output, Hi-Z when DXMIT is HIGH. 17 DVALID Data Valid Output. A LOW value indicates valid data is available in the serial I/O register. 18 RANGE0 Range Control Input 0 (least significant bit). 19 RANGE1 Range Control Input 1. 20 RANGE2 Range Control Input 2 (most significant bit). 21 AGND Analog Ground. 22 V REF External Reference Input, +4.096V nominal. 23 CAP2A External Capacitor for Integrator 2A. 24 CAP2A External Capacitor for Integrator 2A. 25 CAP2B External Capacitor for Integrator 2B. 26 CAP2B External Capacitor for Integrator 2B. 27 AGND Analog Ground. 28 IN2 Input 2: analog input for Integrators 2A and 2B. The integrator that is active is set by the CONV input. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR- BROWN product for use in life support devices and/or systems. NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maxi- mum conditions for extended periods may affect device reliability. ABSOLUTE MAXIMUM RATINGS (1) PIN CONFIGURATION Top View SO IN2 AGND CAP2B CAP2B CAP2A CAP2A V REF AGND RANGE2 (MSB) RANGE1 RANGE0 (LSB) DVALID DOUT DGND IN1 AGND CAP1B CAP1B CAP1A CAP1A AV DD TEST CONV CLK DCLK DXMIT DIN DV DD DDC112 PACKAGE/ORDERING INFORMATION MAXIMUM SPECIFICATION PACKAGE INTEGRAL TEMPERATURE DRAWING ORDERING TRANSPORT PRODUCT LINEARITY ERROR RANGE PACKAGE NUMBER NUMBER (1) MEDIA DDC112U ±0.025% Reading ±1.0ppm% FSR –40°C to +85°C SO-28 217 DDC112U Rails """ " " DDC112U/1K Tape and Reel DDC112UK ±0.025% Reading ±1.0ppm% FSR 0°C to +70°C SO-28 217 DDC112UK Rails """ " " DDC112UK/1K Tape and Reel NOTES: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of “DDC112U/1K” will get a single 1000-piece Tape and Reel. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
1 10000.1 100 10 TINT (ms) Noise (ppm of FSR, rms) C SENSOR = 50pF C SENSOR = 0pF Range 5 TYPICAL PERFORMANCE CURVES At TA = +25°C, characterization done with Range 5 (250pC), TINT = 500µs, VREF = +4.096, AVDD = DVDD = +5V, and CLK = 10MHz, unless otherwise noted. NOISE vs CSENSOR 200 8000 1000 600400 C SENSOR (pF) Noise (ppm of FSR, rms) Range 7 Range 2 Range 1 Range 0 (CEXT = 250pF) NOISE vs INPUT LEVEL 30 4020 9010 100 70 80 1050 60 Input Level (% of Full-Scale) Noise (ppm of FSR, rms) 4.5 3.5 2.5 1.5 0.5 C SENSOR = 50pF C SENSOR = 0pF Range 5 NOISE vs TEMPERATURE –40 –15 10 35 60 85 Temperature (°C) Noise (ppm of FSR, rms) Range 1 Range 2 Range 7 Range 3 C SENSOR = 0pF RANGE DRIFT vs TEMPERATURE –40 –15 10 35 60 85 Temperature (°C) Range Drift (ppm) Ranges 1 - 7 (Internal Integration Capacitor) 2000 1500 1000 500 –500 –1000 –1500 IB vs TEMPERATURE 25 35 45 55 65 75 85 Temperature (°C) IB (pA) All Ranges 0.1 0.01
TYPICAL PERFORMANCE CURVES (Cont.) At TA = +25°C, characterization done with Range 5 (250pC), TINT = 500µs, VREF = +4.096, AVDD = DVDD = +5V, and CLK = 10MHz, unless otherwise noted. 600 POWER SUPPLY REJECTION RATIO vs FREQUENCY 0 100 25 75 50 Frequency (KHz) PSRR (ppm of FSR/V) 100 200 300 400 500 INPUT VOS vs RANGE 1234567 Range VOS (µV) DIGITAL SUPPLY CURRENT vs TEMPERATURE 1.4 1.2 1.0 0.8 0.6 0.4 0.2 –40 –15 10 35 60 85 Temperature (°C) Current (mA) ANALOG SUPPLY CURRENT vs TEMPERATURE –40 –15 10 35 60 85 Temperature (°C) Current (mA) OFFSET DRIFT vs TEMPERATURE 25 35 45 55 65 75 85 Temperature (°C) Offset Drift (ppm of FSR) 100 –50 –100 All Ranges CROSSTALK vs FREQUENCY –20 –40 –60 –80 –100 –120 –140 0 100 200 300 400 500 Frequency (Hz) Separation (dB) Separation Measured Between Inputs 1 and 2
- Figure 4 is used to conceptualize the operation of the
±10ns of the rising edge of CLK. SREF2 , and SRESET are set (see Figure 4). TABLE I. Range Selection of the DDC112. FIGURE 3. Basic Integrator Configuration for Input 1 Shown with a 250pC (CF = 62.5pF) Input Range. to the input of the ΔΣ A/D converter (see Figure 5d).
full scale without having to completely swing to ground. the allowable range, see the Specification table). range unless external capacitors are used. capacitors for sides A and B be the same. figuration of RANGE2-RANGE0 = 000. ramic, polycarbonate, polystyrene, and silver mica. should introduce as little additional noise as possible. the voltage reference is generated by a 4.096V reference. FIGURE 6. Recommended External Voltage Reference Circuit for Best Low Noise Operation with the DDC112.
TEST and CONV work together to implement this feature. of this data sheet for more detail. by one of the two sides of each input. and non-continuous modes—are described below.
1 Ncont Complete m/r/az of side A, then side B (if previous
2 Ncont Prepare side A for integration. 4 Cont Integrate on side B; m/r/az on side A. 5 Cont Integrate on side A; m/r/az on side B. 7 Ncont Prepare side B for integration.
8 Ncont Complete m/r/az of side B, then side A (if previous
TABLE IV . State Descriptions.
6 CONV
FIGURE 9. State Diagram. measurement/reset/auto-zero (m/r/az) cycle is in progress.
NCONT MODE INTEGRATION TIME The DDC112 uses a relatively fast clock. For CLK = 10MHz, this allows TINT to be adjusted in steps of 100ns since CONV should be synchronized to CLK. However, for the internal measurement, reset and auto-zero operations, a slower clock is more efficient. The DDC112 divides CLK by six and uses this slower clock with a period of 600ns to run the m/r/az cycle and data ready logic. Because of the divider, it is possible for the integration time to be a non-integer number of slow clock periods. For example, if TINT = 5000 CLK periods (500µs for CLK = 10MHz), there will be 833 1/3 slow clocks in an integration period. This non-integer relationship between TINT and the slow clock period causes the number of rising and falling slow clock edges within an integration period to change from integration to integration. The digital coupling of these edges to the integrators will in turn change from integration to integration which produces noise. The change in the clock edges is not random, but will repeat every 3 integrations. The coupling noise on the integrators appears as a tone with a frequency equal to the rate at which the coupling repeats. To avoid this problem in cont mode, the internal slow clock is shut down after the m/r/az cycle is complete when it is no longer needed. It starts up again just after the next integra- tion begins. Since the slow clock is always off when CONV toggles, the same number of slow clock edges fall within an integration period regardless of its length. Therefore, T INT ≥ 4794 CLK periods will not produce the coupling problem described above. For the ncont mode however, the slow clock must always be left running. The m/r/az cycle is not completed before an integration ends. It is then possible to have digital coupling to the integrators. The digital coupling noise depends heavily on the layout of the printed circuit board used for the DDC112. For solid grounds and power supplies with good bypassing, it is possible to greatly reduce the coupling. However, for guaranteeing the best performance in the ncont mode, the integration time should be chosen to be an integer multiple of 1/(2f SLOWCLOCK ). For CLK = 10MHz, the inte- gration time should be an integer multiple of 300ns— T INT = 100µs is not. A better choice would be TINT = 99µs. DATA READY The DV ALID signal which indicates that data is ready is generated using the internal slow clock. The phase relation- ship between this clock and CLK is set when power is first applied and is random. Since CONV is synchronized with CLK, it will have a random phase relationship with respect to the slow clock. When T INT > t6, the slow clock will temporarily shut down as described above. This shutdown process synchronizes the internal clock with CONV so that the time between when CONV toggles to when DV ALID goes LOW (t 7 and t8) is fixed. For TINT ≤ t6, the internal slow clock, is not allowed to shut down and the synchronization never occurs. Therefore, the time between CONV toggling and DV ALID indicating data is ready has uncertainty due to the random phase relation- ship between CONV and the slow clock. This variation is ±1/(2f SLOWCLOCK ) or ±3/fCLK . The timing to the second DV ALID in the ncont mode will not have a variation since it is triggered off the first data ready (t 9) and both are derived from the slow clock. Polling DV ALID to determine when data is ready eliminates any concern about the variation in timing since the readback is automatically adjusted as needed. If the data readback is triggered off the toggling of CONV directly (instead of polling), then waiting the maximum value of t 7 or t8 insures that data will always be ready before readback occurs. Data Retrieval In the continuous and non-continuous modes of operation, the data from the last conversion is available for retrieval with the falling edge of DVALID (see Figure 22). The falling edge of DXMIT in combination with the data clock (DCLK) will initiate the serial transmission of the data from the DDC112. Typically, data is retrieved from the DDC112 as soon as DVALID falls and completed before the next CONV transition from HIGH to LOW or LOW to HIGH occurs. If this is not the case, care should be taken to stop activity on DCLK and consequently DOUT by at least 10µs around a CONV transition. If this caution is ignored it is possible that the integration that is being initiated by CONV will have additional noise introduced. The serial output data at DOUT is transmitted in Straight Binary Code per Table VIII. An output offset has been built into the DDC112 to allow for the measurement of input signals near and below zero. Board leakage up to ≈ –0.4% of the positive full scale can be tolerated before the digital output clips to all zeroes. Cascading Multiple Converters Multiple DDC112 units can be connected in serial or parallel configurations, as illustrated in Figures 20 and 21. DOUT can be used with DIN to “daisy chain” several DDC112 devices together to minimize wiring. In this mode of operation, the serial data output is shifted through mul- tiple DDC112s, as illustrated in Figure 20. R PULLUP prevents DIN from floating when DXMIT is HIGH. Care should be taken to keep the capacitive load on DOUT as low as possible when running CLK=15MHz. CODE INPUT SIGNAL 1111 1111 1111 1111 1111 FS 1111 1111 1111 1111 1110 FS – 1LSB 0000 0001 0000 0000 0001 +1LSB 0000 0001 0000 0000 0000 Zero 0000 0000 0000 0000 0000 –0.4% FS TABLE VIII. Straight Binary Code Table.
FIGURE 20. Daisy-Chained DDC112’s.
40 Bits 40 Bits 40 Bits
FIGURE 21. DDC112 in Parallel Operation. DDC112U only, with a maximum load of one DDC112U DIN (4pF typical) with an additional load of (5pF 100kΩ). FIGURE 22. Digital Interface Timing Diagram for Data Retrieval From a Single DDC112. TABLE IX. Timing for the DDC112 Data Retrieval. NOTE: (1) Disable DCLK (preferably hold LOW) when DXMIT is HIGH.
FIGURE 23. Timing Diagram When Using the DIN Function of the DDC112. NOTE: (1) Disable DCLK (preferably LOW) when DXMIT is HIGH. TABLE X. Timing for the DDC112 Data Retrieval Using DIN.
FIGURE 26. Readback Before and After CONV Toggles.