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20-BIT ANALOG-TO-DIGITAL CONVERTER DDC101
DESCRIPTION
The DDC101 is a precision, wide dynamic range, charge digitizing A/D converter with 20-bit resolution. Low level current output devices, such as photosensors, can be directly connected to its input. The most stringent accu- racy requirements of many unipolar output sensor appli- cations occur at low signal levels. To meet this require- ment, Burr-Brown developed the adaptive delta modula- tion architecture of the DDC101 to provide linearly improving noise and linearity errors as the input signal level decreases. The DDC101 combines the functions of current-to-voltage conversion, integration, input program- mable gain amplification, A/D conversion, and digital filtering to produce precision, wide dynamic range re- sults. The input signal can be a low level current con- nected directly into the unit or a voltage connected through a user selected resistor. Although the DDC101 is optimized for unipolar signals, it can also accurately digitize bipolar input signals. The patented delta modula- tion topology combines charge integration and digitiza- tion functions. Oversampling and digital filtering reduce system noise dramatically. Correlated Double Sampling (CDS) captures and eliminates steady state and conver- sion cycle dependent offset and switching errors that are not eliminated with conventional analog circuits. The DDC101 block diagram is shown below. During conversion, the input signal is collected on the internal integration capacitance for a user determined integration period. A high precision, autozeroed comparator samples the analog input node. Tracking logic updates the internal high resolution D/A converter at a 2MHz rate to maintain the analog input at virtual ground. A user programmable digital filter oversamples the tracking logic’s output. The digital filter passes a low noise, high resolution digital output to the serial I/O register. The serial outputs of multiple DDC101 units can be easily connected together in series or parallel if desired to minimize interconnections. l MONOLITHIC CHARGE INPUT ADC l DIGITAL FILTER NOISE REDUCTION: 0.9ppm, rms l DIGITAL ERROR CORRECTION: CDS l CONVERSION RATE: Up to 15kHz l USER FRIENDLY EVALUATION FIXTURE APPLICATIONSFEATURES l DIRECT PHOTOSENSOR DIGITIZATION l PRECISION INSTRUMENTATION l INFRARED PYROMETRY l PRECISION PROCESS CONTROL l CT SCANNER DAS l CHEMICAL ANALYZERS C INT Digital Integration, Tracking and Control Logic Digital Filter and Error Correction Serial I/O Register Serial In Serial Out Reset DAC CDAC DDC101 Integrated Circuit Comparator VREF Analog Input Ground Setup Oversampled Digital Out
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© 1993 Burr-Brown Corporation PDS-1211E Printed in U.S.A. March, 1998 International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 DDC101
C INT , as charge for a user determined integration period, TINT . quency response of the digital filter, is user programmable. ending with a high resolution A/D converter. FIGURE 1. Simplified Equivalent Circuit of DDC101 to Illustrate Function. FIGURE 2. DDC101 Block Diagram.
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authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. keep the comparator input at virtual ground. FIGURE 3. DDC101 Detailed Circuit Diagram.
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All specifications with unipolar current input range, TINT = 1ms, correlated double sampling enabled, System Clock = 2MHz, VREF = –2.5V, TA = +25°C and VS = ±5VDC, unless otherwise noted. DDC101 PARAMETER CONDITIONS MIN TYP MAX UNITS INPUTS Charge Input(6) Unipolar Input Range BTC Output Code –1.95 500 pC/Integration Bipolar Input Range BTC Output Code –251.95 250 pC/Integration Input Current Unipolar or Bipolar Range 7.8 µA Current Input Range Examples (10) Unipolar Input Range T INT = 100µs –0.0195 5 µA Unipolar Input Range T INT = 1ms –1.95 500 nA Bipolar Input Range T INT = 100µs –2.5195 2.5 µA Bipolar Input Range T INT = 1ms –251.95 250 nA Voltage Input Examples(10) Unipolar Input Range(2) R IN = 10MΩ , TINT = 1ms –0.0195 5 V Bipolar Input Range(2) R IN = 10MΩ , TINT = 1ms –2.5195 2.5 V DYNAMIC CHARACTERISTICS Conversion Time 64 256 x 10 6 µs Integration Time 64 10 6 µs System Clock Input 0.5 2 MHz ACCURACY Unipolar Mode Noise Noise, Low Level Current Input(1) CSENSOR = 0pF, L = 8 0.9 ppm of FSR, rms (3) Noise, Low Level Current Input(1) CSENSOR = 0pF, L = 1 1.6 ppm of FSR, rms Noise, Low Level Current Input(1) C SENSOR = 100pF, L = 1 2.1 3 ppm of FSR, rms Noise, Low Level Current Input(1) C SENSOR = 500pF, L = 1 4.2 ppm of FSR, rms Noise, Voltage Input(1, 2) R IN ≥ 20MΩ 1.9 ppm of FSR, rms Differential Linearity Error Unipolar Input Range Entire Range ±0.005% Reading ±0.5ppm FSR, max 0.1% FSR Input ±0.00006 % of FSR 1% FSR Input ±0.00010 % of FSR 10% FSR Input ±0.00055 % of FSR Unipolar or Bipolar Input Range ±0.0015 % of FSR Integral Linearity Error Unipolar Input Range(11) 0 to 500 pc/Integration ±0.0244% Reading ±2.5ppm FSR, max –1.95 to 0 pc/Integration ±0.0244% Reading ±3.0ppm FSR, max 0.1% FSR Input ±0.00028 % of FSR 1% FSR Input ±0.00050 % of FSR 10% FSR Input ±0.0027 % of FSR Unipolar or Bipolar Input Range(11) ±0.003 % of FSR No Missing Codes Unipolar Input Range 18 Bits Bipolar Input Range 16 Bits Input Bias Current T A = +25°C3 1 0 p A DC Gain Error ±0.5 ±2 % of FSR Output Offset Error(8) ±0.5 ppm of FSR Input Offset Voltage(8) ±0.5 ±2m V External Voltage Reference, VREF –2.5 VDC Internal Test Signal 100 nA Internal Test Signal Accuracy ±20 nA Gain Sensitivity to VREF VREF = 2.5V ±0.1V 1:1 PSRR 80 90 dB PERFORMANCE OVER TEMPERATURE Output Offset Drift(8) not including bias current drift 0 µV/°C Input Offset Voltage Drift(8) 1 µV/°C Input Bias Current Drift +25 °C to +45°C 0.1 0.5 pA/ °C Input Bias Current T A = +85°C8 4 0 p A Gain Drift(4) ±15 ppm/ °C DIGITAL INPUT/OUTPUT Logic Family TTL Compatible CMOS Logic Level: VIH IIH = +5µA +2.0 +V CC V VIL IIL = +5µA –0.3 +0.8 V VOH IOH = 2 TTL Loads +2.4 +V CC V VOL IOL = 2 TTL Loads 0.0 0.4 V Data Clock Data I/O 8 MHz SETUP Code I/O(9) 4 MHz Data Format Straight Binary Unipolar or Bipolar Range 20 Bits Two’s Complement Unipolar or Bipolar Range 21 Bits
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SPECIFICATIONS (CONT) ELECTRICAL All specifications with unipolar current input range, TINT = 1ms, correlated double sampling enabled, System Clock = 2MHz, VREF = –2.5V, TA = +25°C and VS = ±5VDC, unless otherwise noted. DDC101 PARAMETER CONDITIONS MIN TYP MAX UNITS POWER SUPPLY REQUIREMENTS Operation(5) ±4.75 ±5 ±5.25 VDC Quiescent Current, Positive Supply VS+ = +5VDC, VDD + = +5VDC 15.6 19.5 mA Analog, VS+ 8.9 mA Digital, VDD + 6.7 mA Quiescent Current, Negative Supply V S– = –5VDC 18.0 22.5 mA Operating Power 170 mW TEMPERATURE RANGE Operating –40 +85 °C Storage –60 +100 °C NOTES: (1) Input = low level (less than 1% of Full Scale); Full Scale IIN = 500nA; TINT = 1ms; Unipolar Input Range; Acquisition Time = 16 clock cycles, Oversampling = 128. (2) Voltage input is converted through user Straight Binary output code has slightly different Charge Range. See Section 6. (8) Input offset voltage is nulled by autozero circuitry and causes no output error. See Section 6 (Internal Error Correction). (9) This is the maximum clock frequency at which SETUP codes can be written to and read from the DDC101. (10) For other input current and voltage configurations, see Discussion of Specifications and Detailed Theory of Operation sections. (11) A best-fit straight line method is used to determine linearity. Two different best-fit straight lines are used for the two unipolar integral linearity specifications. Acquisition Time = 16 clock cycles, Oversampling = 128. Analog Inputs Power Supply ABSOLUTE MAXIMUM RATINGS PACKAGE/ORDERING INFORMATION PACKAGE THERMAL DRAWING RESISTANCE ( θJA ) PRODUCT PACKAGE NUMBER (1) ( °C/W) DDC101U 24-Lead SOIC 239 100 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with ap- propriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications.
V REF TEST In RESET SETUP In SETUP READ DATA/SETUP DATA TRANSMIT In OVERFLOW + Out OVERFLOW – Out DATA VALID Out DATA OUTPUT DIGITAL GROUND V S–, ANALOG ANALOG COMMON ANALOG In ANALOG COMMON VS+, ANALOG VS+, ANALOG RESET SYSTEM In FDS (Final Data Point Start) In SYSTEM CLOCK DATA CLOCK DATA INPUT VDD +, DIGITAL PIN NUMBER NAME DESCRIPTION 1V S –, ANALOG Negative analog power supply voltage, –5VDC. 2 ANALOG COMMON Analog ground point. 3 ANALOG INPUT Input for low level current signal. Photosensor can be directly connected to this input. With a resistor in series, DDC101 will convert a voltage input. 4 ANALOG COMMON Analog ground point. 5V S+, ANALOG Positive analog power supply voltage, +5VDC. Hardwire to pin 6. 6V S+, ANALOG Positive analog power supply voltage, +5VDC. Hardwire to pin 5. 7 RESET SYSTEM In This input resets DDC101, but does not reset the SETUP register. The DDC101 system is reset when this pin is active; reset action is removed when the pin is inactive. 8 FDS In This is Final Data point Start input. This input is the basic user control of the integration and conversion timing. When it becomes active, the DDC101 starts collection of the M, final data point samples. The beginning of the next integration time is exactly M system clock periods after the Final Data point Start command when operating in the continuous mode. 9 SYSTEM CLOCK This clock input sets the basic sampling rate of the DDC101. The DDC101 is specified with a clock speed of 2MHz. The clock speed can be 0.5MHz to 2.0MHz. 10 DATA CLOCK This clock input controls the data transfer rate for the serial DATA INPUT and DATA OUTPUT ports. The DATA CLOCK is independent of the SYSTEM CLOCK. This allows the DATA CLOCK to be operated at higher or lower speeds than the SYSTEM CLOCK. For best noise performance, data should not be transmitted and the DATA CLOCK should not be active during the initial and final data point collection. If data is being transmitted during the initial and final data point collection periods, the DATA CLOCK should be synchronized to the SYSTEM CLOCK, to minimize added noise. DATA CLOCK can be connected to SYSTEM CLOCK, so that the same clock is used for both; however, for best noise performance, the DATA CLOCK input should be active only when data is transmitted. 11 DATA INPUT This input can be used to “daisy chain” the output of several DDC101s together to minimize wiring. The output register of the DDC101 acts as a shift register to pass through the output of previously connected DDC101 units. In this way, multiple DDC101 units can convert simultaneously then sequence the data out serially on the same data line with one common control line and one common data line for all DDC101 units. 12 V DD +, DIGITAL Digital power supply, +5VDC. V DD + must be less than or equal to VS+. 13 DIGITAL GROUND Digital ground point. 14 DATA OUTPUT This output provides serial digital data clocked out at user controlled DATA CLOCK rate. Output data format is a 21-bit Binary Two's Complement word or a 20-bit Straight Binary word. The data word is transmitted MSB first. When DATA TRANSMIT is not active DATA OUTPUT tri-states. 15 DATA VALID This output is activated when conversion is complete and remains active until the DATA TRANSMIT input is activated. 16 OVERFLOW– The OVERFLOW output signals each provide an open collector output so that the overflow outputs from several 17 OVERFLOW+ DDC101s can easily be connected (wire ORed) together to a common pull-up resistor. They are activated when the input is beyond the acceptable range during conversion. Specifically, they are activated when the internal D/A converter input or digital filter exceeds full scale. They are Cleared at the end of conversion 1/2 clock cycle after DATA VALID high. DATA VALID can be used to capture OVERFLOW data into an external register.
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PIN DESCRIPTIONS (CONT) PIN NUMBER NAME DESCRIPTION 18 DATA TRANSMIT In This input controls the transmission of data from the serial I/O register of the DDC101. It can be activated anytime after DATA VALID out becomes active. It must remain active until all data has been collected from the serial I/O register(s) of all DDC101s in the data path. 19 READ DATA/ This input can be used to read back the current SETUP data. When this input is held high, the output from DATA SETUP In OUTPUT is the data collected by the DDC101. When this input is pulled low, an internal shift register is loaded with the current SETUP data on the rising edge of DATA CLOCK. This SETUP data shift register is logically connected between DATA INPUT and DATA OUTPUT pins and can be read in the same way that the data output is read. SETUP data read back does not invalidate data already stored in the DDC101's serial I/O register or data being collected by the DDC101, although digital noise concerns should be considered as discussed in DATA CLOCK. 20 SETUP In This input pin controls the DDC101 SETUP. A 12-bit digital word transmitted into this pin controls Acquisition Time, K, Oversampling, M, Multiple Integrations, L, Input Range and Output Data Format. The DDC101 reads the SETUP code at this pin after the RESET SETUP input transitions from active to inactive. The SETUP code is read into the SETUP register on the 12 positive data clock transitions following that transition. 21 RESET SETUP Resets SETUP register only, does not reset balance of DDC101. The DDC101 reads SETUP input data after this input transitions from active (reset) to inactive. 22 TEST In This is a digital input that controls the connection of an internal DC current source to the DDC101's input. TEST In exercises the DDC101 and is intended to test for functionality only. The typical test input current is 100nA ±20nA. The quiescent current of the DDC101 increases by approximately 1mA when TEST In is active. When TEST is HIGH, the internal current source is ON and current is flowing into the DDC101 input. When TEST is LOW, the current source is disconnected from the input. 23 V REF An external –2.5V reference must be connected to the REFERENCE In pin. Use of an external reference allows multiple DDC101s to use the same system reference for optimum channel matching. The external reference should be filtered to minimize noise contribution (see Figure 24). 24 REFERENCE An external capacitor of 10 µF should be connected to this node to provide proper operation of the internal BUFFER BYPASS D/A converter. The REFERENCE In pin is connected to an internal reference buffer amplifier. The internal reference buffer drives the internal CDAC. This buffer output is not intended for external use. SECTION 4 TIMING CHARACTERISTICS All specifications with Unipolar input range, TINT = 1ms, Current Input, Correlated Double Sampling enabled, Sys Clock = 2MHz, VREF = –2.5V, TA = +25°C and VS = ±5VDC, unless otherwise noted. SYMBOL DESCRIPTION MIN TYP MAX UNITS t1 FDS Setup 30 ns t2 FDS width, Continuous Conversion 50 (M–1) Clocks+t 1+100ns ns t3 FDS width, Asynchronous Conversion M Clocks+t 1 ns t4 FDS HIGH to start of next integration, Asynchronous Conversion 50 ns t5 Setup time for RESET SETUP HIGH to DATA CLOCK HIGH 60 ns t6 Setup time for Setup Codes data valid before rising edge of DATA Clock 30 ns t7 Hold time for Setup Codes data valid after rising edge of DATA Clock 30 ns t8 Propagation delay from rising edge of SYSTEM CLOCK to DATA VALID LOW 50 ns t9 Propagation delay from DATA TRANSMIT LOW to DATA VALID HIGH 35 ns t10 Setup time for DATA CLOCK LOW to DATA TRANSMIT LOW 30 ns t11 Propagation delay from DATA TRANSMIT LOW to valid data out 30 ns t12 Hold time that Data output is valid after falling edge of DATA CLOCK 10 ns t13 Propagation delay from DATA TRANSMIT HIGH to Data Output tri-stated 40 ns t14 Propagation delay from falling edge of SYSTEM CLOCK to OVERFLOW+ and 25 ns OVERFLOW–cleared t15 SYSTEM CLOCK pulse width HIGH 240 ns t16 SYSTEM CLOCK pulse width LOW 240 ns t17 DATA VALID LOW to DATA TRANSMIT LOW, Single DDC101 30 (LxN–21) Clocks ns
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FIGURE 7. OVERFLOW Out Monitoring Timing Diagram. DATA VALID Out can be used to latch data from the overflow status outputs. FIGURE 8. System Clock Timing.
TYPICAL PERFORMANCE CURVES ELECTRICAL System Clock = 2MHz, VS = ±5VDC, VREF = –2.5V, L = 1 Integration/Conversion, and TA = +25°C, unless otherwise noted. SINAD AT 10kHz CONVERSION, UNIPOLAR INPUT 100 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 0dB –60dB Input Frequency (Hz) THD + N (dB) 100µs Integration Time K = 16 Acquisition Clocks M = 32 Oversamples SINAD AT 1kHz CONVERSION, UNIPOLAR INPUT 100 50 100 150 200 250 300 350 400 450 500 0dB –60dB Input Frequency (Hz) THD + N (dB) 1ms Integration Time K = 16 Acquisition Clocks M = 128 Oversamples NOISE vs INPUT LEVEL (UNIPOLAR) WITH CDS Noise (ppm, rms) Input Level of FS C IN = 500pF C IN = 100pF C IN = 0pF 1ms Integration Time K = 16 Acquisition Clocks M = 128 Oversamples NOISE vs INPUT LEVEL (UNIPOLAR) WITHOUT CDS Noise (ppm, rms) Input Level of FS C IN = 500pF C IN = 100pF 1ms Integration Time M = 128 Oversamples C IN = 0pF NOISE vs RESISTOR VALUE 1000 100 Noise (ppm, rms) 0.01 0.1 1 10 100 1G R IN (MΩ ) 100µs Int., M = 16 O/S 1ms Int., M = 128 O/S Low Level, Unipolar Input K = 16 Acquisition Clocks CHARGE INJECTION vs INPUT CAPACITANCE 350 300 250 200 150 100 –50 0 100 200 500 1000 C IN (pF) No CDS Charge Injection (ppm) CDS On, K = 16
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TYPICAL PERFORMANCE CURVES (CONT) ELECTRICAL System Clock = 2MHz, VS = ±5VDC, VREF = –2.5V, L = 1 Integration/Conversion, and TA = +25°C, unless otherwise noted. NOISE vs INPUT CAPACITANCE, UNIPOLAR INPUT 0 100 200 500 1000 2000 C IN (pF) Noise (ppm, rms) No CDS CDS On, K = 16 1ms Integration Time M = 128 Oversamples CHANGE IN IB vs TEMPERATURE 2.0 –2.0 –4.0 –6.0 –8.0 –40 –20 0 20 40 60 80 100 Temperature (°C) Δ IB (pA) NOISE vs TEMPERATURE, UNIPOLAR INPUT –40 –20 0 25 45 65 85 Temperature (°C) Noise (ppm, rms) 1ms Integration Time K = 16 Acquisition Clocks M = 128 Oversamples NOISE vs INTEGRATION TIME, UNIPOLAR INPUT 0.1 1 10 100 Integration Time (ms) Noise (ppm, rms) M = 256 O/S M = 16 O/S M = 64 O/S K = 16 Acquisition Clocks C IN = 0pF INPUT OFFSET VOLTAGE vs INPUT CAPACITANCE 0.050 0.000 –0.050 0.100 –0.150 –0.200 –0.250 –0.300 0 100 500 VBIAS (mV) C IN (pF) NOISE vs OVERSAMPLING, UNIPOLAR INPUT 1.0 0.5 Noise (ppm, rms) 1248 1 6 3 2 6 4 1 2 8 2 5 6 M Oversamples L = 1 Integration/Conversion L = 2 L = 4L = 8L = 16L = 32 L = 64L = 128 L = 256 1ms Integration Time K = 16 Acquisition Clocks C IN = 0pF
NEGATIVE PSRR vs FREQUENCY 100 20 40 60 80 100 120 140 160 180 200 PSRR (dB) 100µs Integration Time K = 16 Acquisition Clocks M = 32 Oversamples Frequency (kHz) POSITIVE PSRR vs FREQUENCY 100 20 40 60 80 100 120 140 160 180 200 Frequency (kHz) PSRR (dB) 1ms Integration Time K = 16 Acquisition Clocks M = 128 Oversamples NEGATIVE PSRR vs FREQUENCY 100 20 40 60 80 100 120 140 160 180 200 Frequency (kHz) PSRR (dB) 1ms Integration Time K = 16 Acquisition Clocks M = 128 Oversamples TYPICAL PERFORMANCE CURVES (CONT) ELECTRICAL System Clock = 2MHz, VS = ±5VDC, VREF = –2.5V, L = 1 Integration/Conversion, and TA = +25°C, unless otherwise noted. POSITIVE PSRR vs FREQUENCY 100 20 40 60 80 100 120 140 160 180 200 PSRR (dB) 100µs Integration Time K = 16 Acquisition Clocks M = 32 Oversamples Frequency (kHz)
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input range, an input current of 0.5µA integrated for 1ms will result in the full scale charge of 500pC. For voltage inputs, the input resistor is chosen to achieve the proper full scale input current. As an example, for a 5V full scale input, a 10MΩ input resistor is selected to achieve a full scale input current of 0.5µA (1ms integration time). Noise of 1.6ppm of FSR is equal to 1.6ppm x 500pC = 0.8fC in this instance, noise is 1.6pA or 8µV. For the unipolar input range, the following table shows the full scale input current required for different integration times to collect 500pC of charge and the equivalent current values for 2 and 5ppm of FSR. CURRENT INPUT The maximum average input current that can be captured by the DDC101 is ±7.8µA. This current will result in an integration time of 64µs for unipolar input range and 32µs for bipolar input range. For longer integration times, the average input current must be less. The maximum input current is limited by the slew and update rate of the internal tracking logic and CDAC. The largest input current that the DDC101 can accurately track is 7.8µA. Input currents larger than 7.8µA and high speed current input pulses can be accurately captured and digitized by the DDC101 with an external input or sensor capacitance on the DDC101 input. The average current during a com- plete integration cycle cannot exceed 7.8µA. Likewise, the total charge input must not exceed 500pC unipolar, 250pC bipolar during the integration time. An external user provided input capacitance, CS, as shown in Figure 9a, will capture the input signal charge if the input current limit is temporarily exceeded during the integration cycle. The DDC101 will then transfer the charge completely to CINT based upon conservation of charge. An additional FIGURE 9a. Current Pulse Input Capture. TABLE I. Integration Time (TINT ) and Full Scale Current (IFS ) for Full Scale 500pC Integration. TINT IFS 2ppm 5ppm 50ms 10nA 0.02pA 0.5pA 5ms 100nA 0.2pA 1pA 1ms 500nA 1pA 2.5pA 500µs1 µA 2pA 5pA 100µs5 µA 10pA 25pA i DDC101C S V Voltage across input must not exceed ±2.5V. Analog Input, pin 3 Analog Common External user provided capacitance, CSOURCE , to store current pulses. SECTION 5 DISCUSSION OF SPECIFICATIONS INPUT The DDC101 is a charge digitizing A/D converter. Low level current output sources, such as a photosensors, can be directly connected to its input. The input signal can also be a voltage connected through a user selected resistor. CHARGE INPUT The maximum charge that can be captured in one integration by the DDC101 is 500pC. In the unipolar input range mode, the maximum positive charge that can be collected in one integration is 500pC. The DDC101 has a small negative range in the unipolar mode of –1.95pC. This small negative underrange is included to allow for a small amount of leakage current from the user’s PC board and sensor. In the bipolar input range, the maximum positive charge that can be collected is +250pC. The maximum negative charge that can be collected is –251.95pC. In addition to the normal mode of one integration per conversion, DDC101 can be configured by the user for 1 to 256 integrations per conversion. When the multiple integra- tions per conversion mode is chosen, the DDC101 DSP circuitry internally averages multiple integration cycles to provide one conversion result. This result has lower noise because it is the average of multiple integrations. In this mode, the maximum total charge that can be captured by the DDC101 in 256 integrations is 128,000pC. TEST CURRENT INPUT An internal DC test current can be connected under user control to the DDC101’s input. The test current is nominally 100nA and will be summed with any applied external input signal. It is derived by a resistive network from the positive power supply. The test current is intended to test for func- tionality only. The TEST In pin of the DDC101 controls the current. When TEST is HIGH, the internal current source is ON and current is flowing into the DDC101 input. When TEST is LOW, the current source is disconnected from the input. With TEST active, positive power supply current increases by approximately 1mA. FULL SCALE RANGE The full scale range (FSR), which is referenced in the specification table, is the difference between the positive full scale charge and the negative full scale charge for the DDC101 in one integration cycle. Specifications such as noise and linearity, which are specified in percent or ppm of FSR, are referring to a value of 500pC for both unipolar and bipolar input ranges. The full scale input current for a given integration time will result in a full scale input charge. As an example for unipolar
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- Oversampling This is the low pass filter characteristic of the digital filter’s oversampling. This response reduces the broad- band noise in the input signal and the DDC101. Broad- band noise decreases as the number of oversamples increases. 3. Multiple Integrations This is the low pass filter characteristic that results when the digital filter is used to average multiple integrations. This will determine the primary response of the DDC101 if two or more integrations are internally averaged. See Section 6 for more details. SECTION 6 DETAILED THEORY OF OPERATION INTEGRATION CYCLE An integration cycle, as illustrated in Figure 11, includes the Acquisition Time, Initial Data Point Sampling, Tracking Interval, and Final Data Point Sampling. The Acquisition Time is K clock periods. The first clock cycle of the Acquisition Time is used to reset the integrating capacitor, C INT , to zero from the previous integration. The balance of the Acquisition Time insures that the DDC101 system is accurately tracking the input signal prior to initial data point acquisition. Close-ups of the Reset and Acquisition time are shown in Figures 12 and 13. The Initial Data Point is then sampled M times. The Integra- tion cycle time consists primarily of the Tracking Interval during which time the DDC101 “tracks” the integration of the input signal. The Tracking Interval is followed by the measurement of the Final Data Point with the same user selected number of samples, M. M and K are user selectable. The entire integration cycle consists of N clock periods as controlled by the user. The DDC101 operates in continuous and non-continuous integration modes. In the continuous mode, one integration follows another with no delay from the end of one integra- tion to the beginning of the next conversion. In the non- continuous mode, each new integration is started separately under user control. The Final Data point Start (FDS) input is the primary user control of the integration cycle. The FDS input controls the end of one integration cycle and the start of the next integration cycle in both the continuous and non-continuous integration modes. Measurement of the M final data point samples begins when the FDS input is activated. CONTINUOUS INTEGRATION MODE In the continuous integration mode, the “Final Data Point Start” command (using the FDS pin) initiates the measure- ment of the M final data point samples. The next integration cycle begins immediately after the final data point sampling NOISE The noise of the DDC101 improves as the input signal level decreases, thus very low level signals can be resolved. Noise is shown in the specification table for low level inputs. For unipolar input range, the DDC101 noise at low level inputs is dominated by comparator noise gained to the output; at full scale inputs, the noise is dominated by D/A converter noise. The noise at low low level inputs is a function of input capacitance; the noise at full scale is relatively independent of input capacitance. For bipolar input operation, the noise is dominated by D/A converter noise and is higher than the full scale unipolar noise. BIPOLAR INPUT ACCURACY Linearity—As a bipolar input device, the linearity of the DDC101 is specified as a percentage of full scale range that does not improve with lower input signal levels. Perfor- mance is generally limited by the linearity of the unit when operated in the bipolar input mode. Noise—In general, noise is not as important as linearity when determining total error. The output noise of the DDC101 in the bipolar mode peaks at midscale (zero input signal level). Output noise is lower for inputs above and below zero. RESET CHARGE ERROR The reset charge error (typically less than 250fC) is an offset error that could result from offset voltage, charge injection and kT/C errors. The DDC101 eliminates the effects of reset charge errors with correlated double sampling. DC BIAS VOLTAGE The DDC101 generates a small bias voltage (typically 500µV) at the input. This voltage is impressed on any sensor that is connected to the input. The DC bias voltage is the actual virtual ground voltage of the DDC101. The DDC101 input comparator circuitry includes an autozero circuit which eliminates this offset internally so that it does not produce an output error. GAIN SENSITIVITY TO VREF The DDC101 gain is dependent upon the external reference voltage, VREF . A change in the value of VREF will be seen as a directly proportional change in the gain of the DDC101. FREQUENCY RESPONSE The DDC101 is a sampling system whose transfer function has three separate frequency components. These compo- nents are multiplied together to make the total frequency characteristic of the DDC101. The three components are: 1. Basic Integration This is the characteristic sin(x)/x response of the basic integration function. This response is controlled by the integration time of the DDC101.
17 DDC101
ment output data format only. is performed each integration cycle. time of 64µs for unipolar inputs and 32µs for bipolar inputs. per conversion as described in the following text. the positive full scale charge. This is +500pC to –1.95pC. level PC board parasitic leakages. negative full scale of –251.95pC. FIGURE 13. Close-up of Reset and Acquisition Time for FIGURE 14. Close-up of End of One Integration Cycle and asynchronously with the end of the previous integration. Sampling (CDS) operation may not be advantageous.
additional conversion sampling limitations. TABLE V. Integrations/Conversion vs Conversion Time. FIGURE 15. Conversion Cycle with Two Integrations. measurement time of the DDC101, TMEAS ; see Figure 16. noise decreases as the number of oversamples increases. the digital filter is used to average multiple integrations. frequency response and are then aliased into DC to fCONV /2.
19 DDC101
TABLE VI. Basic Integration Frequency Response Examples. FIGURE 16. Basic Integration Frequency Response. decreases at approximately 20dB/decade. TABLE VII. Oversample Frequency Response Examples. The DDC101's transfer response has a linear phase characteristic as indicated by the exponential term.
- e − jπfL N − K −1() /fCLK Basic Integration Oversampling Multiple Integrations Linear Phase
21 DDC101
integrator’s signal accumulation characteristics. bit stream transmitted by the user into the SETUP Input pin.
- Acquisition Time Control, K 2 bits
- Multiple Integration Control
- Unipolar or Bipolar Input Range 1 bit
See Figure 5: SETUP Timing Diagram. sition time always begins with one clock period for reset. the Initial Data Point is not acquired if “no CDS” is selected. FIGURE 21. Comparison of DDC101 with Ideal Integrator.
- πfT MEAS sin(πfT MEAS )· M sin(πf/fCLK ) sin(πfM/ fCLK ) .
FIGURE 20. Product of Frequency Response of Basic Inte- TABLE IX. Acquisition Time Control, K.
When operating in the unipolar input range, CDS functions with either output data format—straight binary or binary two’s complement. When operating in the bipolar input range, CDS functions correctly only with binary two’s complement output data format. Oversampling Control Samples/Integration, M This control sets the number of samples, M, used by the DDC101 to oversample the initial and final data points. M can be set for these values: 1, 2, 4, 8, 16, 32, 64, 128, 256. Broadband noise in the conversion is reduced roughly in proportion to the square root of M. Therefore, a conversion with 128 oversamples will have 1/2 the broadband noise of a conversion with 32 oversamples. See the previous fre- quency response discussion. Multiple Integration Control, L This control sets the number of integrations per conversion cycle, L. It is used to reduce the data rate, increase the magnitude of the input signal range, and/or reduce the noise. The product of L and M must be 256 or less. Output Format Two output formats are available for either the unipolar or bipolar input ranges: Binary Two’s Complement (BTC) and Straight Binary. UNIPOLAR INPUT RANGE For Binary Two’s Complement, output data format, the output word is a 21-bit Two’s Complement word. The first bit is the sign bit followed by the Most Significant Bit (MSB), etc. The output range is +100%FS to –0.4%FS, where FS is 500pC. BIPOLAR INPUT RANGE For Binary Two’s Complement, output data format, the output word is a 21-bit Two’s Complement word. The first bit is the sign bit followed by the Most Significant Bit (MSB), etc. The output range is +100%FS to –100.8%FS, where FS is 250pC. For the bipolar input range, the output code table changes with the use of Correlated Double Sam- pling (CDS). (There is no difference with or without CDS in the output code table when using the unipolar input range.) CODE INPUT SIGNAL 0 1111 1111 1111 1111 1111 +100%FS +500pC 0 1111 1111 1111 1111 1110 +100%FS –1LSB 0 0000 0000 0000 0000 0001 +1SLB 0 0000 0000 0000 0000 0000 Zero 0pC 1 1111 1111 1111 1111 1111 –1LSB 1 1111 1111 0000 0000 0000 –0.4%FS –1.95pC TABLE X. BTC Code Table—Unipolar Input Range. For Straight Binary output data format, the output is a 20-bit straight binary word. The first bit is the Most Significant Bit (MSB), etc. The output range is +99.6%FS to –0.4%FS in which +99.6%FS represents positive full scale and –0.4%FS represents the minimum input. CODE INPUT SIGNAL 1111 1111 1111 1111 1111 +99.6%FS 498.05pC 1111 1111 1111 1111 1110 +99.6%FS –1LSB 0000 0001 0000 0000 0001 +1LSB 0000 0001 0000 0000 0000 Zero 0000 0000 0000 0000 0000 –0.4%FS –1.95pC TABLE XI. Straight Binary Code Table — Unipolar Input Range. CODE INPUT SIGNAL 0 1111 1111 1111 1111 1111 +100%FS +250pC 0 1111 1111 1111 1111 1110 +100%FS –1LSB 0 1000 0000 0000 0000 0001 +1LSB 0 1000 0000 0000 0000 0000 Zero 0pC 0 0111 1111 1111 1111 1111 –1LSB 0 0000 0000 0000 0000 0001 –100%FS + 1SLB 0 0000 0000 0000 0000 0000 –100%FS –250pC 1 1111 1111 0000 0000 0000 –100.8%FS –251.95pC TABLE XII. BTC Code Table — Bipolar Input Range with- out CDS. For Straight Binary output data format with the bipolar input range, the output is a 20-bit straight binary word. The first bit is the Most Significant Bit (MSB), etc. The output range is +100%FS to –100%FS in which +100%FS represents positive full scale and –100%FS represents the negative full scale. When using the straight binary output data format in bipolar input range, do not use CDS. This will cause a negative overflow to occur. CODE INPUT SIGNAL 0 0111 1111 1111 1111 1111 +100%FS +250pC 0 0111 1111 1111 1111 1110 +100%FS – 1LSB 0 0000 0000 0000 0000 0001 +1LSB 0 0000 0000 0000 0000 0000 Zero 0pC 1 1111 1111 1111 1111 1111 –1LSB 1 1000 0000 0000 0000 0001 –100%FS + 1LSB 1 1000 0000 0000 0000 0000 –100%FS –250pC 1 0111 1111 0000 0000 0000 –100.8%FS –251.95pC TABLE XIII. BTC Code Table — Bipolar Input Range with CDS. CODE INPUT SIGNAL 1111 1111 1111 1111 1111 +100%FS +250pC 1111 1111 1111 1111 1110 +100%FS – 1LSB 1000 0000 0000 0000 0001 +1LSB 1000 0000 0000 0000 0000 Zero 0pC 0111 1111 1111 1111 1111 –1LSB 0000 0000 0000 0000 0000 –100%FS –250pC TABLE XIV. Straight Binary Code Table — Bipolar Input Range without CDS. SETUP INPUT CODE Acquisition Time Control—K - 2 bits CODE RESULT 00 1 Reset clock period, 0 clock period Acquisition Time, CDS disabled, no initial data point, 01 1 Reset clock period, 0 clock period Acquisition Time 10(1) 1 Reset clock period, 15 clock period Acquisition Time 11 1 Reset clock period, 31 clock period Acquisition Time NOTE: (1) Recommended for continuous integration mode.
23 DDC101
the DDC101 package as possible. the pins for best performance. V DD + that is non-synchronous with DDC101 operation. from the analog input signals as possible on the PC board. use of guard patterns to protect the analog input.
0 Unipolar
1 Bipolar
1 Binary Two's Complement
0 Straight Binary
FIGURE 22. PC Board Layout Showing “Guard” Traces Surrounding Analog Input Pin and Traces. FIGURE 23. Positive Supply Connection Options.
FIGURE 24. Example of Basic DDC101 Circuit Connections. it will be overwritten with new data. periods. This is shown in Figure 25. functions as illustrated in Table XV. TABLE XV. Components of Integration Cycle.
25 DDC101
FIGURE 25. DDC101 Equivalent Integrator Output for Single Integration with CDS. integration time, TINT ) is 1ms. averaged with the result at the midpoint of the sample group. TABLE XVI. Measurement Time with CDS. TABLE XVII. Measurement Time without CDS. DDC101 digital output is precise integration of input during measurement time.
27 DDC101
FIGURE 28. Photo of DEM-DDC101P-C Evaluation Fixture.
25 Pin Cable
34 Pin Cable
FIGURE 29. DEM-DDC101P-C Evaluation Fixture Connection Diagram.