DCR010503 TI | Alldatasheet
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Technical content
DCR01 Series, 1-W, 1000-VRMS Isolated, Regulated DC/DC Converter Modules
1 Features
- 1-kV isolation (operational): 1-second test
- Continuous voltage applied across isolation barrier: 60 VDC, 42.5 VAC
- UL1950 recognized component
- 10-pin PDIP and 12-pin SOP packages
- Input voltage: 5 V, 12 V, or 24 V
- Output voltage: 3.3 V or 5 V
- Device-to-device synchronization
- 400-kHz switching frequency
- Short-circuit protection
- Thermal protection
- High efficiency
- 125 FITs at 55°C
2 Applications
- Point-of-use power conversion
- Digital interface power
- Ground loop elimination
- Power-supply noise reduction
3 Description
The DCR01 family is a series of high-efficiency, input-isolated, output-regulated DC/DC converters. In addition to 1-W nominal, galvanically-isolated output power capability, this range of DC/DC converters offer very low output noise, thermal protection, and high accuracy. This combination of features and small size makes the DCR01 series of devices suitable for a wide range of applications, and is an easy-to-use solution in applications requiring signal path isolation. CAUTION This product has operational isolation and is intended for signal isolation only. It must not be used as a part of a safety isolation circuit requiring reinforced isolation. See definitions in the feature description. Device Information Part Number Package(1) Body Size (NOM) DCR01 PDIP (10) 22.86 mm × 6.61 mm SOP (12) 17.90 mm × 7.50 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. SYNC +VS Input Controller ENABLE ERROR -VS VREC LDO Regulator -VOUT +VOUT DCR01 Block Diagram DCR010503, DCR012405, DCR010505, DCR011203, DCR011205, DCR012403 SBVS013E – OCTOBER 2001 – REVISED JULY 2022 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
12.1 Receiving Notification of Documentation Updates..22
13 Mechanical, Packaging, and Orderable
4 Revision History
Changes from Revision D (June 2016) to Revision E (July 2022) Page Changes from Revision C (May 2003) to Revision D (January 2016) Page
- Added Device Information table, Device Comparison table, ESD Ratings table, Thermal Information table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and DCR010503, DCR012405, DCR010505, DCR011203, DCR011205, DCR012403 SBVS013E – OCTOBER 2001 – REVISED JULY 2022 www.ti.com
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5 Device Comparison Table
at TA = 25°C, +VS = nominal, IO = 10 mA, CIN = 2.2-µF ceramic, CFILTER = 1-µF ceramic, COUT = 0.1-µF ceramic (unless otherwise noted) Device Number (3) Input Voltage VS (V) Output Voltage VO (V) Output Current (mA) Ripple (1) (mVp-p) Noise (2) (mVp-p) Supply Current (mA) IO = 0 mA IO = 10 mA IO = 100% LOAD Typical Typical Maximum Typical Typical Typical Typical Typical DCR010503P 3.3 300 5 35 18 28 335 DCR010503U 8 23 24 33 339 DCR010505P 5 200 6 20 25 40 306 DCR010505U 9 20 25 40 306 DCR011203P 3.3 390 10 54 13 17 173 DCR011203U 300 8 22 13 17 136 DCR011205P 5 200 6 45 13 18 125 DCR011205U 6 21 14 19 123 DCR012403P 3.3 390 10 22 17 18 97 DCR012403U 300 8 22 15 17 75 DCR012405P 5 200 10 22 15 18 69 DCR012405U 13 32 15 18 67 (1) 20-MHz bandwidth, 50% load (2) 100-MHz bandwidth, 50% load (3) The last character in the part number denotes the package type (P = PDIP, U = SOP). www.ti.com DCR010503, DCR012405, DCR010505, DCR011203, DCR011205, DCR012403 SBVS013E – OCTOBER 2001 – REVISED JULY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: DCR010503 DCR012405 DCR010505 DCR011203 DCR011205 DCR012403
6 Pin Configuration and Functions
-VOUT VREC +VOUT 10 DNC SYNC DCR01P 17 -VS
11 ENABLE
12 ERROR
Figure 6-1. 10-Pin PDIP NVE Package (Top View) 1+VS -VOUT VREC NC +VOUT 15 DNC SYNC DCR01U 27 -VS
16 ENABLE
17 ERROR
26 -VS Figure 6-2. 12-Pin SOP DVB Package (Top View) Table 6-1. Pin Functions Pin I/O Description Name PDIP SOP ENABLE 11 16 I Output voltage enable ERROR 12 17 O Error flag active low DNC 10 15 — Do not connect. NC 2 3 — No connection SYNC 18 28 I Synchronization input –VOUT 8 13 O Output ground +VOUT 9 14 O Voltage output VREC 7 12 O Rectified output –VS 17 26, 27 I Input ground +VS 1 1, 2 I Voltage input DCR010503, DCR012405, DCR010505, DCR011203, DCR011205, DCR012403 SBVS013E – OCTOBER 2001 – REVISED JULY 2022 www.ti.com
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2) MIN MAX UNIT Input voltage 5-V input devices 7 V12-V input devices 15 24-V input devices 29 Lead temperature PDIP package Surface temperature of device body or pins (maximum 10 s) 270 °C Reflow solder temperature SOP package Surface temperature of device body or pins 260 °C Storage temperature, Tstg –60 125 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) See the package option addendum at the end of the datasheet for additional package information.
7.2 ESD Ratings
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±250 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Input voltage 5-V input devices 4.5 5 5.5 V12-V input devices 10.8 12 13.2 24-V input devices 21.6 24 26.4 Operating temperature –40 85 °C
7.4 Thermal Information
THERMAL METRIC(1) DCR01 UNITNVE (PDIP) DVB (SOP)
10 PINS 12 PINS
RθJA Junction-to-ambient thermal resistance 60 60 °C/W RθJC(top) Junction-to-case (top) thermal resistance 26 26 °C/W RθJB Junction-to-board thermal resistance 24 24 °C/W ψJT Junction-to-top characterization parameter 7 7 °C/W ψJB Junction-to-board characterization parameter 24 24 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. www.ti.com DCR010503, DCR012405, DCR010505, DCR011203, DCR011205, DCR012403 SBVS013E – OCTOBER 2001 – REVISED JULY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: DCR010503 DCR012405 DCR010505 DCR011203 DCR011205 DCR012403
7.5 Electrical Characteristics
at TA = 25°C, +VS = nominal, IO = 10 mA, CIN = 2.2-µF ceramic, CFILTER = 1-µF ceramic, COUT = 0.1-µF ceramic (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUTPUT Nominal output voltage (+VOUT) DCR01xx03 3.3 V DCR01xx05 5 Setpoint accuracy 0.5% 2% Output short-circuit protected Duration Infinite Line regulation 1 mV/V Over line and load IO = 10 mA to full load, over +VS range 1% 2.5% Temperature variation –40°C ≤ TA ≤ +85°C 1% INPUT Nominal input voltage (+VS) DCR0105xx 5 VDCR0112xx 12 DCR0124xx 24 Voltage range –10% 10% Reflected ripple current 20-MHz bandwidth, IO = 100% Load 8 mAp-p ISOLATION Isolation 1-s flash test Voltage 1 kVrms dV/dt 500 V/s Leakage current 30 nA Continuous working voltage across isolation barrier DC 60 VDC AC 42.5 VAC Barrier capacitance 25 pF OUTPUT ENABLE CONTROL Logic high input voltage 2 VREC V Logic high input current 2 < VENABLE < VREC 100 nA Logic low input voltage –0.2 0.5 V Logic low input current 0 < VENABLE < 0.5 100 nA Rectified output, VREC All 3.3-V outputs 3.3 V All 5-V outputs 5 ERROR FLAG Logic high open-collector leakage VERROR = 5 V 10 µA Logic low output voltage Sinking 2 mA 0.4 V THERMAL SHUTDOWN Junction temperature Temperature activated 150 Temperature deactivated 130 SYNCHRONIZATION PIN Max external capacitance on SYNC pin 3 pF Internal oscillator frequency 720 800 880 kHz External synchronization frequency 720 880 kHz External synchronization signal high 2.5 3 V External synchronization signal low 0 0.4 V TEMPERATURE RANGE Operating –40 85 °C DCR010503, DCR012405, DCR010505, DCR011203, DCR011205, DCR012403 SBVS013E – OCTOBER 2001 – REVISED JULY 2022 www.ti.com
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7.6 Typical Characteristics
at TA = 25°C, +VS = nominal, IO = 10 mA, CIN = 2.2 µF, CFILTER = 1 µF, COUT = 0.1 µF (unless otherwise noted) Load (%) Efficiency (%) 0 10 20 30 40 50 60 70 80 90 100 D001 Ambient Temp 85°C 25°C -40°C DCR010503 Figure 7-1. Efficiency vs Load Load (%) Efficiency (%) 0 10 20 30 40 50 60 70 80 90 100 D002 Ambient Temp 85°C 25°C -40°C DCR010505 Figure 7-2. Efficiency vs Load Load (%) Efficiency (%) 0 10 20 30 40 50 60 70 80 90 100 D003 DCR011203P Figure 7-3. Efficiency vs Load Load (%) Efficiency (%) 0 10 20 30 40 50 60 70 80 90 100 D004 DCR011205P Figure 7-4. Efficiency vs Load Load (%) Efficiency (%) 0 10 20 30 40 50 60 70 80 90 100 D005 DCR012403P Figure 7-5. Efficiency vs Load Load (%) Efficiency (%) 0 10 20 30 40 50 60 70 80 90 100 D006 DCR012405P Figure 7-6. Efficiency vs Load www.ti.com DCR010503, DCR012405, DCR010505, DCR011203, DCR011205, DCR012403 SBVS013E – OCTOBER 2001 – REVISED JULY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: DCR010503 DCR012405 DCR010505 DCR011203 DCR011205 DCR012403
Load (%) Output Voltage (V) 0 10 20 30 40 50 60 70 80 90 100 4.983 4.986 4.989 4.992 4.995 4.998 5.001 5.004 5.007 5.01 5.013 5.016 D010 Device Number DCR012405 DCR011205 DCR010505 All 5-V Output Devices Figure 7-7. 5-V Output Load Regulation Load (%) Output Voltage (V) 0 10 20 30 40 50 60 70 80 90 100 4.94 4.96 4.98 5.02 5.04 5.06 D008 Ambient Temp 85°C 25°C -40°C DCR010505P Figure 7-8. Load Regulation Load (%) Output Voltage (V) 0 10 20 30 40 50 60 70 80 90 100 3.2775 3.28 3.2825 3.285 3.2875 3.29 3.2925 3.295 3.2975 3.3 3.3025 3.305 D009 Device Number DCR010503 DCR012403 DCR011203 All 3.3-V Output Devices Figure 7-9. 3.3-V Output Load Regulation Load (%) Output Voltage (V) 0 10 20 30 40 50 60 70 80 90 100 3.27 3.275 3.28 3.285 3.29 3.295 3.3 3.305 3.31 3.315 3.32 D007 Ambient Temp 85°C 25°C -40°C DCR010503P Figure 7-10. Load Regulation Load (%) Ripple Voltage (mVp-p) 20 40 60 80 1000 All devices except for DCR011203P and DCR012403P 20-MHz Bandwidth Figure 7-11. Output Voltage Ripple Load (%) Ripple Voltage (mVp-p) 30.0 25.0 20.0 15.0 10.0 5.0 20 40 60 80 1000 DCR011203P 20-MHz Bandwidth DCR012403P Figure 7-12. Output Voltage Ripple DCR010503, DCR012405, DCR010505, DCR011203, DCR011205, DCR012403 SBVS013E – OCTOBER 2001 – REVISED JULY 2022 www.ti.com
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Figure 7-19. DCR010505P Output Voltage Noise at 100% Load 200ns/div 5mV/div 20-MHz Bandwidth Figure 7-20. DCR010503P Output Voltage Ripple at 100% Load 200ns/div 20mV/div Load Current Output Voltage 100-MHz Bandwidth Figure 7-21. DCR010503P Output Voltage Noise at 100% Load 10µs/div 30mA Changing to 325mA 200mV/div Load Current Output Voltage Figure 7-22. DCR010503P Load Transient Response 10µs/div 150mA Changing to 300mA 200mV/div Load Current Output Voltage Figure 7-23. DCR010503P Load Transient Response 10µs/div 20mA Changing to 200mA 200mV/div Load Current Output Voltage Figure 7-24. DCR010505P Load Transient Response DCR010503, DCR012405, DCR010505, DCR011203, DCR011205, DCR012403 SBVS013E – OCTOBER 2001 – REVISED JULY 2022 www.ti.com
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10µs/div 100mA Changing to 200mA 200mV/div Load Current Output Voltage Figure 7-25. DCR010505P Load Transient Response www.ti.com DCR010503, DCR012405, DCR010505, DCR011203, DCR011205, DCR012403 SBVS013E – OCTOBER 2001 – REVISED JULY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: DCR010503 DCR012405 DCR010505 DCR011203 DCR011205 DCR012403
8 Detailed Description
8.1 Overview
The DCR01 series of power modules offer isolation from a regulated power supply operating from a choice of input voltages. The DCR01s provide a regulated 3.3-V or 5-V output voltage at a nominal output power of 1 W or above. The DCR01 devices include a low dropout linear regulator internal to the device to achieve a well-regulated output voltage. The DCR01 devices are specified for operational isolation only. The circuit design uses an advanced BiCMOS and DMOS process.
8.2 Functional Block Diagram
-VS VREC LDO Regulator -VOUT +VOUTOscillator 800 kHz Divide-by-2 Reset Watchdog Startup PSU Thermal Shutdown Power Stage Input Controller
8.3 Feature Description
8.3.1 Isolation
Underwriters Laboratories, UL™ defines several classes of isolation that are used in modern power supplies. Safety extra low voltage (SELV) is defined by UL (UL1950 E199929) as a secondary circuit, which is so designated and protected so that under normal and single fault conditions, the voltage between any two accessible parts or between an accessible part and the equipment earthing terminal for operational isolation does not exceed steady state 42.5-VRMS or 60-VDC peak for more than one second.
8.3.1.1 Operation or Functional Isolation
The type of isolation used in the DCR01 products is referred to as operational or functional isolation. Insulated wire used in the construction of the transformer acts as the primary isolation barrier. A high-potential (hipot), one-second duration test (dielectric voltage, withstand test) is a production test used to verify that the isolation barrier is functioning. Products with operational isolation must never be used as an element in a safety-isolation system.
8.3.1.2 Basic or Enhanced Isolation
Basic or enhanced isolation is defined by specified creepage and clearance limits between the primary and secondary circuits of the power supply. Basic isolation is the use of an isolation barrier in addition to the insulated wire in the construction of the transformer. Input and output circuits must also be physically separated by specified distances. DCR010503, DCR012405, DCR010505, DCR011203, DCR011205, DCR012403 SBVS013E – OCTOBER 2001 – REVISED JULY 2022 www.ti.com
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The DCR01 products do not provide basic or enhanced isolation.
8.3.1.3 Working Voltage
For a device with operational isolation, the continuous working voltage that can be applied across the device in normal operation must be less than 42.5 VRMS or 60 VDC. WARNING Do not use the device as an element of a safety isolation system that exceeds the SELV limit. If the device is expected to function correctly with more than 42.5 V RMS or 60 V DC applied continuously across the isolation barrier, then the circuitry on both sides of the barrier must be regarded as operating at an unsafe voltage, and further isolation or insulation systems must form a barrier between these circuits and any user- accessible circuitry according to safety standard requirements.
8.3.1.4 Isolation Voltage Rating
The terms Hipot test , flash-tested, withstand voltage , proof voltage , dielectric withstand voltage , and isolation test voltage are all terms that relate to the same thing; a test voltage applied for a specified time across a component designed to provide electrical isolation to verify the integrity of that isolation. TI’s DCR01 series of DC/DC converters are all 100% production tested at 1.0 kVAC for one second.
8.3.1.5 Repeated High-Voltage Isolation Testing
Repeated high-voltage isolation testing of a barrier component can degrade the isolation capability, depending on materials, construction, and environment. The DCR01 series of DC/DC converters have toroidal, enameled, wire isolation transformers with no additional insulation between the primary and secondary windings. While a device can be expected to withstand several times the stated test voltage, the isolation capability depends on the wire insulation. Any material, including this enamel (typically polyurethane), is susceptible to eventual chemical degradation when subject to very-high applied voltages. Therefore, strictly limit the number of high-voltage tests and repeated high-voltage isolation testing. However, if it is absolutely required, reduce the voltage by 20% from specified test voltage with a duration limit of one second per test.
8.3.2 Power Stage
The DCR01 series of devices use a push-pull, center-tapped topology. The DCR01 devices switch at 400 kHz (divide-by-2 from an 800-kHz oscillator).
8.3.3 Rectification
The output of the transformer is full wave rectified and filtered by the external 1- μF ceramic capacitor connected to VREC.
8.3.4 Regulator
The internal low dropout linear regulator provides a well-regulated output voltage throughout the operating range of the device.
8.3.5 Oscillator and Watchdog
The onboard, 800-kHz oscillator generates the switching frequency through a divide-by-2 circuit. The oscillator can be synchronized to other DCR01 device circuits or an external source, and is used to minimize system noise. A watchdog circuit monitors the operation of the oscillator circuit. The oscillator can be disabled by pulling the SYNC pin low. When the SYNC pin goes low, the output pins transition into tri-state mode, which occurs within 2 μs. www.ti.com DCR010503, DCR012405, DCR010505, DCR011203, DCR011205, DCR012403 SBVS013E – OCTOBER 2001 – REVISED JULY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: DCR010503 DCR012405 DCR010505 DCR011203 DCR011205 DCR012403
8.3.6 ERROR Flag
The DCR01 has an ERROR pin, which provides a power good flag, as long as the internal regulator is in regulation. If the ERROR output is required, place a 10-k Ω resistor between the ERROR pin and the output voltage.
8.3.7 Synchronization
When more than one DC/DC converter is switching in an application, beat frequencies and other electrical interference can be generated. This interference occurs because of the small variations in switching frequencies between the DC/DC converters. The DCR01 series of devices overcome this interference by allowing devices to be synchronized to one another. Synchronize up to eight devices by connecting the SYNC pins of each device, taking care to minimize the capacitance of tracking. Stray capacitance (greater than 3 pF) reduces the switching frequency, or can sometimes stop the oscillator circuit. The maximum recommended voltage applied to the SYNC pin is 3 V. For an application that uses more than eight synchronized devices, use an external device to drive the SYNC pins. The External Synchronization of the DCP01/02 Series of DC/DC Converters application report describes this configuration. Note During the start-up period, all synchronized devices draw maximum current from the input simultaneously. If the input voltage falls below approximately 4 V, the devices may not start up. A ceramic capacitor must be connected close to the input pin of each device. Use a 2.2- μF capacitor for 5-V input devices, and a 0.47-μF capacitor for the 12-V and 24-V devices.
8.3.8 Construction
The basic construction of the DCR01 series of devices is the same as standard integrated circuits. The molded package contains no substrate. The DCR01 series of devices are constructed using an IC, low dropout linear regulator, rectifier diodes, and a wound magnetic toroid on a leadframe. Because the package contains no solder, the devices do not require any special printed-circuit board (PCB) assembly processing. This architecture results in an isolated DC/DC converter with inherently high reliability.
8.3.9 Thermal Considerations
Due to the high power density of this device, it is advisable to provide ground planes on the input and output rails. The output regulator is mounted on a copper leadframe, and a ground plane serves as an efficient heatsink.
8.3.10 Decoupling – Ripple Reduction
Due to the very low forward resistance of the DMOS switching transistors, high current demands are placed upon the input supply for a short time. By using a good-quality low Equivalent Series Resistance (ESR) capacitor of 2.2 μF (minimum) for the 5-V input devices and a 0.47- μF capacitor for the 12-V and 24-V devices, placed close to the IC supply input pins, the effects on the power supply can be minimized. The high switching frequency of 400 kHz allows relatively small values of capacitors to be used for filtering the rectified output voltage. A good-quality, low-ESR, 1- μF ceramic capacitor placed close to the VREC pin and output ground is required and reduces the ripple. The output at VREC is full wave rectified and produces a ripple of 800 kHz. TI recommends that a 0.1- μF, low-ESR, ceramic capacitor is connected close to the output pin and ground to reduce noise on the output. The capacitor values listed are minimum values. If lower ripple is required, the filter capacitor must be increased in value to 2.2 μF. As with all switching power supplies, the best performance is obtained with low-ESR, ceramic capacitors connected close to the device pins. If low-ESR, ceramic capacitors are not used, the ESR generates a voltage drop when the capacitor is supplying the load power. Often a larger capacitor is chosen for this purpose, when a low-ESR, smaller capacitor performs as well. DCR010503, DCR012405, DCR010505, DCR011203, DCR011205, DCR012403 SBVS013E – OCTOBER 2001 – REVISED JULY 2022 www.ti.com
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TI does not recommend that the DCR01 be fitted using an IC socket, as this degrades performance.
8.4 Device Functional Modes
8.4.1 Device Disable and Enable
Each of the DCR01 series devices can be disabled or enabled by driving the SYNC pin using an open-drain CMOS gate. If the SYNC pin is pulled low, the DCR01 becomes disabled. The disable time depends upon the external loading. The internal disable function is implemented in 2 μs. Removal of the pulldown causes the DCR01 to be enabled. Capacitive loading on the SYNC pin must be minimized ( ≤ 3 pF) to prevent a reduction in the oscillator frequency. The External Synchronization of the DCP01/02 Series of DC/DC Converters application report describes disable and enable control circuitry. This document contains information on how to null the effects of additional capacitance on the SYNC pin. The frequency of the oscillator can be measured at V REC, since this is the fundamental frequency of the ripple component.
8.4.2 Regulated Output Disable and Enable
The regulated output of the DCR01 can be disabled by pulling the ENABLE pin LOW. Disabling the output voltage this way still produces a voltage on the V REC pin. When using the ENABLE control, TI recommends placing a 10-kΩ resistor between the V REC and ENABLE pins. The ENABLE pin only controls the internal linear regulator. If disabling the regulated output is not required, pull the ENABLE pin HIGH by shorting it directly to the V REC pin, which enables the regulated output voltage, thus allowing the output to be controlled from the isolated side. www.ti.com DCR010503, DCR012405, DCR010505, DCR011203, DCR011205, DCR012403 SBVS013E – OCTOBER 2001 – REVISED JULY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: DCR010503 DCR012405 DCR010505 DCR011203 DCR011205 DCR012403
9 Application and Implementation
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 DCR01 Single Voltage Output
The DCR01 can be used to provide a single voltage output by connecting it as shown in Figure 9-1. The ERROR output signal is pulled up to the value of V OUT. The value of R ERR depends on the loading on the ERROR line, however, the total load on the ERROR line must not exceed the value given in the Electrical Charcteristics. The output can be permanently enabled by connecting the ENABLE pin to the V REC pin. The DCR01 can be enabled remotely by connecting the ENABLE pin to V REC through a pullup resistor (R EN); the value of this resistor is not critical for the DCR01 as only a small current flows. The switch SW1 can be used to pull the ENABLE pin LOW, thus disabling the output. The switching devices can be a bipolar transistor, FET, or a mechanical device; the main load that it sees is REN. VIN COUT 0.1 µFDCR01 +VS ±VS ERROR CIN (1) ±VOUT +VOUT ±VOUT SYNC +VOUT ENABLE VREC ERROR CFILTER 1 µF RERR 10 k REN 10k SW1 Figure 9-1. DCR01 Single Output Voltage DCR010503, DCR012405, DCR010505, DCR011203, DCR011205, DCR012403 SBVS013E – OCTOBER 2001 – REVISED JULY 2022 www.ti.com
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9.1.2 Generating Two Positive Output Voltages
Two DCR01s can be used to create output voltages of +3.3 V and +5 V, as shown in Figure 9-2 . The two DCR01s are connected in self-synchronization, thus locking the oscillators of both devices to a single frequency. The ERROR and ENABLE facilities can be used in a similar configuration for a single DCR01. The filter capacitors connected to the V REC pins (CFILTER) must be kept separate from each other and connected in close proximity to their respective DCR01. VIN COUT 0.1 µFDCR01 +VS ±VS ERRORCIN (1) ±VOUT +VOUT1 -VOUT SYNC +VOUT ENABLE VREC ERROR1 CFILTER 1 µF RERR 10 k VIN COUT 0.1 µFDCR01 +VS ±VS ERROR CIN (1) ±VOUT +VOUT2SYNC +VOUT ENABLE VREC ERROR2 CFILTER 1 µF RERR 10 k Figure 9-2. Two Positive Voltages from Self-Synchronized DCR01s
9.1.3 Generation of Dual Polarity Voltages from Two Self-Synchronized DCR01s
Two DCR01s can be configured to produce a dual polarity supply (that is, ±5 V); the circuit must be connected as shown in Figure 9-3. Observe that both devices are producing a positive regulated output; therefore the ERROR, ENABLE, and VREC are all relative to the –VOUT pin of that particular device and must not be directly connected together, or in the case of the negative output device, connected to the common 0-V output. VIN COUT 0.1 µFDCR01 +VS ±VS ERRORCIN (1) ±VOUT SYNC +VOUT ENABLE VREC CFILTER 1 µF VIN COUT 0.1 µFDCR01 +VS ±VS ERROR CIN (1) ±VOUT VNEG O/P SYNC +VOUT ENABLE VREC CFILTER 1 µF VPOS O/P Figure 9-3. Dual Polarity Voltage Generation www.ti.com DCR010503, DCR012405, DCR010505, DCR011203, DCR011205, DCR012403 SBVS013E – OCTOBER 2001 – REVISED JULY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: DCR010503 DCR012405 DCR010505 DCR011203 DCR011205 DCR012403
9.2 Typical Application
VIN = 5V COUT 0.1 µF DCR010505 +VS ±VS +VOUT CIN 2.2 µF ±VOUT +VOUT = 5V ±VOUT SYNC ERROR VREC ENABLE CFILTER 1.0 µF RERR 10 k Copyright © 2016, Texas Instruments Incorporated Figure 9-4. DCR01 Typical Schematic
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 9-1 and follow the design procedure. Table 9-1. Design Example Parameters Design Parameter Value Input voltage, VIN 5 V typical Output voltage, VOUT 5 V regulated Output current rating 200 mA Isolation 1000-V operational
9.2.2 Detailed Design Procedure
9.2.2.1 Input Capacitor
For this design, a 2.2-μF ceramic capacitor is required for the input decoupling capacitor.
9.2.2.2 Output Capacitor
For this design, a 0.1-μF ceramic capacitor is required for between +VOUT and –VOUT.
9.2.2.3 Filter Capacitor
A high-quality, low-ESR, 1-μF ceramic capacitor placed close to the VREC pin and output ground is required to reduce output voltage ripple.
9.2.2.4 ERROR Flag
Place a 10-kΩ resistor between the ERROR pin and the output voltage to provide a power good signal when the internal regulator is in regulation. DCR010503, DCR012405, DCR010505, DCR011203, DCR011205, DCR012403 SBVS013E – OCTOBER 2001 – REVISED JULY 2022 www.ti.com
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9.2.3 Application Curves
Load (%) Efficiency (%) 0 10 20 30 40 50 60 70 80 90 100 D002 Ambient Temp 85°C 25°C -40°C Figure 9-5. DCR010505 Efficiency Load (%) Output Voltage (V) 0 10 20 30 40 50 60 70 80 90 100 4.94 4.96 4.98 5.02 5.04 5.06 D008 Ambient Temp 85°C 25°C -40°C Figure 9-6. DCR010505 Load Regulation
10 Power Supply Recommendations
The DCR01 is a switching power supply, and as such, can place high peak current demands on the input supply. To avoid the supply falling momentarily during the fast switching pulses, ground and power planes must be used to connect the power to the input of DCR01. If this connection is not possible, then the supplies must be connected in a star formation with the traces made as wide as possible. www.ti.com DCR010503, DCR012405, DCR010505, DCR011203, DCR011205, DCR012403 SBVS013E – OCTOBER 2001 – REVISED JULY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: DCR010503 DCR012405 DCR010505 DCR011203 DCR011205 DCR012403
11 Layout
11.1 Layout Guidelines
Carefully consider the layout of the PCB for the best results to be obtained. Input and output power and ground planes provide a low-impedance path for the input and output power. For the output, the positive and negative voltage outputs conduct through wide traces to minimize losses. A good-quality, low-ESR, ceramic capacitor placed as close as practical across the input reduces reflected ripple and ensure a smooth start-up. A good-quality, low-ESR, ceramic capacitor placed as close as practical across the rectifier output terminal and output ground to provide the best ripple and noise performance. The location of the decoupling capacitors in close proximity to their respective pins ensures low losses due to the effects of stray inductance, thus improving the ripple performance. This location is of particular importance to the input decoupling capacitor, because this capacitor supplies the transient current associated with the fast switching waveforms of the power drive circuits. If the SYNC pin is being used, the tracking between device SYNC pins must be short to avoid stray capacitance. Never connect a capacitor to the SYNC pin. If the SYNC pin is not being used it is advisable to place a guard ring (connected to input ground) around this pin to avoid any noise pick-up. Ensure that no other trace is in close proximity to this trace SYNC trace to decrease the stray capacitance on this pin. The stray capacitance affects the performance of the oscillator. Figure 11-1 shows a schematic for a single DCR01, SOP package device. Figure 11-2 and Figure 11-3 show a typical layout for the SOP package DCR01 device. The layout shows proper placement of capacitors and power planes.
11.2 Layout Examples
+VS ±VS DCR01U VREC +VOUT ±VOUT13 28SYNC +VS -VS VREC -VOUT +VOUT 27 ±VS +VS ERROR 16ENABLE Figure 11-1. DCR01 PCB Schematic, U Package DCR010503, DCR012405, DCR010505, DCR011203, DCR011205, DCR012403 SBVS013E – OCTOBER 2001 – REVISED JULY 2022 www.ti.com
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
Underwriters Laboratories, UL™ is a trademark of UL LLC. TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. DCR010503, DCR012405, DCR010505, DCR011203, DCR011205, DCR012403 SBVS013E – OCTOBER 2001 – REVISED JULY 2022 www.ti.com
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www.ti.com 14-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DCR010503P Active Production PDIP (NVE) | 10 20 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 DCR010503P DCR010503P.B Active Production PDIP (NVE) | 10 20 | TUBE - Call TI Call TI -40 to 85 DCR010503U Active Production SOP (DVB) | 12 28 | TUBE Yes NIPDAU Level-3-260C-168 HR -40 to 85 DCR010503U DCR010503U.B Active Production SOP (DVB) | 12 28 | TUBE - Call TI Call TI -40 to 85 DCR010503U/1K Active Production SOP (DVB) | 12 1000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 DCR010503U DCR010503U/1K.B Active Production SOP (DVB) | 12 1000 | LARGE T&R - Call TI Call TI -40 to 85 DCR010503U/1KE4 Active Production SOP (DVB) | 12 1000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 DCR010503U DCR010503U/1KE4.B Active Production SOP (DVB) | 12 1000 | LARGE T&R - Call TI Call TI -40 to 85 DCR010503UE4 Active Production SOP (DVB) | 12 28 | TUBE Yes NIPDAU Level-3-260C-168 HR -40 to 85 DCR010503U DCR010505P Active Production PDIP (NVE) | 10 20 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 DCR010505P DCR010505P.B Active Production PDIP (NVE) | 10 20 | TUBE - Call TI Call TI -40 to 85 DCR010505U Active Production SOP (DVB) | 12 28 | TUBE Yes NIPDAU Level-3-260C-168 HR -40 to 85 DCR010505U DCR010505U.B Active Production SOP (DVB) | 12 28 | TUBE - Call TI Call TI -40 to 85 DCR010505U/1K Active Production SOP (DVB) | 12 1000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 DCR010505U DCR010505U/1K.B Active Production SOP (DVB) | 12 1000 | LARGE T&R - Call TI Call TI -40 to 85 DCR010505U/1KE4 Active Production SOP (DVB) | 12 1000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 DCR010505U DCR010505UE4 Active Production SOP (DVB) | 12 28 | TUBE Yes NIPDAU Level-3-260C-168 HR -40 to 85 DCR010505U DCR011203P Active Production PDIP (NVE) | 10 20 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 DCR011203P DCR011203P.B Active Production PDIP (NVE) | 10 20 | TUBE - Call TI Call TI -40 to 85 DCR011203U Active Production SOP (DVB) | 12 28 | TUBE Yes NIPDAU Level-3-260C-168 HR -40 to 85 DCR011203U DCR011203U.B Active Production SOP (DVB) | 12 28 | TUBE - Call TI Call TI -40 to 85 DCR011203U/1K Active Production SOP (DVB) | 12 1000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 DCR011203U DCR011203U/1K.B Active Production SOP (DVB) | 12 1000 | LARGE T&R - Call TI Call TI -40 to 85 DCR011203UE4 Active Production SOP (DVB) | 12 28 | TUBE Yes NIPDAU Level-3-260C-168 HR -40 to 85 DCR011203U DCR011205P Active Production PDIP (NVE) | 10 20 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 DCR011205P DCR011205P.B Active Production PDIP (NVE) | 10 20 | TUBE - Call TI Call TI -40 to 85 DCR011205PE4 Active Production PDIP (NVE) | 10 20 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 DCR011205P DCR011205PE4.B Active Production PDIP (NVE) | 10 20 | TUBE - Call TI Call TI -40 to 85 DCR011205U Active Production SOP (DVB) | 12 28 | TUBE Yes NIPDAU Level-3-260C-168 HR -40 to 85 DCR011205U Addendum-Page 1
www.ti.com 14-Oct-2025 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DCR011205U.B Active Production SOP (DVB) | 12 28 | TUBE - Call TI Call TI -40 to 85 DCR011205U/1K Active Production SOP (DVB) | 12 1000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 DCR011205U DCR011205U/1K.B Active Production SOP (DVB) | 12 1000 | LARGE T&R - Call TI Call TI -40 to 85 DCR011205UE4 Active Production SOP (DVB) | 12 28 | TUBE Yes NIPDAU Level-3-260C-168 HR -40 to 85 DCR011205U DCR012403P Active Production PDIP (NVE) | 10 20 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 DCR012403P DCR012403P.B Active Production PDIP (NVE) | 10 20 | TUBE - Call TI Call TI -40 to 85 DCR012403U Active Production SOP (DVB) | 12 28 | TUBE Yes NIPDAU Level-3-260C-168 HR -40 to 85 DCR012403U DCR012403U.B Active Production SOP (DVB) | 12 28 | TUBE - Call TI Call TI -40 to 85 DCR012405P Active Production PDIP (NVE) | 10 20 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 DCR012405P DCR012405P.B Active Production PDIP (NVE) | 10 20 | TUBE - Call TI Call TI -40 to 85 DCR012405PE4.B Active Production PDIP (NVE) | 10 20 | TUBE - Call TI Call TI -40 to 85 DCR012405U Active Production SOP (DVB) | 12 28 | TUBE Yes NIPDAU Level-3-260C-168 HR -40 to 85 DCR012405U DCR012405U.B Active Production SOP (DVB) | 12 28 | TUBE - Call TI Call TI -40 to 85 DCR012405U/1K Active Production SOP (DVB) | 12 1000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 DCR012405U DCR012405U/1K.B Active Production SOP (DVB) | 12 1000 | LARGE T&R - Call TI Call TI -40 to 85 DCR012405UE4 Active Production SOP (DVB) | 12 28 | TUBE Yes NIPDAU Level-3-260C-168 HR -40 to 85 DCR012405U (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Addendum-Page 2
www.ti.com 14-Oct-2025 Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3
PACKAGE MATERIALS INFORMATION www.ti.com 10-Oct-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) DCR010503P NVE PDIP 10 20 533.4 14.33 13.03 8.07 DCR010503U DVB SOP 12 28 532.13 14.73 5.13 6.6 DCR010503UE4 DVB SOP 12 28 532.13 14.73 5.13 6.6 DCR010505P NVE PDIP 10 20 533.4 14.33 13.03 8.07 DCR010505U DVB SOP 12 28 532.13 14.73 5.13 6.6 DCR010505UE4 DVB SOP 12 28 532.13 14.73 5.13 6.6 DCR011203P NVE PDIP 10 20 533.4 14.33 13.03 8.07 DCR011203U DVB SOP 12 28 532.13 14.73 5.13 6.6 DCR011203UE4 DVB SOP 12 28 532.13 14.73 5.13 6.6 DCR011205P NVE PDIP 10 20 533.4 14.33 13.03 8.07 DCR011205PE4 NVE PDIP 10 20 533.4 14.33 13.03 8.07 DCR011205U DVB SOP 12 28 532.13 14.73 5.13 6.6 DCR011205UE4 DVB SOP 12 28 532.13 14.73 5.13 6.6 DCR012403P NVE PDIP 10 20 533.4 14.33 13.03 8.07 DCR012403U DVB SOP 12 28 532.13 14.73 5.13 6.6 DCR012405P NVE PDIP 10 20 533.4 14.33 13.03 8.07 DCR012405U DVB SOP 12 28 532.13 14.73 5.13 6.6 DCR012405UE4 DVB SOP 12 28 532.13 14.73 5.13 6.6 Pack Materials-Page 1
www.ti.com PACKAGE OUTLINE C TYP0.32 0.23 10.65 10.01 8X 1.27 12X 0.51 0.33 2X 16.51
2.65 MAX
0.3 0.1 1.27 0.40 A NOTE 3 18.1 17.7 B 7.6 7.4 4222497/A 10/2015 SOP - 2.65 mm max heightDVB0012A PLASTIC SMALL OUTLINE NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. Reference JEDEC registration MS-013. 1 28
0.25 C A B
0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 0.900
www.ti.com EXAMPLE BOARD LAYOUT (9.3)
0.07 MAX
0.07 MIN
12X (2) 12X (0.6) 8X (1.27) (R ) TYP 0.05 (16.51) 4222497/A 10/2015 SOP - 2.65 mm max heightDVB0012A PLASTIC SMALL OUTLINE SYMM SYMM LAND PATTERN EXAMPLE SCALE:6X 14 15 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN (9.3) 8X (1.27) 12X (0.6) 12X (2) (R )0.05 (16.51) 4222497/A 10/2015 SOP - 2.65 mm max heightDVB0012A PLASTIC SMALL OUTLINE NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. SYMM SYMM 14 15 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X
MPDI055 – APRIL 2001 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 NVE (R-PDIP-T10/18) PLASTIC DUAL-IN-LINE 0.300 (7,63) 4202497/A 03/01 0.014 (0,36) 0.008 (0,20) 0.060 (1,52) 0.300 (7,62) 0.325 (8,26) MIN 4 PL Full Lead 0.115 (2,92) 0.150 (3,81) 0.115 (2,92) 0.045 (1,14) 0.014 (0,36) 0.022 (0,56) Area 0.280 (7,11) 0.240 (6,10) 0.920 (23,37) 0.880 (22,35) Index –C– 0.010 (0,25)C 0.100 (2,54) 0.430 (10,92) MAX Seating Plane Plane Base 0.005 (0,13) 0.015 (0,38) MIN 0.210 (5,33) MAX 0.000 (0,00)M D E F F D E D NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001-AC with the exception of lead count. D. Dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 (0,25). E. Dimensions measured with the leads constrained to be perpendicular to Datum C. F. Dimensions are measured at the lead tips with the leads unconstrained. G. A visual index feature must be located within the cross-hatched area.
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