DCR010503 TI1 | Alldatasheet
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+V S Input Controller ENABLE ERROR -VS VREC LDO Regulator -VOUT +VOUT Copyright © 2016, Texas Instruments Incorporated Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community Reference Design An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DCR010503,DCR012405,DCR010505 DCR011203,DCR011205,DCR012403 SBVS013D –OCTOBER 2001–REVISED JUNE 2016 DCR01Series,1-W,1000-VrmsIsolated,RegulatedDC–DCConverterModules
1 Features
1• 1000-Vrms Isolation (Operational)
- UL1950 Recognized Component
- 53 W/in3 (3.3W/cm3) Power Density
- 10-Pin PDIP and 12-Pin SOP Packages
- Device-to-Device Synchronization
- Thermal Protection
- 400-kHz Switching
- 125 FITs at 55ºC
- ±10% Input Range
- Short-Circuit Protected
- 5-V, 12-V, and 24-V Inputs
- 3.3-V and 5-V Outputs
- High Efficiency
2 Applications
- Point-of-Use Power Conversion
- Digital Interface Power
- Ground Loop Elimination
- Power-Supply Noise Reduction
3 Description
The DCR01 family is a series of high-efficiency, input- isolated, output-regulated DC–DC converters. In addition to 1 W nominal, galvanically-isolated output power capability, this range of DC–DCs offer very low output noise, thermal protection, and high accuracy. This combination of features and small size makes the DCR01 series of devices suitable for a wide range of applications, and is an easy-to-use solution in applications requiring signal path isolation. CAUTION This product has operational isolation and is intended for signal isolation only. It must not be used as a part of a safety isolation circuit requiring reinforced isolation. See definitions in Feature Description. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) DCR01 PDIP (10) 22.86 mm × 6.61 mm SOP (12) 17.90 mm × 7.50 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. DCR01 Block Diagram
DCR010503,DCR012405,DCR010505 DCR011203,DCR011205,DCR012403 SBVS013D –OCTOBER 2001–REVISED JUNE 2016 www.ti.com Product Folder Links: DCR010503 DCR012405 DCR010505 DCR011203 DCR011205 DCR012403 Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Table of Contents
12.1 Receiving Notification of Documentation Updates 20
13 Mechanical, Packaging, and Orderable
4 Revision History
Changes from Revision C (May 2003) to Revision D Page
- Added Device Information table, Device Comparison table, ESD Ratings table, Thermal Information table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
DCR010503,DCR012405,DCR010505 DCR011203,DCR011205,DCR012403 www.ti.com SBVS013D –OCTOBER 2001–REVISED JUNE 2016 Product Folder Links: DCR010503 DCR012405 DCR010505 DCR011203 DCR011205 DCR012403 Submit Documentation FeedbackCopyright © 2001–2016, Texas Instruments Incorporated (1) The last character in the part number denotes the package type; P = PDIP, U = SOP (2) 20-MHz Bandwidth, 50% Load (3) 100-MHz Bandwidth, 50% Load
5 Device Comparison Table
at TA = 25°C, +VS = nominal, IO = 10 mA, CIN = 2.2-µF ceramic, CFILTER = 1-µF ceramic, COUT = 0.1-µF ceramic (unless otherwise noted) DEVICE NUMBER (1) INPUT VOLTAGE VS (V) OUTPUT VOLTAGE VO (V) OUTPUT CURRENT (mA) RIPPLE (2) (mVp-p) NOISE (3) (mVp-p) SUPPLY CURRENT (mA) IO = 0 mA IO = 10 mA IO = 100% LOAD TYP TYP MAX TYP TYP TYP TYP TYP DCR010503P 3.3 300 5 35 18 28 335 DCR010503U 8 23 24 33 339 DCR010505P 5 200 6 20 25 40 306 DCR010505U 9 20 25 40 306 DCR011203P 3.3 390 10 54 13 17 173 DCR011203U 300 8 22 13 17 136 DCR011205P 5 200 6 45 13 18 125 DCR011205U 6 21 14 19 123 DCR012403P 3.3 390 10 22 17 18 97 DCR012403U 300 8 22 15 17 75 DCR012405P 5 200 10 22 15 18 69 DCR012405U 13 32 15 18 67
-VOUT VREC NC +V OUT 15 DNC SYNC DCR01U 27 -VS
16 ENABLE
17 ERROR
-VOUT VREC +V OUT 10 DNC SYNC DCR01P 17 -VS
11 ENABLE
12 ERROR
DCR010503,DCR012405,DCR010505 DCR011203,DCR011205,DCR012403 SBVS013D –OCTOBER 2001–REVISED JUNE 2016 www.ti.com Product Folder Links: DCR010503 DCR012405 DCR010505 DCR011203 DCR011205 DCR012403 Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated
6 Pin Configuration and Functions
ENABLE 11 16 I Output Voltage Enable ERROR 12 17 O Error Flag Active Low DNC 10 15 — Do Not Connect NC 2 3 — No Connection SYNC 18 28 I Synchronization Input –VOUT 8 13 O Output Ground +VOUT 9 14 O Voltage Output VREC 7 12 O Rectified Output –VS 17 26, 27 I Input Ground +VS 1 1, 2 I Voltage Input
DCR010503,DCR012405,DCR010505 DCR011203,DCR011205,DCR012403 www.ti.com SBVS013D –OCTOBER 2001–REVISED JUNE 2016 Product Folder Links: DCR010503 DCR012405 DCR010505 DCR011203 DCR011205 DCR012403 Submit Documentation FeedbackCopyright © 2001–2016, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) See the package option addendum at the end of the datasheet for additional package information.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2) MIN MAX UNIT Input voltage 5-V input devices 7 V12-V input devices 15 24-V input devices 29 Lead temperature PDIP package Surface temperature of device body or pins (maximum 10 s) 270 °C Reflow solder temperature SOP package Surface temperature of device body or pins 260 °C Storage temperature, Tstg –60 125 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.2 ESD Ratings
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±250
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Input voltage 5-V input devices 4.5 5 5.5 V12-V input devices 10.8 12 13.2 24-V input devices 21.6 24 26.4 Operating temperature –40 85 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
7.4 Thermal Information
THERMAL METRIC(1) DCR01 UNITNVE (PDIP) DVB (SOP)
10 PINS 12 PINS
RθJA Junction-to-ambient thermal resistance 60 60 °C/W RθJC(top) Junction-to-case (top) thermal resistance 26 26 °C/W RθJB Junction-to-board thermal resistance 24 24 °C/W ψJT Junction-to-top characterization parameter 7 7 °C/W ψJB Junction-to-board characterization parameter 24 24 °C/W
DCR010503,DCR012405,DCR010505 DCR011203,DCR011205,DCR012403 SBVS013D –OCTOBER 2001–REVISED JUNE 2016 www.ti.com Product Folder Links: DCR010503 DCR012405 DCR010505 DCR011203 DCR011205 DCR012403 Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated
7.5 Electrical Characteristics
at TA = 25°C, +VS = nominal, IO = 10 mA, CIN = 2.2-µF ceramic, CFILTER = 1-µF ceramic, COUT = 0.1-µF ceramic (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUTPUT Nominal output voltage (+VOUT) DCR01xx03 3.3 V DCR01xx05 5 Setpoint accuracy 0.5% 2% Output short-circuit protected Duration Infinite Line regulation 1 mV/V Over line and load IO = 10 mA to Full Load, Over +VS range 1% 2.5% Temperature variation –40°C ≤ TA ≤ +85°C 1% INPUT Nominal input voltage (+VS) DCR0105xx 5 VDCR0112xx 12 DCR0124xx 24 Voltage range –10% 10% Reflected ripple current 20-MHz Bandwidth, IO = 100% Load 8 mAp-p ISOLATION Isolation 1-s Flash Test Voltage 1 kVrms dV/dt 500 V/s Leakage Current 30 nA Continuous working voltage across isolation barrier DC 60 VDC AC 42.5 VAC Barrier capacitance 25 pF OUTPUT ENABLE CONTROL Logic high input voltage 2 VREC V Logic high input current 2 < VENABLE < VREC 100 nA Logic low input voltage –0.2 0.5 V Logic low input current 0 < VENABLE < 0.5 100 nA Rectified output, VREC All 3.3-V Outputs 3.3 V All 5-V Outputs 5 ERROR FLAG Logic high open-collector leakage VERROR = 5 V 10 µA Logic low output voltage Sinking 2 mA 0.4 V THERMAL SHUTDOWN Junction temperature Temperature Activated 150 Temperature Deactivated 130 SYNCHRONIZATION PIN Max external capacitance on SYNC pin 3 pF Internal oscillator frequency 720 800 880 kHz External synchronization frequency 720 880 kHz External synchronization signal high 2.5 3 V External synchronization signal low 0 0.4 V TEMPERATURE RANGE Operating –40 85 °C
7.6 Typical Characteristics
Figure 1. Efficiency vs Load Figure 2. Efficiency vs Load Figure 3. Efficiency vs Load Figure 4. Efficiency vs Load Figure 5. Efficiency vs Load Figure 6. Output Voltage Ripple
-VS VREC LDO Regulator -VOUT +V OUTOscillator 800 kHz Divide-by-2 Reset Watchdog Startup PSU Thermal Shutdown Power Stage Input Controller Copyright © 2016, Texas Instruments Incorporated DCR010503,DCR012405,DCR010505 DCR011203,DCR011205,DCR012403 www.ti.com SBVS013D –OCTOBER 2001–REVISED JUNE 2016 Product Folder Links: DCR010503 DCR012405 DCR010505 DCR011203 DCR011205 DCR012403 Submit Documentation FeedbackCopyright © 2001–2016, Texas Instruments Incorporated
8 Detailed Description
8.1 Overview
The DCR01 series of power modules offer isolation from a regulated power supply operating from a choice of input voltages. The DCR01s provide a regulated 3.3-V or 5-V output voltage at a nominal output power of 1 W or above. The DCR01 devices include a low dropout linear regulator internal to the device to achieve a well- regulated output voltage. The DCR01 devices are specified for operational isolation only. The circuit design uses an advanced BiCMOS/DMOS process.
8.2 Functional Block Diagram
8.3 Feature Description
8.3.1 Isolation
Underwriters Laboratories, UL™ , defines several classes of isolation that are used in modern power supplies. Safety extra low voltage (SELV) is defined by UL (UL1950 E199929) as a secondary circuit which is so designated and protected that under normal and single fault conditions the voltage between any two accessible parts, or between an accessible part and the equipment earthing terminal for operational isolation does not exceed steady state 42.4 VRMS or 60 VDC peak.
8.3.1.1 Operation or Functional Isolation
The type of isolation used in the DCR01 products is referred to as operational or functional isolation. Insulated wire used in the construction of the transformer acts as the primary isolation barrier. A high-potential (hipot), one- second duration test (dielectric voltage, withstand test) is a production test used to verify that the isolation barrier is functioning. Products with operational isolation must never be used as an element in a safety-isolation system.
8.3.1.2 Basic or Enhanced Isolation
Basic or enhanced isolation is defined by specified creepage and clearance limits between the primary and secondary circuits of the power supply. Basic isolation is the use of an isolation barrier in addition to the insulated wire in the construction of the transformer. Input and output circuits must also be physically separated by specified distances.
DCR010503,DCR012405,DCR010505 DCR011203,DCR011205,DCR012403 SBVS013D –OCTOBER 2001–REVISED JUNE 2016 www.ti.com Product Folder Links: DCR010503 DCR012405 DCR010505 DCR011203 DCR011205 DCR012403 Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Feature Description (continued) NOTE The DCR01 products DO NOT provide basic or enhanced isolation.
8.3.1.3 Working Voltage
For a device with operational isolation, the continuous working voltage that can be applied across the device in normal operation must be less than 42.4 VRMS or 60 VDC, (SELV limits). WARNING Do not use the device as an element of a safety isolation system if SELV is exceeded. If the device is expected to function correctly with more than 42.4 VRMS or 60 VDC applied continuously across the isolation barrier, then the circuitry on both sides of the barrier must be regarded as operating at an unsafe voltage, and further isolation or insulation systems must form a barrier between these circuits and any user- accessible circuitry according to safety standard requirements.
8.3.1.4 Isolation Voltage Rating
The terms Hipot test, flash-tested, withstand voltage, proof voltage, dielectric withstand voltage, and isolation test voltage are all terms that relate to the same thing; a test voltage applied for a specified time across a component designed to provide electrical isolation to verify the integrity of that isolation. TI’s DCR01 series of DC-DC converters are all 100% production tested at 1 kVAC for one second.
8.3.1.5 Repeated High-Voltage Isolation Testing
Repeated high-voltage isolation testing of a barrier component can degrade the isolation capability, depending on materials, construction, and environment. The DCV01 series of DC–DC converters have toroidal, enameled, wire isolation transformers with no additional insulation between the primary and secondary windings. While a device can be expected to withstand several times the stated test voltage, the isolation capability depends on the wire insulation. Any material, including this enamel (typically polyurethane), is susceptible to eventual chemical degradation when subject to very-high applied voltages. Therefore, strictly limit the number of high-voltage tests and repeated high-voltage isolation testing. However, if it is absolutely required, reduce the voltage by 20% from specified test voltage with a duration limit of one second per test.
8.3.2 Power Stage
The DCR01 series of devices use a push-pull, center-tapped topology. The DCV01 devices switch at 400 kHz (divide-by-2 from an 800-kHz oscillator).
8.3.3 Rectification
The transformer’s output is full wave rectified and filtered by the external 1-μF ceramic capacitor connected to VREC.
8.3.4 Regulator
The internal low dropout linear regulator provides a well-regulated output voltage throughout the operating range of the device.
8.3.5 Oscillator and Watchdog
The onboard, 800-kHz oscillator generates the switching frequency through a divide-by-2 circuit. The oscillator can be synchronized to other DCR01 device circuits or an external source, and is used to minimize system noise.
DCR010503,DCR012405,DCR010505 DCR011203,DCR011205,DCR012403 www.ti.com SBVS013D –OCTOBER 2001–REVISED JUNE 2016 Product Folder Links: DCR010503 DCR012405 DCR010505 DCR011203 DCR011205 DCR012403 Submit Documentation FeedbackCopyright © 2001–2016, Texas Instruments Incorporated Feature Description (continued) A watchdog circuit monitors the operation of the oscillator circuit. The oscillator can be disabled by pulling the SYNC pin low. When the SYNC pin goes low, the output pins transition into tri-state mode, which occurs within 2 μs.
8.3.6 ERROR Flag
The DCR01 has an ERROR pin which provides a power good flag, as long as the internal regulator is in regulation. If the ERROR output is required, place a 10-kΩ resistor between the ERROR pin and the output voltage.
8.3.7 Synchronization
When more than one DC–DC converter is switching in an application, beat frequencies and other electrical interference can be generated. This interference occurs because of the small variations in switching frequencies between the DC–DC converters. The DCR01 series of devices overcome this interference by allowing devices to be synchronized to one another. Synchronize up to eight devices by connecting the SYNC pins of each device, taking care to minimize the capacitance of tracking. Stray capacitance (greater than 3 pF) reduces the switching frequency, or can sometimes stop the oscillator circuit. The maximum recommended voltage applied to the SYNC pin is 3 V. For an application that uses more than eight synchronized devices use an external device to drive the SYNC pins. The application report External Synchronization of the DCP01/02 Series of DC/DC Converters describes this configuration. NOTE During the start-up period, all synchronized devices draw maximum current from the input simultaneously. If the input voltage falls below approximately 4 V, the devices may not start up. A ceramic capacitor should be connected close to each device's input pin. Use a 2.2-μF capacitor for 5-V input devices, and a 0.47-μF capacitor for the 12-V and 24-V devices.
8.3.8 Construction
The basic construction of the DCR01 series of devices is the same as standard integrated circuits. The molded package contains no substrate. The DCV01 series of devices are constructed using an IC, low dropout linear regulator, rectifier diodes, and a wound magnetic toroid on a leadframe. Because the package contains no solder, the devices do not require any special printed-circuit board (PCB) assembly processing. This architecture results in an isolated DC–DC converter with inherently high reliability.
8.3.9 Thermal Considerations
Due to the high power density of this device, it is advisable to provide ground planes on the input and output rails. The output regulator is mounted on a copper leadframe, and a ground plane serves as an efficient heatsink.
8.3.10 Decoupling – Ripple Reduction
Due to the very low forward resistance of the DMOS switching transistors, high current demands are placed upon the input supply for a short time. By using a good quality low Equivalent Series Resistance (ESR) capacitor of 2.2 μF (minimum) for the 5-V input devices and a 0.47-μF capacitor for the 12-V and 24-V devices, placed close to the IC supply input pins, the effects on the power supply can be minimized. The high switching frequency of 400 kHz allows relatively small values of capacitors to be used for filtering the rectified output voltage. A good-quality, low-ESR, 1-μF ceramic capacitor placed close to the VREC pin and output ground is required and reduces the ripple. The output at VREC is full wave rectified and produces a ripple of 800 kHz. TI recommends that a 0.1-μF, low-ESR, ceramic capacitor is connected close to the output pin and ground to reduce noise on the output. The capacitor values listed are minimum values. If lower ripple is required, the filter capacitor should be increased in value to 2.2 μF.
DCR010503,DCR012405,DCR010505 DCR011203,DCR011205,DCR012403 SBVS013D –OCTOBER 2001–REVISED JUNE 2016 www.ti.com Product Folder Links: DCR010503 DCR012405 DCR010505 DCR011203 DCR011205 DCR012403 Submit Documentation Feedback Copyright © 2001–2016, Texas Instruments Incorporated Feature Description (continued) As with all switching power supplies, the best performance is obtained with low ESR,ceramic capacitors connected close to the device pins. If low ESR, ceramic capacitors are not used, the ESR generates a voltage drop when the capacitor is supplying the load power. Often a larger capacitor is chosen for this purpose, when a low ESR, smaller capacitor would perform as well. NOTE TI does not recommend that the DCR01 be fitted using an IC socket, as this degrades performance.
8.4 Device Functional Modes
8.4.1 Device Disable and Enable
Each of the DCR01 series devices can be disabled or enabled by driving the SYNC pin using an open-drain CMOS gate. If the SYNC pin is pulled low, the DCR01 becomes disabled. The disable time depends upon the external loading. The internal disable function is implemented in 2 μs. Removal of the pulldown causes the DCR01 to be enabled. Capacitive loading on the SYNC pin must be minimized (≤ 3 pF) to prevent a reduction in the oscillator frequency. The application report External Synchronization of the DCP01/02 Series of DC/DC Converters describes disable and enable control circuitry. This document contains information on how to null the effects of additional capacitance on the SYNC pin. The oscillator’s frequency can be measured at VREC, as this is the fundamental frequency of the ripple component.
8.4.2 Regulated Output Disable and Enable
The regulated output of the DCR01 can be disabled by pulling the ENABLE pin LOW. Disabling the output voltage this way still produces a voltage on the VREC pin. When using the ENABLE control, TI recommends placing a 10-kΩ resistor between the VREC and ENABLE pins. The ENABLE pin only controls the internal linear regulator. If disabling the regulated output is not required, pull the ENABLE pin HIGH by shorting it directly to the VREC pin. This enables the regulated output voltage, thus allowing the output to be controlled from the isolated side.
9 Application and Implementation
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 DCR01 Single Voltage Output
line; however, the total load on the ERROR line must not exceed the value given in Electrical Characteristics. the main load that it sees is REN. Figure 24. DCR01 Single Output Voltage
9.1.2 Generating Two Positive Output Voltages
DCR01s are connected in self-synchronization, thus locking the oscillators of both devices to a single frequency. proximity to their respective DCR01. Figure 25. Two Positive Voltages from Self-Synchronized DCR01s
9.1.3 Generation of Dual Polarity Voltages from Two Self-Synchronized DCR01s
the case of the negative output device, connected to the common 0-V output. Figure 26. Dual Polarity Voltage Generation
9.2 Typical Application
Figure 27. DCR01 Typical Schematic
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 1 and follow the design procedure. Table 1. Design Example Parameters
9.2.2 Detailed Design Procedure
9.2.2.1 Input Capacitor
For this design, a 2.2-μF, ceramic capacitor is required for the input decoupling capacitor.
9.2.2.2 Output Capacitor
For this design, a 0.1-μF, ceramic capacitor is required for between +VOUT and –VOUT.
9.2.2.3 Filter Capacitor
reduce output voltage ripple.
9.2.2.4 ERROR Flag
internal regulator is in regulation.
9.2.3 Application Curves
Figure 28. DCR010505 Efficiency Figure 29. DCR010505 Load Regulation
10 Power Supply Recommendations
The DCR01 is a switching power supply, and as such can place high peak current demands on the input supply. connected in a star formation with the traces made as wide as possible.
11 Layout
11.1 Layout Guidelines
Carefully consider the layout of the PCB in order for the best results to be obtained. output, the positive and negative voltage outputs conduct through wide traces to minimize losses. and ensure a smooth start-up. output ground gives the best ripple and noise performance. switching waveforms of the power drive circuits. If the SYNC pin is being used, the tracking between device SYNC pins must be short to avoid stray capacitance. the performance of the oscillator. layout for the SOP package DCR01 device. The layout shows proper placement of capacitors and power planes.
11.2 Layout Examples
Figure 30. DCR01 PCB Schematic, U Package Figure 31. PCB Layout Example, Figure 32. PCB Layout Example,
12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
changed. For change details, review the revision history included in any revised document.
12.2 Related Links
resources, tools and software, and quick access to sample or buy. Table 2. Related Links
12.3 Community Resources
solve problems with fellow engineers. contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments. Underwriters Laboratories, UL are trademarks of UL LLC. All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
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www.ti.com 28-Jun-2016 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples DCR010503P ACTIVE PDIP NVE 10 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 DCR010503P DCR010503U ACTIVE SOP DVB 12 28 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR -40 to 85 DCR010503U DCR010503U/1K ACTIVE SOP DVB 12 1000 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR -40 to 85 DCR010503U DCR010503UE4 ACTIVE SOP DVB 12 28 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR -40 to 85 DCR010503U DCR010505P ACTIVE PDIP NVE 10 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 DCR010505P DCR010505U ACTIVE SOP DVB 12 28 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR -40 to 85 DCR010505U DCR010505U/1K ACTIVE SOP DVB 12 1000 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR -40 to 85 DCR010505U DCR010505U/1KE4 ACTIVE SOP DVB 12 1000 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR -40 to 85 DCR010505U DCR010505UE4 ACTIVE SOP DVB 12 28 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR -40 to 85 DCR010505U DCR011203P ACTIVE PDIP NVE 10 20 TBD CU NIPDAU Level--- -40 to 85 DCR011203P DCR011203U ACTIVE SOP DVB 12 28 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR -40 to 85 DCR011203U DCR011203U/1K ACTIVE SOP DVB 12 1000 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR -40 to 85 DCR011203U DCR011203UE4 ACTIVE SOP DVB 12 28 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR -40 to 85 DCR011203U DCR011205P ACTIVE PDIP NVE 10 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 DCR011205P DCR011205U ACTIVE SOP DVB 12 28 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR -40 to 85 DCR011205U DCR011205U/1K ACTIVE SOP DVB 12 1000 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR -40 to 85 DCR011205U DCR011205UE4 ACTIVE SOP DVB 12 28 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR -40 to 85 DCR011205U
www.ti.com 28-Jun-2016 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples DCR012403P ACTIVE PDIP NVE 10 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 DCR012403P DCR012403U ACTIVE SOP DVB 12 28 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR -40 to 85 DCR012403U DCR012405P ACTIVE PDIP NVE 10 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 DCR012405P DCR012405U ACTIVE SOP DVB 12 28 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR -40 to 85 DCR012405U DCR012405U/1K ACTIVE SOP DVB 12 1000 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR -40 to 85 DCR012405U DCR012405UE4 ACTIVE SOP DVB 12 28 Pb-Free (RoHS) CU NIPDAU Level-3-260C-168 HR -40 to 85 DCR012405U (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
www.ti.com 28-Jun-2016 Addendum-Page 3 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
MPDI055 – APRIL 2001 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 NVE (R-PDIP-T10/18) PLASTIC DUAL-IN-LINE 0.300 (7,63) 4202497/A 03/01 0.014 (0,36) 0.008 (0,20) 0.060 (1,52) 0.300 (7,62) 0.325 (8,26) MIN 4 PL Full Lead 0.115 (2,92) 0.150 (3,81) 0.115 (2,92) 0.045 (1,14) 0.014 (0,36) 0.022 (0,56) Area 0.280 (7,11) 0.240 (6,10) 0.920 (23,37) 0.880 (22,35) Index –C– 0.010 (0,25)C 0.100 (2,54) 0.430 (10,92) MAX Seating Plane Plane Base 0.005 (0,13) 0.015 (0,38) MIN 0.210 (5,33) MAX 0.000 (0,00)M D E F F D E D NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001-AC with the exception of lead count. D. Dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 (0,25). E. Dimensions measured with the leads constrained to be perpendicular to Datum C. F. Dimensions are measured at the lead tips with the leads unconstrained. G. A visual index feature must be located within the cross-hatched area.
www.ti.com PACKAGE OUTLINE C TYP0.32 0.23 10.65 10.01 8X 1.27 12X 0.51 0.33 2X 16.51
2.65 MAX
0.3 0.1 1.27 0.40 A NOTE 3 18.1 17.7 B 7.6 7.4 4222497/A 10/2015 SOP - 2.65 mm max heightDVB0012A PLASTIC SMALL OUTLINE NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. Reference JEDEC registration MS-013. 1 28
0.25 C A B
0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 0.900
www.ti.com EXAMPLE BOARD LAYOUT (9.3)
0.07 MAX
0.07 MIN
12X (2) 12X (0.6) 8X (1.27) (R ) TYP 0.05 (16.51) 4222497/A 10/2015 SOP - 2.65 mm max heightDVB0012A PLASTIC SMALL OUTLINE SYMM SYMM LAND PATTERN EXAMPLE SCALE:6X 14 15 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN (9.3) 8X (1.27) 12X (0.6) 12X (2) (R )0.05 (16.51) 4222497/A 10/2015 SOP - 2.65 mm max heightDVB0012A PLASTIC SMALL OUTLINE NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. SYMM SYMM 14 15 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X
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