DCP010505DBP-U

DCP01B BURR-BROWN | Alldatasheet

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Technical content

SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004 Miniature, 1W Isolated UNREGULATED DC/DC CONVERTERS DCP01B SERIES

FEATURES

/C0068Up To 85% Efficiency /C0068Thermal Protection /C0068Device-to-Device Synchronization /C0068Short-Circuit Protection /C0068EN55022 Class B EMC Performance /C0068UL1950 Recognized Component /C0068JEDEC DIP-14 and SOP-14 Packages

APPLICATIONS

/C0068 Point-of-Use Power Conversion /C0068Ground Loop Elimination /C0068Data Acquisition /C0068Industrial Control and Instrumentation /C0068Test Equipment

DESCRIPTION

The DCP01B series is a family of 1W, unregulated, isolated DC/DC converters. Requiring a minimum of external components and including on-chip device protection, the DCP01B series provides extra features such as output disable and synchronization of switching frequencies. The use of a highly-integrated package design results in highly reliable products with a power density of 40W/in (2.4W/cm3). This combination of features and small sizes makes the DCP01B suitable for a wide range of applications. IBIAS Power Stage VOUT ÷ 2 Reset 800kHz Oscillator Watch− dog/ start− up PSU Thermal Shutdown SYNC OUT SYNC IN VS Power Controller IC www.ti.com Copyright  2000−2004, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) DCP01B SERIES UNIT 5V models 7 V Input voltage 15V models 18 VInput voltage 24V models 29 V Storage temperature −40 to +125 °C Lead temperature (soldering, 10s) +270 °C (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. SUPPLEMENTAL ORDERING INFORMATION Basic Model Number: 1W Product Voltage Input: 5V In Voltage Output: Dual Output: Model Revision: Package Code: 5V Out P=D I P−14 P−U=S O P−14 (Gullwing) ORDERING INFORMATION (1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER (2) TRANSPORT MEDIA SINGLE VOLTAGE (3) DIP-14 NVA −40°C to +100°C DCP010505BP DCP010505BP Rails DCP010505 SOP-14 (4) DUA −40°C to +100°C DCP010505BP −U DCP010505BP −U/700 Tape and Reel DIP-14 NVA −40°C to +100°C DCP010512BP DCP010512BP Rails DCP010512 SOP-14 (4) DUA −40°C to +100°C DCP010512BP −U DCP010512BP −U/700 Tape and Reel DIP-14 NVA −40°C to +100°C DCP010515BP DCP010515BP Rails DCP010515 SOP-14 (4) DUA −40°C to +100°C DCP010515BP −U DCP010515BP −U/700 Tape and Reel DIP-14 NVA −40°C to +100°C DCP012405BP DCP012405BP Rails DCP012405 SOP-14 (4) DUA −40°C to +100°C DCP012405BP −U DCP012405BP −U/700 Tape and Reel DUAL VOLTAGE (3) DIP-14 NVA −40°C to +100°C DCP010505DBP DCP010505DBP Rails DCP010505 SOP-14 (4) DUA −40°C to +100°C DCP010505DBP −U DCP010505DBP −U/700 Tape and Reel DIP-14 NVA −40°C to +100°C DCP010512DBP DCP010512DBP Rails DCP010512 SOP-14 (4) DUA −40°C to +100°C DCP010512DBP −U DCP010512DBP −U/700 Tape and Reel DIP-14 NVA −40°C to +100°C DCP010515DBP DCP010515DBP Rails DCP010515 SOP-14 (4) DUA −40°C to +100°C DCP010515DBP −U DCP010515DBP −U/700 Tape and Reel DIP-14 NVA −40°C to +100°C DCP011512DBP DCP011512DBP Rails DCP011512 SOP-14 (4) DUA −40°C to +100°C DCP011512DBP −U DCP011512DBP −U/700 Tape and Reel DIP-14 NVA −40°C to +100°C DCP011515DBP DCP011515DBP Rails DCP011515 SOP-14 (4) DUA −40°C to +100°C DCP011515DBP −U DCP011515DBP −U/700 Tape and Reel DIP-14 NVA −40°C to +100°C DCP012415DBP DCP012415DBP Rails DCP012415 SOP-14 (4) DUA −40°C to +100°C DCP012415DBP −U DCP012415DBP −U/700 Tape and Reel (1) All devices also available in tray quatities. For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or refer to our web site at www.ti.com. (2) Models with a (/) are available only in Tape and Reel in the quantities indicated (for example, /700 indicates 700 devices per reel). Ordering 700 pieces of “DCP010505BP −U/700” will get a single 700-piece Tape and Reel. (3) Single voltage versions have six active pins; dual voltage versions have seven active pins. (4) SOP package is gullwing surface-mount.

SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004 www.ti.com

ELECTRICAL CHARACTERISTICS

At TA = +25°C, VS = nominal, CIN = 2.2µF, and COUT = 0.1µF, unless otherwise noted. DCP01B SERIES PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Output Power 100% full load 0.97 W Ripple O/P capacitor = 1µF, 50% load 20 mV PP Room to cold 0.046 %/°C Voltage vs Temperature Room to hot 0.016 %/°C Input Voltage range on VS −10 +10 % Isolation 1s flash test 1 kVrms Voltage 60s test, UL1950(1) 1 kVrms Line Regulation Voltage Source (VS) Minimum VS ≤ IO constant ≤ typical VS Typical VS ≤ IO constant ≤ maximum VS 1 15(2) change of VS Switching/Synchronization Oscillator frequency (fOSC ) Switcing frequency = fOSC /2 800 kHz Sync input low 0.4 V Sync input current VSYNC = +2V 75 µA Disable time 2 µs Capacitance loading on SYNCIN pin External 3 pF Reliability Demonstrated MSL 3−(U) versions TA = +55°C −40 +70 °C Thermal Shutdown IC temperature at shutdown +150 °C Shutdown current 3 mA Temperature Range Operating −40 +100 °C (1) During UL1950 recognition tests only. (2) Line regulation is measured at constant load current. Line regulation = (VOUT at IOUT fixed)/VS. Variation % = VS min to VS typ, VS typ to VS max. ELECTRICAL CHARACTERISTICS PER DEVICE At TA = +25°C, VS = nominal, CIN = 2.2µF, and COUT = 0.1µF, unless otherwise noted. INPUT VOLTAGE (V) OUTPUT VOLTAGE (V) LOAD REGULATION (%) NO LOAD CURRENT (mA) EFFICIENCY (%) BARRIER CAPACITANCE (pF) VS VNOM = VS Typical IQ C ISO 75% LOAD (3) 10% TO 100% LOAD (4) 0% LOAD 100% LOAD VISO = 750VRMS PRODUCT MIN TYP MAX MIN TYP MAX TYP MAX TYP TYP TYP (3) 100% load current = 1W/VS typical. (4) Load regulation = (VOUT at 10% load − VOUT at 100% load)/VOUT at 75% load.

SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004 www.ti.com PIN ASSIGNMENTS (Single Voltage Version) NVA and DUA PACKAGES (TOP VIEW) DCP01B V S +VOUT NC SYNC IN SYNC OUT Terminal Functions (Single Voltage) TERMINAL NAME NO. I/O DESCRIPTION VS 1 I Voltage input 0V 2 I Input side common 0V 5 O Output side common +VOUT 6 O +Voltage out NC 7 Not connected SYNC OUT 8 O Unrectified transformer output SYNC IN 14 I Synchronization pin NOTE : I = input and O = output. PIN ASSIGNMENTS (Dual Voltage Version) NVA and DUA PACKAGES (TOP VIEW) DCP01DB VS +VOUT −VOUT SYNC IN SYNC OUT Terminal Functions (Dual Voltage) TERMINAL NAME NO. I/O DESCRIPTION VS 1 I Voltage input 0V 2 I Input side common 0V 5 O Output side common +VOUT 6 O +Voltage out −VOUT 7 O −Voltage out SYNC OUT 8 O Unrectified transformer output SYNC IN 14 I Synchronization pin NOTE : I = input and O = output.

SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004 www.ti.com TYPICAL CHARACTERISTICS At TA = 25°C, unless otherwise noted. DCP010505B OUTPUT RIPPLE vs LOAD (20MHz BW) Load (%) Ripple (mVPP ) 20 30 50 70 60 80 90 1004010 1µF Ceramic 4.7µFC e r a m i c 10µF Ceramic DCP010505B V OUT vs VS VS (V) VOUT (V) 5.5 5.4 5.3 5.2 5.1 5.0 4.9 4.8 4.7 4.6 4.5 4.4 DCP010505B V OUT vs LOAD Load (%) VOUT (V) 5.8 5.7 5.6 5.5 5.4 5.3 5.2 5.1 5.0 4.9 4.8 4.7 10010 20 30 40 50 60 70 80 90 DCP010505B EFFICIENCY vs LOAD Load (%) Efficiency (%) 10010 20 30 40 50 60 70 80 90 DCP010505DB V OUT vs LOAD Load (%) VOUT (V) 5.8 5.7 5.6 5.5 5.4 5.3 5.2 5.1 5.0 4.9 4.8 4.7 10010 20 30 40 50 60 70 80 90 +V OUT −VOUT DCP010505DB EFFICIENCY vs LOAD Load (%) Efficiency (%) 10010 20 30 40 50 60 70 80 90

SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = 25°C, unless otherwise noted. DCP010512B V OUT vs LOAD Load (%) VOUT (V) 14.5 14.0 13.5 13.0 12.5 12.0 11 .5 11 .0 10010 20 30 40 50 60 70 80 90 DCP010512B EFFICIENCY vs LOAD Load (%) Efficiency (%) 10010 20 30 40 50 60 70 80 90 DCP010512DB V OUT vs LOAD Load (%) VOUT (V) 14.5 14.0 13.5 13.0 12.5 12.0 11 .5 11 .0 10.5 10.0 20 30 50 70 60 80 90 1004010 +VOUT −VOUT DCP010512DB EFFICIENCY vs LOAD Load (%) Efficiency (%) 20 30 50 70 60 80 90 1004010 DCP010515B V OUT vs LOAD Load (%) VOUT (V) 18.0 17.5 17.0 16.5 16.0 15.5 15.0 14.5 14.0 10010 20 30 40 50 60 70 80 90 DCP010515B EFFICIENCY vs LOAD Load (%) Efficiency (%) 10010 20 30 40 50 60 70 80 90

SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = 25°C, unless otherwise noted. DCP010515DB V OUT vs LOAD Load (%) VOUT (V) 20 30 50 70 60 80 90 1004010 +V OUT −VOUT DCP010515DB EFFICIENCY vs LOAD Load (%) Efficiency (%) 20 30 50 70 60 80 90 1004010 DCP012405B V OUT vs LOAD Load (%) VOUT (V) 5.60 5.50 5.40 5.30 5.20 5.10 5.00 4.90 4.80 20 30 60 50 70 80 1004010 DCP012405B EFFICIENCY vs LOAD Load (%) Efficiency (%) 20 30 70 60 80 90 10040 5010 DCP010505B CONDUCTED EMISSIONS (125% Load) Emission Level, Peak (dBµA) Frequency (MHz) 10.15 10 30 −10 −20 DCP010505B CONDUCTED EMISSIONS (8% Load) Emission Level, Peak (dBµA) Frequency (MHz) 10.15 10 30 −10 −20

SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = 25°C, unless otherwise noted. DCP011512DBP V OUT vs LOAD Load (%) VOUT (V) 13.50 13.00 12.50 12.00 11.50 11.00 10.50 10010 20 30 40 50 60 70 80 90 +VOUT −VOUT DCP011512DBP EFFICIENCY vs LOAD Load (%) Efficiency (%) 20 30 50 70 60 80 90 1004010 DCP011515DBP EFFICIENCY vs LOAD Load (%) Efficiency (%) 10010 20 30 40 50 60 70 80 90 DCP01 1515DBP VOUT vs LOAD Load (%) Efficiency (%) 17.00 16.50 16.00 15.50 15.00 14.50 14.00 13.50 13.00 10010 20 30 40 50 60 70 80 90 +VOUT −VOUT DCP012415DBP EFFICIENCY vs LOAD Load (%) Efficiency (%) 10010 20 30 40 50 60 70 80 90 DCP012415DBP V OUT vs LOAD Load (%) VOUT (V) 16.50 16.00 15.50 15.00 14.50 14.00 13.50 10010 20 30 40 50 60 70 80 90 +V OUT −VOUT

SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004 www.ti.com FUNCTIONAL DESCRIPTION OVERVIEW The DCP01B offers up to 1W of unregulated output power with a typical efficiency of up to 85%. This is achieved through highly integrated packaging technology and the implementation of a custom power stage and control IC. The circuit design uses an advanced BiCMOS/DMOS process. For additional information, refer to the application notes located in the DCP01B product folder at www.ti.com. POWER STAGE This uses a push-pull, center-tapped topology switching at 400kHz (divide-by-2 from 800kHz oscillator). OSCILLATOR AND WATCHDOG The onboard 800kHz oscillator generates the switching frequency via a divide-by-2 circuit. The oscillator can be synchronized to other DCP01B circuits or an external source, and is used to minimize system noise. A watchdog circuit checks the operation of the oscillator circuit. The oscillator can be stopped by pulling the SYNC pin low. The output pins will be tri-stated. This will occur in 2µs. THERMAL SHUTDOWN The DCP01B is protected by a thermal shutdown circuit. If the on-chip temperature exceeds 150°C, the device will shut down. Once the temperature falls below 150°C, normal operation will resume. If the thermal condition continues, operation will randomly cycle on and off. This will continue until the temperature is reduced. SYNCHRONIZATION In the event that more than one DC/DC converter is needed onboard, beat frequencies and other electrical interference can be generated. This is due to the small variations in switching frequencies between the DC/DC converters. The DCP01B overcomes this by allowing devices to be synchronized to one another. Up to eight devices can be synchronized by connecting the SYNC IN pins together, taking care to minimize the stray capacitance. Stray capacitance (> 3pF) will have the effect of reducing the switching frequency, or even stopping the oscillator circuit. If synchronized devices are used, it should be noted that at startup, all devices will draw maximum current simultaneously. This can cause the input voltage to dip. If it dips below the minimum input voltage (4.5V), the devices may not start up. A 2.2µF capacitor should be connected close to the input pins. If more than eight devices are to be synchronized, it is recommended that the SYNC IN pins are driven by an external device. Details are contained in Application Report SBAA035, External Synchronization of the DCP01/02 Series of DC/DC Converters, available for download at www.ti.com. CONSTRUCTION The DCP01B basic construction is the same as standard ICs. There is no substrate within the molded package. The DCP01B is constructed using an IC, rectifier diodes, and a wound magnetic toroid on a leadframe. Since there is no solder within the package, the DCP01B does not require any special PCB assembly processing. This results in an isolated DC/DC converter with inherently high reliability. ADDITIONAL FUNCTIONS DISABLE/ENABLE The DCP01B can be disabled or enabled by driving the SYNC pin using an open drain CMOS gate. If the SYNC IN pin is pulled low, the DCP01B will be disabled. The disable time depends upon the external loading; the internal disable function is implemented in 2µs. Removal of the pull-down will cause the DCP01B to be enabled. Capacitive loading on the SYNCIN pin should be minimized in order to prevent a reduction in the oscillator frequency. DECOUPLING Ripple Reduction A high switching frequency of 400kHz allows simple filtering. To reduce ripple, it is recommended that at least a 1µF capacitor is used on V OUT . Dual outputs should have both the positive and negative buses decoupled to VOUT ground (pin 5). The required 2.2µF low equivalent series resistance (ESR) ceramic capacitor on the input of the 5V to 15V versions, and the ≥ 0.47µF low-ESR ceramic capacitor on the 24V versions help reduce ripple and noise. See Application Bulletin SBVA012, DC-to-DC Converter Noise Reduction, available for download at www.ti.com.

SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004 www.ti.com

APPLICATION INFORMATION

The DCP01B, DCV01, and DCP02 are three families of miniature DC/DC converters providing an isolated unregulated voltage output. All are fabricated using a CMOS/DMOS process with the DCP01B replacing the familiar DCP01 family that was fabricated from a bipolar process. The DCP02 is essentially an extension of the DCP01B family providing a higher power output with a significantly improved load regulation, and the DCV01 is tested to a higher isolation voltage. TRANSFORMER DRIVE CIRCUIT Transformer drive transistors have a characteristically low value of transistor on resistance (RDS ); thus, more power is transferred to the transformer. The transformer drive circuit is limited by the base current available to switch on the power transistors driving the transformer and their characteristic current gain (beta), resulting in a slower turn-on time. Consequently, more power is dissipated within the transistor. This results in a lower overall efficiency, particularly at higher output load currents. SELF-SYNCHRONIZATION The input synchronizations facility (SYNCIN), allows for easy synchronizing of multiple devices. If two to eight devices (maximum) have their respective SYNCIN pins connected together, then all devices will be synchronized. Each device has its own onboard oscillator. This is generated by charging a capacitor from a constant current and producing a ramp. When this ramp passes a threshold, an internal switch is activated that discharges the capacitor to a second threshold before the cycle is repeated. When several devices are connected together, all the internal capacitors are charged simultaneously. When one device passes its threshold during the charge cycle, it starts the discharge cycle. All the other devices sense this falling voltage and, likewise, initiate a discharge cycle so that all devices discharge together. A subsequent charge cycle is only restarted when the last device has finished its discharge cycle. OPTIMIZING PERFORMANCE Optimum performance can only be achieved if the device is correctly supported. By the very nature of a switching converter, it requires power to be instantly available when it switches on. If the converter has DMOS switching transistors, the fast edges will create a high current demand on the input supply. This transient load placed on the input is supplied by the external input decoupling capacitor, thus maintaining the input voltage. Therefore, the input supply does not see this transient (this is an analogy to high-speed digital circuits). The positioning of the capacitor is critical and must be placed as close as possible to the input pins and connected via a low-impedance path. The optimum performance is primarily dependent on two factors: 1. Connection of the input and output circuits for minimal loss. 2. The ability of the decoupling capacitors to maintain the input and output voltages at a constant level. PCB Design The copper losses (resistance and inductance) can be minimized by the use of mutual ground and power planes (tracks) where possible. If that is not possible, use wide tracks to reduce the losses. If several devices are being powered from a common power source, a star-connected system for the track must be deployed; devices must not be connected in series, as this will cascade the resistive losses. The position of the decoupling capacitors is important. They must be as close to the devices as possible in order to reduce losses. See the PCB Layout section for more details.

impedance indicates the capacitors’ resonant frequency. this point, the capacitor is not effective as a capacitor. Figure 4. Capacitor Impedance vs Frequency VIN is the voltage at the device input. ITR is the transient load current. switch on, the voltage at the input pins will fall momentarily. the transformer and destruction of the device. correctly. Otherwise, the device will be caught up in a loop. voltage as derated by the vendor. the value of the ESR for the filter capacitor.

SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004 www.ti.com DUAL OUTPUT VOLTAGE DCP AND DCVs The voltage output for the dual DCPs is half wave rectified; therefore, the discharge time is 1.25µs. Repeating the above calculations using the 100% load resistance of 25Ω (0.2A per output), the results are shown below: τ = 25µs TDIS = 1.25µs. VDIS = 244mV VESR = 20mV Ripple Voltage = 266mV This time, it is the capacitor discharging that is contributing to the largest component of ripple. Changing the output filter to 10µF, and repeating the calculations: Ripple Voltage = 45mV. This value is composed of almost equal components. The above calculations are given only as a guide. Capacitor parameters usually have large tolerances and can be susceptible to environmental conditions. PCB LAYOUT Figure 5 and Figure 6 illustrate a printed circuit board (PCB) layout for the two conventional (DCP01/02, DCV01), and two SO-28 surface-mount packages (DCP02U). Figure 7 shows the schematic. Input power and ground planes have been used, providing a low-impedance path for the input power. For the output, the common or 0V has been connected via a ground plane, while the connections for the positive and negative voltage outputs are conducted via wide traces in order to minimize losses. The location of the decoupling capacitors in close proximity to their respective pins ensures low losses due to the effects of stray inductance; thus, improving the ripple performance. This is of particular importance to the input decoupling capacitor as this supplies the transient current associated with the fast switching waveforms of the power drive circuits. The Sync pin, when not being used, is best left as a floating pad. A ground ring or annulus connected around the pin will prevent noise being conducted onto the pin. If the Sync pin is being connected to one or more Sync pins, then the linking trace should be narrow and must be kept short in length. In addition, no other trace should be in close proximity to this trace because that will increase the stray capacitance on this pin, and that will effect the performance of the oscillator. Ripple and Noise Careful consideration should be given to the layout of the PCB, in order that the best results can be obtained. The DCP01B is a switching power supply and as such can place high peak current demands on the input supply. In order to avoid the supply falling momentarily during the fast switching pulses, ground and power planes should be used to connect the power to the input of DCP01B. If this is not possible, then the supplies must be connected in a star formation with the traces made as wide as possible. If the SYNC IN pin is being used, then the trace connection between device SYNCIN pins should be short to avoid stray capacitance. If the SYNCIN pin is not being used, it is advisable to place a guard ring (connected to input ground) around this pin to avoid any noise pick up. The output should be taken from the device using ground and power planes; this ensures minimum losses. A good quality low-ESR ceramic capacitor placed as close as practical across the input will reduce reflected ripple and ensure a smooth startup. A good quality low-ESR capacitor (ceramic preferred) placed as close as practical across the rectifier output terminal and output ground gives the best ripple and noise performance. See SBVA012 for more information on noise rejection. THERMAL MANAGEMENT Due to the high power density of this device, it is advisable to provide ground planes on the input and output.

(1) Capacitors C2−1, C4−1, C7−1, and C9−1 are through-hole plated components connected in parallel with C2, C4, C7 and C9 (1206 SMD), respectively. (2) For optimum low-noise performance, use low-ESR capacitors. (3) Do not connect the SYNC pin jumper (JP1−JP4) if the SYNC function is not being used. (4) Connections to the power input should be made with a minimum wire of 16/0.2 twisted pair, with the length kept short. (5) VSx and 0Vx are input supply and ground respecively (x represents the channel). (6) +Vx and −Vx are the positive and negative outputs, referenced to a common ground COMx. (7) JPx are the links used for self-synchronization; if this facility is not being used, the links should be unconnected. (8) R1 −R8 are the power output loads; do not fit these if an external load is connected. (9) CON1 and CON2 are DIL-14; CON3 and CON4 are SO-28 packages. Figure 7. Example of PCB Layout, Schematic Diagram

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) DCP010505BP ACTIVE PDIP NVA 7 25 TBD CU SNPB Level-NA-NA-NA DCP010505BP-U ACTIVE SOP DUA 7 25 TBD CU SNPB Level-3-240C-168 HR DCP010505BP-U/700 ACTIVE SOP DUA 7 700 TBD CU SNPB Level-3-240C-168 HR DCP010505DBP ACTIVE PDIP NVA 7 25 TBD CU SNPB Level-NA-NA-NA DCP010505DBP-U ACTIVE SOP DUA 7 25 TBD CU SNPB Level-3-240C-168 HR DCP010505DBP-U/700 ACTIVE SOP DUA 7 700 TBD CU SNPB Level-3-240C-168 HR DCP010512BP ACTIVE PDIP NVA 7 25 TBD CU SNPB Level-NA-NA-NA DCP010512BP-U ACTIVE SOP DUA 7 25 TBD CU SNPB Level-3-240C-168 HR DCP010512BP-U/700 ACTIVE SOP DUA 7 700 TBD CU SNPB Level-3-240C-168 HR DCP010512DBP ACTIVE PDIP NVA 7 25 TBD CU SNPB Level-NA-NA-NA DCP010512DBP-U ACTIVE SOP DUA 7 25 TBD CU SNPB Level-3-240C-168 HR DCP010512DBP-U/700 ACTIVE SOP DUA 7 700 TBD CU SNPB Level-3-240C-168 HR DCP010515BP ACTIVE PDIP NVA 7 25 TBD CU SNPB Level-NA-NA-NA DCP010515BP-U ACTIVE SOP DUA 7 25 TBD CU SNPB Level-3-240C-168 HR DCP010515BP-U/700 ACTIVE SOP DUA 7 700 TBD CU SNPB Level-3-240C-168 HR DCP010515DBP ACTIVE PDIP NVA 7 25 TBD CU SNPB Level-NA-NA-NA DCP010515DBP-U ACTIVE SOP DUA 7 25 TBD CU SNPB Level-3-240C-168 HR DCP010515DBP-U/700 ACTIVE SOP DUA 7 700 TBD CU SNPB Level-3-240C-168 HR DCP011512DBP ACTIVE PDIP NVA 7 25 TBD CU SNPB Level-NA-NA-NA DCP011512DBP-U ACTIVE SOP DUA 7 25 TBD CU SNPB Level-3-240C-168 HR DCP011512DBP-U/700 ACTIVE SOP DUA 7 700 TBD CU SNPB Level-3-240C-168 HR DCP011515DBP ACTIVE PDIP NVA 7 25 TBD CU SNPB Level-NA-NA-NA DCP011515DBP-U ACTIVE SOP DUA 7 25 TBD CU SNPB Level-3-240C-168 HR DCP011515DBP-U/700 ACTIVE SOP DUA 7 700 TBD CU SNPB Level-3-240C-168 HR DCP012415DBP ACTIVE PDIP NVA 7 25 TBD CU SNPB Level-NA-NA-NA DCP012415DBP-U ACTIVE SOP DUA 7 25 TBD CU SNPB Level-3-240C-168 HR DCP012415DBP-U/700 ACTIVE SOP DUA 7 700 TBD CU SNPB Level-3-240C-168 HR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2005 Addendum-Page 1

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2005 Addendum-Page 2

MPDI058 – APRIL 2001 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 NVA (R-PDIP-T7/14) PLASTIC DUAL-IN-LINE – C – 0.010 (0,25) CM E F C C H D D D C E 4202489/A 03/01 0.280 (7,11) 0.240 (6,10) Area 14 8 0.775 (19,69) 0.735 (18,67) 0.150 (3,81) 0.115 (2,92) 0.115 (2,92) 0.195 (4,95) 0.300 (7,62) 0.325 (8,26) 0.022 (0,56) 0.014 (0,36) Seating Plane 0.014 (0,36) 0.008 (0,20) 0.070 (1,78) 0.045 (1,14) Index 0.430 (10,92) MAX 0.015 (0,38) MIN 0.005 (0,13) MIN Full Lead 4 PL 0.210 (5,33) MAX Base Plane 0.000 (0,00) 0.060 (1,52) F NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Dimensions are measured with the package seated in JEDEC seating plane gauge GS-3. D. Dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 (0,25). E. Dimensions measured with the leads constrained to be perpendicular to Datum C. F. Dimensions are measured at the lead tips with the leads unconstrained. G. Pointed or rounded lead tips are preferred to ease insertion. H. Lead shoulder maximum dimension does not include dambar protrusions. Dambar protrusions shall not exceed 0.010 (0,25). I. Distance between leads including dambar protrusions to be 0.005 (0,13) minumum. J. A visual index feature must be located within the cross–hatched area. K. For automatic insertion, any raised irregularity on the top surface (step, mesa, etc.) shall be symmetrical about the lateral and longitudinal package centerlines. L. Falls within JEDEC MS-001-AA.

MPDS097 – APRIL 2001 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DUA (R-PDSO-G7/14) PLASTIC SMALL-OUTLINE 4202490/A 03/01 0.405 (10,30) 0.420 (10,70) 0.008 (0,20) 0.014 (0,36) 0.025 (0,65) 0.043 (1,10) 0.045 (1,15) 0.057 (1,45) 80.735 (18,67) 0.775 (19,69) 0.280 (7,11) 0.240 (6,10) 0.014 (0,36) 0.022 (0,56) 0.045 (1,14) 0.070 (1,78) 0.005 (0,13) MIN Full Lead 4 PL Seating Plane Base Plane Index Area 0.015 (0,38) MIN 0.210 (5,33) MAX 0.100 (2,54) 0.300 (7,62) 0.325 (8,26) C C 0 /C00345° D C NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 (0,25). D. Lead shoulder maximum dimension does not include dambar protrusions. Dambar protrusions shall not exceed 0.010 (0,25). E. Distance between leads including dambar protrusions to be 0.005 (0,13) minimum. F. A visual index feature must be located within the cross–hatched area. G. For automatic insertion, any raised irregularity on the top surface (step, mesa, etc.) shall be symmetrical about the lateral and longitudinal package centerlines.

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