DCORDIC DCD | Alldatasheet

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All trademarks mentioned in this document are trademarks of their respective owners. http://www.dcd.pl Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved. http://www.DigitalCoreDesign.com DDCCOORRDDIICC CORDIC processor ver 1.16 OVERVIEW The DCORDIC uses the CORDIC algorithm to compute trigonometric , reverse trigono- metric, hyperbolic and reverse hyperbolic functions. It supports sine, cosine, arcus tangent func- tions for hyperbolic and trigonometric sys- tems. Logarithm, square root and exponent functions can also be computed. It supports fixed point 24-bit numbers. OPERATING MODES Trigonometric system Hyperbolic system Rotation mode Vectoring mode

APPLICATIONS

24-bit precision (IEEE-754 single preci- sion real mantissa format) 4-ulp accuracy (34-bit internal registers) Fully configurable Performs the following functions: sin(θ), cos(θ) sinh(θ), cosh(θ) arctan(x) arctanh(x) ln(x), ex, x DELIVERABLES Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF netlist VHDL & VERILOG test bench environ- ment Active-HDL automatic simulation mac- ros ModelSim automatic simulation macros Tests with reference responses Technical documentation Installation notes HDL core specification Datasheet Synthesis scripts Example application Technical support IP Core implementation support 3 months maintenance

  • Delivery the IP Core updates, mi- nor and major versions changes
  • Delivery the documentation up- dates
  • Phone & email support

All trademarks mentioned in this document are trademarks of their respective owners. Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved. http://www.DigitalCoreDesign.com http://www.dcd.pl LICENSING Comprehensible and clearly defined licensing methods without royalty fees make using of IP Core easy and simply. Single Design license allows use IP Core in single FPGA bitstream and ASIC implemen- tation. Unlimited Designs , One Year licenses allow use IP Core in unlimited number of FPGA bitstreams and ASIC implementations. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited. There is no time restric- tion except One Year license where time of use is limited to 12 months. Single Design license for VHDL, Verilog source code called HDL Source ○ Encrypted, or plain text EDIF called Netlist One Year license for Encrypted Netlist only Unlimited Designs license for HDL Source Netlist Upgrade from HDL Source to Netlist Single Design to Unlimited Designs SYMBOL datai(29:0) datao(29:0) busyrd we addr(1:0) trigsel hyprsel rotatemode vectormode en rst clk PINS DESCRIPTION PIN TYPE DESCRIPTION clk Input Global clock rst Input Global reset en Input Enable computing datai[29:0] Input Data bus (input) we Input Write data into register rd Input Read data from register cs Input Chip select addr[1:0] Input Select register to read/write rotatemode Input Rotate mode select vectormode Input Vectoring mode select hyprsel Input Hyperbolic system select trigsel Input Trigonometric system select datao[29:0] Output Data bus (output) busy Output Busy indicator BLOCK DIAGRAM ROM – stores constant coefficients used for hyperbolic and trigonometric opera- tions. Registers – contains all data registers hold temporary operation results as well as final results. Input arguments are writ- ten to this register also. Control Unit – maintains control opera- tion on Registers module, Shifters module and ROM unit, while busy is active. ROM Registers Shifters Control unit clk rst en datai(29:0) datao(29:0) addr(1:0) we rd busy Interface rotatemode vectormode trigsel hyprsel Shifters – performs shifting operations in successful iterations. Number of shifts

All trademarks mentioned in this document are trademarks of their respective owners. Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved. http://www.DigitalCoreDesign.com http://www.dcd.pl vary and depend on internal iteration cy- cle and computed functions. Interface – performs communication be- tween internal CORDIC modules and ex- ternal devices. Signalizes when output registers contain a valid result. CONTACTS For any modification or special request please contact to Digital Core Design or local distributors. Headquarters: Wroclawska 94 41-902 Bytom, POLAND e-mail: info@dcd.pliinnffoo@@ddccdd..ppll tel. : +48 32 282 82 66 fax : +48 32 282 74 37 Distributors: