DCL520C00

Toshiba Semiconductor

HIGH SPEED DUAL CHANNEL DIGITAL ISOLATORS 2025-02-10 Rev.1.0

Manufacturer: Toshiba Semiconductor

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Industrial automation systems
Motor control
Inverter
Switching power supply 2. Description DCL520C00/DCL520D00/DCL521C00/DCL521D00 are dual-channel digital isolators based on Toshiba complementary metal-oxide semiconductor (CMOS) technology. High reinforced insulation is achieved by Toshiba CMOS technology and the magnetic coupling structure. DCL520C00/DCL520D00/DCL521C00/DCL521D00 data channels are available in a variety of configuration with a withstand voltage of 3000 Vrms. DCL520C00/DCL520D00/DCL521C00/DCL521D00 can operate with a temperature range of -40 to 125 °C and a wide supply voltage of 2.25 to 5.5 V. 3. Features Data rate : Up to 150 Mbps Supply voltage : 2.25 V to 5.5 V Temperature Range : -40 °C to 125 °C Propagation Delay :10.9 ns Typical (5.0 V operation) Default Output : High and Low Options High CMTI(min) : 100 kV/μs Withstand Voltage : 3.0 kVrms Safety-Related Certification : UL : UL1577 VDE : DIN EN IEC 60747-17 (VDE 0884-17) (Applying) (Note 1) CQC : (Planning) Note 1:When a VDE approved type is needed, please contact your Toshiba sales representative. Do not design your products or systems based on the information on this document. Please contact your Toshiba sales representative for updated information before designing your products.

Rev.1.0 © 2021-2025 Toshiba Electronic Devices & Storage Corporation Preliminary 4. Internal Circuit (Simplified Schematic) 5. Pin configuration and Functions DCL520C00 / DCL520D00 DCL521C00 / DCL521D00 5.1. Pin Functions PIN I/O DESCRIPTION NAME DCL520C00 DCL520D00 DCL521C00 DCL521D00 VDD1 1 1 ― Power Supply, side 1 VI1 2 7 I Input, Channel1 VI2 3 3 I Input, Channel2 GND1 4 4 ― GND connection for VDD1, side 1 GND2 5 5 ― GND connection for VDD2, side 2 VO2 6 6 O Output, Channel2 VO1 7 2 O Output, Channel1 VDD2 8 8 ― Power Supply, side 2 1 ● 8 VI1 VO12 7 VDD1 VDD2 3 6 4 5 VI2 VO2 GND2GND1 1 ● 8VDD1 VO1 2 7 VDD2 3 6 VO2 VI1 4 5 VI2 GND2GND1

Rev.1.0 © 2021-2025 Toshiba Electronic Devices & Storage Corporation Preliminary 6. Functional Description (1) DCL520C00/ DCL520D00 VDDI VDDO INPUT (VIx) OUTPUT (VOx) COMMENTS PU PU (Note1) L L Normal Operation H H OPEN Default Default mode: When INPUT is open, the corresponding channel output goes to its default logic status. DCL520C00=L, DCL520D00=H PD L or OPEN PU PD X Undetermined When VDD2 is unpowered, a channel output is undetermined. PD L or OPEN PD X H - Don’t use, since a certain voltage will be output through the internal ESD circuit. PU= Powered up (VDD≥2.25 V), PD=Powered down (VDD≤1.7 V), H=High Level, L=Low Level, X=don’t care Note1 : The state of the output pin is fixed after 20μs from the time the power supply voltage VDDO is turned on(PD⇒PU). (2) DCL521C00/ DCL521D00 VDDI VDDO INPUT (VIx) OUTPUT (VOx) COMMENTS PU PU (Note1) L L Normal Operation H H OPEN Default Default mode: When INPUT is open, the corresponding channel output goes to its default logic status. DCL521C00=L, DCL521D00=H PD L or OPEN PU PD X Undetermined When VDD2 is unpowered, a channel output is undetermined. PD L or OPEN PD X H - Don’t use, since a certain voltage will be output through the internal ESD circuit. PU= Powered up (VDD≥2.25 V), PD=Powered down (VDD≤1.7 V), H=High Level, L=Low Level, X=don’t care Note1 : The state of the output pin is fixed after 20μs from the time the power supply voltage VDDO is turned on(PD⇒PU).

Rev.1.0 © 2021-2025 Toshiba Electronic Devices & Storage Corporation Preliminary 7. Absolute Maximum Ratings (Ta = 25 °C) PARAMETER SYMBOL MIN MAX UNIT Power supply voltage VDD1, VDD2 -0.5 6.0 V Input Voltage VI -0.5 VDD1+0.5 (Note1) V Output Voltage VO -0.5 VDD2+0.5 (Note1) V Output Current IO -15 15 mA Storage Temperature Tstg -65 150 °C Operating Temperature Topr -40 125 °C Soldering Temperature (10 s) T sol ― 260 °C Maximum Withstanding Isolation Voltage (60 s) BV S ― 3000 Vrms Note1: Maximum voltage must not exceed 6 V. 8. Recommended Operating Conditions (Note) PARAMETER SYMBOL MIN MAX UNIT Power supply voltage VDD1, VDD2 2.25 5.5 V Junction Temperature TJ -40 150 °C Ambient Temperature Ta -40 125 °C Note: The recommended operating conditions are given as a design guide necessary to obtain the intended performance of the device. Each parameter is an independent value. When creating a system design using this device, the electrical characteristics specified in this data sheet should also be considered. Note: A ceramic capacitor (0.1 μF) should be connected between pin 1 (VDD1) and pin 4 (GND1) for VDD1 and between pin 8 (VDD2) and pin 7 (GND2) for VDD2, and should be the layout on the IC as close as possible (less than 10 mm). Otherwise, the IC may not switch properly.

Rev.1.0 © 2021-2025 Toshiba Electronic Devices & Storage Corporation Preliminary 9. Electrical Characteristics 9.1. Electrical Characteristics – 5 V Supply All typical specifications are at Ta=25 °C、VDD1=VDD2=5 V. Minimum/maximum specifications apply over the entire recommended operating range of 4.5 V≤VDD1≤5.5 V, 4.5 V≤VDD2≤5.5 V, and -40 °C≤Ta≤125 °C, unless otherwise noted. PARAMETER TEST CONDITIONS Fig. SYMBOL MIN T Y P. MAX UNIT DC SPECIFICATIONS Under voltage Lockout Threshold when supply voltage is rising 12-1 VDDxUV+ ― 2.1 2.25 V Threshold when supply voltage is falling VDDxUV- 1.7 1.9 ― Supply voltage hysteresis VDDxUVH 0.1 0.2 ― Output Voltage Logic High VIx=H , IOH=-20 μA 12-2 VOH VDDO-0.1 (Note1) VDDO (Note1) ― V VIx=H , IOH=-4 mA VDDO-0.4 (Note1) VDDO-0.2 (Note1) ― Output Voltage Logic Low VIx=L , IOL =20 μA 12-2 VOL ― 0 0.1 V VIx=L , IOL =4 mA ― 0.2 0.4 Output impedance ― 12-2 ZO ― 50 ― Ω High-level input voltage ― 12-3 VIH 0.7*VDDI (Note1) ― ― V Low-level input voltage ― 12-3 VIL ― ― 0.3*VDDI (Note1) V Input Voltage Hysteresis ― 12-3 VHYS ― 0.37 ― V Input Current VI= VDDI(Note1) or 0 V - II ― ― ±10 μA SWITCHING SPECIFICATIONS Data Rate ― - t_bps DC ― 150 Mbps Pulse Width ― - PW 6.6 ― ― ns Propagation Delay 50 kHz,Duty=50 %, tr=tf=2 ns,CL=15 pF 12-4 tPHL , tPLH ― 10.9 18.3 ns Pulse Width Distortion |tPHL – tPLH| 12-4 PWD ― 0.8 2.5 ns Propagation Delay Skew (Between any two units)(Note2) ― - tPSK(PP) ― ― 10 ns Channel Matching Same Direction 12-4 tskCD ― ― 3.2 ns Opposing Direction 12-4 tskOD ― ― 3.6 ns Output Rise Time 10 % - 90 % 12-4 tr ― 0.9 ― ns Output Fall Time 90 % - 10 % 12-4 tf ― 0.9 ― ns Common mode transient Immunity VI= VDDI or 0 V , VCM=1500 V , Ta=25 °C 12-5 CMTI 100 ― ― kV/μs Note1: VDDI=Input-side VDDx , VDDO=Output-side VDDx Note2: The propagation delay skew, tpsk, is equal to the magnitude of the difference in propagation delay that will be seen between units at the same given conditions (supply voltage, input current, temperature, etc.).

Rev.1.0 © 2021-2025 Toshiba Electronic Devices & Storage Corporation Preliminary 9.2. Electrical Characteristics – 3.3 V Supply All typical specifications are at T a=25 °C、VDD1=VDD2=3.3 V. Minimum/maximum specifications apply over the entire PARAMETER TEST CONDITIONS Fig. SYMBOL MIN T Y P. MAX UNIT DC SPECIFICATIONS Under voltage Lockout Threshold when supply voltage is rising 12-1 VDDxUV+ ― 2.1 2.25 V Threshold when supply voltage is falling VDDxUV- 1.7 1.9 ― Supply voltage hysteresis VDDxUVH 0.1 0.2 ― Output Voltage Logic High VIx=H , IOH=-20 μA 12-2 VOH VDDO-0.1 (Note1) VDDO (Note1) ― V VIx=H , IOH=-4 mA VDDO-0.4 (Note1) VDDO-0.2 (Note1) ― Output Voltage Logic Low VIx=L , IOL =20 μA 12-2 IOL ― 0 0.1 V VIx=L , IOL =4 mA ― 0.2 0.4 Output impedance ― 12-2 ZO ― 50 ― Ω High-level input voltage ― 12-3 VIH 0.7*VDDI (Note1) ― ― V Low-level input voltage ― 12-3 VIL ― ― 0.3*VDDI (Note1) V Input Voltage Hysteresis ― 12-3 VHYS ― 0.32 ― V Input Current VI= VDDI(Note1) or 0 V - II ― ― ±10 μA SWITCHING SPECIFICATIONS Data Rate ― - t_bps DC ― 150 Mbps Pulse Width ― - PW 6.6 ― ― ns Propagation Delay 50 kHz,Duty=50 %, tr=tf=2 ns,CL=15 pF 12-4 tPHL , tPLH ― 11.6 19.1 ns Pulse Width Distortion |tPHL – tPLH| 12-4 PWD ― 0.8 2.5 ns Propagation Delay Skew (Between any two units)(Note2) ― - tPSK(PP) ― ― 10 ns Channel Matching Same Direction 12-4 tskCD ― ― 3.3 ns Opposing Direction 12-4 tskOD ― ― 3.7 ns Output Rise Time 10 % - 90 % 12-4 tr ― 0.8 ― ns Output Fall Time 90 % - 10 % 12-4 tf ― 0.8 ― ns Common mode transient Immunity VI= VDDI or 0 V , VCM=1500 V , Ta=25 °C 12-5 CMTI 100 ― ― kV/μs Note1: VDDI=Input-side VDDx , VDDO=Output-side VDDx Note2: The propagation delay skew, tpsk, is equal to the magnitude of the difference in propagation delay that will be seen between units at the same given conditions (supply voltage, input current, temperature, etc.)

Rev.1.0 © 2021-2025 Toshiba Electronic Devices & Storage Corporation Preliminary 9.3. Electrical Characteristics – 2.5 V Supply All typical specifications are at T a=25 °C、VDD1=VDD2=2.5 V. Minimum/maximum specifications apply over the entire recommended operating range of 2.25 V ≤VDD1≤2.75 V, 2.25 V≤VDD2≤2.75 V, and -40 °C≤Ta≤125 °C, unless otherwise noted. PARAMETER TEST CONDITIONS Fig. SYMBOL MIN T Y P. MAX UNIT DC SPECIFICATIONS Under voltage Lockout Threshold when supply voltage is rising 12-1 VDDxUV+ ― 2.1 2.25 V Threshold when supply voltage is falling VDDxUV- 1.7 1.9 ― Supply voltage hysteresis VDDxUVH 0.1 0.2 ― Output Voltage Logic High VIx=H , IOH=-20 μA 12-2 VOH VDDO-0.1 (Note1) VDDO (Note1) ― V VIx=H , IOH=-4 mA VDDO-0.4 (Note1) VDDO-0.2 (Note1) ― Output Voltage Logic Low VIx=L , IOL =20 μA 12-2 IOL ― 0 0.1 V VIx=L , IOL =4 mA ― 0.2 0.4 Output impedance ― 12-2 ZO ― 50 ― Ω High-level input voltage ― 12-3 VIH 0.7*VDDI (Note1) ― ― V Low-level input voltage ― 12-3 VIL ― ― 0.3*VDDI (Note1) V Input Voltage Hysteresis ― 12-3 VHYS ― 0.32 ― V Input Current VI= VDDI(Note1) or 0 V - II ― ― ±10 μA SWITCHING SPECIFICATIONS Data Rate ― - t_bps DC ― 150 Mbps Pulse Width ― - PW 6.6 ― ― ns Propagation Delay 50 kHz,Duty=50 %, tr=tf=2 ns,CL=15 pF 12-4 tPHL , tPLH ― 12.6 21.0 ns Pulse Width Distortion |tPHL – tPLH| 12-4 PWD ― 1.0 2.5 ns Propagation Delay Skew (Between any two units)(Note2) ― - tPSK(PP) ― ― 10 ns Channel Matching Same Direction 12-4 tskCD ― ― 3.5 ns Opposing Direction 12-4 tskOD ― ― 3.9 ns Output Rise Time 10 % - 90 % 12-4 tr ― 0.8 ― ns Output Fall Time 90 % - 10 % 12-4 tf ― 0.8 ― ns Common mode transient Immunity VI= VDDI or 0 V , VCM=1500 V , Ta=25 °C 12-5 CMTI 100 ― ― kV/μs Note1: VDDI=Input-side VDDx , VDDO=Output-side VDDx Note2: The propagation delay skew, tpsk, is equal to the magnitude of the difference in propagation delay t hat will be seen between units at the same given conditions (supply voltage, input current, temperature, etc.)

Rev.1.0 © 2021-2025 Toshiba Electronic Devices & Storage Corporation Preliminary 9.4. Supply Current Characteristics – 5 V Supply All typical specifications are at T a=25 °C、VDD1=VDD2=5 V. Minimum/maximum specifications apply over the entire (1) DCL520X00 PARAMETER TEST CONDITIONS SYMBOL MIN T Y P. MAX UNIT Supply Current ( DC Signal ) VI=0(DCL520C00), VI=1(DCL520D00) IDD1(Q) ― 1.1 1.7 mA IDD2(Q) ― 2.6 4 mA VI=0(DCL520D00), VI=1(DCL520C00) IDD1(Q) ― 10.5 16 mA IDD2(Q) ― 2.9 4.3 mA 1 Mbps fCLK=500 kHz, duty=50 % cycle square wave. CL=15 pF IDD1(1) ― 5.9 9.2 mA IDD2(1) ― 2.8 4.4 mA 25 Mbps fCLK=12.5 MHz, duty=50 % cycle square wave. CL=15 pF IDD1(25) ― 5.9 8.7 mA IDD2(25) ― 5.2 7.4 mA 100 Mbps fCLK=50 MHz, duty=50 % cycle square wave. CL=15 pF IDD1(100) ― 6.9 9.6 mA IDD2(100) ― 14 19.4 mA (2) DCL521X00 PARAMETER TEST CONDITIONS SYMBOL MIN T Y P. MAX UNIT Supply Current ( DC Signal ) VI=0(DCL521C00), VI=1(DCL521D00) IDD1(Q) ― 2.0 3.0 mA IDD2(Q) ― 2.0 3.0 mA VI=0(DCL521D00), VI=1(DCL521C00) IDD1(Q) ― 7.2 10.4 mA IDD2(Q) ― 7.2 10.4 mA 1 Mbps fCLK=500 kHz, duty=50 % cycle square wave. CL=15 pF IDD1(1) ― 4.6 6.8 mA IDD2(1) ― 4.6 6.8 mA 25 Mbps fCLK=12.5 MHz, duty=50 % cycle square wave. CL=15 pF IDD1(25) ― 6.1 8.5 mA IDD2(25) ― 6.1 8.5 mA 100 Mbps fCLK=50 MHz, duty=50 % cycle square wave. CL=15 pF IDD1(100) ― 11.1 15.6 mA IDD2(100) ― 11.1 15.6 mA

Rev.1.0 © 2021-2025 Toshiba Electronic Devices & Storage Corporation Preliminary 9.5. Supply Current Characteristics – 3.3 V Supply All typical specifications are at T a=25 °C、VDD1=VDD2=3.3 V. Minimum/maximum specifications apply over the entire (1) DCL520X00 PARAMETER TEST CONDITIONS SYMBOL MIN T Y P. MAX UNIT Supply Current ( DC Signal ) VI=0(DCL520C00), VI=1(DCL520D00) IDD1(Q) ― 1.1 1.5 mA IDD2(Q) ― 2.6 3.8 mA VI=0(DCL520D00), VI=1(DCL520C00) IDD1(Q) ― 10.4 15.5 mA IDD2(Q) ― 2.8 4.2 mA 1 Mbps fCLK=500 kHz, duty=50 % cycle square wave. CL=15 pF IDD1(1) ― 5.7 9 mA IDD2(1) ― 2.7 4.2 mA 25 Mbps fCLK=12.5 MHz, duty=50 % cycle square wave. CL=15 pF IDD1(25) ― 5.7 8.3 mA IDD2(25) ― 4.4 6.4 mA 100 Mbps fCLK=50 MHz, duty=50 % cycle square wave. CL=15 pF IDD1(100) ― 6.5 8.9 mA IDD2(100) ― 9.2 15.7 mA (2) DCL521X00 PARAMETER TEST CONDITIONS SYMBOL MIN T Y P. MAX UNIT Supply Current ( DC Signal ) VI=0(DCL521C00), VI=1(DCL521D00) IDD1(Q) ― 2.0 2.8 mA IDD2(Q) ― 2.0 2.8 mA VI=0(DCL521D00), VI=1(DCL521C00) IDD1(Q) ― 7.1 10.2 mA IDD2(Q) ― 7.1 10.2 mA 1 Mbps fCLK=500 kHz, duty=50 % cycle square wave. CL=15 pF IDD1(1) ― 4.5 6.6 mA IDD2(1) ― 4.5 6.6 mA 25 Mbps fCLK=12.5 MHz, duty=50 % cycle square wave. CL=15 pF IDD1(25) ― 5.5 7.6 mA IDD2(25) ― 5.5 7.6 mA 100 Mbps fCLK=50 MHz, duty=50 % cycle square wave. CL=15 pF IDD1(100) ― 8.7 12.3 mA IDD2(100) ― 8.7 12.3 mA

Rev.1.0 © 2021-2025 Toshiba Electronic Devices & Storage Corporation Preliminary 9.6. Supply Current Characteristics – 2.5 V Supply All typical specifications are at T a=25 °C、VDD1=VDD2=2.5 V. Minimum/maximum specifications apply over the entire recommended operating range of 2.25 V≤VDD1≤2.75 V, 2.25 V≤VDD2≤2.75 V, and -40 °C≤Ta≤125° C, unless otherwise noted. (1) DCL520X00 PARAMETER TEST CONDITIONS SYMBOL MIN T Y P. MAX UNIT Supply Current ( DC Signal ) VI=0(DCL520C00), VI=1(DCL520D00) IDD1(Q) ― 0.98 1.5 mA IDD2(Q) ― 2.52 3.7 mA VI=0(DCL520D00), VI=1(DCL520C00) IDD1(Q) ― 10.4 15.4 mA IDD2(Q) ― 2.8 4.1 mA 1 Mbps fCLK=500 kHz, duty=50 % cycle square wave. CL=15 pF IDD1(1) ― 5.6 8.8 mA IDD2(1) ― 2.7 4.1 mA 25 Mbps fCLK=12.5 MHz, duty=50 % cycle square wave. CL=15 pF IDD1(25) ― 5.5 8 mA IDD2(25) ― 4 5.9 mA 100 Mbps fCLK=50 MHz, duty=50 % cycle square wave. CL=15 pF IDD1(100) ― 6.4 8.4 mA IDD2(100) ― 7.5 13.3 mA (2) DCL521X00 PARAMETER TEST CONDITIONS SYMBOL MIN T Y P. MAX UNIT Supply Current ( DC Signal ) VI=0(DCL521C00), VI=1(DCL521D00) IDD1(Q) ― 1.9 2.8 mA IDD2(Q) ― 1.9 2.8 mA VI=0(DCL521D00), VI=1(DCL521C00) IDD1(Q) ― 7.1 10.1 mA IDD2(Q) ― 7.1 10.1 mA 1 Mbps fCLK=500 kHz, duty=50 % cycle square wave. CL=15 pF IDD1(1) ― 4.4 6.5 mA IDD2(1) ― 4.4 6.5 mA 25 Mbps fCLK=12.5 MHz, duty=50 % cycle square wave. CL=15 pF IDD1(25) ― 5.2 7.2 mA IDD2(25) ― 5.2 7.2 mA 100 Mbps fCLK=50 MHz, duty=50 % cycle square wave. CL=15 pF IDD1(100) ― 7.6 10.9 mA IDD2(100) ― 7.6 10.9 mA

Rev.1.0 © 2021-2025 Toshiba Electronic Devices & Storage Corporation Preliminary 10. Insulation Specifications PARAMETER Symbol TEST CONDITIONS VALUE UNIT Minimum External Clrearance CLR ― 4.0 mm Minimum External Creepage CPG ― 4.0 mm Distance Through The Insulation DTI ― 17 μm Comparative Tracking Index CTI ― 400 V Material Group ― According to IEC 60664-1 Ⅱ ― Overvoltage Category Per IEC 60664-1 ― Related Mains Voltage ≤ 150 VRMS I-IV ― ― Related Mains Voltage ≤ 300 VRMS I-III ― DIN EN IEC 60747-17; EN IEC 60747-17 Maximum Repititive Peak Isolation Voltage VIORM AC voltage (bipolar) 566 VPK Maximum Transient Isolation Voltage VIOTM VTEST = VIOTM, t = 60 s (qualification) , VTEST= 1.2 × VIOTM, t = 1 s (100 % production) 4243 VPK Maximum Impulse Voltage VIMP IEC 62368-1 1.2/50 μs waveform 5000 VPK Maximum surge isolation Voltage VIOSM Test method per IEC 62368-1, 1.2/50 μs waveform, VTEST ≥ 1.3 × VIMP (qualification) , min.10 kV

10000 VPK

voltage Vpd(m) Method A, After Input/Output safety test subgroup2&3, VIORM × 1.2 = Vpd (m), tini = 60 sec, tm = 10 sec, partial discharge < 5 pC 679 VPK Method A, After environmental tests subgroup 1, VIORM × 1.6 = Vpd (m), tini = 60 sec, tm = 10 sec, partial discharge < 5 pC 906 Method B2; At routine test (100 % production) and preconditioning (type test) VIORM × 1.875 = Vpd (m), 100 % production test, tini = tm = 1 sec, partial discharge < 5 pC 1062 Barrier capacitance, input to output CIO f = 1 MHz 0.8 pF Input Capacitance CI VIx 1.9 pF Isolation Resistance RIO VIO = 500 V, TA = 25 °C >1012 Ω VIO = 500 V, 100 °C ≤ TA ≤ 125 °C ≥1011 VIO = 500 V at TS = 150 °C ≥109 Pollution Degree ― ― 2 ― Climaic Category ― ― 40/125/21 ― UL 1577 Maximum Withstanding Isolation Voltage VISO VTEST = VISO , t = 60 s (qualification), VTEST = 1.2 × VISO , t = 1 s (100 % production) 3000 Vrms

Rev.1.0 © 2021-2025 Toshiba Electronic Devices & Storage Corporation Preliminary 11. Safety Limiting Values PARAMETER Symbol TEST CONDITIONS Value Unit Safety Input, Output Or Supply Current IS VDD1=VDD2=5.5 V, Tj=150 °C,Ta=25 °C 255 mA VDD1=VDD2=3.6 V, Tj=150 °C,Ta=25 °C 390 mA VDD1=VDD2=2.75 V, Tj=150 °C,Ta=25 °C 510 mA Safety Input, Output Or Total Power PS Tj=150 °C, Ta=25 °C 1403 W Maximum Safety Temperature TS - 150 °C Fig. 11.1 Thermal Derating Curve for Safety Limiting CurrentーTa

Rev.1.0 © 2021-2025 Toshiba Electronic Devices & Storage Corporation Preliminary 12. Test Circuit 1: Default=L︓VDD, Default=H︓GND Fig. 12.1.1 DCL520C00/DCL520D00 V DD1UV+/ VDD1UV- Test Circuit 1: Default=L︓VDD, Default=H︓GND Fig. 12.1.2 DCL521C00/DCL521D00 V DD1UV+/ VDD1UV- Test Circuit 1: Default=L︓VDD, Default=H︓GND Fig. 12.1.3 DCL520C00/DCL520D00 V DD2UV+/ VDD2UV- Test Circuit 1: Default=L︓VDD, Default=H︓GND Fig. 12.1.4 DCL521C00/DCL521D00 V DD2UV+/ VDD2UV- Test Circuit

Rev.1.0 © 2021-2025 Toshiba Electronic Devices & Storage Corporation Preliminary Fig. 12.2.1 DCL520C00/DCL520D00 V OH/VOL Test Circuit Fig. 12.2.2 DCL521C00/DCL521D00 V OH/VOL Test Circuit Fig. 12.3.1 DCL520C00/DCL520D00 V IH/VIL Test Circuit Fig. 12.3.2 DCL521C00/DCL521D00 V IH/VIL Test Circuit

Rev.1.0 © 2021-2025 Toshiba Electronic Devices & Storage Corporation Preliminary 1: The input pulse is supplied by a generator having the following characteristics: PRR≤50 kHz, 50 ％ duty cycle, tr≤2 ns, tf≤2 ns, ZO =50 Ω. At the input, 50 Ω resistor is required to terminate input generator signal. It is needed not in actual application. 2: CLx=15 pF includes instrumentation and fixture capacitance. Fig.12.4.1 DCL520C00/DCL520D00 Switching Test Circuit 1: The input pulse is supplied by a generator having the following characteristics: PRR≤50 kHz, 50 ％ duty cycle, tr≤2 ns, tf≤2 ns, ZO =50 Ω. At the input, 50 Ω resistor is required to terminate input generator signal. It is needed not in actual application. 2: CLx=15 pF includes instrumentation and fixture capacitance. Fig.12.4.2 DCL521C00/DCL521D00 Switching Test Circuit Fig.12.4.3 Switching Test Circuit and Voltage Waveforms (1) (2) (2) (1) (2) (2)

Rev.1.0 © 2021-2025 Toshiba Electronic Devices & Storage Corporation Preliminary 1: CLx=15 pF includes instrumentation and fixture capacitance. Fig.12.5.1 DCL520C00/DCL520D00 Common -Mode Transient Immunity Test Circuit 1: CLx=15 pF includes instrumentation and fixture capacitance. Fig.12.5.2 DCL521C00/DCL521D00 Common -Mode Transient Immunity Test Circuit

Rev.1.0 © 2021-2025 Toshiba Electronic Devices & Storage Corporation Preliminary 13. Characteristics Curves Note: The following characteristics curves are presented for reference only and not guaranteed by production test, unless otherwise noted. Fig.13.1 DCL520x00 IDD1 Supply CurrentーData rate Fig.13.2 DCL520xx00 IDD2 Supply CurrentーData rate Fig.13.3 DCL521x00 IDD1 Supply CurrentーData rate Fig.13.4 DCL521xx00 IDD2 Supply CurrentーData rate Fig.13.5 VOH-IOH Fig.13.6 VOL-IOL

Rev.1.0 © 2021-2025 Toshiba Electronic Devices & Storage Corporation Preliminary 14. Application Note 14-1. Eye diagram The following figure shows typical eye diagrams of DCL521xx00 at the maximum data rate of 150 Mbps with pseudorandom bit sequences (PRBS), supply voltage 3.0V for reference only. Fig.14.1 DCL5 21x00 Eye diagram at 150Mbps 14-2. PCB layout A ceramic capacitor (0.1 μ F) should be connected between pin 1 (V DD1) and pin 2 (GND 1) for VDD1 and between pin 16 (VDD2) and pin 15 (GND 2) for VDD2, and it should be the layout on the IC as close as possible (less than 10mm). Otherwise, the IC may not operate properly. Fig.14.2 Recommended Printed Circuit Board Layout

Rev.1.0 © 2021-2025 Toshiba Electronic Devices & Storage Corporation Preliminary 15. Package Information Implementation category Surface Mount Pin Number 8 Weight (g) 0.072 (Typical) Package Dimension (mm) Width × Length × Height 4.9 ×6.0×1.55 (Typical) Package Dimension (mm) Land Pattern Example (mm) [for reference only] Nominal Optional Large interval between primary-secondary side

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Product Information

DCL520C00 specifications and overview.

Summary

HIGH SPEED DUAL CHANNEL DIGITAL ISOLATORS 2025-02-10 Rev.1.0

Description

HIGH SPEED DUAL CHANNEL DIGITAL ISOLATORS 2025-02-10 Rev.1.0

Source title DCL520C00 Datasheet(PDF) - Toshiba Semiconductor

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