DCH010515S TI | Alldatasheet
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Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DCH010505D, DCH010505S DCH010512D, DCH010512S DCH010515D, DCH010515S SBVS073J –NOVEMBER 2006–REVISED MAY 2020 DCH01Series,1-W,3000-VDCIsolated,UnregulatedDC/DCConverterModules
1 Features
1• 3-kVDC Isolation (operational): 1-second test
- Continuous voltage applied across isolation barrier: 60 VDC / 42.5 VAC
- UL60950 certified product
- Industry standard footprint
- JEDEC 7-pin SIP package
- Input voltage: 5 V ±10%
- Output voltage: ±5 V, ±12 V, or ±15 V
- Supports series operation for higher output voltage
- Supports parallel operation for higher output power
- Up to 78% efficiency
2 Applications
- Point-of-use power conversion
- Ground loop elimination
- Data acquisition
- Industrial control and instrumentation
- Test equipment
3 Description
The DCH010505, DCH010512, and DCH010515 devices are a family of miniature, 1-W, 3-kV isolated DC/DC converters. Featured in an industry standard 7-pin SIP package, the DCH01 series requires minimal external components, reducing board space. The DCH01 series provides both single and dual split-supply outputs. The use of a highly integrated package design results in highly reliable products with high power densities. High performance and small size makes the DCH01 suitable for a wide range of applications including signal chain applications and ground loop elimination. WARNING: This product has operational isolation and is intended for signal isolation only. It must not be used as a part of a safety isolation circuit requiring reinforced isolation. See definitions in Feature Description. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) DCH0105xx EDJ-Single (7) 19.50 mm × 10.00 mm EDJ-Dual (7) 19.50 mm × 10.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Single-Output Block Diagram Dual-Output Block Diagram
DCH010505D, DCH010505S DCH010512D, DCH010512S DCH010515D, DCH010515S SBVS073J –NOVEMBER 2006–REVISED MAY 2020 www.ti.com Product Folder Links: DCH010505D DCH010505S DCH010512D DCH010512S DCH010515D DCH010515S Submit Documentation Feedback Copyright © 2006–2020, Texas Instruments Incorporated Table of Contents
12.2 Receiving Notification of Documentation Updates 17
13 Mechanical, Packaging, and Orderable
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision I (November 2016) to Revision J Page Changes from Revision H (January 2009) to Revision I Page
- Added ESD Ratings table, Feature Description section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
5 Device Comparison Tables
Table 1. DCH01 Products Table 2. Part Numbering Scheme
6 Pin Configuration and Functions
DCH010505D, DCH010505S DCH010512D, DCH010512S DCH010515D, DCH010515S SBVS073J –NOVEMBER 2006–REVISED MAY 2020 www.ti.com Product Folder Links: DCH010505D DCH010505S DCH010512D DCH010512S DCH010515D DCH010515S Submit Documentation Feedback Copyright © 2006–2020, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Input voltage (5-V input models) 7 V Storage temperature, Tstg –55 125 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.2 ESD Ratings
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±250
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT +VI Input voltage 4.5 5.5 V TA Operating ambient temperature –40 85 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
7.4 Thermal Information
THERMAL METRIC(1) DCH01 SERIES UNITEDJ (SIP-SINGLE) EDJ (SIP-DUAL)
7 PINS 7 PINS
RθJA Junction-to-ambient thermal resistance 66 66 °C/W ψJT Junction-to-top characterization parameter 3 3 °C/W ψJB Junction-to-board characterization parameter 66 66 °C/W
DCH010505D, DCH010505S DCH010512D, DCH010512S DCH010515D, DCH010515S www.ti.com SBVS073J –NOVEMBER 2006–REVISED MAY 2020 Product Folder Links: DCH010505D DCH010505S DCH010512D DCH010512S DCH010515D DCH010515S Submit Documentation FeedbackCopyright © 2006–2020, Texas Instruments Incorporated (1) 100% load current = 1 W / VNOM typical. (2) Load regulation = (VO at 10% load – VO at 100% load) / VO at 100% load. (3) This converter does not have continuous over-current protection.
7.5 Electrical Characteristics
At TA = 25°C and VI = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VI Input voltage All devices nominal 5 V VNOM Output voltage 100% load(1) DCH010505S 5.1 V DCH010505D ±5.2 DCH010512S 12.4 DCH010512D ±12.5 DCH010515S 15.2 DCH010515D ±15.3 Load regulation 10% to 100% load(2) DCH010505S 10% DCH010505D 9% DCH010512S 6% DCH010512D 5% DCH010515S 6% DCH010515D 5% Output ripple 100% LOAD(1) DCH010505S 35 mVPP DCH010505D 20 DCH010512S 18 DCH010512D 19 DCH010515S 31 DCH010515D 22 IQ Input current No load; 0% load DCH010505x 60 mADCH010512x 65 DCH010515x 65 Efficiency 100% load(1) DCH010505x 72% DCH010512S 74% DCH010512D 75% DCH010515S 75% DCH010515D 76% CISO Barrier capacitance DCH010505x & DCH010515x 3 pF DCH010512x 4 Output power 100% full load 1(3) W Over current duration(3) 1 sec Input voltage on VI –10% 10% Isolation voltage 100% tested for 1 second 3.5 kVDC Line regulation 1% change in VI 1% Switching frequency (fSW) 70 kHz Calculated reliability Per Telcordia SR-332, 50% stress, TA = 40°C Single output 18 FITS Dual output 22
7.6 Typical Characteristics
Figure 1. DCH010505S Efficiency Figure 2. DCH010505D Efficiency Figure 3. DCH010505S Load Regulation Figure 4. DCH010505D Load Regulation Figure 5. DCH010505S Ripple Voltage Figure 6. DCH010505D Ripple Voltage
Figure 19. Safe Operating Area (All DCH0105 Products)
8 Detailed Description
8.1 Overview
voltage represents an operational isolation to transient voltages and must not be relied upon for safety isolation.
8.1.1 Repeated High-Voltage Isolation Testing
Repeated high-voltage isolation testing can degrade the isolation capability of the DCH01.
8.2 Functional Block Diagrams
Figure 20. Single-Output Block Diagram Figure 21. Dual-Output Block Diagram
8.3 Feature Description
8.3.1 Isolation
Underwriters Laboratories (UL)™ defines several classes of isolation that are used in modern power supplies. exceed steady state 42-V peak or 60 VDC for more than 1 second.
8.3.1.1 Operation or Functional Isolation
DCH010505D, DCH010505S DCH010512D, DCH010512S DCH010515D, DCH010515S www.ti.com SBVS073J –NOVEMBER 2006–REVISED MAY 2020 Product Folder Links: DCH010505D DCH010505S DCH010512D DCH010512S DCH010515D DCH010515S Submit Documentation FeedbackCopyright © 2006–2020, Texas Instruments Incorporated Feature Description (continued)
8.3.1.2 Basic or Enhanced Isolation
Basic or enhanced isolation is defined by specified creepage and clearance limits between the primary and secondary circuits of the power supply. Basic isolation is the use of an isolation barrier in addition to the insulated wire in the construction of the transformer. Input and output circuits must also be physically separated by specified distances.
8.3.1.3 Continuous Voltage
For a device that has no specific safety agency approvals (operational isolation), the continuous voltage that can be applied across the part in normal operation is less than 42.4 VRMS or 60 VDC. Ensure that both input and output voltages maintain normal SELV limits. The isolation test voltage represents a measure of immunity to transient voltages. WARNING Do not use the device as an element of a safety isolation system when SELV is exceeded. If the device is expected to function correctly with more than 42.4 VRMS or 60 VDC applied continuously across the isolation barrier, then the circuitry on both sides of the barrier must be regarded as operating at an unsafe voltage. Further isolation or insulation systems must form a barrier between these circuits and any user- accessible circuitry according to safety standard requirements.
8.3.1.4 Isolation Voltage
Hipot test, flash-tested, withstand voltage, proof voltage, dielectric withstand voltage, and isolation test voltage are all terms that relate to the same thing: a test voltage applied for a specified time across a component designed to provide electrical isolation to verify the integrity of that isolation. TI’s DCH01 series of dc-dc converters are all 100% production tested at 3.5 kVDC for 1 second.
8.3.1.5 Repeated High-Voltage Isolation Testing
Repeated high-voltage isolation testing of a barrier component can degrade the isolation capability, depending on materials, construction, and environment. The DCH01 series of dc-dc converters have toroidal, enameled, wire isolation transformers with no additional insulation between the primary and secondary windings. While a device can be expected to withstand several times the stated test voltage, the isolation capability depends on the wire insulation. Any material, including this enamel (typically polyurethane), is susceptible to eventual chemical degradation when subject to very-high applied voltages. Therefore, strictly limit the number of high-voltage tests and repeated high-voltage isolation testing. However, if it is absolutely required, reduce the voltage by 20% from specified test voltage with a duration limit of 1 second per test.
9 Application and Implementation
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Optional Input and Output Filters
9.1.1.1 Input and Output Capacitors
ceramic capacitor reduces the output ripple or noise by 10% to 30%. input power pins, reduces reflected conducted ripple or noise by 30% to 50%. The recommended maximum capacitive load on the output of the DCH01 is 100 µF (non-ceramic). inductor to be effective in reduction of ripple and noise. pins to be effective. The ferrite bead is small (5.1 mm x 3 mm), easy to use, low cost, and has low dc resistance. Figure 22. DCH01 Series π Filter
Figure 23. DCH01 Series π Filter (5 V at 1 W)
9.1.2 Start-Up
See Figure 24 for start-up waveforms. Figure 24. Start0up Waveforms
9.1.3 Connecting the DCH01 in Series
shown in Figure 25). For example, a dual 5-V DCH01 could be connected to provide a 10-V rail. Figure 25. Connecting Dual Outputs in Series
9.1.4 Connecting the DCH01 in Parallel
Figure 26. Connecting Multiple DCH01s in Parallel
9.2 Typical Application
Figure 27. Typical Application Schematic
9.2.1 Design Requirements
Table 3. Design Example Parameters
9.2.2 Detailed Design Procedure
9.2.2.1 Input Capacitor
For any DCH01 design, select a 2.2-µF, low-ESR, ceramic input capacitor to ensure a good startup performance.
9.2.2.2 Output Capacitor
For any DCH01 design, select a 4.7-µF, low-ESR, ceramic output capacitor to reduce output ripple.
9.2.3 Application Curves
Figure 28. DCH010505S Efficiency Figure 29. DCH010505 Start-up Waveforms
10 Power Supply Recommendations
The DCH01 is a switching power supply, and as such can place high peak current demands on the input supply. connected in a star formation with the traces made as wide as possible.
11 Layout
11.1 Layout Guidelines
Carefully consider the layout of the PCB in order for the best results to be obtained. output, the positive and negative voltage outputs conduct through wide traces to minimize losses. and ensure a smooth start-up. switching waveforms of the power drive circuits.
11.2 Layout Example
Figure 30. DCH01 Single Output Layout Figure 31. DCH01 Single Output Layout
12 Device and Documentation Support
12.1 Related Links
resources, tools and software, and quick access to sample or buy. Table 4. Related Links
12.2 Receiving Notification of Documentation Updates
changed. For change details, review the revision history included in any revised document.
12.3 Support Resources
from the experts. Search existing answers or ask your own question to get the quick design help you need. not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
E2E is a trademark of Texas Instruments. Underwriters Laboratories (UL) is a trademark of UL LLC. All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com 2-Jun-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DCH010505DN7 Active Production SIP MODULE (EDJ) | 5 70 | TIW TRAY Exempt Call TI N/A for Pkg Type -40 to 85 DCH010505DN7.B Active Production SIP MODULE (EDJ) | 5 70 | TIW TRAY Exempt Call TI N/A for Pkg Type -40 to 85 DCH010505SN7 Active Production SIP MODULE (EDJ) | 4 70 | TIW TRAY Exempt Call TI N/A for Pkg Type -40 to 85 DCH010505SN7.B Active Production SIP MODULE (EDJ) | 4 70 | TIW TRAY Exempt Call TI N/A for Pkg Type -40 to 85 DCH010512DN7 Active Production SIP MODULE (EDJ) | 5 70 | TIW TRAY Exempt Call TI N/A for Pkg Type -40 to 85 DCH010512DN7.B Active Production SIP MODULE (EDJ) | 5 70 | TIW TRAY Exempt Call TI N/A for Pkg Type -40 to 85 DCH010512SN7 Active Production SIP MODULE (EDJ) | 4 70 | TIW TRAY Exempt Call TI N/A for Pkg Type -40 to 85 DCH010512SN7.B Active Production SIP MODULE (EDJ) | 4 70 | TIW TRAY Exempt Call TI N/A for Pkg Type -40 to 85 DCH010515DN7 Active Production SIP MODULE (EDJ) | 5 70 | TIW TRAY In-Work Call TI N/A for Pkg Type -40 to 85 DCH010515DN7.B Active Production SIP MODULE (EDJ) | 5 70 | TIW TRAY In-Work Call TI N/A for Pkg Type -40 to 85 DCH010515SN7 Active Production SIP MODULE (EDJ) | 4 70 | TIW TRAY Exempt Call TI N/A for Pkg Type -40 to 85 DCH010515SN7.B Active Production SIP MODULE (EDJ) | 4 70 | TIW TRAY Exempt Call TI N/A for Pkg Type -40 to 85 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Addendum-Page 1
www.ti.com 2-Jun-2025 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2
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