MAX19527EVKIT MAXIM | Alldatasheet

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Features

S_ Single_Power-Supply_Operation S_ Direct_Interface_with_the_Maxim_DCEP_Data_Board_ Using_a_QSH_Connector S_ Low-Voltage_and_Low-Power_Operation S_ On-Board_Single-Ended-to-Differential_ Transformer_Circuitry S_ Differential_or_Single-Ended_Clock_Configuration S_ On-Board_Clock-Shaping_Circuit_with_Adjustable_ Duty_Cycle S_ On-Board_or_Stand-Alone_SPI™_Interface_Control S_ DCEP_Board_Available S_ Fully_Assembled_and_Tested +Denotes lead(Pb)-free and RoHS compliant.

Ordering Information

Windows, Windows XP, and Windows Vista are registered trademarks of Microsoft Corp. SPI is a trademark of Motorola, Inc. DESIGNATION QTY DESCRIPTION B9, CMOUT, TP1–TP8 10 Red PC test points C1–C16, C58, C62–C65, C114 22 0.1FF Q10%, 10V X5R ceramic capacitors (0402) TDK C1005X5R1A104K or Murata GRM155R61A104K C41–C56 16 39pF Q5%, 50V C0G ceramic capacitors (0402) TDK C1005C0G1H390J or Murata GRM1555C1H390J C57, C77, C81 3 1FF Q10%, 6.3V X5R ceramic capacitors (0402) TDK C1005X5R0J105K or Murata GRM155R60J105K DESIGNATION QTY DESCRIPTION C59, C89, C90, C95–C98, C103–C106, C111, C112, C113, C130, C133, C135, C136, C137, C140, C141, C144, C145, C146 0.1FF Q10%, 50V X5R ceramic capacitors (0603) TDK C1608X5R1H104K or Murata GRM188R51H104K C60, C61, C66–C69 0 Not installed, ceramic capacitors (0603) C74, C78 2 220FF Q20%, 6.3V tantalum capacitors (C case) AVX TPSC227M006R0250 or KEMET T495C227K006ATE225 C75, C79 0 Not installed, tantalum capacitors (C case) PART TYPE MAX19527EVKIT+ EV Kit DCEP Data Converter Evaluation Platform

MAX19527 Evaluation KitEvaluates: MAX19527 Component List (continued) DESIGNATION QTY DESCRIPTION C76, C80, C82 3 10FF Q20%, 10V X5R ceramic capacitors (1210) TDK C3225X5R1A106M or Murata GRM32ER61A106K C83, C85, C86, C88, C131 5 10FF Q20%, 10V X5R ceramic capacitors (0805) TDK C2012X5R1A106K Murata GRM219R61A106K C84, C87, C91–C94, C99-C102, C107–C110, C115, C116 0.01FF Q10%, 50V X5R ceramic capacitors (0603) Murata GRM188R61H103K or TDK C1608X5R1H103K C132 1 1FF Q10%, 10V X5R ceramic capacitor (0603) TDK C1608X5R1A105K Murata GRM188R61A105K C134 1 0.033FF Q10%, 16V (min) X5R ceramic capacitor (0603) Murata GRM188R71E333K or TDK C1608X7R1E333K C138, C139, C142, C143 4 22pF Q5%, 50V C0G ceramic capacitors (0603) TDK C1608C0G1H220J CLK, IN1–IN8 9 SMA PC-mount connectors D1 1 Dual Schottky diode (SOT23) Central Semi CMPD6263S+ (Top Mark: D96) H1 1 120-position high-speed connector H2 1 Dual-row (2 x 20) 40-pin header J1 1 Dual-row (2 x 16) 32-pin header J2 1 2-pin header J10 1 Dual-row (2 x 5) 10-pin header JU1–JU8, JU10, JU14, JU15 11 2-pin headers JU9 1 3-pin header JU11, JU12, JU13 3 4-pin headers JU20–JU27 0 Not installed, 2-pin headers— short L101 0 Not installed, ferrite bead (0603) DESIGNATION QTY DESCRIPTION P1 1 USB type-B right-angle PC-mount receptacle R1–R32, R73–R76, R81–R84, R89, R90, R93, R95 44 100I Q1% resistors (0603) R33–R48 16 10I Q1% resistors (0402) R57–R72 16 0I ±5% resistors (0805) R77–R80, R85– R88, R91, R92, R96, R98, R99, R102, R103, R104, R105 Not installed, resistors (0603) R99, R103, and R104 are short (PC trace); all others are open R94 1 10kI potentiometer, 19-turn, 3/8in R97 1 100kI ±1% resistor (0603) R100, R101 2 49.9I ±1% resistors (0603) R130, R131 2 27I ±5% resistors (0603) R132 1 1.5kI ±5% resistor (0603) R133 1 2.2kI ±5% resistor (0603) R134, R137 2 10kI ±5% resistors (0603) R135 1 470I ±5% resistor (0603) R136 1 1.1I ±5% resistor (0603) SW1 1 Momentary 6mm pushbutton switch T1–T8 8 1:1, 800MHz RF transformers Mini-Circuits ADT1-1WT+ T9 1 1:2 RF transformer Coilcraft TTWB-2-B U1 1 Octal 12-bit 50Msps ADC (144 CTBGA) Maxim MAX19527EXE+ U2, U3 2 500mA LDO regulators (8 TDFN-EP*) Maxim MAX8902AATA+ (Top Mark: ABG) U4, U5, U6 3 Dual 2 x 2 crosspoint switches (32 TQFP) Maxim MAX9392EHJ+ U7 1 TinyLogic ULP-A inverter (6 SC70) Fairchild NC7WV04P6X (Top Mark: V07)

Evaluates: MAX19527 Component List (continued) *EP = Exposed pad. Component Suppliers Note: Indicate that you are using the MAX19527 when contacting these component suppliers. MAX19527 EV Kit Files DESIGNATION QTY DESCRIPTION U8 1 UART-to-USB converter (32 TQFP) FTDI FT232BL U9 1 93C46 type 3-wire EEPROM (8 SO) Atmel AT93C46EN-SH-B U10 1 Ultra-high-speed microcontroller (44 TQFP) Maxim DS89C450-ENL+ U11 1 Level translator (20 TSSOP) Maxim MAX3002EUP+ DESIGNATION QTY DESCRIPTION U12 1 Quad three-state driver (14 SO) Fairchild 74AC125SC U13 0 Not installed, LDO regulator (5 SC70) U14 0 Not installed, level translator (14 TSSOP) Y1 1 14.7456MHz crystal Y2 1 6MHz crystal — 15 Shunts (JU1–JU15) — 1 PCB: MAX19527 EVALUATION KIT+ SUPPLIER PHONE WEBSITE AVX Corporation 843-946-0238 www.avxcorp.com Central Semiconductor Corp. 631-435-1110 www.centralsemi.com Coilcraft, Inc. 847-639-6400 www.coilcraft.com Fairchild Semiconductor 888-522-5372 www.fairchildsemi.com KEMET Corp. 864-963-6300 www.kemet.com Mini-Circuits 718-934-4500 www.minicircuits.com Murata Electronics North America, Inc. 770-436-1300 www.murata-northamerica.com Samtec, Inc. 800-726-8329 www.samtec.com TDK Corp. 847-803-6100 www.component.tdk.com FILE DESCRIPTION INSTALL.EXE Installs the EV kit files on your computer MAX19527.EXE Application program FTD2XX.INF USB device driver file UNINST.INI Uninstalls the EV kit software USB_Driver_Help_200.PDF USB driver installation help file

MAX19527 Evaluation KitEvaluates: MAX19527 Quick Start Recommended Equipment

  • MAX19527 EV kit
  • Single 3.3V, 1A DC power supply
  • Signal generator with low phase noise and low jitter for clock input (e.g., HP 8644B)
  • Signal generator for analog signal input (e.g., HP 8644B)
  • Maxim DCEP
  • Analog bandpass filters (e.g., K&L Microwave) for input and clock signals
  • User-supplied Windows 2000, Windows XP, or Windows Vista PC with two spare USB ports Note: In the following sections, software-related items are identified by bolding. Text in bold refers to items from the EV kit software. Text in bold_ and_ underlined refers to items from the Windows operating system. Procedure The EV kit is a fully assembled and tested surface-mount board. Follow the steps below to verify board operation. Caution:_Do_not_turn_on_power_supplies_or_enable_sig- nal_generators_until_all_connections_are_completed. 1) Verify that shunts are configured in their default positions (Table 1) for proper startup operation of the EV kit software. 2) Connect the clock generator output to the clock bandpass filter input. 3) Connect the output of the clock bandpass filter to the EV kit CLK SMA connector. 4) Connect the outputs of the analog signal generators to the input of the signal bandpass filters. Keep the cable connection between the signal generators, filters, and EV kit board as short as possible for optimum dynamic performance. 5) Connect the output of the signal bandpass filters to the IN_ SMA connectors. It is recommended that a 3dB or 6dB attenuation pad be used to reduce reflections and distortion from the bandpass filter. 6) Carefully connect the boards by aligning J5 on the DCEP board to H1 on the EV kit. Gently press them together. 7) Connect the USB cable from the computer’s type-A USB port to the DCEP board’s type-B USB port. 8) Connect the 3.3V, 1A power supply to the +3.3V PCB pad. Connect the ground terminal of this supply to the corresponding GND pad. 9) Visit www.maxim-ic.com/evkitsoftware to down- load the latest version of the EV kit software and install it on your computer by running the INSTALL.EXE program. The program files are cop- ied and icons are created in the Windows Start_ |_ Programs menu. 10) Apply power to the DCEP board at J4 using the DCEP board provided supply connector. 11) Enable the 3.3V power supply. 12) Enable the signal generators. 13) Set the clock signal generator for an output amplitude of ≥ 2.7V P-P (recommended +16dBm to +19dBm for optimum AC performance for input frequencies > 25MHz) and the frequency (f CLK) as appropriate. 14) Set the analog input signal generators for an output amplitude of ≤ 1.5VP-P, and to the desired frequen- cy. 15) Verify that the signal generators are phase locked to each other. Adjust the output power level of the sig- nal generators to overcome cable, bandpass filter, and attenuation pad losses at the input. 16) Start the EV kit program by opening its icon in the Start_|_Programs menu. 17) Refer to the Data Converter Evaluation Platform (DCEP) User’s Guide for information on installing the DCEP software. 18) Start the DCEP program by opening its icon in the Start_|_Programs menu. 19) Create a new database in the DCEP by adding the device module file, MAX19527-EVK-xx.dsm. Refer to the Opening a New Database section in the Data Converter Evaluation Platform (DCEP) User’s Guide for additional information. 20) Collect data using the DCEP software.

Evaluates: MAX19527 Table_1._Jumper_Configuration_(JU1–JU15) *Default position. JUMPER SHUNT_POSITION EV_KIT_FUNCTION JU1 Not installed IN1 input network disconnected from CMOUT Installed* IN1 input network connected to CMOUT JU2 Not installed IN2 input network disconnected from CMOUT Installed* IN2 input network connected to CMOUT JU3 Not installed IN3 input network disconnected from CMOUT Installed* IN3 input network connected to CMOUT JU4 Not installed IN4 input network disconnected from CMOUT Installed* IN4 input network connected to CMOUT JU5 Not installed IN5 input network disconnected from CMOUT Installed* IN5 input network connected to CMOUT JU6 Not installed IN6 input network disconnected from CMOUT Installed* IN6 input network connected to CMOUT JU7 Not installed IN7 input network disconnected from CMOUT Installed* IN7 input network connected to CMOUT JU8 Not installed IN8 input network disconnected from CMOUT Installed* IN8 input network connected to CMOUT JU9 1-2 SHDN connected to AVDD (power-management mode to SHDN = 1) 2-3* SHDN connected to GND (power-management mode to SHDN = 0) JU10 Not installed CMOUT disconnected from input networks Installed* CMOUT connected to input networks JU11 1-2* SCLK signal supplied by the USB circuitry 1-3 Maintains the ADC register’s content 1-4 For future use Not installed SCLK signal supplied by an external source at header J10 JU12 1-2* SDIO signal supplied by the USB circuitry 1-3 Maintains the ADC register’s content 1-4 For future use Not installed SDIO signal supplied by an external source at header J10 JU13 1-2* CS signal supplied by the USB circuitry 1-3 Maintains the ADC register’s content 1-4 For future use Not installed CS signal supplied by an external source at header J10 JU14 Installed* 1.8V LDO (U2) powers the AVDD input Not installed 1.8V LDO(U2) output disconnected from the AVDD input JU15 Installed* 1.8V LDO (U3) powers the OVDD input Not installed 1.8V LDO (U3) output disconnected from the OVDD input

tab sheet provides controls for power management. the main window Reg00–Reg10 register designators. Figure 1. MAX19527 EV Kit Software (Input/Output/Clock Tab)

Evaluates: MAX19527 Input/Output/Clock Tab Output Format The Output_ Format group box contains several func- tions that format the output data. The Reverse_ Bit_ Order checkbox allows the user to change the LVDS output data to a MSB-first format and displays the bit-order configuration. The Format checkbox configures the output data format to binary or two’s complement, and displays the current data format. The Test_Data_Level drop-down list gives the user the option of configuring the ADC’s OUT1–OUT8 channels to display the normal LVDS data outputs, or setting the channel’s outputs to a static high or low state. Data Test Pattern The Test_Data drop-down list gives the user the option to choose between normal and test data modes. Select Normal from the drop-down list to operate the LVDS outputs under normal conditions. In normal operation, all GUI functions in the Data_ Test_ Pattern group box (with the exception of the Test_Data drop-down list) are disabled. When Pattern is selected, all GUI functions in the Data_Test_Pattern group box become active. The Test_ Pattern drop-down list allows the user to choose between several test patterns for data-timing alignment. Selecting Normal from the Test_Data drop- down list configures the test pattern channels according to the option selected in the Test_Data_Level drop-down list. Selecting Pattern from the Test_Data drop-down list allows the user to generate factory test and custom pat- terns at the output channels. See Table 2 for generating the IC test patterns. Three buttons (WriteCUSTOM1, WriteCUSTOM2, and WriteCUSTOM1-2) and their respective edit boxes also become active when Pattern is selected from the Test_ Data drop-down list. The buttons are available for load- ing customized 8-bit test patterns in the ADC’s 0x07, 0x08, and 0x09 registers. The registers are updated by pressing the WriteCUSTOM1, WriteCUSTOM2, or WriteCUSTOM1-2 buttons. LVDS Output Adjustments The LVDS_ Output_ Adjustments group box contains controls to set the channel OUT1–OUT8 common-mode output voltage, output current, and back termination. The CM_Adjust drop-down list sets the output driver’s common-mode voltage. The Current_Adjust drop-down list sets the output driver’s current. The Termination drop-down list sets the termination resistance. Input Common-Mode Voltage When checked, the SELF checkbox applies a common- mode voltage to the ADC’s IN_+/IN_- input pins and disables the common-mode input pins when not select- ed. The Adjust drop-down list sets the common-mode voltage according to the value selected. The selected common-mode voltage can be monitored through the CMOUT test point. When enabling SELF, verify that shunts are not installed on jumpers JU1–JU8 System Timing The Test_ FRAME_ Level drop-down list gives the user the option of configuring the ADC’s FRAME LVDS output channel to display the normal FRAME output frequency (identical to input clock frequency), or setting the FRAME output to a static high or low state. The CLK_ Controls group box contains controls for manipulating the input clock signal. The PLL_Frequency_ drop-down list programs the clock multiplier for the inter- nal PLL in order to set the sampling frequency range. Ensure that the input clock frequency, applied at the EV kit CLK SMA connector, falls between the selected minimum and maximum frequency in the drop-down list. The Output_Phase drop-down list adjusts the phase of the serial LVDS output clock (CLKOUT), relative to the output data frame. Refer to the timing diagrams in the MAX19527 IC data sheet for additional information. The Test_CLKOUT_Level drop-down list gives the user the option of configuring the ADC’s CLKOUT LVDS output channel to display the normal CLKOUT signal, or setting the output signal to a static high or low state. The 100_ Ohm_ Input_ Term checkbox switches 100I across differential clock inputs when checked. Table_2._Test_Pattern_Selection TEST_ PATTERNS OUTPUT Skew (010101010101) à repeats every frame SYNC (111111000000) à repeats every frame Custom Custom test pattern à repeats every two frames Ramp 12-bit ramp from 0 to 4095 and repeats Pseudo9 Pseudorandom data pattern (short 29 sequence) Pseudo23 Pseudorandom data pattern (long 223 sequence)

configuring the Data, FRAME, and CLKOUT test levels. label, respectively (Figure 4). Figure 2. MAX19527 EV Kit Software (Power Management Tab)

MAX19527 Evaluation KitEvaluates: MAX19527 Keyboard Navigation Press Ctrl + Tab to navigate to the tab sheets. The selected tab sheet is indicated by a dotted outline. Press the Tab key to select each GUI control. The selected control is indicated by a dotted outline. Using Shift + Tab moves the selection to the previously selected con- trol. Buttons respond to the keyboard's space bar and some controls respond to the keyboard's up and down arrow keys. Activate the program's menu bar by press- ing the F10 key and then press the letter of the desired menu item. Most menu items have one letter underlined, indicating their shortcut key. When a number is entered into the edit boxes, it can be sent to the device by pressing the Enter key. The data is also sent when Tab or Shift + Tab is pressed. Detailed Description of Hardware The MAX19527 EV kit is a fully assembled and tested circuit board that contains all the components necessary to evaluate the performance of the MAX19527 50Msps octal, 12-bit ADC. The ADC accepts differential input signals; however, on-board transformers (T1–T8) convert the single-ended signals applied to the IN1–IN8 SMA connectors to the required differential signals. The input signals of the ADC can be measured using a differential oscilloscope probe at header J1. The ADC’s digital LVDS output signals are accessible at header H2. Output drivers (U4, U5, and U6) are used for buffering the LVDS output signals when interfacing the EV kit to the DCEP board. The EV kit can be configured for communicating to the SPI interface using the on-board USB circuitry or a user- supplied external 3-wire controller using jumpers JU11 JU12, and JU13. The EV kit is designed as a six-layer PCB to optimize the performance of the ADC. Separate analog, digital, and buffer power planes minimize noise coupling between analog and digital signals. The analog and clock inputs and the LVDS outputs use 100I differential microstrip transmission lines. All singled-ended digital outputs use 50I microstrip transmission lines. The trace lengths of the 100I differential LVDS output lines are matched to within a few thousands of an inch to minimize layout- dependent output-signal skew. Power Supplies The EV kit operates from a single 3.3V DC power supply applied at the +3.3V and GND PCB pads and provides on-board regulation to power the IC analog and digital circuit blocks, and the MAX9392 LVDS buffers. The analog circuit block (AVDD) is regulated to 1.8V using the MAX8902A (U2). To power the analog circuit using the EV kit circuitry, install a shunt on jumper JU14. To disconnect the 1.8V power source, remove the shunt at JU14. See Table 3 for proper JU14 configuration. The digital circuit block (OVDD) is regulated to 1.8V using the MAX8902A (U3). To power the digital circuit using the EV kit circuitry, install a shunt on jumper JU15. To disconnect the 1.8V power source from OVDD, remove the shunt on JU15. See Table 4 for proper JU15 configuration. Jumpers JU14 and JU15 are provided to disconnect the power sources or to measure current through AVDD and OVDD, respectively. Clock Input The data converter allows either differential or single- ended signals to drive the clock inputs. The EV kit supports both methods. In single-ended operation, the clock signal is applied at the CLK SMA connector and connects to the ADC through a buffer (U7). In differential mode, an on-board transformer converts a user-supplied single-ended analog input and generates a differential analog signal, which is then applied to the ADC’s input pins. The clock signal applied to the ADC can be observed at header J2. Table_3._AVDD_Input_Power_Configuration_ (JU14) Table_4._OVDD_Input_Power_Configuration_ (JU15) *Default position. *Default position. SHUNT_POSITION AVDD_(V) Installed* 1.8V LDO (U2) powers the AVDD input Not installed Power disconnected from the AVDD input SHUNT_POSITION OVDD_(V) Installed* 1.8V LDO (U3) powers the OVDD input Not installed Power disconnected from the OVDD input

Evaluates: MAX19527 Configuring the EV Kit for Single-Ended Clock Operation To configure the EV kit for single-ended clock operation, the following modifications must be made to the clock circuit: 1) Cut the traces at locations R99, R103, and R104. 2) Install 0I resistors at locations R96, R102, and R105. 3) Install a 49.9I ±1% resistor at location R98. In single-ended clock configuration, potentiometer R94 can be utilized to control the duty cycle of the clock input signal. Measure the clock input at header J2 and adjust R94 until the desired duty cycle is achieved. Input Signals Although the ADC accepts differential analog input sig- nals, the EV kit only requires single-ended analog input signals. Insertion losses due to a series-connected filter and the interconnecting cables decrease the amount of power seen at the EV kit input. Account for these losses when setting the signal generator amplitude. On-board transformers (T1–T8) convert the single-ended analog input signals and generate the recommended differential analog signals at the ADC’s differential input pins. Jumpers JU1–JU8 are available to provide a common-mode voltage to the EV kit input circuit networks when jumper JU10 is installed. JU10 supplies the programmed common-mode voltage supplied by the ADC’s CMOUT output. Install a shunt on JU10 and the respective IN_ channel jumpers to set the input network common-mode voltage. See Table 5 for proper jumper configuration. Output Signals The ADC features eight 12-bit, serial, LVDS digital outputs (OUT_) that transmit the converted differential analog input signals (IN1–IN8). Two additional outputs (CLKOUT and FRAME) are provided for system timing. Refer to the System Timing Requirements section in the MAX19527 IC data sheet for additional information. Output Termination The ADC features trimmed, selectable internal termina- tion resistors between the positive and negative line of each output (OUT1–OUT8, CLKOUT, and FRAME). The EV kit circuit also features 100I termination resis- tors for the ADC output, located at the inputs of the MAX9392 LVDS crosspoint switches (U4, U5, and U6). MAX9392 ICs are used to buffer the ADC’s outputs when connecting the DCEP board to the EV kit, which allows monitoring of the output signals at header H2. SPI Interface Control The EV kit communicates to the ADC’s SPI interface using the on-board USB circuitry or external 3-wire signals (applied at header J10). Place shunts across pins 1-2 of jumpers JU11, JU12, and JU13 to control the SPI interface using the USB cir- cuitry. Remove shunts from JU11, JU12, and JU13 when using external 3-wire signals at header J10. See Tables 6, 7, and 8 for proper JU11, JU12, and JU13 configura- tion, respectively. Table_5._IN__Common-Mode_Input-Voltage_Configuration_(JU10,_JU1–JU8) Table_6._SCLK_Input_Configuration_(JU11) *Default position. X = Don’t care *Default position. SHUNT_POSITION INPUT_NETWORKS_(IN1–IN8) COMMON-MODE_SETTINGJU10 JU1–JU8 Installed* Installed* Input network connected to CMOUT Not installed Input common-mode voltage disconnected from CMOUT Not installed X Input networks disconnected from CMOUT SHUNT_POSITION SCLK_PIN EV_KIT_FUNCTION 1-2* Connects to SCLK EV kit level translator circuitry SCLK signal supplied by USB circuitry 1-3 Connects to ground Maintains the ADC register’s content 1-4 Connects to SCLK DCEP level translator circuitry For future use Not installed Connects to header J10-1 SCLK signal supplied by an external source at header J10

shunts across pins 1-3 of JU11, JU12, and JU13. Maxim’s DCEP is required for evaluation of this EV kit. module file can be downloaded from www.maxim-ic. Figure 5. Refer to the Opening a New Database section Guide for additional information.

Figure 5. Device Module DCEP GUI Window

MAX19527 Evaluation KitEvaluates: MAX19527 Figure 6a. MAX19527 EV Kit Schematic (Sheet 1 of 4)

Evaluates: MAX19527 Figure 6b. MAX19527 EV Kit Schematic (Sheet 2 of 4)

MAX19527 Evaluation KitEvaluates: MAX19527 Figure 6c. MAX19527 EV Kit Schematic (Sheet 3 of 4)

Evaluates: MAX19527 Figure 6d. MAX19527 EV Kit Schematic (Sheet 4 of 4)

Figure 7. MAX19527 EV Kit Component Placement Guide—Component Side

Figure 8. MAX19527 EV Kit PCB Layout—Component Side

Figure 9. MAX19527 EV Kit PCB Layout (Inner Layer 2)—Ground Planes

Figure 10. MAX19527 EV Kit PCB Layout (Inner Layer 3)—Power Planes

Figure 11. MAX19527 EV Kit PCB Layout (Inner Layer 4)—Ground Planes

Figure 12. MAX19527 EV Kit PCB Layout (Inner Layer 5)—Routing Plane

Figure 13. MAX19527 EV Kit PCB Layout—Solder Side

Figure 14. MAX19527 EV Kit PCB Component Placement Guide—Solder Side

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. © 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. MAX19527 Evaluation KitEvaluates: MAX19527

Revision History

REVISION_ DATE DESCRIPTION PAGES_ CHANGED 0 9/10 Initial release —