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- Manufacturer or author: Analog Devices, Inc.
- PDF pages: 36
Technical content
20 V, 1 A, Ultra-Low Noise, Ultra-High PSRR Linear Regulator with VIOC Control
Rev. 0 DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
FEATURES
►Ultra-low output RMS noise: 1.0 μV rms (10 Hz to 100 kHz) ►Ultra-low output noise spectral density: 3 nV/√Hz at 10 kHz ►Ultra-low 1/f noise: 8 µV p-p (0.1 Hz to 10 Hz) ►Ultra-high PSRR: 80 dB at 1 MHz ►Output current: 1 A ►Wide input voltage range: 2.2 V to 20 V ►Single capacitor improves noise and PSRR ►SET pin current: 100 µA, ±0.5% initial accuracy ►VIOC pin to manage power dissipation ►Single resistor programs output voltage ►Programmable current limit ►Low-dropout voltage: 310 mV ►Output voltage range: 0.2 V to 15 V ►Programmable power good ►Fast start-up capability ►Precision enable/UVLO ►Parallelable for lower noise and higher current ►Internal current limit with foldback ►Minimum output capacitor: 2 parallel 10 µF ceramic ►Compact, low profile, 14-lead, 4 mm × 3 mm, DFN package
APPLICATIONS
►RF power supplies: phase-locked loops, voltage-controlled oscil- lators, mixers, low-noise amplifiers, and power amplifiers ►Low-noise instrumentation ►High-speed and high-precision data converters ►Medical applications: imaging and diagnostics ►Postregulator for switching supplies TYPICAL APPLICATION Figure 1. Typical Application and spread heat on the printed circuit board (PCB). 14-lead 4 mm × 3 mm, DFN package. Figure 2. PSRR vs. Frequency
analog.com Rev. 0 | 2 of 36 SET Pin (Bypass) Capacitance: Noise, PSRR, Transient Response, and Soft-Start... 24 High-Efficiency Linear Regulator: Voltage
REVISION HISTORY
10/2022—Revision 0: Initial Version
analog.com Rev. 0 | 3 of 36
ELECTRICAL CHARACTERISTICS
TJ = −40°C to +125°C for the minimum and maximum values, TA = 25°C for the typical values, output capacitance (COUT) = two parallel 10 μF ceramic capacitors, and SET capacitance (CSET) = 4.7 μF, unless otherwise noted. Table 1. Electrical Characteristics
1.3 V ≤ VOUT ≤ 15 V
1 The EN/UV pin threshold must be met to ensure device operation. input-voltage range. If operating at the maximum input voltage, limit the output-current range. 3 OUTS ties directly to OUT. and for temperature see Figure 19, which was measured in a typical application circuit. quiescent current does include the SET and ILIM pins. as the noise of the reference current. The output noise then equals the error-amplifier noise. Use of a SET pin bypass capacitor also increases the start-up time. VIN – VOUT differential voltages. See Figure 32 for the current limit as a function of VIN – VOUT. – VOUT differentials greater than 11 V. Control (VIOC) section for further information. Set the source current of the VIOC pin between 10 µA and 300 µA.
Table 2. Absolute Maximum Ratings
1 Parasitic diodes exist internally between the VIOC, ILIM, PG, PGFB, SET,
2 SET and OUTS pins are clamped using diodes and two 25 Ω series resistors. 3 Maximum OUT-to-OUTS differential is guaranteed by design.
4 The LT3041 is tested and specified under pulse load conditions such that TJ
is guaranteed over the full –40°C to 125°C operating TJ range. ing conditions for extended periods may affect product reliability. damage may occur on devices subjected to high energy ESD. performance degradation or loss of functionality.
Figure 3. Pin Configuration Table 3. Pin Function Descriptions bypass capacitor generally suffices, applications with large load transients can require higher input capacitance to prevent input-supply droop. reverse-current flows into the LT3041, and no negative voltage appears at the load. The device protects itself and the load. Voltage Input-to-Output Control (VIOC) section for further details. drive PG more than 0.3 V less than GND during normal operation or during a fault condition. of the LT3041; therefore, do not drive ILIM more than 0.3 V less than GND during normal operation or during a fault condition. 8 PGFB Power-Good Feedback. The PG pin pulls high if PGFB increases beyond 302 mV on its rising edge, with 7 mV hysteresis on its falling edge. an external resistor connected between SET and GND. The output voltage of the LT3041 is determined by VSET = ISET × SET resistance (RSET). expense of an increased start-up time. For optimum load regulation, Kelvin connect the ground side of the SET pin resistor directly to the load. during normal operation or during a fault condition. more than 0.3 V less than GND during normal operation or during a fault condition.
less than GND during normal operation or during a fault condition. backside to the PCB ground and connect it directly to the GND pins.
analog.com Rev. 0 | 24 of 36 LT3041 to help this issue. However, the additional capacitance re- quires significantly more capacitance compared to additional input bypassing. Series resistance between the supply and the input of the LT3041 also helps stabilize the application; as little as 0.1 Ω to 0.5 Ω suffices. This impedance dampens the LC tank circuit at the expense of the dropout voltage. A better alternative is to use a higher ESR tantalum or electrolytic capacitor at the input of the LT3041 in parallel with a 10 μF ceramic capacitor. PSRR AND INPUT CAPACITANCE For applications using the LT3041 for post-regulating switching converters, placing a capacitor directly at the input of the LT3041 results in AC current (at the switching frequency) to flow near the LT3041. This relatively high-frequency switching current generates a magnetic field that couples to the output of the LT3041, degrading its effective PSRR. While highly dependent on the PCB, the switch- ing preregulator, and the input capacitance, among other factors, the PSRR degradation can be easily more than 30 dB at 1 MHz. This degradation is present even if the LT3041 is desoldered from the board because it effectively degrades the PSRR of the PCB itself. While negligible for conventional, low PSRR, LDO regulators, the ultra-high PSRR of the LT3041 requires careful attention to higher order parasitics to extract the full performance offered by the regulator. To mitigate the flow of the high-frequency switching current near the LT3041, as long as the output capacitor of the switching converter is located more than an inch away from the LT3041, remove the input capacitor of the LT3041. Magnetic coupling rapidly decreases with increasing distance. Nonetheless, if the switching preregulator is placed too far away (conservatively more than a couple inches) from the LT3041, with no input capacitor present, as with any regulator, the input of the LT3041 oscillates at the parasitic LC resonance frequency. In addition, it is generally a common (and a preferred) practice to bypass the regulator input with some capaci- tance. Therefore, this option is fairly limited in its scope and not the most palatable solution. To that end, Analog Devices recommends using the LT3041 dem- onstration board layout for achieving the best possible PSRR per- formance (see the DC3158A user guide). The LT3041 evaluation board layout uses magnetic-field cancellation techniques to prevent PSRR degradation caused by this high-frequency current flow, while using the input capacitor. FILTERING HIGH-FREQUENCY SPIKES For applications where the LT3041 is used to post regulate a switching converter, its high PSRR effectively suppresses any noise present at the switching frequency of the switching converter, typi- cally 100 kHz to 4 MHz. However, the high-frequency (hundreds of MHz) spikes, beyond the bandwidth of the LT3041, associated with the power-switch transition times of the switching converter almost directly pass through the LT3041. While the output capacitor is intended partly to absorb these spikes, its ESL limits its ability at these frequencies. A ferrite bead or even the inductance associated with a short (for example, 0.5”) PCB trace between the output of the switching converter and the input of the LT3041 can serve as an LC filter to suppress these high-frequency spikes. OUTPUT NOISE The LT3041 offers many advantages with respect to noise perform- ance. Traditional linear regulators have several sources of noise. The most critical noise sources for a traditional regulator are its voltage reference, error amplifier, noise from the resistor-divider network used for setting the output voltage, and the noise gain created by this resistor-divider. Many low-noise regulators pin out their voltage reference to allow for noise reduction by bypassing the reference voltage. Unlike most linear regulators, the LT3041 does not use a voltage reference. Instead, the LT3041 uses a 100 μA current reference. The current reference operates with a typical noise-current level of 20 pA/√Hz (6 nA rms over a 10 Hz to 100 kHz bandwidth). The resultant voltage noise equals the current noise multiplied by the resistor value, which, in turn, is RMS summed with the noise of the error amplifier and the thermal noise of the resistor, √4kTR, where k = Boltzmann’s constant (1.380649 × 10–23J/K), and T is the absolute temperature. One problem that conventional linear regulators face is that the resistor-divider setting the output voltage gains up the reference noise. In contrast, the unity-gain follower architecture of the LT3041 presents no gain from the SET pin to the output. Therefore, if a capacitor bypasses the SET pin resistor, the output noise is inde- pendent of the programmed output voltage. The resultant output noise is then set just by the noise of the error amplifier, typically 3 nV/√Hz from a 10 kHz to 1 MHz bandwidth and 1 μV rms from a 10 Hz to 100 kHz bandwidth using a 4.7 μF SET pin capacitor. Paralleling multiple LT3041 devices further reduces noise by √N, for N parallel regulators. Refer to the Figure 51, Figure 52, Figure 54, Figure 56, and Figure 58 for the noise spectral density (for the 10 Hz to 10 MHz frequency range and for the 0.1 Hz to 10 Hz 1/f noise frequency range) and RMS integrated noise over various load currents and SET pin capacitance information. SET PIN (BYPASS) CAPACITANCE: NOISE, PSRR, TRANSIENT RESPONSE, AND SOFT- START In addition to reducing output noise, using a SET pin bypass capacitor also improves PSRR and transient performance. Note that any bypass-capacitor leakage deteriorates the DC regulation of the LT3041. Capacitor leakage of even 100 nA is a 0.1% DC error. Therefore, Analog Devices recommends the use of a good quality, low-leakage ceramic capacitor. Using a SET pin bypass capacitor also soft starts the output and limits inrush current. The RC time constant, formed by the SET pin
analog.com Rev. 0 | 25 of 36 resistor and capacitor, controls the soft-start time. The ramp-up rate from 0% to 90% of nominal VOUT is the following: t S S ≈ 2 . 3 × R SE T × C S ET F as t S tar t − U p Di s abl ed (1) FAST STARTUP For ultra-low noise applications that require low 1/f noise (that is, at frequencies below 100 Hz), a larger value, SET pin capacitor is required of up to 22 μF. Typically, this larger value significantly increases the start-up time of the regulator. However, the LT3041 incorporates fast start-up circuitry that increases the SET pin cur- rent to approximately 10 mA during startup. As shown in the Figure 70, the 10 mA current source remains engaged while PGFB is less than 302 mV, unless the regulator is in current limit, dropout, thermal shutdown, or the input voltage is less than the minimum VIN. If the fast start-up capability is not used, connect PGFB to IN or to OUT for output voltages more than 302 mV, and note that this also disables the power-good functionality. EN/UV The EN/UV pin is used to put the regulator into a micropower shut- down state. The LT3041 has an accurate 1.28 V turn-on threshold on the EN/UV pin with 110 mV of hysteresis. This threshold can be used with a resistor-divider from the input supply to define an accurate UVLO threshold for the regulator. The EN/UV pin current (IEN/UV) at the threshold from Table 1 must be considered when calculating the resistor-divider network as follows: V I N U VL O = 1.28 V × 1 + R EN 2 R E N 1 + I E N / U V × R E N 2 (2) where: REN1 and REN2 are the resistors from the EN/UV pin to GND and the EN/UV pin to IN, respectively. IEN/UV can be ignored if REN1 is less than 100 kΩ. If unused, connect the EN/UV pin to IN. PROGRAMMABLE POWER GOOD As illustrated in the Figure 70, the power-good threshold is user- programmable using the ratio of two external resistors, RPG2 and RPG1: V OU T PG _ T HRES HOL D = 0.302 V × 1 + R PG 2 R PG 1 + I PG F B × R PG 2 (3) If the PGFB pin increases to more than 302 mV, the open-drain PG pin deasserts and becomes high impedance. The power-good comparator has 7 mV hysteresis and 20 μs of deglitching. The IPGFB from Table 1 must be considered when determining the resistor-divider network. The IPGFB can be ignored if RPG1 is less than 30 kΩ. If the power-good functionality is not used, float the PG pin. Note that programmable power good and fast start-up capabilities are disabled for output voltages less than 302 mV. EXTERNALLY PROGRAMMABLE CURRENT LIMIT The current-limit threshold of the ILIM pin is 300 mV. Connecting a resistor from ILIM to GND sets the maximum current flowing out of the ILIM pin, which, in turn, programs the current limit of the LT3041. With a 150 mA × kΩ programming scale factor, calculate the current limit as follows: C u rr en t L i mi t = 150 m A × kΩ R I L I M (4) For example, a 150 Ω resistor programs the current limit to 1 A and a 200 Ω resistor programs the current limit to 750 mA. For good accuracy, Kelvin connect this resistor to the GND pin of the LT3041. When IN-to-OUT differential is greater than 11 V, the foldback circuitry of the LT3041 decreases the internal current limit. As a result, internal current limit can override the externally programmed current-limit level to keep the LT3041 within its safe-operating area (SOA). See Figure 32. As shown in the Figure 70, the ILIM pin sources current proportion- al (1:500) to the output current; therefore, it also serves as a current monitoring pin with a 0 V to 300 mV range. If external current limit or current monitoring is not used, connect ILIM to GND. OUTPUT OVERSHOOT RECOVERY During a load-step change from full load to no load (or light load), the output voltage overshoots before the regulator responds to turn the power transistor off. Given that there is no load (or a light load) present at the output, it takes a long time to discharge the output capacitor. As illustrated in the Figure 70, the LT3041 incorporates an over- shoot recovery circuitry that turns on a current sink to discharge the output capacitor in the event OUTS is higher than SET. This current is typically about 5 mA. No load recovery is disabled for input voltages less than 2.5 V or output voltages less than 1.5 V. If OUTS is externally held more than SET, the current sink turns on in an attempt to restore OUTS to its programmed voltage. The current sink remains on until the external circuitry releases OUTS. DIRECT PARALLELING FOR HIGHER CURRENT Higher output current is obtained by paralleling multiple LT3041 devices. Connect all SET pins together and all IN pins together. Connect the OUT pins together using small pieces of PCB trace (used as a ballast resistor) to equalize currents in the LT3041 devices. PCB trace resistance in milliohms per inch is shown in Table 5.
analog.com Rev. 0 | 30 of 36 or if the EN/UV pin is pulled high after the input voltage is already turned on. The load-line in such cases intersects the output-current profile at two points. The regulator now has two stable operating points. With this double intersection, the input-power supply may need to be cycled down to zero and brought back up again to result in the output recover. Other LDO regulators with foldback current-limit protection (such as the LT1965 and LT1963A) also exhibit this phenomenon; therefore, it is not unique to the LT3041. PROTECTION FEATURES The LT3041 incorporates several protection features for battery- powered applications. Precision current-limit and thermal-overload protection protect the LT3041 against overload and fault conditions at the output of the device. For normal operation, do not allow the junction temperature to exceed 125°C. To protect the low-noise error amplifier of the LT3041, the SET-to- OUTS protection clamp limits the maximum voltage between SET and OUTS with a maximum DC current of 20 mA through the clamp. Therefore, for applications where SET is actively driven by a voltage source, the voltage source must be current limited to 20 mA or less. Moreover, to limit the transient current flowing through these clamps during a transient fault condition, limit the maximum value of the SET pin capacitor (CSET) to 22 μF. The LT3041 also incorporates reverse-input protection whereby the IN pin withstands reverse voltages of up to –20 V without causing any input-current flow and without developing negative voltages at the OUT pin. The regulator protects both itself and the load against batteries that are plugged in backwards. In circuits where a backup battery is required, several different input and output conditions can occur. The output voltage can be held up while the input is either pulled to GND, pulled to some intermediate voltage, or left open-circuit. In all cases, the reverse-current protec- tion circuitry prevents current flow from the output to the input. Nonetheless, due to the OUTS-to-SET clamp, unless the SET pin is floating, current can flow to GND through the SET pin resistor as well as up to 15 mA to GND through the output overshoot recovery circuitry. This current flow through the output overshoot recovery circuitry can be significantly reduced by placing a Schottky diode between the OUTS and SET pins, with its anode at the OUTS pin.
RELATED PRODUCTS
analog.com Rev. 0 | 35 of 36 Table 8. Related Products
registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Figure 98. 14-Lead, 4 mm × 3 mm, Plastic DFN 1 All models are RoHS compliant parts. Table 9. Evaluation Boards 1 The DC3158A is a RoHS compliant part.