LTM4640 AD | Alldatasheet
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Technical content
20VIN, 20A Step-Down DC-to-DC µModule Regulator Rev. 0 DOCUMENT FEEDBACK TECHNICAL SUPPORT
FEATURES
Complete Solution in <1cm2 (Single-Sided PCB) or 0.5cm2 (Dual-Sided PCB) Wide Input Voltage Range: 3.1V to 20V 0.6V to 3.3V Output Voltage Up to 20A DC output current ±1.5% Maximum Total DC Output Voltage Error Differential Remote Sensing Amplifier Fast Transient Response External Frequency Synchronization Multiphase Parallel Current Sharing with up to 4 × LTM4640s Power Good Indicator Overvoltage and Overtemperature Protection 49-Pin, 6.25mm × 6.25mm × 5.07mm, BGA package Pin compatible with LTM4626, LTM4638, and LTM4657
APPLICATIONS
Telecom, Datacom, Networking, and Industrial Equipment Medical Diagnostic Equipment Data Storage Rack Units and Cards Test and Debug Systems GENERAL DESCRIPTION The LTM4640 is a complete 20A step-down switching mode power µModule® (micromodule) regulator in a tiny 6.25mm × 6.25mm × 5.07mm BGA package. The package includes the switching controller, the power MOSFETs, an inductor, and the supporting components. Operating over an input voltage range of 3.1V to 20V, the LTM4640 supports an output voltage range of 0.6V to 3.3V, set by a single external resistor. Its high-efficiency design delivers up to 20A continuous output current. Only bulk input and output capacitors are needed. The LTM4640 supports selectable discontinuous- conduction mode (DCM) operation and output voltage tracking for supply rail sequencing. Its high switching frequency and controlled on-time valley current mode architecture enable a very fast transient response to line and load changes without sacrificing stability. Fault protection features include overvoltage and overtemperature protection. The LTM4640 is available with a RoHS-compliant terminal finish. TYPICAL APPLICATION Figure 1. 20A, 1VOUT DC-to-DC Step-Down µModule Regulator Figure 2. 1VOUT Efficiency vs. Load Current
analog.com Rev. 0 2 of 38 TABLE OF CONTENTS
analog.com Rev. 0 3 of 38
REVISION HISTORY
10/2024 - Rev. 0: Initial Release.
Table 1. Electrical Characteristics
analog.com Rev. 0 5 of 38 (TA = 25°C. VIN = 12V per the typical application shown in Figure 1, unless otherwise specified.) PARAMETER SYMBOL CONDITIONS COMMENTS MIN TYP MAX UNITS Output current limit IOUTPK VIN = 12V, VOUT = 1.5V 26 A Voltage at FB pin VFB IOUT = 0A, VOUT = 1.5V –40°C ≤ TJ ≤ 125°C 0.594 0.60 0.606 V Current at FB pin IFB 3 ±30 nA Resistor between VOSNS + and FB pins RFBHI 10 kΩ Track pin soft start pull-up current ITRACK/SS TRACK/SS = 0V 6 10 µA VIN Undervoltage lockout VIN(UVLO) VIN falling 2.45 2.6 2.75 V VIN hysteresis 350 mV Minimum on-time tON(MIN) 3 25 ns Minimum off-time tOFF(MIN) 3 50 ns PGOOD trip level VPGOOD VFB with respect to set output VFB ramping negative –12 –8 –5 % VFB with respect to set output VFB ramping positive 5 8 12 % PGOOD leakage IPGOOD VPGOOD = INTVCC, VFB = 0.6V 2 µA PGOOD voltage low VPGL IPGOOD = 1mA 0.02 0.1 V Internal VCC voltage VINTVCC VIN = 4V to 20V 3.2 3.3 3.4 V Oscillator frequency fOSC 600 kHz The LTM4640, including the E-grade and I-grade parts (see Table 14), is tested under pulsed load conditions such as that TJ ≈ TA. The LTM4640E is guaranteed to meet performance specifications over the 0°C to 125°C internal operating temperature range. Specifications over the –40°C to 125°C internal operating temperature range are assured by design, characterization, and correlation with statistical process controls. The LTM4640I is guaranteed to meet specifications over the full –40°C to 125°C internal operating temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance, and other environmental factors. 2 See Thermal Considerations and Output Current Derating for different VIN, VOUT, and TA conditions. 3 100% tested at wafer level. The LTM4640, includes overtemperature protection that is intended to protect the device during momentary overload conditions. The junction temperature exceeds 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair the device’s reliability. 5 Guaranteed by design. Validated from bench measurements.
TA = 25°C unless otherwise specified. Table 2. Absolute Maximum Ratings other environmental factors. overload conditions. The junction temperature exceeds 125°C when overtemperature protection is active. extended periods may affect product reliability.
attention to PCB thermal design is required. The following ESD information is provided for handling of ESD-sensitive devices in an ESD-protected area only. device model (CDM) per ANSI/ESDA/JEDEC JS-002. Table 3. LTM4640 ESD Ratings
Figure 3. Pinout Configuration Table 4. Pin Descriptions θJA VALUE IS OBTAINED WITH DEMO BOARD. A7 TSENSE– Low-Side of the Internal Temperature Monitor. Information section for details. connect the GND pins together.
analog.com Rev. 0 9 of 38 PIN NAME DESCRIPTION CFG 1 B3 INTVCC Internal 3.3V Regulator Output of the Switching Mode Regulator Channel. The internal power drivers and control circuits are powered by this voltage. The LTM4640 has an internal 2.2µF decoupling capacitor. No external decoupling capacitor is required. B4 RUN Run Control Input Pin. Enable regulator operation by connecting the RUN pin above 1.35V. Connecting it below 1.1V shuts down the specific regulator channel. B5 PGOOD Output Power Good Pin with Open-Drain Logic. The PGOOD pin is pulled to ground when the voltage on the FB pin is out of ±8% of the internal 0.6V reference. B7 SW Switching node of each channel that is used for testing purposes. Also, an R-C snubber network is applied to reduce or eliminate switch node ringing. Otherwise, leave it floating. See the Applications Information section for details. C1 FB The Negative Input of the Error Amplifier for the Switching Mode Regulator. This pin is internally connected to VOSNS + with a 10kΩ precision resistor. The output voltage is programmed with an additional resistor between FB and VOSNS – pins. In a PolyPhase® operation, connect the FB pins together to allow for a parallel operation. See the Applications Information section for details. C2 VOSNS Negative Input to the Differential Remote Sense Amplifier. Connect an external resistor between FB and VOSNS – pins to set the output voltage of the specific channel. See the Applications Information section for details. D1 COMPa Current control threshold and error amplifier compensation point of the switching mode regulator channel. The internal current comparator threshold is linearly proportional to this voltage. Connect the COMPa pins from different channels together for a parallel operation. The device is internally compensated. Connect to the COMPb pin to use the internal compensation. Or connect to a Type-II C-R-C network to use customized compensation. D2 MODE/CLKIN Discontinuous Mode Select Pin and External Synchronization Input to Phase Detector. Connect MODE/CLKIN to GND for discontinuous-conduction mode (DCM) operation. Floating MODE/CLKIN or connecting it to a voltage above 1V selects forced continuous mode (FCM). Furthermore, connecting MODE/CLKIN to an external clock synchronizes the system clock to the external clock and puts the part in FCM. See the Applications Information section for details. D3–D4, E3– E4, F4, G4 VIN Power input pins connect to the drain of the internal top MOSFET, and the signal VIN to the internal 3.3V regulator for the control circuitry for each switching mode regulator channel. Apply input voltages between these pins and GND pins. Recommend placing input decoupling capacitance directly between each of the VIN pins and the GND pins. E1 FREQ Switching Frequency Program Pin. The frequency is set internally to 600kHz. An external resistor is placed from this pin to GND to increase frequency, or from this pin to INTVCC to reduce frequency. See the Applications Information section for frequency adjustment. E2 TRACK/SS Output Tracking and Soft Start Pin of the Switching Mode Regulator. The TRACK/SS pin allows the user to control the rise time of the output voltage. Putting a voltage below 0.6V on this pin bypasses the internal reference input to the error amplifier, instead it servos the FB pin to the TRACK voltage. Above 0.6V, the tracking function
Table 5. LTM4640 Component BGA Pinout a soft start function. See the Applications Information section for details. compensation in the majority of applications. peak amplitude is INTVCC to GND. See the Applications Information section for details.
Figure 16. Steady-State Output Voltage Ripple typical application schematic is shown in Figure 37. startup when the TRACK pin is ramping up to 0.6V. normal operation. The regulator does not execute its soft start function when exiting an overvoltage condition.
Information section for details. Figure 17. LTM4640 Simplified Block Diagram Table 6. Decoupling Requirements because of the variation of the actual capacitance over bias voltage and temperature.
specific external capacitor requirements for a particular application. imposes a maximum duty cycle which is calculated with Equation 1. where tOFF(MIN) is the minimum off-time, typically 50ns for LTM4640, and fSW (Hz) is the switching frequency. Output Current Derating section. – pin programs the output voltage given by Equation 3. Table 7 summarizes the RFB values required for some of the typical output voltage applications. Table 7. RFB Resistor Table vs. Various Output Voltages for an example of a parallel operation.
Figure 18. 2-Phase Parallel Configurations capacitance. The bulk capacitor is an aluminum electrolytic capacitor or polymer capacitor. where η% is the estimated efficiency of the power μModule regulator. analysis for further optimization. thus skipping cycles. The inductor current does not reverse in this mode.
analog.com Rev. 0 17 of 38 Forced Continuous Mode In applications where fixed frequency operation is more critical than low current efficiency, and where the lowest output ripple is desired, FCM operation should be used. FCM operation can be enabled by connecting the MODE/CLKIN pin to INTVCC. In this mode, the inductor current can reverse during low output loads, the COMP voltage is in control of the current comparator threshold throughout, and the top MOSFET always turns on with each oscillator pulse. During startup, FCM is disabled, and the inductor current is prevented from reversing until the LTM4640’s output voltage is in regulation. Operating Frequency The operating frequency of the LTM4640 is optimized to achieve the compact package size and the minimum output ripple voltage while keeping high efficiency. The default operating frequency is 600kHz. In most applications, no additional frequency adjustment is required. If an operating frequency other than 600kHz is required by the application, the operating frequency is increased by adding a resistor, RFSET, between the FREQ pin and GND, as shown in Figure 38, or is decreased by adding a resistor between the FREQ pin and INTVCC. The RFSET resistance value is calculated with Equation 5. 𝑅𝐹𝑆𝐸𝑇 = 1.67×1011Ω×𝐻𝑧 𝑓−600𝑘𝐻𝑧 (𝑓>600𝑘𝐻𝑧) 2.72×1011Ω×𝐻𝑧 600𝑘𝐻𝑧−𝑓 (𝑓<600𝑘𝐻𝑧) (5) The programmable operating frequency range is from 400kHz to 3MHz. Frequency Synchronization and Clock In The LTM4640 has a phase-locked loop comprised of an internal voltage-controlled oscillator and a phase detector. This allows the internal top MOSFET turn-on to be locked to the rising edge of the external clock. The external clock frequency range must be within ±30% around the operating frequency set by the RFSET resistor. A pulse detection circuit detects a clock on the CLKIN pin to turn on the phase-locked loop. The pulse width of the clock must be at least 100ns. The clock’s high level must be above 1V and the clock’s low level below 0.3V. During the startup of the regulator, the phase-locked loop function is disabled. Multiphase Operation For output loads that demand more than 20A of current, multiple LTM4640s are paralleled to run out-of-phase to provide more output current without increasing input and output voltage ripples. The CLKOUT signal is connected to the MODE/CLKIN pin of the following LTM4640 stage to line up both the frequency and the phase of the entire system. Connecting the PHMODE pin to INTVCC, GND, or FLOAT generates a phase difference (between CLKIN and CLKOUT) of 180°, 120°, or 90°, respectively, which corresponds to 2-phase, 3- phase, or 4-phase operation. Figure 39 shows a 2-phase design. For a 3-phase or a 4-phase operation to achieve the best performance, it is recommended to use an external clock integrated circuit (IC) to provide the desired phase difference for each LTM4640. An optional low-pass filter is added to each external clock signal before it is fed to the LTM4640. Figure 19 shows a 4-phase design in such a way. Interleaving among more than four phases is not recommended.
subordinate regulator, as shown in Figure 22. rate (SR) is given by Equation 8. RTR(TOP) = 10kΩ and RTR(BOT) = 6.65kΩ are a good combination for the ratio metric tracking. 10kΩ is used, then a 5kΩ is used to reduce the TRACK/SS pin offset to a negligible value. slew rate (MR) is the same as the subordinate device output slew rate (SR), waveform as shown in Figure 23. Figure 23. Output Coincident Tracking Waveform
analog.com Rev. 0 21 of 38 From Equation 8, we could easily find that, in coincident tracking, the subordinate regulator’s TRACK/SS pin resistor divider is always the same as its feedback divider (Equation 9). 𝑅𝐹𝐵(𝑆𝑈𝐵) 𝑅𝐹𝐵(𝑆𝑈𝐵) +10𝑘Ω= 𝑅𝑇𝑅(𝐵𝑂𝑇) 𝑅𝑇𝑅(𝑇𝑂𝑃) +𝑅𝑇𝑅(𝐵𝑂𝑇) (9) For example, RTR(TOP) = 10kΩ and RTR(BOT) = 10kΩ is a good combination for coincident tracking for a VOUT(MAIN) = 1.5V and VOUT(SUB) = 1.2V application. Power Good The PGOOD pin is an open-drain pin that can be used to monitor valid output voltage regulation. This pin is pulled low when the output voltage exceeds a ±8% window around the regulation point. To prevent unwanted PGOOD glitches during transients or dynamic VOUT changes, the LTM4640’s PGOOD falling edge includes a blanking delay of approximately 25 switching cycles. RUN Enable Pulling the RUN pin to ground forces the LTM4640 into the shutdown state, turning off both power MOSFETs and most of its internal control circuitry. Bringing the RUN pin above 0.6V turns on the internal reference only, while keeping the power MOSFETs off. Increasing the RUN pin voltage above 1.35V turns on the entire device. Prebiased Output Startup There may be situations that require the power supply to start up with some charge on the output capacitors. The LTM4640 can safely power up into a prebiased output without discharging it. The LTM4640 accomplishes this by forcing discontinuous-conduction mode (DCM) operation until the TRACK/SS pin voltage reaches 0.6V reference voltage. This prevents the bottom FET from turning on during the prebiased output startup, which would discharge the output. SW Pins and Optional Snubber Circuit The SW pin is generally for testing purposes. The SW pin can also be used to dampen out switch node ringing caused by the LC parasitic in the switched current path using a series R-C snubber circuit. The resistor dampens the resonance, and the capacitor is chosen to only affect the high-frequency ringing across the resistor. The snubber circuit is optional, as the LTM4640 can operate well with proper PCB layout. If needed, below are suggestions regarding snubber circuit design. If the stray inductance or capacitance can be measured or approximated, then it is possible to use an analytical technique to select the snubber values. The inductance is usually easier to predict. It combines the power path board inductance in combination with the MOSFET interconnect bond wire inductance. First, the SW pin is monitored with a wide bandwidth scope with a high frequency scope probe. The ring frequency is measured for its value. The impedance ZL is calculated with Equation 10. 𝑍𝐿 =2π×f×L (10) where f is the resonant frequency of the ring, and L is the total parasitic inductance in the switch path. If a resistor is selected that is equal to ZL, then the ringing should be dampened. The snubber capacitor value is chosen so that its impedance is equal to the resistor at the ring frequency. This is calculated with Equation 11.
analog.com Rev. 0 22 of 38 𝑍𝐶 = 1 2π×f×C (11) These values are a good place to start. Modifications to these components should be made to attenuate the ringing with the least amount of power loss. Stability Compensation The LTM4640 has already been internally compensated for all output voltages and capacitor combinations, including all ceramic capacitor applications when COMPb is connected to COMPa. Note that a 22pF to 100pF feedforward capacitor (CFF) is required for connecting from VOUT to VFB pins for all ceramic output capacitor applications to achieve high bandwidth control loop compensation with enough phase margin. Table 12 provides most of the application requirements using optimized internal compensation. For specific optimized requirements, disconnect COMPb from COMPa and apply a Type II compensation network from COMPa to GND to achieve external compensation. Choose the components of the Type-II network dependent on the desired output response for line and load variations as well as loop stability parameters—phase margin and gain margin of the feedback loop. In general, selecting a low capacitance and a high resistance for the Type-II network at COMPa pin leads to a fast transient response but may adversely affect the loop stability parameters. The LTpowerCAD design tool is available to download online to perform specific control loop optimization and to analyze the control stability and load transient performance. Differential Remote Sense Amplifier An accurate differential remote sense amplifier is built into the LTM4640 to sense output voltages accurately at the remote load points. This is especially true for high current loads. It is important that the VOSNS+ and VOSNS– pins are connected properly at the remote output sense point, and that the feedback resistor, RFB, is connected between the VFB and VOSNS– pins (see Figure 37). In a multiphase single output application, only one set of differential sensing amplifiers and one set of feedback resistors is required, while connecting RUN, TRACK/SS, VOUT, VFB, and COMPa of different channels together. See Figure 39 for an example of a paralleling application. Input Overvoltage Protection To protect the internal power MOSFET devices against transient voltage spikes, the LTM4640 constantly monitors the VIN pin for an overvoltage condition. When the VIN rises above 24.5V, the regulator suspends operation by shutting off both power MOSFETs on the corresponding channel. Once VIN drops below 21.5V, the regulator immediately resumes normal operation. The regulator executes its soft start function when exiting an overvoltage condition. Output Current Limit Under overload or short-circuit conditions, the output current is no higher than the specified output current limit. The LTM4640 may still be switching, but the output voltage regulation is not guaranteed, which is dependent on the load resistance under such conditions. Continuous operation under such conditions is not recommended, as this may cause the maximum operating junction temperature to be exceeded, which may impair the device’s reliability.
temperature described by the classic diode Equation 12. current) is a process-dependent parameter. The VT is broken out with Equation 13. constants into one term (see Equation 14). always greater than IS, leaves us with the results given in Equation 15. approximate –2mV/°C temperature relationship as shown in Figure 24. Figure 24. Diode Voltage VD vs. Temperature T(°C)
analog.com Rev. 0 24 of 38 To obtain a linear voltage proportional to the temperature, we cancel the IS variable in the natural logarithm term to remove the IS dependency from Equation 15. This is accomplished by measuring the diode voltage at two currents: I1 and I2, where I1 = 10 × I2, and subtracting is given in Equation 16. ∆𝑉𝐷 =𝑇(𝐾𝐸𝐿𝑉𝐼𝑁) ×𝐾𝐷 ×𝑙𝑛𝐼1 𝐼𝑆 −𝑇(𝐾𝐸𝐿𝑉𝐼𝑁) ×𝐾𝐷 ×𝑙𝑛𝐼2 𝐼𝑆 (16) Combining like terms, and then simplifying the natural log terms yields Equation 17. ∆𝑉𝐷 =𝑇(𝐾𝐸𝐿𝑉𝐼𝑁) ×𝐾𝐷 ×𝑙𝑛(10) (17) and redefining the constant is given in Equation 18. 𝐾′𝐷 =𝐾𝐷 ×𝑙𝑛(10)=198𝜇𝑉 𝐾 (18) yields Equation 19. ∆𝑉𝐷 =𝐾′𝐷 ×𝑇(𝐾𝐸𝐿𝑉𝐼𝑁) (19) Equation 20 solves for temperature. 𝑇(𝐾𝐸𝐿𝑉𝐼𝑁) =∆𝑉𝐷 𝐾′𝐷 𝑇(°𝐶𝐸𝐿𝑆𝐼𝑈𝑆) =𝑇(𝐾𝐸𝐿𝑉𝐼𝑁) −273.15 (20) Where 300.15K = 27°C is an example. If we take the difference in voltage across the diode measured at two currents with a ratio of 10, the resulting voltage is 198μV per Kelvin of the junction with a zero intercept at 0 Kelvin. The internal diode-connected NPN transistor between TSENSE+ and TSENSE– pins is used to monitor the internal temperature of the LTM4640. Thermal Considerations and Output Current Derating The thermal resistances reported in the Pin Configurations and Function Descriptions section are consistent with those parameters defined by JESD5112 and are intended for use with finite element analysis (FEA) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation performed on a µModule package mounted to a hardware test board. The motivation for providing these thermal coefficients is found in JESD5112 (Guidelines for Reporting and Using Electronic Package Thermal Information). Many designers may use laboratory equipment and a test vehicle, such as an evaluation (demo) board, to anticipate the µModule regulator’s thermal performance in their application at various electrical and environmental operating conditions to complement any FEA activities. Without FEA software, the thermal resistances reported in the Pin Configurations and Function Descriptions section are, in and of themselves, not relevant to providing guidance on thermal performance; instead, the derating curves provided in Figure 29 through Figure 34 can be used in a manner that yields insight and guidance about the user’s application and can be adapted to correlate thermal performance to the user’s application.
JESD5112; these coefficients are quoted or paraphrased as follows.
- θJA, the thermal resistance from junction to ambient, is the natural convection junction-to-ambient air
mounted to a 95mm × 76mm PCB with four layers.
- θJCbottom, the thermal resistance from the junction to the bottom of the product case, is determined with all
but the test conditions don’t generally match the user’s application.
- θJCtop, the thermal resistance from the junction to the top of the product case, is determined with nearly all
μModule regulator, whereas green resistances are external to the µModule package. Figure 25. Graphical Representation of JESD51–12 Thermal Coefficients the absence of a heat sink and airflow, most of the heat flow is into the board.
analog.com Rev. 0 26 of 38 simplicity—but also, not ignoring practical realities—an approach has been taken by using FEA software modeling and laboratory testing in a controlled environment chamber to reasonably define and correlate the thermal resistance values supplied in this data sheet: (1) Initially, FEA software accurately builds the mechanical geometry of the LTM4640 and the specified PCB with all of the correct material coefficients and accurate power loss source definitions; (2) this model simulates a software-defined JEDEC environment consistent with JSED5112 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the JEDEC- defined thermal resistance values; (3) the model and FEA software evaluates the LTM4640 with heat sink and airflow; (4) having solved for and analyzed these thermal resistance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a controlled environment chamber while operating the device at the same power loss as the one which was simulated. An outcome of this process and due diligence yields the set of derating curves shown in Figure 29 through Figure 34. After these laboratory tests have been performed and correlated to the LTM4640, then the θJB and θBA are summed together to provide a value that should closely equal the θJA value because approximately 100% of power loss flows from the junction through the board into ambient with no airflow or top mounted heat sink. The 1V, 1.5V, and 3.3V power loss curves in Figure 26 through Figure 28 can be used in coordination with the load current derating curves in Figure 29 through Figure 34 for calculating an approximate θJA thermal resistance for the LTM4640 with various airflow conditions. The power loss curves are taken at room temperature and are increased with a multiplicative factor according to the ambient temperature. This approximate factor is 1.2 for 120°C, at junction temperature. The maximum load current is achievable while increasing ambient temperature if the junction temperature is less than 120°C, which is a 5°C guard band from a maximum junction temperature of 125°C. When the ambient temperature reaches a point where the junction temperature is 120°C, then the load current is lowered to maintain the junction at 120°C, while increasing ambient temperature up to 120°C. The derating curves are plotted with the output current starting at 20A and the ambient temperature at 30°C. The output voltages are 1V, 1.5V, and 3.3V. These are chosen to include the lower and higher output voltage ranges to correlate the thermal resistance. Thermal models are derived from several temperature measurements in a controlled temperature chamber and thermal modeling analysis. The junction temperatures are monitored while ambient temperature is increased with and without airflow. The power loss increase with ambient temperature change is factored into the derating curves. The junctions are maintained at 120°C maximum while lowering output current or power with increasing ambient temperature. The decreased output current decreases the internal µModule loss as the ambient temperature is increased. The monitored junction temperature of 120°C minus the ambient operating temperature specifies how much µModule temperature rise can be allowed. For example, in Figure 30, the load current is derated to ~10A at ~95°C with no airflow or heat sink, and the power loss for the 12V to 1V at 10A output is about 1.8W. The 1.8W loss is calculated with the ~1.5W room temperature loss from the 12V to 1V power loss curve at 10A, and the 1.2 multiplying factor at 120°C junction temperature. If the 95°C ambient temperature is subtracted from the 120°C junction temperature, then the difference of 25°C divided by 1.8W equals a 13.9°C/W θJA thermal resistance. Table 9 specifies a 14°C/W value, which is very close. Table 10 and Table 11 provide equivalent thermal resistances for 1.5V and 3.3V outputs with and without airflow and heat sinking. The derived thermal resistances in Table 9, Table 10, and Table 11 for the various conditions can be multiplied by the calculated power loss as a function of ambient temperature to derive temperature rise above ambient, thus maximum junction temperature. Room temperature power loss can be derived from the efficiency curves in the Typical Performance Characteristics section and adjusted with the previous ambient temperature multiplicative factors. The printed circuit board is a 1.6mm thick 6-layer board with two- ounce copper for all six layers. The PCB dimensions are 90mm × 90mm.
Table 12. Output Voltage Response vs. Component Matrix (See Figure 37) fuse with a rating twice the maximum input current must be provided to protect the unit from catastrophic failure. The device does support thermal shutdown.
analog.com Rev. 0 34 of 38 Related Parts Table 13.Related Parts PART NUMBER DESCRIPTION COMMENT LTM4657 8A µModule regulator, pin compatible with LTM4626, LTM4638 and LTM4640 3.1V ≤ VIN ≤ 20V, 0.6V ≤ VOUT ≤ 5.5V, 6.25mm × 6.25mm × 3.87mm BGA LTM4626 12A µModule regulator, pin compatible with LTM4657, LTM4638 and LTM4640 3.1V ≤ VIN ≤ 20V, 0.6V ≤ VOUT ≤ 5.5V, 6.25mm × 6.25mm × 3.87mm BGA LTM4638 15A µModule regulator, pin compatible with LTM4657, LTM4626 and LTM4640 3.1V ≤ VIN ≤ 20V, 0.6V ≤ VOUT ≤ 5.5V, 6.25mm × 6.25mm × 5.02mm BGA LTM4702 10A Silent Switcher 3 µModule regulator, pin compatible with LTM4703 and LTM4707 3V ≤ VIN ≤ 16V, 0.3V ≤ VOUT ≤ 6V, 6.25mm × 6.25mm × 5.07mm BGA LTM4703 12A Silent Switcher 3 µModule regulator, pin compatible with LTM4702 and LTM4707 3V ≤ VIN ≤ 16V, 0.3V ≤ VOUT ≤ 6V, 6.25mm × 6.25mm × 5.07mm BGA LTM4707 15A Silent Switcher 3 µModule regulator, pin compatible with LTM4702 and LTM4703 3V ≤ VIN ≤ 16V, 0.3V ≤ VOUT ≤ 6V, 6.25mm × 6.25mm × 5.07mm BGA LTM4622 Dual 2.5A or single 5A µModule regulator 3.6V ≤ VIN ≤ 20V, 0.6V ≤ VOUT ≤ 5.5V, 6.25mm × 6.25mm × 1.82mm (LGA) or 2.42mm (BGA) LTM4705 Dual 5A or single 10A µModule regulator 3.1V ≤ VIN ≤ 20V, 0.6V ≤ VOUT ≤ 5.5V, 6.25mm × 7.5mm × 3.22mm BGA LTM4646 Dual 10A or single 20A µModule regulator 4.5V ≤ VIN ≤ 20V, 0.6V ≤ VOUT ≤ 5.5V, 11.25mm × 15mm × 5.01mm BGA LTM4630/ LTM4630A Dual 18A or single 36A µModule regulator, pin compatible with LTM4650 4.5V ≤ VIN ≤ 15V (18V for LTM4630A), 0.6V ≤ VOUT ≤ 1.8V (8V for LTM4630A), 16mm × 16mm × 4.41mm (LGA) or 5.01mm (BGA) LTM4650/ LTM4650A Dual 25A or single 50A µModule regulator, pin compatible with LTM4630 4.5V ≤ VIN ≤ 15V (16V for LTM4650A), 0.6V ≤ VOUT ≤ 1.8V (5.5V for LTM4650A), 16mm × 16mm × 4.41mm (LGA) or 5.01mm (BGA) LTM4668/ LTM4668A LTM4668A), 6.25mm × 6.25mm × 2.1mm BGA LTM4643 Configurable quad 3A µModule regulator, Pin compatible with LTM4644 4V ≤ VIN ≤ 20V, 0.6V ≤ VOUT ≤ 3.3V, 9mm × 15mm × 1.82mm LGA, 2.42mm BGA LTM4644 Configurable quad 4A µModule regulator, pin compatible with LTM4643 4V ≤ VIN ≤ 14V, 0.6V ≤ VOUT ≤ 5.5V, 9mm × 15mm × 5.01mm BGA
Figure 41. 49-Pin, 6.25mm × 6.25mm × 5.07mm, BGA
J-STD-609. The temperature grade is identified by a label on the shipping container. Recommended LGA and BGA PCB assembly and manufacturing procedures. LGA and BGA package and tray drawings. Table 15. Evaluation Boards DC3107A 20VIN, 20A Step-Down DC-to-DC µModule Regulator evaluation (demo) board.
Table 16. Design Resources Search using the Quick Power Search parametric table.
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