LTC7890 AD | Alldatasheet
Document overview
- Manufacturer or author: Analog Devices, Inc.
- PDF pages: 41
Technical content
analog.com Rev. 0 | 2 of 41 Power and Bias Supplies (VIN, EXTVCC, Dead Time Control (DTCA and DTCB Pins).... 17 Startup and Shutdown (RUNx and Light Load Operation: Burst Mode Operation, Pulse Skipping Mode, or Frequency Selection, Spread Spectrum, and Phase-Locked Loop (FREQ and Dead Time Control (DTCA and DTCB Pins).... 23 Fault Conditions: Current Limit and Foldback.. 29 Fault Conditions: Overtemperature Phase-Locked Loop and Frequency
REVISION HISTORY
4/2023—Revision 0: Initial Version
analog.com Rev. 0 | 3 of 41
ELECTRICAL CHARACTERISTICS
TJ = −40°C to +150°C for the minimum and maximum values, TA = 25°C for the typical values, VIN = 12 V, RUN1 and RUN2 = 12 V, VPRG1 = floating, EXTVCC = 0 V, DRVSET = 0 V, DRVUV = 0 V, TGUP1 = TGDN1 = TGxx1, BGUP1 = BGDN1 = BGxx1, TGUP2 = TGDN2 = TGxx2, BGUP2 = BGDN2 = BGxx2, and DTCA and DTCB = 0 V, unless otherwise noted. Table 1. Electrical Characteristics
Table 1. Electrical Characteristics (Continued)
1 This specification is not tested in production. 2 The LTC7890 is tested in a feedback loop that servos ITHx voltage (VITHx) to a specified voltage and measures the resultant feedback voltage (VFBx). 3 SENSE1– bias current is reflected to the input supply by the formula IVIN = ISENSE1– × VOUT1/(VIN × η), where η is the efficiency. 4 Rise and fall times are measured using 10% and 90% levels. Delay times are measured using 50% levels.
Table 2. Absolute Maximum Ratings ed to capacitive loads only. Otherwise, permanent damage can occur.
2 The LTC7890 is specified over the –40°C to 150°C operating junction temper-
layout, rated package thermal impedance, and other environmental factors. ing conditions for extended periods may affect product reliability. damage may occur on devices subjected to high energy ESD. performance degradation or loss of functionality.
Figure 3. Pin Configuration Table 3. Pin Function Descriptions GND. Minimize the capacitance on FREQ. inductor current operation. Tying MODE to INTVCC through a 100 kΩ resistor selects the pulse skipping operation. input to INTVCC to enable spread spectrum dithering of the oscillator, or to GND to disable spread spectrum dithering. down the LTC7890, reducing IQ to approximately 1 µA. Tie the RUN1 pin to VIN for always on operation. down the LTC7890, reducing IQ to approximately 1 µA. Tie the RUN2 pin to VIN for always on operation. 6 GND Ground. The GND pin and the exposed pad must be soldered to PCB ground for rated electrical and thermal performance. thresholds, as listed in Table 1. when SENSE2– is greater than INTVCC. SENSE2+ pins, in conjunction with the current sense resistor (RSENSE), set the current trip threshold.
Table 3. Pin Function Descriptions (Continued) another voltage supply connected to TRACK/SS2 allows the output to track the other supply during startup. one of three different levels (25 mV, 75 mV, or 50 mV, respectively). 17 PGOOD2 Power-Good Open-Drain Logic Output for Channel 2. PGOOD2 is pulled to GND when the voltage on VFB2 is not within ±10% of its set point. 20 SW2 Switch Node Connection to Inductor for Channel 2. falling slew rate. BGDN2 also serves as the Kelvin sense of the bottom FET gate during turn on. slew rate. BGUP2 also serves as the Kelvin sense of the bottom FET gate during turn off. a 4.7 µF to 10 µF ceramic or other low equivalent series resistance (ESR) capacitor. Supplies (VIN, EXTVCC, DRVCC, and INTVCC) section and INTVCC Regulators (OPTI-DRIVE) section. Do not exceed 30 V on EXTVCC. Connect EXTVCC to GND if the EXTVCC LDO regulator is not used. 27 VIN Main Supply Pin. A bypass capacitor must be tied between VIN and GND. slew rate. BGUP1 also serves as the Kelvin sense of the bottom FET gate during turn off. falling slew rate. BGDN1 also serves as the Kelvin sense of the bottom FET gate during turn on. 31 SW1 Switch Node Connection to Inductor for Channel 1. 34 PGOOD1 Power-Good Open-Drain Logic Output for Channel 1. PGOOD1 is pulled to GND when the voltage on VFB1 is not within ±10% of its set point.
V. Connect VPRG1 to INTVCC or GND to program the output to 12 V or 5 V, respectively, through an internal resistor divider on VFB1. another voltage supply connected to TRACK/SS1 allows the output to track the other supply during startup. external resistive divider across the output. If VPRG1 is tied to GND or INTVCC, VFB1 receives the remotely sensed output voltage directly. SENSE1+ pins, in conjunction with RSENSE, set the current trip threshold. further reducing the input referred IQ. 41 GND (EPAD) Ground (Exposed Pad). The exposed pad must be soldered to PCB ground for rated electrical and thermal performance.
Figure 34. DTCB = 100 kΩ Dead Time Delay Histogram
Figure 35. Functional Diagram comparator IR, or the beginning of the next clock cycle.
analog.com Rev. 0 | 17 of 41 available from both the VIN pin and the EXTVCC pin to provide power to INTVCC, which can be programmed from 4 V to 5.5 V through control of the DRVSET pin. When the EXTVCC pin is tied to a voltage less than its switchover voltage, the VIN LDO regulator supplies power to INTVCC. If EXTVCC is taken more than its switchover voltage, the VIN LDO regulator turns off and the EXTVCC LDO regulator turns on. When enabled, the EXTVCC LDO regulator supplies power to INTVCC. Using the EXTVCC pin allows the INTVCC power to be derived from a high efficiency external source, such as the LTC7890 switching regulator output. HIGH-SIDE BOOTSTRAP CAPACITOR Each top FET driver is biased from the floating bootstrap capacitor (CB), which normally recharges through an internal switch between BOOSTx and DRVCC whenever the bottom FET turns on. The inter- nal switch is high impedance whenever the bottom FET is off, which prevents the bootstrap capacitor from overcharging whenever SWx rings less than GND during the dead times. If the input voltage decreases to a voltage close to its output, the loop may enter dropout and attempt to turn on the top FET continu- ously. The dropout detector detects this event and forces the top FET off and the bottom FET on for a short time every tenth cycle to allow CBx to recharge, resulting in a 99% duty cycle at 370 kHz operation and approximately 98% duty cycle at 2 MHz operation. If the bootstrap capacitor voltage falls to approximately less than 75% of the INTVCC voltage, the boost refresh pulses increase to every fourth cycle to deliver more charge to CBx, resulting in slightly lower duty cycles in dropout. DEAD TIME CONTROL (DTCA AND DTCB PINS) The LTC7890 dead time delays can be programmed from near zero to 60 ns by configuring the DTCA and DTCB pins. The DTCA pin programs the dead time associated with the bottom FET turning off and the top FET turning on. The DTCB pin programs the dead time associated with top FET turning off and the bottom FET turning on. In this section, TGx represents the voltage sensed at the top FET gate and BGx represents the voltage sensed at the bottom FET gate. Tying the DTCA pin to GND programs adaptive dead time control, which means the driver logic waits for the bottom FET to turn off before turning on the top FET. Adaptive dead time control results in dead times of approximately 20 ns between BGx falling to TGx rising. Tying the DTCB pin to GND programs adaptive dead time control, which means the driver logic waits for the top FET to turn off before turning on the bottom FET. Adaptive dead time control results in dead times of approximately 20 ns between TGx falling to BGx rising. Tying the DTCA pin to INTVCC programs smart near zero dead time control, which reduces the delay between the rising edge of SWx to the falling edge of BGx to near zero. Placing a resistor between the DTCA pin and GND adds additional delay between SWx rising and BGx falling from 7 ns to 60 ns. See the Dead Time Control (DTCA and DTCB Pins) section on dead time control for more information. Tying the DTCB pin to INTVCC programs smart near zero dead time control, which reduces the delay between the falling edge of SWx to the rising edge of BGx to near zero. Placing a resistor between the DTCB pin and GND adds additional delay between SWx falling and BGx rising from 7 ns to 60 ns. See the Dead Time Control (DTCA and DTCB Pins) section on dead time control for more information. STARTUP AND SHUTDOWN (RUNX AND TRACK/SSX PINS) The two channels of the LTC7890 can be independently shut down using the RUN1 and RUN2 pins. Pulling a RUNx pin to less than 1.08 V shuts down the main control loop for that channel. Pulling both RUNx pins to less than 0.7 V disables both controllers and most internal circuits, including the INTVCC LDO regulators. In this shutdown state, the LTC7890 draws only 1 μA of IB. The RUNx pin must be externally pulled up or driven directly by logic. Each RUNx pin can tolerate up to 100 V (absolute maximum). Therefore, the RUNx pin can be tied to VIN in always on applica- tions where one or both controllers are enabled continuously and never shut down. Additionally, a resistive divider from VIN to a RUNx pin can be used to set a precise input UVLO so that the power supply does not operate to less than the user adjustable level. The startup of each channel's VOUTx is controlled by the voltage on the corresponding TRACK/SSx pin. When the voltage on the TRACK/SSx pin is less than the 0.8 V internal reference voltage, the LTC7890 regulates the VFBx voltage to the TRACK/SSx pin voltage instead of the 0.8 V reference voltage. This method allows the TRACK/SSx pin to be used as a soft start, which smoothly ramps the output voltage on startup, limiting the input supply inrush current. An external capacitor from the TRACK/SSx pin to GND is charged by an internal 12 μA pull-up current, creating a voltage ramp on the TRACK/SSx pin. As the TRACK/SSx voltage rises linearly from 0 V to 0.8 V (and beyond), VOUTx rises smoothly from zero to its final value. Alternatively, the TRACK/SSx pin can make the startup of VOUTx track that of another supply. Typically, this tracking requires con- necting to the TRACK/SSx pin through an external resistor divider from the other supply to GND (see the RUNx Pins and Undervolt- age Lockout section and Soft Start and Tracking (TRACK/SSx Pin) section).
analog.com Rev. 0 | 18 of 41 LIGHT LOAD OPERATION: BURST MODE OPERATION, PULSE SKIPPING MODE, OR FORCED CONTINUOUS MODE (MODE PIN) The LTC7890 can be set to enter high efficiency Burst Mode opera- tion, constant frequency pulse skipping mode, or forced continuous conduction mode at light load currents. To select Burst Mode operation, tie the MODE pin to GND. To select forced continuous operation, tie the MODE pin to INTVCC. To select pulse skipping mode, tie the MODE pin to a dc voltage greater than 1.2 V and less than INTVCC – 1.3 V. An internal 100 kΩ resistor to GND invokes Burst Mode operation when the MODE pin is floating, and pulse skipping mode when the MODE pin is tied to INTVCC through an external 100 kΩ resistor. When the controllers are enabled for Burst Mode operation, the minimum peak current in the inductor is set to approximately 25% of its maximum value, even though the voltage on the ITHx pin may indicate a lower value. If the average inductor current is higher than the load current, the error amplifier decreases the voltage on the ITHx pin. When the ITHx voltage drops to less than 0.425 V, the internal sleep signal goes high (enabling sleep mode) and both external FETs turn off. The ITHx pin is then disconnected from the output of the error amplifier and parked at 0.45 V. In sleep mode, much of the internal circuitry turns off, reducing the IQ drawn by the LTC7890. If one channel is in sleep mode and the other channel is shut down, the LTC7890 draws only 15 µA of IQ. If both channels are in sleep mode, the LTC7890 draws only 20 µA of IQ. When VOUT on Channel 1 is 3.2 V or higher, the majority of this IQ is supplied by the SENSE1– pin, which further reduces the input referred IQ by the ratio of VIN/VOUT multiplied by the efficiency. In sleep mode, the load current is supplied by the output capacitor. As the output voltage decreases, the output of the error amplifier rises. When the output voltage drops enough, the ITHx pin is reconnected to the output of the error amplifier, the sleep signal goes low, and the controller resumes normal operation by turning on the top FET on the next cycle of the internal oscillator. When a controller is enabled for Burst Mode operation, the inductor current is not allowed to reverse. The reverse current comparator (IR) turns off the bottom FET just before the inductor current reach- es zero, preventing it from reversing and going negative. Therefore, the controller operates in discontinuous operation. In forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. The peak inductor current is determined by the voltage on the ITHx pin, just as in normal operation. In this mode, the efficiency at light loads is lower than in Burst Mode operation. However, continuous operation has the advantage of lower output voltage ripple and less interference to audio circuitry. In forced continuous mode, the output ripple is independent of the load current. When the MODE pin is connected for pulse skipping mode, the LTC7890 operates in pulse-width modulation (PWM) pulse skipping mode at light loads. In this mode, constant frequency operation is maintained down to approximately 1% of the designed maximum output current. At light loads, ICMP can remain tripped for several cycles and force the top FET to stay off for the same number of cycles (that is, skipping pulses). The inductor current is not allowed to reverse (discontinuous operation). This mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced RF interference, as compared to Burst Mode operation. Pulse skipping mode provides higher low current efficiency than forced continuous mode, but not nearly as high as Burst Mode operation. Unlike forced continuous mode and pulse skipping mode, Burst Mode operation cannot be synchronized to an external clock. Therefore, if Burst Mode operation is selected and the switching fre- quency is synchronized to an external clock applied to the PLLIN/ SPREAD pin, the LTC7890 switches from Burst Mode operation to forced continuous mode. FREQUENCY SELECTION, SPREAD SPECTRUM, AND PHASE-LOCKED LOOP (FREQ AND PLLIN/SPREAD PINS) The free running switching frequency of the LTC7890 controller is selected using the FREQ pin. Tying FREQ to GND selects 370 kHz, whereas tying FREQ to INTVCC selects 2.25 MHz. Placing a resistor between FREQ and GND allows the frequency to be programmed between 100 kHz and 3 MHz. Switching regulators can be particularly troublesome for applica- tions where electromagnetic interference (EMI) is a concern. To improve EMI, the LTC7890 can operate in spread spectrum mode, which is enabled by tying the PLLIN/SPREAD pin to INTVCC. This feature varies the switching frequency within typical boundaries of the frequency set by the FREQ pin and +20%. A phase-locked loop (PLL) is available on the LTC7890 to syn- chronize the internal oscillator to an external clock source connect- ed to the PLLIN/SPREAD pin. The PLL of the LTC7890 aligns the turn-on of the external top FET of Channel 1 to the rising edge of the synchronizing signal. The turn-on of the external top FET of Channel 2 is 180° out of phase to the rising edge of the external clock source. The PLL frequency is prebiased to the free running frequency set by the FREQ pin before the external clock is applied. If prebiased near the external clock frequency, the PLL only must make slight changes to synchronize the rising edge of the external clock to the rising edge of TG1. For more rapid lock in to the external clock, use the FREQ pin to set the internal oscillator to approximately the frequency of the external clock. The PLL of the LTC7890 is guaranteed to lock to an external clock source whose frequency is between 100 kHz and 3 MHz.
analog.com Rev. 0 | 19 of 41 The PLLIN/SPREAD pin is transistor-transistor logic (TTL)-compati- ble with thresholds of 1.6 V (rising) and 1.1 V (falling), and this pin is guaranteed to operate with a clock signal swing of 0.5 V to 2.2 V. OUTPUT OVERVOLTAGE PROTECTION The LTC7890 has an overvoltage comparator for each channel that guards against transient overshoots as well as other more serious conditions that can cause output overvoltage. When the VFBx pin rises more than 10% above its regulation point of 0.8 V, the top FET turns off, and the inductor current is not allowed to reverse. FOLDBACK CURRENT When the output voltage falls to less than 70% of its nominal level, foldback current limiting is activated, progressively lowering the peak current limit in proportion to the severity of the overcurrent or short-circuit condition. Foldback current limiting is disabled during the soft start interval (as long as the VFBx voltage is keeping up with the TRACK/SSx voltage). POWER-GOOD The LTC7890 has a PGOODx pin for each channel that is con- nected to an open drain of an internal N-channel MOSFET. The MOSFET turns on and pulls the PGOODx pin low when the VFBx voltage is not within ±10% of the 0.8 V reference. The PGOODx pin is also pulled low when the RUNx pin is low (shut down). When the VFBx voltage is within the ±10% requirement, the MOSFET turns off, and the PGOODx pin is allowed to be pulled up by an external resistor to a source no greater than 6 V, such as INTVCC.
when deciding whether to use DCR sensing or sense resistors. loads. Peak efficiency is about the same with either method. capacitance to maintain low output ripple voltage. PLLIN/SPREAD pins, as shown in Table 4. Table 4. Setting the Switching Frequency Using FREQ and PLLIN/SPREAD
0 V 0 V 370 kHz
0 V, INTVCC, or Resistor
Figure 39. Relationship Between Oscillator Frequency and Resistor Value at Synchronization section for details.
pin to select the light load operating mode. Table 5. Using the MODE Pin to Select Light Load Operating Mode
0 V or Floating Burst Mode Forced continuous
operation has the highest possible efficiency at light loads. is independent of the load current. compromise between light load efficiency, output ripple, and EMI. operating mode based on the conditions present in the system. falling are sensed at the BGDNx and BGUPx pins, respectively). bottom FET turning on (SWx transitioning from high to low). BGx rising to approximately 20 ns. Figure 40. DTCx Pins Tied to GND–Adaptive Dead Time Control
analog.com Rev. 0 | 25 of 41 P M AI N = V OU T V I N I M A X 2 1 + δ R D S ON + V I N
2 I M A X
2 R DR C M IL L ER ×
V I NTC C − V T HMI N + 1 V THMI N f (12) P SY NC = V I N − V O U T V I N I M A X 2 1 + δ R D S ON (13) where: PMAIN is the power dissipation from the main switch. δ is the temperature dependency of RDS(ON) (δ ≈ 0.005/°C). RDR is the effective driver resistance at the Miller threshold voltage of the FET (RDR ≈ 2 Ω). VINTCC is the INTVCC voltage. VTHMIN is the typical FET minimum threshold voltage. PSYNC is the power dissipation from the synchronous switch. Both FETs have I2R losses (I2R is the power loss equation of the FETs when on in steady state), whereas the main N-channel equations include an additional term for transition losses, which are highest at high input voltages. For VIN < 20 V, the high current effi- ciency generally improves with larger FETs. However, for VIN> 20 V, the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CMILLER provides higher efficiency. The synchronous FET losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. CIN AND COUT SELECTION The selection of the input capacitance (CIN) is usually based on the worst case rms current drawn through the input network (battery, fuse, or capacitor). The highest VOUT × output current (IOUT) product must be used in Equation 14 to determine the maximum rms capacitor current requirement. Increasing the output current drawn from the other controller actual- ly decreases the input rms ripple current from its maximum value. The out of phase technique typically reduces the rms ripple current of the input capacitor by a factor of 30% to 70% when compared to a single-phase power supply solution. In continuous mode, the source current of the top FET is a square wave of duty cycle VOUT/VIN. To prevent large voltage transients, use a low effective series resistance (ESR) capacitor sized for the maximum rms current (IRMS). At IMAX, the maximum rms capacitor current is given by Equation 14, as follows: C I N Req ui r ed I RMS ≈ I M A X V I N V O U T V I N − V OU T 1 / 2 (14) Equation 14 has a maximum at VIN = 2 VOUT, where IRMS = IOUT/2. This simple worst case condition is commonly used for design because even significant deviations do not offer much relief. Note that the ripple current ratings of capacitor manufacturers are often based on only 2000 hours of life. This basis makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. Several capacitors can be paralleled to meet size or height requirements in the design. Due to the high operating frequency of the LTC7890, ceramic capacitors can also be used for CIN. Consult the manufacturer if there is any question. The benefit of the LTC7890 2-phase operation can be calculated by using this equation for the higher power controller and then calculating the loss that would result if both controller channels switched on at the same time. The total rms power lost is lower when both controllers are operating due to the reduced overlap of current pulses required through the ESR of the input capacitor. This result is why the requirement of the input capacitor previously calculated for the worst case controller is adequate for the dual controller design. Also, the input protection fuse resistance, battery resistance, and PC board trace resistance losses are also reduced due to the reduced peak currents in a 2-phase system. The overall benefit of a multiphase design is only fully realized when the source impedance of the power supply and/or battery is included in the efficiency testing. Place the drains of the top FETs within 1 cm of each other, and ensure these drains share common CIN. Separating the drains and CIN can produce undesirable resonances at VIN. Placing a small (0.1 μF to 1 μF) bypass capacitor between the chip VIN pin and GND close to the LTC7890 is also suggested. An optional 1 Ω to 10 Ω resistor placed between CIN and the VIN pin provides further isolation from a noisy input supply. The selection of the output capacitance (COUT) is driven by the ESR. Typically, once the ESR requirement is satisfied, the capaci- tance is adequate for filtering. The output ripple (ΔVOUT) is approxi- mated to Equation 15, as follows: ∆ V OU T ≈ ∆ I L ES R + 1 8 f C OU T (15) where: ΔIL is the ripple current in the inductor. f is the operating frequency. The output ripple is highest at the maximum input voltage because ΔIL increases with the input voltage.
Figure 50. Relationship Between INTVCC Voltage and Resistor Value at the Table 6. DRVSET Pin Configurations and Voltage Settings Table 7. DRVUV Pin Configurations and Voltage Settings (MODE = INTVCC) at maximum VIN. try is required to derive INTVCC power from the output.
- EXTVCC grounded. This connection causes the internal VIN
ty of up to 10% or more at high input voltages.
- EXTVCC connected directly to a LTC7890 switching regulator
- EXTVCC connected to an external supply. If an external supply
voltage results in higher efficiency.
- EXTVCC connected to an output derived boost or charge pump.
5 V, efficiency gains can still be realized by connecting EXTVCC
EXTVCC switchover threshold.
analog.com Rev. 0 | 29 of 41 TOPSIDE FET DRIVER SUPPLY (CB) External bootstrap capacitors (CB) connected to the BOOSTx pins supply the gate drive voltage for the topside FETs. CB in Figure 35 is charged through an internal switch from DRVCC when the SWx pin is low and the bottom FET is tuned on. The on resistance of the internal switch is approximately 7 Ω. When the topside FET turns on, the driver places the CB voltage across the gate source of the desired FET, which enhances the FET and turns on the topside switch. The switch node voltage, SWx, rises to VIN and the BOOSTx pin follows. With the topside FET on, the boost voltage is more than the input supply: VBOOST = VIN + VINTVCC. The value of CB needs to be 100 times that of the total input capacitance of the topside FETs. For a typical application, a value of CB = 0.1 μF is sufficient. MINIMUM ON-TIME CONSIDERATIONS The minimum on time (tON(MIN)) is the smallest time duration that the LTC7890 is capable of turning on the top FET. tON(MIN) is deter- mined by the internal timing delays and the gate charge required to turn on the FET. Low duty-cycle applications can approach this minimum on-time limit. Take care to ensure the results in Equation 22, as follows: t O N MI N < V OU T / V I N × f (22) If the duty cycle falls to less than what can be accommodated by the minimum on time, the controller begins to skip cycles. The output voltage continues to regulate, but the ripple voltage and current increase. The minimum on time for the LTC7890 is approx- imately 40 ns. However, as the peak sense voltage decreases, the minimum on time gradually increases up to about 60 ns. This change is of particular concern in forced continuous applications with low ripple current at light loads. If the duty cycle drops to less than the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. FAULT CONDITIONS: CURRENT LIMIT AND FOLDBACK The LTC7890 includes current foldback to reduce the load current when the output is shorted to GND. If the output voltage falls below 70% of its regulation point, the maximum sense voltage is progres- sively lowered from 100% to 40% of its maximum value. Under short-circuit conditions with low duty cycles, the LTC7890 begins cycle skipping to limit the short-circuit current. In this situation, the bottom FET dissipates most of the power, but less than in normal operation. The short-circuit ripple current (ΔIL(SC)) is determined by the tON(MIN) ≈ 40 ns, the input voltage, and the inductor (L) value given by Equation 23, as follows: ∆ I L S C = t ON MIN × V I N / L (23) The resulting average short-circuit current (ISC) is given by Equation 24, as follows: I SC = 40 % × I L I M M A X − ∆ I L SC / 2 (24) where ILIM(MAX) is the maximum peak inductor current. FAULT CONDITIONS: OVERVOLTAGE PROTECTION If an output voltage rises 10% more than its set regulation point, the top FET turns off and remains off until the overvoltage condition clears. During the overvoltage condition, the inductor current is also not allowed to reverse, except during the boost refresh pulses described in the High-Side Bootstrap Capacitor section. FAULT CONDITIONS: OVERTEMPERATURE PROTECTION At higher temperatures, or in cases where the internal power dissipation causes excessive self heating (such as a short from INTVCC to GND), internal overtemperature shutdown circuitry shuts down the LTC7890. When the internal die temperature exceeds 180°C, the INTVCC LDO regulator and gate drivers disable. When the die cools to 160°C, the LTC7890 enables the INTVCC LDO regulator and resumes operation, beginning with a soft start startup. Avoid long-term overstress (TJ > 125°C) because it can degrade the performance or shorten the life of the device. PHASE-LOCKED LOOP AND FREQUENCY SYNCHRONIZATION The LTC7890 has an internal PLL that allows the turn on of the top FET to be synchronized to the rising edge of an external clock signal applied to the PLLIN/SPREAD pin. Rapid phase locking can be achieved by using the FREQ pin to set a free running frequency near the desired synchronization frequen- cy. Before synchronization, the PLL is prebiased to the frequency set by the FREQ pin. Consequently, the PLL only needs to make minor adjustments to achieve phase lock and synchronization. Although it is not required, placing the free running frequency near the external clock frequency prevents the oscillator from passing through a large range of frequencies as the PLL locks. When synchronized to an external clock, the LTC7890 operates in pulse skipping mode if it is selected by the MODE pin, or in forced continuous mode otherwise. The LTC7890 is guaranteed to synchronize to an external clock applied to the PLLIN/SPREAD pin that swings up to at least 2.2 V and down to 0.5 V or less. Note that the LTC7890 can only be synchronized to an external clock frequency within the range of 100 kHz to 3 MHz.
analog.com Rev. 0 | 30 of 41 EFFICIENCY CONSIDERATIONS The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. Analyzing individu- al losses is useful for determining what is limiting the efficiency and which change produces the most improvement. The percent efficiency can be expressed by Equation 25, as follows: %Efficiency = 100% − (L1 + L2 + L3 + …) (25) where L1, L2, L3, and so on, are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC7890 circuits: IC VIN current, INTVCC regulator current, I2R losses, and topside FET transition losses. The VIN current is the dc supply current given in Table 1, which excludes FET driver and control currents. Other than at light loads in Burst Mode operation, VIN current typically results in a small (<0.1%) loss. The INTVCC current is the sum of the FET driver and control currents. The FET driver current results from switching the gate capacitance of the power FETs. Each time a FET gate is switched from low to high to low again, a packet of charge (dQ) moves from INTVCC to GND. The resulting dQ/time duration (dt) is a current out of INTVCC that is typically much larger than the control circuit current. In continuous mode, gate charge current (IGATECHG) = Frequency (f) x (QT + QB), where QT and QB are the gate charges of the top and bottom FETs. Supplying INTVCC from an output derived source through EXTVCC scales the VIN current required for the driver and control circuits by a factor of VOUTx/(VIN × efficiency). For example, in a 20 V to 5 V application, 10 mA of INTVCC current results in approximately 2.5 mA of VIN current. This result reduces the midcurrent loss from 10% or more (if the driver was powered directly from VIN) to only a few percent. I2R losses are predicted from the dc resistances of the input fuse (if used), FET, inductor, current sense resistor, and input and output capacitor ESR. In continuous mode, the average output current flows through L and RSENSE but is chopped between the top and bottom FETs. If the two FETs have approximately the same RDS(ON), the resistance of one FET can be summed with the resistances of L, RSENSE, and ESR to obtain the I2R losses. For example, if each RDS(ON) = 30 mΩ, load resistance (RL) = 50 mΩ, RSENSE = 10 mΩ, and ESR = 40 mΩ (the sum of both input and output capacitance losses), the total resistance is 130 mΩ. The resulting losses range from 3% to 13% as the output current increases from 1 A to 5 A for a 5 V output or a 4% to 20% loss for a 3.3 V output. Efficiency varies as the inverse square of VOUT for the same external components and output power level. The combined effects of increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system. Transition losses apply only to the top FETs and become significant only when operating at higher input voltages (typically 15 V or greater). Transition losses can be estimated using Equation 26, as follows: Transition Loss = 1.7(VIN)2 × IL(MAX) × CRSS × f (26) where CRSS is the reverse transfer capacitance. Other hidden losses, such as copper trace and internal battery resistances, can account for an additional 5% to 10% efficiency degradation in portable systems. It is important to include these system level losses during the design phase. The internal battery and fuse resistance losses can be minimized by making sure that CIN has adequate charge storage and low ESR at the switching frequency. A 25 W supply typically requires a minimum of 20 μF to 40 μF of capacitance with a maximum of 20 mΩ to 50 mΩ of ESR. Other losses, including inductor core losses, generally account for less than 2% total additional loss. CHECKING TRANSIENT RESPONSE To check the regulator loop response, look at the load current transient response. Switching regulators take several cycles to respond to a step in dc (resistive) load current. When a load step occurs, VOUTx shifts by an amount equal to ΔILOAD × ESR, where ESR is the effective series resistance of COUT. ΔILOAD also begins to charge or discharge COUT, generating the feedback error signal that forces the regulator to adapt to the current change and return VOUTx to its steady state value. During this recovery time, VOUTx can be monitored for excessive overshoot or ringing, which indicates a stability problem. OPTI-LOOP compensation allows the transient response to be optimized over a wide range of output capacitance and ESR values. The availability of the ITHx pin not only allows optimization of control loop behavior, but it also provides a dc-coupled and ac filtered closed-loop response test point. The dc step, rise time, and settling at this test point reflects the closed-loop response. Assuming a predominantly second-order system, the phase margin and/or damping factor can be estimated using the percentage of overshoot seen at the ITHx pin. The bandwidth can also be estimated by examining the rise time at the ITHx pin. The ITHx external components shown in Figure 52, Figure 54, Figure 56, and Figure 58 provide an adequate starting point for most applications. The ITHx series compensation resistor (RC) and capacitor (CC) filter sets the dominant pole zero loop compensation. The values can be modified slightly (from 0.5 times to 2 times their initial values) to optimize transient response when the final PCB layout is done and the particular output capacitor type and value are determined. The output capacitors must be selected because the various types and values determine the loop gain and phase. An output current pulse of 20% to 80% of the full load current, with a rise time of 1 μs to 10 μs, produces output voltage and ITHx pin waveforms that give
analog.com Rev. 0 | 31 of 41 a sense of the overall loop stability without breaking the feedback loop. Placing a power FET directly across from the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load step condition. The initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop. Therefore, this signal cannot be used to determine phase margin. For this reason, it is better to look at the ITHx pin signal, which is in the feedback loop and is the filtered and compensated control loop response. The gain of the loop increases by increasing RC, and the bandwidth of the loop increases by decreasing CC. If RC increases by the same factor that CC decreases, the zero frequency is kept the same, keeping the phase shift the same in the most critical frequency range of the feedback loop. The output voltage settling behavior is related to the stability of the closed-loop system and demonstrates the actual overall supply performance. A second, more severe transient is caused by switching in loads with large (>1 μF) supply bypass capacitors. The discharged by- pass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUTx. No regulator can alter its delivery of current quickly enough to prevent this sudden step change in output volt- age, if the load switch resistance is low and it is driven quickly. If the ratio of load capacitance (CLOAD) to COUT is greater than 1:50, the switch rise time must be controlled so that the load rise time is limited to approximately CLOAD × 25 μs/μF. Therefore, a 10 μF capacitor requires a 250 μs rise time, limiting the charging current to about 200 mA. DESIGN EXAMPLE As a design example, assume the nominal input voltage (VIN(NOMINAL)) = 12 V, VIN(MAX) = 22 V, VOUTx = 3.3 V, IOUT = 20 A, and f = 1 MHz. Take the following steps to design an application circuit: 1. Set the operating frequency. The frequency is not one of the internal preset values. Therefore, a resistor from the FREQ pin to GND is required, with a value given by Equation 27, as follows: R F REQ in kΩ = 37 MHz/1 MHz = 37 kΩ (27) 2. Determine the inductor value. Initially, select a value based on an inductor ripple current of 30%. To calculate the inductor value, use Equation 28, as follows: L = V OU T f ∆ I L 1 − V OU T V I N N OMI N AL = 0.4 μH (28) The highest value of the ripple current occurs at the maximum input voltage. In this case, the ripple at VIN = 22 V is 35%. 3. Verify that the minimum on time of 40 ns is not violated. The minimum on time occurs at VIN(MAX), as shown in Equation 29: t ON MI N = V O U T V I N M A X × f = 150 ns (29) This time is sufficient to satisfy the minimum on-time require- ment. If the minimum on time is violated, the LTC7890 skips pulses at high input voltage, resulting in lower frequency opera- tion and higher inductor current ripple than desired. If undesira- ble, this behavior can be avoided by decreasing the frequency (with the inductor value accordingly adjusted) to avoid operation near the minimum on time. 4. Select the RSENSE resistor value. The peak inductor current is the maximum dc output current plus half of the inductor ripple current, or 20 A × (1 + 0.30/2) = 23 A in this case. The RSENSE resistor value is then calculated based on the minimum value for the maximum current sense threshold (45 mV for ILIM = float), given by Equation 30, as follows: R S ENS E ≤ 45 mV / 23 A ≅ 2 m Ω (30) To allow for additional margin, a lower value RSENSE can be used (for example, 1.8 mΩ). However, be sure that the inductor saturation current has sufficient margin more than VSENSE(MAX)/ RSENSE, where the maximum value of 55 mV is used for VSENSE(MAX). 5. Select the feedback resistors. If light load efficiency is required, use high value feedback resistors to minimize the current due to the feedback divider. However, in most applications, a feedback divider current in the range of 10 μA to 100 μA or more is acceptable. For a 50 μA feedback divider current, RA = 0.8 V/50 μA = 16 kΩ. RB is then calculated as RB = RA(3.3 V/0.8 V – 1) = 50 kΩ. 6. Select the FETs. The best way to evaluate FET performance in a particular application is to build and test the circuit on the bench, facilitated by an LTC7890 evaluation board. However, an educated guess about the application is helpful to initially select FETs. Because this is a high current, low voltage appli- cation, I2R losses likely dominate over transition losses for the top FET. Therefore, choose a FET with lower RDS(ON) as opposed to lower gate charge to minimize the combined loss terms. The bottom FET does not experience transition losses, and its power loss is generally dominated by I2R losses. For this reason, the bottom FET is typically chosen to be of lower RDS(ON) and higher gate charge than the top FET. Due to the high current in this application, two FETs may be needed in parallel to more evenly balance the dissipated power and to lower the RDS(ON). When using silicon MOSFETs, be sure to select logic level threshold MOSFETs because the gate drive voltage is limited to 5.5 V (INTVCC). 7. Select the input and output capacitors. CIN is chosen for an rms current rating of at least 10 A (IOUT/2, with margin) at temperature. COUT is chosen with an ESR of 3 mΩ for low output ripple. Multiple capacitors connected in parallel may be required to reduce the ESR to this level. The output ripple in continuous mode is highest at the maximum input voltage. The
analog.com Rev. 0 | 32 of 41 output voltage ripple (VORIPPLE) due to ESR is approximately given by Equation 31, as follows: VORIPPLE = ESR × ΔIL = 3 mΩ × 6 A = 18 mV p-p (31) On the 3.3 V output, 18 mV p-p is equal to 0.55% of the peak-to-peak voltage ripple. 8. Determine the bias supply components. Because the regulated output is not greater than the EXTVCC switchover threshold, it cannot be used to bias INTVCC. However, if another 5 V supply is available, connect that supply to EXTVCC to improve the efficiency. For a 6.7 ms soft start, select a 0.1 μF capacitor for the TRACK/SSx pin. As a first pass estimate for the bias components, select the INTVCC capacitance (CINTVCC) = 4.7 μF and CB = 0.1 μF. 9. Determine and set application specific parameters. Set the MODE pin based on the trade-off of light load efficiency and constant frequency operation. Set the PLLIN/SPREAD pin based on whether a fixed, spread spectrum, or phase-locked frequency is desired. The RUNx pin can control the minimum input voltage for regulator operation, or the RUNx pin can be tied to VIN for always on operation. Use ITHx compensation components from the typical applications as a first guess, check the transient response for stability, and modify as necessary. PCB LAYOUT CHECKLIST Figure 51 shows the current waveforms present in the various branches of the synchronous regulators operating in the continuous mode. When laying out the PCB, use the following checklist to ensure proper operation of the IC. 1. Place the top N-channel FETs MTOP1 and MTOP2 (shown in the Typical Applications section) within 1 cm of each other with a common drain connection at CIN. Do not attempt to split the input decoupling for the two channels as it can cause a large resonant loop. 2. Route the BGUPx and BGDNx traces together and connect them as close as possible to the bottom FET gate. If using gate resistors, connect the resistor connections to the FET gate as close as possible to the FET. Connecting BGUPx and BGDNx further away from the bottom FET gate can cause inaccuracies in the dead time control circuit of the LTC7890. Route the TGUPx and TGDNx traces together and connect them as close as possible to the top FET gate. 3. The combined IC GND pin and the GND return of CINTVCC must return to the combined COUT negative terminals. The path formed by the top N-channel FET and the CIN capacitor must have short leads and PCB trace lengths. Connect the output ca- pacitor negative terminals as close as possible to the negative terminals of the input capacitor by placing the capacitors next to each other and away from the loop. 4. Connect the LTC7890 VFBx pin resistive dividers to the positive terminals of COUT and the signal GND. Place the divider close to the VFBx pin to minimize noise coupling into the sensitive VFBx node. The feedback resistor connections must not be along the high current input feeds from the input capacitors. 5. Route the SENSEx− and SENSEx+ leads together with mini- mum PCB trace spacing. Route these traces away from the high frequency switching nodes on an inner layer, if possible. The filter capacitor between SENSEx+ and SENSEx− must be as close as possible to the IC. Ensure accurate current sensing with Kelvin connections at the sense resistor. 6. Connect the INTVCC decoupling capacitor close to the IC, between the INTVCC and the power GND pin. This capacitor carries the current peaks of the FET drivers. Place an additional 1 μF ceramic capacitor next to the DRVCC and GND pins to help improve noise performance. 7. Keep the switching nodes (SW1 and SW2), top gate no- des (TGUP1/TGDN1 and TGUP2/TGDN2), and boost nodes (BOOST1 and BOOST2) away from sensitive small signal no- des, especially from the voltage and current sensing feedback pins of the other channel. All of these nodes have large and fast moving signals. Therefore, keep these nodes on the output side of the LTC7890 and ensure they occupy the minimum PCB trace area. 8. Use a modified star ground technique: a low impedance, large copper area central grounding point on the same side of the PCB as the input and output capacitors, with tie ins for the bottom of the INTVCC decoupling capacitor, the bottom of the voltage feedback resistive divider, and the GND pin of the IC.
Figure 51. Branch Current Waveform
analog.com Rev. 0 | 34 of 41 PCB LAYOUT DEBUGGING Start with one controller on at a time. Use a dc to 50 MHz current probe to monitor the current in the inductor while testing the circuit. Monitor the output switching node (the SWx pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well. Check for proper performance over the operating voltage and current range expected in the application. The frequency of operation is maintained over the input voltage range down to dropout and until the output load drops to less than the low current operation threshold, typically 25% of the maximum designed current level in Burst Mode operation. The duty-cycle percentage is maintained from cycle to cycle in a well designed, low noise PCB implementation. Variation in the duty cycle at a subharmonic rate can suggest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. Overcompensation of the loop can tame an improper PCB layout if regulator bandwidth optimization is not required. Turn on both controllers at the same time after each controller is checked for its individual performance. A particularly difficult region of operation is when one controller channel is nearing its current comparator trip point when the other channel is turning on its top FET, which occurs around 50% duty cycle on either channel due to the phasing of the internal clocks and may cause minor duty-cycle jitter. Reduce VIN from its nominal level to verify operation of the reg- ulator in dropout. Check the operation of the UVLO circuit by further lowering VIN while monitoring the outputs to verify operation. Investigate whether any problems exist only at higher output cur- rents or only at higher input voltages. If problems coincide with high input voltages and low output currents, look for capacitive coupling between the BOOSTx, SWx, TGxxx, and possibly BGxxx connections and the sensitive voltage and current pins. Place the capacitor across the current sensing pins next to the pins of the IC. This capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. If problems are encountered with high current output loading at lower input voltages, look for inductive coupling between CIN, the top FET, and the bottom FET components to the sensitive current and voltage sensing traces. In addition, investigate the common GND path voltage pickup between these components and the GND pin of the IC. A problem that may be missed in an otherwise properly working switching regulator results when the current sensing leads are hooked up backwards. The output voltage under this improper hookup is maintained, but the advantages of current mode control are not realized. Compensation of the voltage loop is more sensi- tive to component selection. This behavior can be investigated by temporarily shorting out the current sensing resistor. The regulator maintains control of the output voltage even during this condition.
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RELATED PRODUCTS
Table 8. Related Products
4.5 V ≤ VIN ≤ 40 V, VOUT up to 40 V, IQ = 12 µA, PLL fixed frequency of 100 kHz to 3 MHz, 4
4.5 V ≤ VIN ≤ 40 V, VOUT up to 40 V, IQ = 14 µA, PLL fixed frequency of 100 kHz to 3 MHz, 6
Figure 60. 40-Lead Plastic Side Wettable QFN 1 All models are RoHS compliant parts.
©2023 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Rev. 0 | 41 of 41 EVALUATION BOARDS Model1 Description DC2938A Evaluation Board 1 The DC2938A is an RoHS compliant part.