DC2903A-A

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Five-Channel, Low Dropout, 300 mA, Current Source Output, 16-Bit SoftSpan DAC Data Sheet LTC2672 Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2020 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Per channel programmable output current ranges: 300 mA, 200 mA, 100 mA, 50 mA, 25 mA, 12.5 mA, 6.25 mA, and 3.125 mA Flexible 2.1 V to VCC output supply voltages Flexible single- or dual-supply operation

0.6 V maximum dropout voltage guaranteed

Separate voltage supply per output channel Internal switches to optional negative supply Full 16-bit resolution at all ranges Guaranteed operation −40°C to 125°C (H-grade) Precision internal reference (10 ppm/°C maximum V REF temperature coefficient) or external reference Analog multiplexer monitors voltages and currents A/B toggle via SPI or dedicated pin

1.71 V to V

32-Lead Lead Frame Chip Scale Package [LFCSP]

APPLICATIONS

Semiconductor optical amplifier biasing Resistive heaters Current mode biasing FUNCTIONAL BLOCK DIAGRAM LTC2672-16 DAC0 VDD0 OUT0 FULL SCALE ADJUST INTERNAL REFERENCE ANALOG MUX SPAN0 SERIAL INTERFACE VDD1 OUT1 VDD2 OUT2 VDD3 OUT3 VDD4 OUT4 FAULT FAULT DETECT CS/LD IOVCC SCK SDI SDO LDAC CLR TGP MUX VCC 13, 27 15, 26 REF FSADJ REFLO REFCOMP GND 1, 8, 14, 32 DAC1 SPAN1 DAC2 SPAN2 DAC3 SPAN3 DAC4 SPAN4 25700-001 Figure 1. GENERAL DESCRIPTION The LTC2672-16 is a five-channel, 16-bit current source, digital- to-analog converter (DAC) that provides five high compliance current source outputs with guaranteed 600 mV dropout at 200 mA. There are eight current ranges that are programmable per channel with full-scale outputs of up to 300 mA. The channels can be paralleled to allow either ultrafine adjustments of large currents or combined outputs of up to 1.5 A. A dedicated supply pin is provided for each output channel. Each channel can be operated from 2.1 V to V CC, and internal switches allow any output to be pulled to the optional negative supply. The LTC2672-16 includes a precision integrated 1.25 V reference (10 ppm/°C maximum), with the option to use an external reference. The serial peripheral interface (SPI) compatible, 3-wire serial interface operates on logic levels as low as 1.71 V and at clock rates as high as 50 MHz. Note than throughout this data sheet, multifunction pins, such as CS /LD, are referred to by the entire pin name or by a single function of the pin.

Rev. 0 | Page 2 of 26 TABLE OF CONTENTS

REVISION HISTORY

12/2020—Revision 0: Initial Version

Rev. 0 | Page 3 of 26 SPECIFICATIONS All specifications apply over the full operating junction temperature range −40°C to +125°C, unless otherwise noted. Typical values are at TJ = 25°C, VCC = IOVCC = 5 V, V− = –3.3 V, VDDx = 5 V, FSADJ = VCC, and VREF = 1.25 V external, unless otherwise specified. Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit DC PERFORMANCE Resolution 16 Bits Monotonicity All ranges1 16 Bits Differential Nonlinearity DNL All ranges 1 −1 +0.45 +1 LSB Integral Nonlinearity INL All ranges 1 −64 +12 +64 LSB Current Offset Error IOS All current ranges 1 −0.4 +0.1 +0.4 %FSR IOS Temperature Coefficient All current ranges 10 ppm/°C Gain Error GE2 300 mA and 200 mA output current ranges −0.9 +0.3 +0.9 %FSR 100 mA, 50 mA, and 25 mA output current ranges 12.5 mA, 6.25 mA, and 3.125 mA output current ranges Gain Temperature Coefficient FSADJ = V CC 30 ppm/°C Total Unadjusted Error TUE2 300 mA and 200 mA output current ranges −1.4 +0.4 +1.4 %FSR 100 mA, 50 mA, and 25 mA output current ranges 12.5 mA, 6.25 mA, and 3.125 mA output current ranges −2 +0.8 +2 %FSR Power Supply Rejection PSR Range = 100 mA, I OUTx = 50 mA VCC = 4.75 V to 5.25 V 0.5 LSB VDDX = 2.85 V to 3.15 V 0.4 LSB VDDX = 4.75 V to 5.25 V 0.7 LSB V− = −3.25 V to −2.75 V 0.6 LSB DC Crosstalk3 Result of a 200 mW change in dissipated power 0.1 %FSR Dropout Voltage (VDDX − VOUTX4) V DROPOUT 200 mA range; (V DDX − V−) = 4.75 V 0.45 0.6 V 200 mA range; (V DDX – V–) = 2.85 V 0.5 0.65 V 300 mA range; (V DDX – V–) = 4.75 V 0.75 V 300 mA range; (V DDX – V–) = 2.85 V 0.85 1.15 V Off Mode Output Leakage Current5 800 Ω load to GND −1 +0.1 +1 μA OUTx Switch to V− Resistance RPULLDOWN Span code = 1000b, sinking 80 mA 8 12 Ω AC PERFORMANCE T A = 25°C for all ac performance specifications Settling Time6, 7 t SET Full-Scale Step 3.125 mA Range ±0.0015% (±1 LSB at 16b) 21.1 μs ±0.024% (±1 LSB at 12b) 3.8 μs 145 mA to 155 mA Step 200 mA Range ±0.0015% (±1 LSB at 16b) 7.2 μs ±0.024% (±1 LSB at 12b) 3.6 μs Full-Scale Step 200 mA Range ±0.0015% (±1 LSB at 16b) 200 μs ±0.024% (±1 LSB at 12b) 3.5 μs Glitch Impulse At midscale transition, 200 mA range, resistive load that connects the DAC output to GND (R LOAD) = 4 Ω 1.0 nA × s DAC to DAC Crosstalk8 100 mA to 200 mA step, R LOAD = 15 Ω 230 pA × s

Rev. 0 | Page 4 of 26 Parameter Symbol Test Conditions/Comments Min Typ Max Unit iNOISE Output current noise density internal reference, IOUTx = 150 mA, RLOAD = 4 Ω, CLOAD = 10 μF Frequency (f) = 1 kHz 12 nA/√Hz f = 10 kHz 5 nA/√Hz f = 100 kHz 0.5 nA/√Hz f = 1 MHz 0.05 nA/√Hz REFERENCE Reference Output Voltage VREF 1.248 1.250 1.252 V VREF Temperature Coefficient9 −10 +3 +10 ppm/°C VREF Line Regulation V CC = 5 V ± 10% 50 μV/V VREF Short-Circuit Current V CC = 5.5 V, forcing output to GND 2.5 mA REFCOMP Pin Short-Circuit Current V CC = 5.5 V, forcing output to GND 65 μA VREF Load Regulation V CC = 5 V, IREF = 100 μA sourcing 140 mV/mA VREF Output Voltage Noise Density REFCOMP pin current (CREFCOMP) = REFCOMP pin capacitance (CREF) = 0.1 μF, at f = 10 kHz 32 nV/√Hz External Reference Input Current 0.001 1 μA External Reference Input Capacitance10 40 pF External Reference Input Voltage REFC OMP pin is tied to GND 1.225 1.275 V External Full-Scale Adjust Resistor R FSADJ R FSADJ to GND 19 20 41 kΩ DIGITAL INPUT/OUPUT Digital Output High Voltage VOH SDO pin, load current = −100 μA IOVCC − 0.2 V Digital Output Low Voltage VOL SDO pin, load current = 100 μA 0.2 V FAULT pin, load current = 100 μA 0.2 V Digital High-Z Output Leakage Current SDO pin leakage current (CS/LD high) −1 +1 μA FAULT pin leakage current (not asserted) 1 μA Digital Input Current V IN = GND to IOVCC −1 +1 μA Digital Input Capacitance10 C IN 8 pF High Level Input Voltage VIH 2.85 ≤ IO VCC ≤ VCC 0.8 × IO VCC V 1.71 ≤ IO VCC ≤ 2.85 0.8 × IO VCC V Low Level Input Voltage VIL 2.85 ≤ IO VCC ≤ VCC 0.3 V 1.71 ≤ IO VCC ≤ 2.85 0.3 V POWER SUPPLY Analog Supply Voltage VCC 2.85 5.5 V Digital I/O Supply Voltage IOVCC 1.71 V CC V Negative Supply V− −5.5 0 V Output Supplies VDDx 200 mA range and below (relative to GND) 2.1 V CC V 300 mA range and below (relative to GND) 2.4 V CC V Output Supplies, Total Voltage11 Safe operating area (V DDx relative to V−) 2.85 9 V VCC Supply Current All ranges (code = 0, all channels) 4 5.3 mA IOVCC Supply Current All ranges (code = 0, all channels) 0.01 1 μA V− Supply Current All ranges (cod e = 0, all channels) 7.5 11 mA VDDX Supply Current All ranges (code = 0, per channel) 1.5 2.2 mA 25 mA range (code = full-scale, per channel) 12 28 32 mA 200 mA range (code = full-scale, per channel) 12 205 215 mA VCC Shutdown Current13, 14 I SLEEP 50 500 μA IOVCC Shutdown Current13, 14 0.01 1 μA V− Shutdown Current13, 14 0.29 1.2 mA VDDX Shutdown Current13, 14 80 250 μA

Rev. 0 | Page 5 of 26 Parameter Symbol Test Conditions/Comments Min Typ Max Unit MONITOR MULTIPLEXER MUX Pin DC Output Impedance 15 kΩ MUX Pin Leakage Current Monitor multiplexer disabled (high impedance) −1 +0.1 +1 μA MUX Pin Output Voltage Range Monitor multiplexer selected to OUT0 pin voltage to OUT4 pin voltage V− V CC V MUX Pin Continuous Current11 TA = 25°C (do not exceed) −1 +1 mA 1 Offset current is measured at Code 384 for the LTC2672-16. Linearity is defined from Code 384 to Code 65535 for the LTC2672-16. 2 For the full-scale current (IFS) = 300 mA, RLOAD = 10 Ω. For IFS = 200 mA, RLOAD = 15 Ω. For IFS = 100 mA, RLOAD = 30 Ω. For IFS = 50 mA, RLOAD = 50 Ω. For IFS = 25 mA, RLOAD = 3 IFS = 200 mA and RLOAD = 15 Ω. DC crosstalk is measured with a 100 mA to 200 mA current step on all four aggressor channels. Total power dissipation change is 4 × 50 mW = 200 mW. The monitor channel is held at 3/4 × IFS or 150 mA. 4 VOUTx is the channel output voltage. 5 The loads attached to the OUTx pins must be terminated to GND. 6 VDDX = 5 V (3.125 mA range), VDDX = 3.6 V (200 mA range), and V− = −3.3 V for all ranges. For large current output steps, internal thermal effects result in a final settling tail. In most cases, the tail is too small to affect settling to ±0.024%, but several milliseconds can be needed for full settling to the ±0.0015% level. For optimal results, always solder the exposed pad (Pin 33) to a solid GND plane and set VDDX as low as practicable for each channel to reduce power dissipation in the device. The listed results were obtained using the DC2903 evaluation board demo circuit with no additional heatsinks. 7 Internal reference mode. The load is 15 Ω (200 mA range) or 800 Ω (3.125 mA range) terminated to GND. 8 DAC to DAC crosstalk is the glitch that appears at the output of one DAC because of a 100 mA to 200 mA step change in an adjacent DAC channel. The measured DAC is at midscale (100 mA output current) in the 200 mA span range, with the internal reference, VDDX = 5 V, V− = −3.3 V. 9 The temperature coefficient is calculated by first computing the ratio of the maximum change in the output voltage to the nominal output voltage, and then dividing the ratio by the specified temperature range. 10 Guaranteed by design and not production tested. 11 Stresses beyond those listed for extended periods can cause permanent damage to the device or affect device reliability and lifetime. 12 Single channel at a specified output. 13 VCC = IOVCC = 5 V, VDDx = 5 V, V− = −3.3 V. 14 Digital inputs are at 0 V or IOVCC.

All specifications apply over the full operating junction temperature range −40°C to +125°C, otherwise specifications are at TJ = 25°C. Digital input low and high voltages are 0 V and IOVCC, respectively. Table 2. 2.85 V ≤ VCC ≤ 5.5 V, 2.85 V ≤ IOVCC ≤ VCC 1 Guaranteed by design and not production tested. 1 Guaranteed by design and not production tested.

operational section of this specification is not implied. extended periods may affect product reliability. PCB thermal design is required. the junction to case thermal resistance. Table 5. Thermal Resistance

1 Thermal impedance simulated values are based on JEDEC 2S2P thermal test

board with no bias. See JEDEC JESD-51.

1. GROUND. SOLDER THIS PAD DIRECTLY TO

Figure 5. Pin Configuration Table 6. Pin Function Descriptions 1, 8, 14, 32 GND Analog Ground. Ti e GND to an analog ground plane. software. Tie TGP to GND if the toggle operations are not used. Logic levels are determined by IOVCC. word lengths of 24 bits, 32 bits, or multiples of 32 bits. Logic levels are determined by IOVCC. 5 SCK Serial Clock Input. Logic levels are determined by IO VCC. Table 7) is executed. Logic levels are determined by IOVCC. has no effect if CS/LD is low. Logic levels are determined by IOVCC. If LDAC is not used, tie LDAC to IOVCC. 9 REFLO Reference Low. REFLO is the signal ground for the reference. Tie REFLO directly to GND. CREFCOMP is the capacitance tied to REFCOMP. The allowable external reference input range is 1.225 V to 1.275 V. the use of an external reference at start-up.

Rev. 0 | Page 10 of 26 Pin No. Mnemonic Description 12 FSADJ Full-Scale Current Adjust Pin. FSADJ can be used in one of two ways to produce either nominal, internally calibrated output ranges, or incrementally tunable ranges. In either case, the reference voltage, VREF, is forced across a resistor, RFSADJ, to define a reference current that scales the outputs for all ranges and channels. Full- scale currents are proportional to the voltage at REF and are inversely proportional to RFSADJ. If FSADJ is tied to VCC, an internal RFSADJ (20 kΩ) is selected, which results in nominal output ranges. An external resistor of 19 kΩ to 41 kΩ can be used instead by connecting the resistor between FSADJ and GND. In this case, the external resistor controls the scaling of the ranges and the internal resistor is automatically disconnected. See Table 9 for details. When using an external resistor, FSADJ is sensitive to stray capacitance and must be compensated with a snubber network that consists of a series combination of 1 kΩ and 1 μF connected in parallel to RFSADJ. With the recommended compensation, FSADJ is stable while driving stray capacitance up to 50 pF. 13, 27 V CC Analog Supply Voltage. 2.85 V ≤ VCC ≤ 5.5 V. All output supply voltages must be less than or equal to VCC, (VDDx ≤ VCC). Bypass VCC to GND with a 1 μF capacitor. 15, 26 V − Negative Supply Voltage. −5.5 V ≤ V− ≤ GND. Bypass V− to GND with a 1 μF capacitor unless V− is connected to GND. See Figure 28 for safe operating voltages. 16, 19, 20, 23, 24 OUT4 to OUT0 DAC Analog Current Outputs. Each current output pin has a dedicated analog supply pin, V DD0 to VDD4. The load attached to OUTx must be terminated to GND. For information on combining outputs, see the Load Termination and Combining Channels section. 17, 18, 21, 22, 25 VDD4 to VDD0 Output Supplies. VDD0 to VDD4 operate at 2.1 V to VCC with respect to GND, and at 2.85 V to 9 V with respect to V−. These five positive supply inputs provide independent supplies for each of the five DAC current output pins, OUT0 to OUT4, respectively. Note that the highest output supply voltage must be less than or equal to VCC (VDDx ≤ VCC). Bypass each supply input to GND separately with a 1 μF capacitor. Unused output supplies must be connected to a valid VCC or VDDX supply. Do not leave these pins floating. See Figure 28 for safe operating voltages. 28 MUX Analog Multiplexer Output. Pin voltages and currents can be monitored by measuring the voltage at MUX. When the multiplexer is disabled, MUX becomes high impedance. The available multiplexer selections are shown in Table 10. 30 FAULT Active Low Fault Detection Pin. This open-drain, N-channel output pulls low when any valid fault condition is detected. FAULT is released on the next CS/LD rising edge. A pull-up resistor is required (5 kΩ recommended). 31 CLR Active Low Asynchronous Clear Input. A logic low at this level triggered input clears the device to the default reset code and output range, which is zero-scale with the outputs off. The control registers are cleared to zero. Logic levels are determined by IOVCC. 33 GND Ground. Solder this pad direct ly to the analog ground plane.

Rev. 0 | Page 14 of 26 TERMINOLOGY Integral Nonlinearity (INL) INL is a measurement of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. INL for this DAC is defined from Code 384 to Code 65535. Differential Nonlinearity (DNL) DNL is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified DNL of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. Because the output must have a finite output current, DNL for this DAC is defined from Code 384 to Code 65,535. Current Offset Error (I OS) Unipolar offset error is typically measured when zero code is loaded to the DAC register. Because offset can be either positive or negative polarity and the output current cannot go below zero, offset for this DAC is defined at Code 384 and calculated based on the expected output at that code. I OS Temperature Coefficient The IOS temperature coefficient is a measure of the change in IOS with a change in temperature, and is expressed in ppm/°C. Gain Error Gain error is a measure of the span error of the DAC, and is the deviation in slope of the DAC transfer characteristic from the ideal expressed as a percentage of full-scale range (%FSR). Gain Error Temperature Coefficient The gain error temperature coefficient is a measurement of the change in gain error with changes in temperature, and is expressed in ppm/°C. Power Supply Rejection (PSR) PSR indicates how the output of the DAC is affected by changes in the supply voltage. PSR is the change in V OUTX because of a specified change in VCC, V−, or VDDX for a full-scale output of the DAC and is expressed in LSB. Settling Time Settling time is the amount of time it takes for the output of a DAC to settle to a specified error window for a full-scale input change and is measured from the rising edge of CS/LD. Glitch Impulse Glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. Glitch impulse is normally specified as the area of the glitch in nA × sec, and is measured when the digital input code is changed by 1 LSB at the midscale transition. DC Crosstalk DC crosstalk is the dc change in the output level of one DAC in response to a 100 mA to 200 mA change in the outputs of all other DAC channels. The monitored channel is maintained at 150 mA (3/4 × I FS). DC crosstalk is expressed in %FSR. DAC to DAC Crosstalk DAC to DAC crosstalk is the glitch that appears at the output of one DAC because of a step change from 100 mA to 200 mA in another DAC channel. The measured DAC is at midscale (100 mA output current) in the 200 mA range. The energy of the glitch is expressed in nA × sec. Output Noise Spectral Density Output noise spectral density is a measurement of the internally generated random noise. Random noise is characterized as a spectral density (nA/√Hz) and is measured by loading the DAC to 150 mA (3/4 × I FS) and measuring noise at the output.

Rev. 0 | Page 15 of 26 THEORY OF OPERATION The LTC2672-16 is a five-channel, current source output DAC with selectable output ranges, precision reference, and a multiplexer for surveying the channel output voltages and currents. Each output draws its current from a separate dedicated positive supply pin that accepts voltages of 2.1 V to V CC to allow optimization of power dissipation and headroom for a wide range of loads. Internal 12 Ω switches allow any output pin to be connected to an optional negative V − supply voltage and sink up to 80 mA. LOAD TERMINATION AND COMBINING CHANNELS The load attached to any OUTx pins must be terminated to ground. OUTx pins that are not used in the system design must be left open (no connect). Any combination of OUTx pins can be tied together if currents greater than 300 mA are needed or for finer control of large currents. The LTC2672-16 offers the following four span categories:  Eight current ranges  Off mode  Switch to V  Power-down All channels tied together must be operated in the same span category. The device is tolerant of mixing span categories, but avoid doing so because mixing can increase supply currents and/or compromise accuracy. When the combined channels are operated in the current range span category (3.125 mA to 300 mA), the ranges and DAC codes do not need to be the same for each channel. POWER-ON RESET The outputs reset to a current off state (off mode) on power-up, which makes system initialization consistent and repeatable. When power-on initialization is complete, select the output span via the SPI bus using Table 7, Table 8, and Table 9. POWER SUPPLY SEQUENCING The supplies (VCC, IOVCC, V−, and VDD0 to VDD4) can be powered up in any convenient order. If an external reference is used, do not allow the input voltage at REF to rise above V CC + 0.3 V during supply turn on and turn off sequences (see the Absolute Maximum Ratings section). When startup is complete, ensure that no supply exceeds V CC. DC reference voltages of 1.225 V to 1.275 V are acceptable. Supply bypassing is critical to achieving the best possible performance. Use at least 1 μF of low ESR capacitance to ground on all supply pins and locate the capacitor as close to the device as possible. A 0.1 μF capacitor can be used for IOVCC. DATA TRANSFER FUNCTIONS The DAC input to output transfer functions for all resolutions and output ranges ≥25 mA are shown in Figure 22. The input code is in straight binary format for all ranges.

don’t care bits to the device first, followed by the 24-bit word. processors that have a minimum word width of 16 bits or more. The complete 24-bit and 32-bit sequences are shown in Figure 4. Table 7. Write Operation for SPI Commands

0000 Write code to DAC Channel x

1000 Write code to all DAC channels

0110 Write span to DAC Channel x

1110 Write span to all DAC channels

0001 Power up and update DAC Channel x

1001 Power up and update all DAC channels

0011 Write code to DAC Channel x, power up and

0010 Write code to DAC Channel x, power up,

1010 Power up, write code to and update all DAC

0100 Power down Channel x

0101 Power down chip

1011 Monitor multiplexer

1100 Toggle select

1101 Global toggle

0111 Configuration command

1111 No operation

Table 8. DAC Address Mapping given in Table 8 causes the command to be ignored. buffered registers comprises an input register and a DAC register. the code is updated while the span is refreshed and unchanged. negative pulse, or a toggle operation.

Rev. 0 | Page 19 of 26 MONITOR MULTIPLEXER The LTC2672-16 includes a multiplexer for monitoring both the voltages and currents at the five current output pins (OUTx). Additionally, VDDx, the negative V− supply, core supply (VCC), reference voltage (VREF), and die temperature can all be monitored. The MUX pin is intended for use with high impedance inputs only. The impedance at the MUX pin is typically 15 kΩ. The continuous dc output current at the MUX pin must be limited to ±1 mA to avoid damaging internal circuitry. The operating range of the multiplexer extends rail-to-rail from V − to VCC and its output is disabled (high impedance) at power-up. The syntax and codes for the multiplexer command are shown in Figure 24 and Table 10. CURRENT MEASUREMENT USING THE MULTIPLEXER Measure the current of any output pin by using the multiplexer command (1011b) with one of the multiplexer current measurement codes from Table 10. The multiplexer responds by outputting a voltage proportional to the actual output current. The proportionality factor is given by the following equation: IOUTX = IFS × VMUX/VREF (1) where: I OUTX is the output current the OUTX pin. The current measurement function does not sense the current at the OUTx pins, but instead uses the DAC settings to predict the output current. Therefore Equation 1 is invalid if the output pin is open (or dropping out), or if the span is not set to one of the eight current ranges. In Equation 1, note that V MUX varies only with the DAC code (and reference voltage), and is the same for every span setting. IFS must be given the value of the active span setting for the equation to evaluate correctly. VMUX has the same optimal linearity as the current outputs, but calibrating for slope error (±15% FSR) is necessary for accurate results. ±1% FSR accuracy is achievable with a one-point or two-point calibration. DIE TEMPERATURE MEASUREMENT USING THE MULTIPLEXER Measure the die temperature by using the multiplexer command with the multiplexer Control Code 01010b. The voltage at the MUX pin (V MUX) in this case is linearly related to the die temperature by a temperature coefficient of −3.7 mV/°C. The measured junction temperature, TJ, is then TJ = 25°C + (1.4 V − VMUX)/(3.7 mV/°C) (2) If needed, the temperature monitor can be calibrated by measuring the initial temperature and voltage, and then substituting these values for 25°C and 1.4 V, respectively, in the equation. MONITOR MULTIPLEXER PRECHARGE CONSIDERATIONS The analog multiplexer in the LTC2672-16 is unbuffered. This obviates error terms from amplifier offsets. However, without buffers, the high impedance current outputs can be disturbed because of charge transfer at the moment when the MUX pin is connected. The LTC2672-16 contains circuitry that suppresses charging glitches on the output pins (OUTx) by precharging the MUX pin before connecting the MUX pin to the output. Because of the precharge behavior, the multiplexer output becomes valid approximately 7 μs after the multiplexer command is given (CS/LD rising). Residual charging transients can be further reduced by adding capacitance to the output pins, if needed. Do not add capacitance to the MUX pin as this action can increase the disturbance to the outputs during multiplexer switching. Up to 100 pF on the MUX pin is allowable. TOGGLE OPERATIONS Some systems require that the DAC outputs switch repetitively between two output levels (for example, switching between an on and off state). The LTC2672-16 toggle function facilitates these kinds of operations by providing two input registers (Register A and Register B) per DAC channel. Toggling between Register A and Register B is controlled by three signals. The first signal is the toggle select command, which acts on the data field of 5 bits, each of which controls a single channel (see Figure 25). The second signal is the global toggle command, which controls all selected channels using the global toggle bit, TGB (see Figure 26). Lastly, the TGP pin allows the use of an external clock or logic signal to toggle the DAC outputs between Register A and Register B. The signals from these controls are combined as shown in Figure 27. If the toggle function is not needed, tie the TGP pin (Pin 2) to ground and leave the toggle select register in its power-on reset state (cleared to zero). Input Register A then functions as the sole input register, and Register B is not used. TOGGLE SELECT REGISTER (TSR) The toggle select command (1100b) syntax is shown in Figure 25. Each bit in the 5-bit TSR data field controls the corresponding DAC channel of the same name (T0 controls Channel 0, T1 controls Channel 1,…, and T4 controls Channel 4). The toggle select bits (T0 to T4) have a dual function. First, each toggle select bit controls which input register (Register A or Register B) receives data from a write code operation. When the toggle select bit of a given channel is high, write code operations are directed to Input Register B of the addressed channel. When the bit is low, write code operations are directed to Input Register A. In addition, each toggle select bit enables the corresponding channel for a toggle operation.

Rev. 0 | Page 20 of 26 WRITING TO INPUT REGISTER A AND INPUT REGISTER B When channels to toggle are chosen, write the desired codes to Input Register A for the chosen channels, then set the channel toggle select bits using the toggle select command and write the desired codes to Input Register B. When these steps are complete, the channels are ready to toggle. For example, to set up Channel 3 to toggle between Code 4096 and Code 4200, take the following steps: 1. Write Code Channel 3 (code = 4096) to Register A 00000011 00010000 00000000. 2. Toggle select (set Bit T3) 11000000 00000000 00001000. 3. Write Code Channel 3 (code = 4200) to Register B 00000011 00010000 01101000. The write code of Step 3 is directed to Register B because in Step 2, Bit T3 was set to 1. Channel 3 now has Input Register A and Register B holding the two desired codes, and is prepared for the toggle operation. Note that after writing to Register B, the code for Register A can still be changed. The state of the toggle select bit determines to which register (Register A or Register B) a write is directed. For example, to change Register A while toggling Register B, take the following steps: 1. Reset the toggle select bit, Bit T3, to 0 (11000000 00000000 00000000). 2. Write the new Register A code. If the code used for this example is 4300, the instruction is 00000011 00010000 11001100 3. Set the toggle select bit, Bit T3, back to 1 (see previous Step 2). It is not necessary to write to Register B again. Channel 3 is ready for the toggle operation. TOGGLING BETWEEN REGISTER A AND REGISTER B When the input registers have been written to for all desired channels and the corresponding toggle select bits are set high, as in the previous example, the channels are ready for toggling. The LTC2672-16 supports three types of toggle operations: one in which all selected channels are toggled together using the SPI port, another in which all selected channels are toggled together using an external clock or logic signal, and a third in which any combination of channels can be instructed to update from either input register. The internal toggle update circuit is edge triggered, so only transitions (of TGB or TGP) trigger an update from the respective input register. To toggle all selected channels together using the SPI port, ensure the TGP pin is high and that the bits in the toggle select register corresponding to the desired channels are also high. Use the global toggle command (1101b) to alternate codes and sequentially change the global toggle bit, TGB (see Figure 26). Changing TGB from 1 to 0 updates the DAC registers from the respective Input Register A. Changing TGB from 0 to 1 updates the DAC registers from the respective Input Register B. Note that in this way, up to five channels can be toggled with just one serial command. To toggle all selected channels using an external logic signal, ensure that the TGB bit in the global toggle register is high and that in the toggle select register, the bits corresponding to the desired channels are also high. Apply a clock or logic signal to the TGP pin to alternate codes. The TGP falling edges update the DAC registers from the associated Input Register A. The TGP rising edges update the DAC registers from the associated Input Register B. Note that after the input registers are set up, all toggling is triggered by the signal applied to the TGP pin with no further SPI instructions needed. To cause any combination of channels to update from either Input Register A or Input Register B, ensure that the TGP pin is high and that the TGB bit in the global toggle register is also high. Use the toggle select command to set the toggle select bits as needed to select the input register (Register A or Register B) with which each channel is to be updated. Then, update all channels either by using the serial command (1001b) or by applying a negative pulse to the LDAC pin. Any channels that have toggle select bits that are 0 update from Input Register A, and channels that have toggle select bits that are 1 update from Input Register B (see Figure 27). By alternating between toggle select and update operations, up to five channels can be simultaneously switched to Register A or Register B as needed.

The serial output of the shift register appears at the SDO pin.

32 SCK rising edges before being output at the next SCK falling

the next 32 SCK rising edges. signals are common to all devices in the series. The SDO pin can be used to verify data transfer to the device. Table 11 lists the FR bits and their associated trigger conditions. pull-up resistor on the bus is required (5 kΩ is recommended). Table 11. Fault Register (FR) set and the SPI instruction is ignored. releases the FAULT pin regardless of the die temperature. potential of the system design must be evaluated carefully. assert, and the instruction itself to be ignored. FR6 is unused in this device.

Rev. 0 | Page 24 of 26 SWITCH TO V− MODE Span Code 1000b can be used to pull outputs below GND. In switch to V− mode, the output current is turned off for the addressed channel(s), and the channel voltage VOUTX pulls to V−. The pulldown switch can sink up to 80 mA at an effective resistance of 12 Ω maximum. Note that exceeding 80 mA can affect reliability and device lifetime. Switch to V − mode can be invoked with the write span to all channels or write span to DAC Channel x command and the desired address. Span codes are shown in Table 9. A diagram of an output in switch to V mode is shown in Figure 29, where RON is the resistance when the NMOS transistor is conducting. GAIN ADJUSTMENT USING THE FSADJ PIN The full-scale output currents are proportional to the reference voltage, and inversely proportional to the resistance associated with FSADJ, that is, I OUTFS ~ VREF/RFSADJ (3) If the FSADJ pin is tied to VCC, the LTC2672-16 uses an internal RFSADJ ~ 20 kΩ, trimmed to ensure optimal full-scale current error with no user intervention. Optionally, FSADJ can instead be connected to a grounded external resistor to tune the default current ranges to the application using an appropriately specified precision resistor. Values from 19 kΩ to 41 kΩ are supported. The new current ranges can be calculated using the external R FSADJ column of Table 9. The internal resistor is automatically disconnected when using an external resistor. When using an external resistor, the FSADJ pin is sensitive to stray capacitance. The FSADJ pin must be compensated with a snubber network consisting of a series combination of 1 kΩ and 1 μF connected in parallel to RFSADJ. With the recommended compensation, the FSADJ pin is stable while driving stray capacitance of up to 50 pF. OFFSET CURRENT AND CODE ZERO The offset current error of the LTC2672-16 is guaranteed ±0.4 %FSR maximum. If the offset of a given channel is positive, some nonzero current flows at code zero. If negative, the current is zero (leakage only) for a range of codes close to zero. Offset and linearity endpoints are measured at Code 384 (LTC2672-16) guaranteeing that the DAC is operating with a measurable output current at the point of measurement. A channel with a positive offset error may not completely turn off, even at code zero. To turn an output completely off, set the span to off (Span Code 0000b from Table 9), and update the channel. REFERENCE MODES The LTC2672-16 can be used with either an internal or external reference. As with voltage DACs, the reference voltage scales the outputs, so that the outputs reflect any errors in the reference. Full scale output currents are limited to 300 mA maximum per channel regardless of reference voltage. The internal 1.25 V reference has a typical temperature drift of ±2 ppm/°C and an initial output tolerance of ±2 mV maximum. The reference is trimmed, tested, and characterized independent of the DACs, and the DACs are tested and characterized with an ideal external reference. To use the internal reference, leave the REFCOMP pin floating with no dc path to GND. In addition, the RD bit in the configuration register must have a value of 0. This value is reset to 0 at power-up and can be reset using the configuration command, 0111b. Figure 30 shows the command syntax. For reference stability and low noise, tie a 0.1 μF capacitor between REFCOMP and GND. In this configuration, the internal reference can drive up to 0.1 μF with optimal stability. To ensure stable operation, the capacitive load on the REF pin must not exceed that on the REFCOMP pin. A buffer is needed if the internal reference is to drive external circuitry. To use an external reference, tie the REFCOMP pin to GND, which disables the output of the internal reference at startup so that the REF pin becomes a high impedance input. Apply the reference voltage at the REF pin after powering up. Set the RD bit to 1 using the configuration command, 0111b. The REF input voltage range is 1.225 V to 1.275 V. BOARD LAYOUT The load regulation and dc crosstalk performance of the device is achieved in the device by minimizing the common-mode resistance of the signal and power grounds. As with any high resolution converter, clean board grounding is important. A low impedance analog ground plane is necessary, as well as star grounding techniques. Keep the board layer used for star ground continuous to minimize ground resistances, that is, use the star ground concept without using separate star traces. Resistance from the REFLO pin to the star point must be as low as possible. The GND pin (Pin 33) is recommended as the star ground point. For optimal performance, stitch the ground plane with arrays of vias on 150 mil to 200 mil centers to connect the plane with the ground pours from the other board layers, which reduces the overall ground resistance and minimizes ground loop area.

1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
4. EXPOSED PAD SHALL BE SOLDER PLATED
5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

3.50 REF

0.50 BSC

0.200 REF

Figure 31. 32-Lead Lead Frame Chip Scale Package [LFCSP]

Rev. 0 | Page 26 of 26 NOTES ©2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D25700-12/20(0)