LTM8060F AD | Alldatasheet

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Technical content

Quad 40VIN, 3A Silent Switcher μModule Regulator with Package-Level EMI Shield Rev. 0 DOCUMENT FEEDBACK TECHNICAL SUPPORT

FEATURES

 Package-Level EMI Shielding  Minimize Near-Field Electric Field Noise  Reduce Near-Field Magnetic Field Noise  Pin-to-Pin Compatible with the LTM8060  Four Complete 3A (4A peak) Step-Down Switching Power Supplies  Low Noise Silent Switcher Architecture  Compliant with CISPR22 Class B/CISPR25 Class 5  Wide Input Voltage Range: 3V to 40V  Wide Output Voltage Range: 0.8V to 8V  4A Continuous Output Current per Channel at 12VIN, 3.3VOUT, fSW = 2MHz, TA = 60°C  Multiphase or Multi-module Parallelable for Increased Output Current  Low Thermal Resistance, θJA = 8.4°C/W, θJCtop = 4.6°C/W, θJCbot = 1°C/W  Selectable Switching Frequency: 200kHz to 3MHz  Available in a Compact 165-Pin, 16mm × 11.9mm × 2.9mm, Pre-Soldered Grid Array (PSGA) Package

APPLICATIONS

 Automated Test Equipment  Industrial Supplies  Medical Equipment GENERAL DESCRIPTION The LTM8060F is a quad 40VIN, 3A (4A peak) step-down Silent Switcher® power μModule® (micromodule) regulator with package-level Electromagnetic interference (EMI) shield. The package-level EMI shield enables the Faraday cage to be applied directly to the LTM8060F package, and the EMI shield is electrically connected to the GND pins, providing a compact and effective near-field EMI reduction. The EMI shield eliminates all electric field noise, and a 10dB reduction is achieved on magnetic field noise. The Silent Switcher architecture minimizes EMI while delivering high efficiency. Included in the package are the controllers, the power switches, the inductors, and the support components. Operating over a wide input voltage range, the LTM8060F supports output voltages from 0.8V to 8V and a switching frequency range of 200kHz to 3MHz, each set by a single resistor. Only the bulk input and the output filter capacitors are needed to finish the design. The LTM8060F outputs can be paralleled in an array for up to 12A (16A peak) capability (see Figure 1). Figure 1. Configurable Output Array

analog.com Rev. 0 3 of 43 TABLE OF CONTENTS

analog.com Rev. 0 4 of 43

REVISION HISTORY

10/2024 - Rev. 0: Initial Release.

Table 1. Electrical Characteristics

analog.com Rev. 0 6 of 43 (TA = 25°C, VINn = 12V, RUNn = 2V unless otherwise noted.1, 2 ) PARAMETER SYMBOL CONDITIONS COMMENTS MIN TYP MAX UNITS SYNCn Threshold to Enable Spread Spectrum VEN(SYNC) 2.8 4.0 V SYNCn Current ISYNC SYNCn = 6V 60 μA TRSSn Source Current ITRSS TRSSn = 0V 2 μA TRSSn Pull-Down Resistance RTRSS Fault condition, TRSSn = 0.1V 200 Ω The LTM8060FE is guaranteed to meet performance specifications from 0°C to 125°C internal. Specifications over the full –40°C to 125°C internal operating temperature range are assured by design, characterization, and correlation with statistical process controls. The LTM8060FI is guaranteed to meet specifications over the full –40°C to 125°C internal operating temperature range. Note that the maximum internal temperature is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. 2 The n represents each individual channel. Four outputs are tested separately, and the same testing condition is applied to each output. The maximum current out of any channel may be limited by the internal temperature of the LTM8060F. For different VIN, VOUT, and TA conditions, see the output current derating curves in the Applications Information section.

TA = 25°C unless otherwise specified. Table 2. Absolute Maximum Ratings extended periods may affect product reliability.

attention to PCB thermal design is required. voltage values are for characterization only. Table 3. LTM8060F ESD Ratings

Figure 5. Pinout Configuration Table 4. Pin Descriptions

2 GND

θ VALUES ARE DETERMINED BY SIMULATION PER JESD51 CONDITIONS. θJA VALUE IS OBTAINED WITH DEMO BOARD. SEE THE TYPICAL PERFORMANCE CHARACTERISTICS SECTION FOR LAB MEASURED DERATING CURVES.

analog.com Rev. 0 10 of 43 PIN NAME DESCRIPTION CFG 1 Bank

4 VIN2

Input Power for the Channel 2 Regulator. Decouple VIN2 to ground with an external low Equivalent series resistance (ESR) capacitor. See Table 6 for recommended values. Bank

5 VIN34

Input Power for the Channel 3 and Channel 4 Regulator. The VIN34 bank powers the internal control circuitry for both Channel 3 and Channel 4 and is monitored by undervoltage lockout circuitry. The VIN34 voltage must be greater than 3V for either Channel 3 or Channel 4 of the LTM8060F to operate. Decouple VIN34 to ground with an external low-ESR capacitor. See Table 6 for recommended values. Bank

6 VIN1

Input Power for the Channel 1 Regulator. The VIN1 powers the internal control circuitry for Channel 1 and Channel 2 and is monitored by undervoltage lockout circuitry. The VIN1 voltage must be greater than 3V for either Channel 1 or Channel 2 of the LTM8060F to operate. Decouple VIN1 to ground with an external low-ESR capacitor. See Table 6 for recommended values. Banks 8, 3, 1, VOUT1−OUT4 Power Output for Channel 1, through Channel 4, respectively. Apply the output filter capacitor and the output load between these pins and the GND plane. C10, N2 CLKOUT12, 34 Synchronization Output. When SYNC12, 34 > 2.8V, the CLKOUT12, 34 pins provide a waveform about 90° out-of-phase with Channel 1 and Channel 3, respectively. This allows synchronization with other regulators with up to four phases. When an external clock is applied to the SYNC12, 34 pins, the CLKOUT12, 34 pins will output a waveform with about the same phase, duty cycle, and frequency as the SYNC12, 34 waveform. In Burst Mode® operation, the CLKOUT12, 34 pins will be internally grounded. Float these pins if the CLKOUT12, 34 function is not used. Do not drive these pins. C11, N1 SYNC12, 34 External Clock Synchronization Input. Ground these pins for low ripple Burst Mode operation at low output loads; this will also disable the CLKOUT function. Apply a DC voltage between 2.8V and 4V for forced continuous mode (FCM) operation with spread spectrum modulation. Float the SYNCn pin for FCM operation without spread spectrum modulation. Apply a clock source to the SYNCn pin for synchronization to an external frequency. The LTM8060F will be in FCM when an external frequency is applied. E9, D10, L3, M2 PG1−PG4 The PGn pins are the open-drain output of an internal comparator. The PGn pin remains low until the FBn pin is within ±7.5% of the final regulation voltage, and until there are no fault conditions. The PGn pin is pulled low during VINn UVLO, thermal shutdown, or when the RUNn pins are low. E10, L2 DNC Do not connect these pins. E11, D11, L1, M1 RUN1−RUN4 The corresponding channel of the LTM8060F is shut down when these pins are low and active when these pins are high. Connect to VINn if the shutdown feature is not used. An external resistor divider from VINn can be used to program a VINn threshold below which the corresponding channel of the LTM8060F will shut down. Do not float these pins.

analog.com Rev. 0 11 of 43 PIN NAME DESCRIPTION CFG 1 K8, K9, F4, F3 SHARE1−SHARE4 Channel 1 through Channel 4 Current Sharing Control. Connect SHAREn together when paralleling outputs. The LTM8060F can also share current between modules. See the Typical Applications section for current sharing between channels and current sharing between modules. K11, K10, F1, F2 FB1−FB4 The LTM8060F regulates the FBn pin to 800mV. Connect the feedback resistor to these pins to set the output voltage. L11, E1 RT12, 34 Connect a resistor between RTn and ground to set the switching frequency. Do not drive these pins. M10, D2 BIAS12, 34 The internal regulator will draw current from BIASn instead of VIN1 or VIN34 when BIASn is connected to a voltage higher than 3.2V. For output voltages of 3.3V and above, these pins should be connected to VOUTn. If these pins are connected to a supply other than VOUTn, use a local bypass capacitor on these pins. N10, L10, C2, E2 AUX1−AUX4 Low Current Voltage Source for BIAS. In many designs, the BIAS pin is simply connected to VOUT via the AUX pin. The AUXn pins are internally connected to VOUTn and placed adjacent to the BIASn pins to ease printed circuit board routing. Although these pins are internally connected to VOUT, they are not intended to deliver a higher current, so do NOT connect these pins to the load. If these pins are not connected to BIAS, leave them floating. N11, M11 TRSS1, 2 Output Tracking and Soft Start Pins. These pins allow the user to control the output voltage ramp rate during startup. A TRSSn voltage below 0.8V forces the LTM8060F to regulate the FBn pin to equal the TRSSn pin voltage. When TRSSn is above 0.8V, the tracking function is disabled, and the internal reference resumes control of the error amplifier. An internal 2μA pull-up current on these pins allow a capacitor to program output voltage slew rate. These pins are pulled to ground during shutdown and fault conditions; use a series resistor if driving from a low impedance output. These pins may be left floating if the soft start feature is not being used.

Table 5. LTM8060F Pinout (Sorted by Pin Number)

Figure 51. Dual Channel Derating, VOUT = 5V CH1/CH3 ON, CH2/CH4 OFF, BIAS = 5V, peak current of up to 4A per channel. The continuous current is determined by the internal operating temperature. input voltage range for VIN1 and VIN34 is 3V to 40V, while the input voltage range for VIN2 is 2V to 40V. supports reliable clock interleaving. See Figure 52 for the Simplified Block Diagram. source (typically the regulated output voltage). This improves efficiency. Connect BIASn to GND if it is not used. To enhance efficiency, the LTM8060F automatically switches to Burst Mode operation in light or no-load situations. voltage source. See the Applications Information section for more details.

Figure 52. LTM8060F Simplified Block Diagram The LTM8060F contains power good comparators that trip when the FBn pin is at about ±8% of its regulated value. The LTM8060F is equipped with a thermal shutdown that inhibits power switching at high junction temperatures. damage or impair the reliability of the device.

For most applications, the design process is straightforward, and summarized as follows.

  1. See Table 6 and find the row with the desired input range and output voltage.
  2. Apply the recommended CIN, COUT, RFB, and RT values.
  3. Connect BIAS as indicated.

Performance Characteristics section for guidance. synchronization function is used. See the Synchronization section for details. A 1% resistor is recommended to maintain output voltage accuracy. Figure 53. Set Output Voltage with a FB Resistor and environmental conditions. The ceramic capacitors are small, robust, and have very low ESR. However, not all ceramic capacitors are suitable.

exceeding the device’s rating. This situation can be avoided easily; see the Hot-Plugging Safely section. Table 6. Recommended Component Values and Configuration (TA = 25°C) 1 The LTM8060F may be capable of the operating at lower input voltages but may skip switching cycles. 2 A bulk input capacitor is required. resultant frequencies. The resistors in Table 7 are standard 1% E96 values. has too much output ripple or too large of an output capacitor. Table 7. Switching Frequency vs. RT Value

analog.com Rev. 0 25 of 43 fSW (MHz) RT (kΩ) 0.2 200 0.3 137 0.4 100 0.5 76.8 0.6 64.9 0.7 54.9 0.8 46.4 0.9 41.2 1.0 35.7 1.2 27.4 1.4 23.2 1.6 19.6 1.8 16.9 2.0 14.7 2.2 12.7 2.4 11.3 2.6 10.2 2.8 9.09 3.0 8.06 BIASn Pin Considerations The BIASn pin provides drive power for the internal power switching stage and operates other internal circuitry. For proper operation, it must be powered by at least 3.2V. If the output voltage is programmed to 3.2V or higher, BIASn may be simply connected to VOUTn. If VOUTn is less than 3.2V, BIASn can be connected to VINn or some other voltage source. If the BIASn pin voltage is too high, the efficiency of the LTM8060F may suffer. The optimum BIASn voltage is dependent upon many factors, such as load current, input voltage, output voltage, and switching frequency. In all cases, ensure that the maximum voltage at the BIASn pin is less than 10V. If BIASn power is applied from a remote or noisy voltage source, it may be necessary to apply a decoupling capacitor locally to the pin. A 1µF ceramic capacitor works well. The BIASn pin may also be connected to GND at the cost of a small degradation in efficiency. Maximum Load The maximum practical continuous load that the LTM8060F can drive per channel, while rated at 3A (4A peak), depends upon both the internal current limit and the internal temperature. The internal current limit is designed to prevent damage to the LTM8060F in the case of overload or short-circuit. The internal temperature of the LTM8060F depends upon operating conditions such as the ambient temperature, the power delivered, and the heat-sinking capability of the system. For example, if VOUT1 of LTM8060F is configured to regulate at 1.5V, and the other three channels are turned off, VOUT1 may continuously deliver 4A from 24VIN if the ambient temperature is controlled to less than 60°C. This is much higher than the 3A (4A peak) rating. See the Typical Performance Characteristics section. Similarly, if all four channels of the LTM8060F are delivering 3.3VOUT and the ambient temperature is 100°C, each channel will deliver at most 1.5A from 24VIN, which is less than the 3A (4A peak) rating.

analog.com Rev. 0 30 of 43 feedback voltage will be regulated to the internal reference voltage. The TRSSn pin may be left floating if the function is not needed. An active pull-down circuit is connected to the TRSSn pin, which will discharge the external soft start capacitor in the case of fault conditions and restart the ramp when the faults are cleared. Fault conditions that clear the soft start capacitor are the RUNn pin transitioning low, VINn voltage falling too low, or thermal shutdown. Prebiased Output As discussed in the Output Voltage Tracking and Soft Start section, the LTM8060F regulates the output to the FBn voltage determined by the TRSSn pin whenever TRSSn is less than 0.8V. If the LTM8060F output is higher than the target output voltage, and SYNCn is not held below 0.8V, the LTM8060F will attempt to regulate the output to the target voltage by returning a small amount of energy back to the input supply. If nothing is loading the input supply, its voltage may rise. Take care that it does not rise so high that the input voltage exceeds the absolute maximum rating of the LTM8060F. If SYNC is grounded, the LTM8060F will not return current to the input. Frequency Foldback The LTM8060F is equipped with frequency foldback, which acts to reduce the thermal and energy stress on the internal power elements during a short circuit or output overload condition. If the LTM8060F detects that the output has fallen out of regulation, the switching frequency is reduced as a function of how far the output is below the target voltage. This in turn limits the amount of energy that can be delivered to the load under fault. During the startup time, frequency foldback is also active to limit the energy delivered to the potentially large output capacitance of the load. When a clock is applied to the SYNCn pin, the SYNCn pin is floated or held high, the frequency foldback is disabled, and the switching frequency will slow down only during overcurrent conditions. Synchronization To select low ripple Burst Mode operation, connect the SYNCn pin below about 0.8V (this can be ground or a logic low output). To synchronize the LTM8060F oscillator to an external frequency, connect a square wave (with about 20% to 80% duty cycle) to the SYNCn pin. The square wave amplitude should have valleys that are below 0.8V and peaks above 1.5V. The LTM8060F may be synchronized over a 200kHz to 3MHz range. The LTM8060F will not enter Burst Mode operation at light output loads while synchronized to an external clock. The RT resistor should be chosen to set the switching frequency equal to or below the lowest synchronization input. For example, if the synchronization signal will be 500kHz and higher, the RT should be selected for 500kHz or lower. The LTM8060F features spread-spectrum operation to further reduce electromagnetic interference/electromagnetic interference compatibility (EMI/EMC) emissions. To enable spread-spectrum operation, apply between 2.8V and 4V to the SYNCn pin. In this mode, triangular frequency modulation is used to vary the switching frequency between the value programmed by RT to about 20% higher than that value. The modulation frequency is about 7kHz. For example, when the LTM8060F is programmed to 2MHz, the frequency will vary from 2MHz to 2.4MHz at a 7kHz rate. When spread-spectrum operation is selected, the Burst Mode operation is disabled, and the part may run in discontinuous-conduction mode. Shorted Input Protection Care needs to be taken in systems where the output is held high when the input to the LTM8060F is absent. This may occur in battery charging applications or in battery backup systems where a battery or some other supply is diode OR’ed with the LTM8060F’s output. If the VINn pin is allowed to float and the RUNn pin is held high (either by a logic signal or because it is connected to VINn), then the LTM8060F’s internal circuitry pulls its quiescent current

circuit that runs only when the input voltage is present, and that protects against a shorted or reversed input. Figure 66. The Input Diode Prevents a Shorted Input from Discharging a Backup Battery Connected to the Output. It also heat sinking are acceptable.

  1. Place the RFB and RT resistors as close as possible to their respective pins.
  2. Place the CIN capacitor as close as possible to the VIN and GND connection of the LTM8060F.
  3. Place the COUT capacitor as close as possible to the VOUT and GND connection of the LTM8060F.
  4. Place the CIN and COUT capacitors such that their ground current flows directly adjacent to or underneath
  5. Connect all the GND connections to as large a copper pour or plane area as possible on the top layer.

Avoid breaking the ground connection between the external components and the LTM8060F.

  1. Use vias to connect the GND copper area to the board’s internal ground planes. Liberally distribute

than a board that uses larger holes.

Figure 67. Layout Showing Suggested External Components, GND Plane, and Thermal Vias improve the efficiency of the circuit, though it is likely to be the largest component in the circuit. The LTM8060F output current may need to be derated if it is required to operate in a high ambient temperature. system’s line, load, and environmental operating conditions.

  1. θJA – Thermal resistance from junction to ambient.
  2. θJCbot – Thermal resistance from the junction to the bottom of the product case.
  3. θJCtop – Thermal resistance from the junction to the top of the product case.

confusion and inconsistency. These definitions are given in JESD5112 and are quoted or paraphrased as follows.

  1. θJA is the natural convection junction-to-ambient air thermal resistance measured in one cubic foot

which does not reflect an actual application or viable operating condition.

  1. θJCbot is the junction-to-board thermal resistance with all the component power dissipation flowing

match the user’s application.

  1. θJCtop is determined with nearly all the component power dissipation flowing through the top of the

not generally match the user’s application. all the thermal resistances simultaneously. shown. The blue resistances are contained within the µModule regulator, and the green is outside. Figure 68. Graphical Representation of Thermal Coefficients, Including the JESD5112 Terms

Figure 69. 8.5V to 40V Input to 5V at 3A (4A Peak), 3.3V at 3A (4A Peak), 5V at 3A (4A Peak), and 3.3V at 3A (4A Peak) (Note 3) of the Electrical Characteristics table and the derating curves in the Applications Information section.

(Note 3) of the Electrical Characteristics table and the derating curves in the Applications Information section.

Figure 71. 3V to 40V Input to Paralleled 1V at 16A (Note 3) of the Electrical Characteristics table and the derating curves in the Applications Information section.

Figure 72. Two LTM8060F are Paralleled to Supply 1V at 32A Output in FCM (Note 3) of the Electrical Characteristics table and the derating curves in the Applications Information section.

Figure 73. Two LTM8060F are Paralleled to Supply 1V at 32A Output (Note 3) of the Electrical Characteristics table and the derating curves in the Applications Information section.

Table 11. Related Parts

Figure 74. 165-Pin, 16mm × 11.9mm × 2.9mm, Pre-Soldered Grid Array (PSGA)

analog.com Rev. 0 41 of 43 ORDERING GUIDE Table 12.Ordering Guide MODEL TEMPERATURE RANGE1 PACKAGE DESCRIPTION PACKAGE OPTION LTM8060FEV#PBF –40°C to 125°C LTM8060FV part marking SAC305 (RoHS) pad finish* E1 finish code Moisture sensitivity level 4 (MSL 4) rated device 165-Pin, 16mm × 11.9mm × 2.9mm, Pre-Soldered Grid Array (PSGA) LTM8060FIV#PBF –40°C to 125°C LTM8060FV part marking SAC305 (RoHS) pad finish E1 finish code Moisture sensitivity level 4 (MSL 4) rated device 165-Pin, 16mm × 11.9mm × 2.9mm, Pre-Soldered Grid Array (PSGA) 1 The LTM8060FE is guaranteed to meet performance specifications from 0°C to 125°C internal. Specifications over the full – 40°C to 125°C internal operating temperature range are assured by design, characterization, and correlation with statistical process controls. The LTM8060FI is guaranteed to meet specifications over the full –40°C to 125°C internal operating temperature range. Note that the maximum internal temperature is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance, and other environmental factors. Contact the factory for parts specified with wider operating temperature ranges. *Pad finish code is per IPC/JEDEC J-STD-609. The device temperature grade is indicated by a label on the shipping container. This product is not recommended for second side reflow. This product is moisture sensitive. For more information, go to Recommended LGA and BGA PCB assembly and manufacturing procedures. The PSGA package should follow BGA assembly and manufacturing procedures. LGA and BGA package and tray drawings. Table 13.Evaluation Board PART NUMBER DESCRIPTION DC2820A-B 40VIN quad 3A Silent Switcher µModule regulator with EMI shield.

analog.com Rev. 0 42 of 43 SELECTOR GUIDE Package Photos (Part Marking Is Laser Mark) Design Resources Table 14.Design Resources SUBJECT DESCRIPTION µModule Design and Manufacturing Resources Design:  Selector guides  Demo boards and Gerber files.  Free simulation tools Manufacturing:  Quick start guide  PCB design, assembly, and manufacturing guidelines  Package and board level reliability µModule Regulator Products Search  Sort table of products by parameters and download the result as a spread sheet.  Search using the Quick Power Search parametric table. Digital Power System Management The Analog Devices family of digital power supply management ICs are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature EEPROM for storing user configurations and fault logging.

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