DC2728A

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Rev 0For more information www.analog.com TYPICAL APPLICATION FEATURES DESCRIPTION 60V Dual Output Step-Up Controller with Digital Power System Management The LT C®7880 is a dual PolyPhase® DC/DC synchronous step-up switching regulator controller with I2C-based PM- Bus compliant serial interface. This controller employs a constant-frequency , current-mode architecture, with high voltage input and output capability along with program - mable loop compensation. The LTC7880 is supported by the L TpowerPlay™ software development tool with graphical user interface (GUI). Switching frequency, output voltage, and device address can be programmed both by digital interface as well as external configuration resistors. Parameters can be set via the digital interface or stored in EEPROM. The gate drive for the LTC7880 can be programmed from 6.3V to 9V to maximize efficiency. Both outputs have an independent power good indicator and FAUL T function. The LTC7880 can be configured for discontinuous (pulse- skipping) mode or continuous inductor current mode.

APPLICATIONS

n PMBus /I 2C Compliant Serial Interface – Telemetry Read-Back Includes Input and Output Voltage and Current, Temperature and Faults – Programmable Voltage, Current Limit, Digital Soft-Start/Stop, Sequencing , Margining, OV/UV/OC, Frequency, and Control Loop Compensation n Output Error Less Than ±0.5% Over Temperature n Integrated 16-Bit ADC and 12-Bit DAC n Internal EEPROM with ECC and Fault Logging n Integrated N-Channel MOSFET Gate Drivers Power Conversion n Wide Input Voltage Range: 5V to 40V n Operates Down to 2.5V After Start-Up n VOUT0, VOUT1 Range: Up to 60V n Analog Current Mode Control n Accurate PolyPhase ® Current Sharing for Up to 6 Phases (50kHz to 500kHz) n Available in a 52-Lead (7mm × 8mm) QFN Package n Automotive Always-On and Start-Stop Systems n Industrial and Point of Load Applications All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. patents, including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 5408150, 6580258, 6304066, 7420359, 8786268 Patent Pending. Licensed under U.S. Patent 7000125 and other related patents worldwide. V IN = 12V V OUT = 24V f SW = 150kHz LOAD CURRENT (A) EFFICIENCY (%) POWER LOSS (W)

7880 TA01bEfficiency and Power Loss

3m/uni03A96.8µH 6.8µH 220µF

7880 TA01a

V VIN LTC7880 DRVCC TG0 BOOST0 SW0 BG0 10nF EXTVCC 100pF 47µF 0.1µF 4.7µF 5V TO 40V DOWN TO 2.5V AFTER STARTUP IF VBIAS IS POWERED FROM VOUT 3m/uni03A9 0.1µF VOUT 24V AT 10A VOUT FOLLOWS VIN FOR VIN > 24V SDA SCL ALERT RUN0 RUN1 PMBus INTERFACE FAUL T MANAGEMENT TO/FROM OTHER ADI DEVICES FAUL T0 FAUL T1 PGOOD0 PGOOD1 SHARE_CLK TH0 THR0 I I ISENSE0 SENSE1– SENSE0+ SENSE1+ I I I TH1 THR1 I I VDD33 VDD25 1µF 1µF VSENSE0+ 10nF 10nF *SOME DETAILS OMITTED FOR CLARITY TSNS0 TSNS1 5m/uni03A9 BIAS IOUT– IOUT+ Document Feedback

Rev 0 For more information www.analog.com TABLE OF CONTENTS

Electrical Characteristics

Typical Performance Characteristics Pin Functions Block Diagram Overview Main Control Loop C RC Protection P ower-Up and Initialization E vent-Based Sequencing Shutdown Light-Load Current Operation O peration at Low SENSE Pin Common Mode Voltage PWM Loop Compensation Switching Frequency and Phase Output Voltage Sensing Output Current Sensing Input Current Sensing PolyPhase Load Sharing External/Internal Temperature Sense RCONFIG (Resistor Configuration) Pins Fault Handling Status Registers and ALERT Masking Mapping Faults to FAULT Pins Power Good Pins Serial Interface Communication Protection Device Addressing Output Overvoltage Fault Response Output Undervoltage Response Peak Input Overcurrent Response Responses to Timing Faults Responses to OT/UT Faults Internal Overtemperature Fault/Warn Response 28 E xternal Overtemperature and Undertemperature R esponses to External Faults Fault Logging Bus Timeout Protection Similarity Between PMBus, SMBus and I2C P MBus Serial Digital Interface PMBus Command Summary PMBus Commands Applications Information Current Limit Programming L ow Value Resistor Current Sensing Inductor DCR Current Sensing S lope Compensation and Inductor Peak Current ....43 Inductor Value Calculation Inductor Core Selection Power MOSFET and Optional Schottky Diode Selection Variable Delay Time, Soft-Start and Output Voltage Ramping Digital Servo Mode Soft Off (Sequenced Off) U ndervoltage Lockout Fault Indications Open-Drain Pins Phase-Locked Loop and Frequency

Rev 0For more information www.analog.com TABLE OF CONTENTS External Temperature Sense Derating EEPROM Retention at Temperature O utput Current Sense Amplifier External Resistor Configuration Pins (RCONFIG) ....53 Voltage Selection Frequency Selection Phase Selection Address Selection Using RCONFIG Efficiency Considerations Programmable Loop Compensation Checking Transient Response PolyPhase Configuration PC Board Layout Checklist P C Board Layout Debugging Design Example Additional Design Checks Connecting the USB to I2C/SMBus/PMBus Adapter to the LTC7880 In System LTpowerPlay: An Interactive GUI for Digital Power .64 PMBus Communication and Command Processing PMBus Command Details Addressing and Write Protect G eneral Configuration COMMANDS On/Off/Margin PWM Configuration Voltage Input Voltage and Limits Output Voltage and Limits Current and Limits Input Current and Limits Temperature Timing Timing—On Sequence/Ramp Timing—Off Sequence/Ramp F F ault Responses All Faults Fault Responses Input Voltage Fault Responses Output Voltage Fault Responses IC Temperature Fault Responses External Temperature Fault Sharing Fault Sharing Propagation Fault Sharing Response Scratchpad Fault Warning and Status Telemetry EEPROM Memory Commands Store/Restore Fault Logging Fault Log Operation Typical Applications Package Description Typical Application Related Parts

Rev 0 For more information www.analog.com PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS Top Gate Transient Voltage (TG0, TG1) BOOST0, BOOST1 Switch Transient Voltage (SW0, SW1) DRVCC, BG0, BG1, (BOOST0– SW0), (BOOST1– SW1) VIN0, VIN1, ISENSE0+, ISENSE1+, RUN, SDA, SCL, ALERT ASELn, VOUTn_CFG, FREQ_CFG, (VSENSE0+ – IOUT+), (VSENSE0+ – IOUT–), (VIN0 – ISENSE0+), (VIN0 – ISENSE0–), PGOOD0, PGOOD1, FAULT, SHARE_CLK, ITH0, ITH1, ITHR0, ITHR1, VDD33, WP , TSNS0, TSNS1, SYNC Operating Junction Temperature Range Storage Temperature Range (Note 1) 1615 17 18 19 TOP VIEW GND UKG PACKAGE VARIATION: UKG52 52-LEAD (7mm × 8mm) PLASTIC QFN TJMAX = 125°C, θJA = 31°C/W, θJC = 2°C/W EXPOSED PAD (PIN 53) IS GND, MUST BE SOLDERED TO PCB 20 21 22 23 24 25 26 52 50 48 47 46 44 43 42

1 SW0

ISENSE0– TSNS0 VIN0 NC ISENSE1+ ISENSE1– ITHR0 ITH0 SYNC SCL BOOST1 SW1 TG1 NC TSNS1 V IN1 PGOOD0 PGOOD1 I THR1 ITH1 VDD33 SHARE_CLK WP V DD25 BOOST0 NC BG0 NC V BIAS IOUT+ IOUT– VSENSE0+ DRVCC EXTVCC BG1 NC SDA ALERT FAULT0 FAULT1 RUN0 RUN1 ASEL0 ASEL1 V OUT0_CFG VOUT1_CFG FREQ_CFG PHAS_CFG 51 49 45 ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC7880EUKG#PBF LTC7880EUKG#TRPBF LTC7880UKG 52-Lead (7mm × 8mm) Plastic QFN –40°C to 125°C LTC7880IUKG#PBF LTC7880IUKG#TRPBF LTC7880UKG 52-Lead (7mm × 8mm) Plastic QFN –40°C to 125°C Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container . Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. See Derating EEPROM Retention at T emperature in the Applications Information section for junction temperatures in excess of 125°C.

Rev 0For more information www.analog.com ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). VBIAS = 16V, EXTVCC = 0V, VRUN0 = 1.8V, VRUN1 = 1.8V fSYNC = 250kHz (externally driven), and all programmable parameters at factory default unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Supply Voltage VBIAS Bias Voltage Range (Note 12) l 5 60 V VIN Input Voltage Range (Note 12) l 2.5 40 V IQ VBIAS Voltage Supply Current Normal Operation (Note 14) VRUN = 3.3V, No Caps on TG and BG VRUN = 0V mA mA V UVLO Undervoltage Lockout Threshold When V BIAS > 4.2V VDRVCC Falling VDRVCC Rising 3.7 3.95 V V TINIT Initialization Time Delay from RESTORE_USER_ALL, MFR_REST, or VDRVCC > VUVLO Until TON_DELAY Can Begin 35 ms Control Loop VOUTR0 Range 0 Maximum VOUT Range 0 Set Point Accuracy Range 0 Resolution Range 0 LSB Step Size, FSR = 63.2V 12V ≤ V OUT ≤ 58V (Note 10) l –0.5 15.2 0.5 V Bits mV VOUTR1 Range 1 Maximum VOUT Range 1 Set Point Accuracy Range 1 Resolution Range 1 LSB Step Size, FSR = 31.6V 6V ≤ V OUT ≤ 28V l –0.5 7.6 0.5 V Bits mV VLINEREG Line Regulation 16V < VIN0, VIN1 < 40V l ±0.05 %/V VLOADREG Load Regulation ∆VITH = 1.35V – 0.7V ∆VITH = 1.35V – 2.0V l l 0.01 –0.01 0.1 –0.1 gm0,1 Resolution 3 bits Error Amplifier gm(MAX) ITH =1.35V 5.76 mmho Error Amplifier gm(MIN) ITH =1.35V 1.00 mmho Error Amplifier gm LSB Step Size I TH =1.35V 0.68 mmho RITHR0,1 Resolution 5 bits Compensation Resistor RITHR(MAX) 62 kΩ Compensation Resistor RITHR(MIN) 0 kΩ IISENSE ISENSE Current VISENSE = 40V l ±1 ±2 µA VI(lLIMIT) Resolution 3 bits VILIM(MAX) Hi Range Lo Range l l mV mV VILIM(MIN) Hi Range Lo Range 37.5 mV mV Gate Driver (DR VSET = 2) TG tr tf TG T ransition Time: Rise Time Fall Time (Note 4) C LOAD = 3300pF CLOAD = 3300pF ns ns BG t r tf BG T ransition Time: Rise Time Fall Time (Note 4) C LOAD = 3300pF CLOAD = 3300pF ns ns TG/BG t1D Top Gate Off to Bottom Gate On Delay Time (Note 4) C LOAD = 3300pF 50 ns BG/TG t2D Bottom Gate Off to Top Gate On Delay Time (Note 4) C LOAD = 3300pF 50 ns DCMAX Maximum Duty Cycle 92 %

Rev 0 For more information www.analog.com ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). VBIAS = 16V, EXTVCC = 0V, VRUN0 = 1.8V, VRUN1 = 1.8V fSYNC = 250kHz (externally driven), and all programmable parameters at factory default unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Charge Pump IBOOST Max Charge Pump Output Current V BOOST = 16.5V, VSW = 12V, fSYNC = 250kHZ VBOOST = 19V, VSW = 12V, fSYNC = 250kHZ µA µA OV/UV Output V oltage Supervisor N Resolution 9 Bits VRANGE0 Range 0 Maximum Threshold 60 V VRANGE1 Range 1 Maximum Threshold 30 V VOUSTP0 Range 0 Step Size, FSR = 63.078V (Note 10) 123.2 mV VOUSTP1 Range 1 Step Size, FSR = 31.539V 61.6 mV VTHACC0 Range 0 Threshold Accuracy 10V < VOUT < 60V l ±2.5 % VTHACC1 Range 1 Threshold Accuracy 5V < VOUT < 30V l ±2.5 % tPROPOV1 OV Comparator to FAUL T Low Time V OD = 10% of Threshold 35 µs tPROPUV1 UV Comparator to FAUL T Low Time V OD = 10% of Threshold 35 µs VIN1 Voltage Supervisor N Resolution 9 Bits VIN(RANGE) Maximum Threshold (Note 11) 21.8 V VIN(STP) Step Size 42.6 mV VIN(THACCH) Threshold Accuracy 6V < VIN1 < 20V l ±3 % tPROP(VIN) Comparator Response Time (VIN_ON and VIN_OFF) VOD = 10% of Threshold 100 µs Output Voltage Readback N Resolution LSB Step Size 977 Bits µV VF/S Full-Scale Sense Voltage (Note 10) VRUN = 0V (Note 8) 67.6 V VOUT_TUE Total Unadjusted Error TJ = 25°C, 8V < VOUT < 58V (Note 8) l 0.2 ±0.5 VOS Zero-Code Offset Voltage l ±3 mV tCONVERT Conversion Time (Note 6) 90 ms VIN1 Voltage Readback N Resolution (Note 5) 10 Bits VF/S Full-Scale Input Voltage (Note 11) 45 V VIN_TUE Total Unadjusted Error TJ = 25°C, 6V < VIN1 < 40V l 0.5 tCONVERT Conversion Time (Note 6) 100 ms Input Current Readback N Resolution LSB Step Size (Note 5) 0V ≤ |V ISENSE+ – VISENSE–| < 16mV 16mV ≤ |VISENSE+ – VISENSE–| < 32mV 32mV ≤ |VISENSE+ – VISENSE–| < 64mV 64mV ≤ |VISENSE+ – VISENSE–| < 100mV 15.26 30.52 122 Bits µV µV µV µV IF/S Full-Scale Output Current (Note 7) RISENSE = 1mΩ ±100 A IIN_TUE Total Unadjusted Error (Note 8) 10mV ≤ VISENSE ≤ 100mV l ±1.5 % VOS Zero-Code Offset Voltage ±32 µV tCONVERT Conversion Time (Note 6) 90 ms

Rev 0For more information www.analog.com ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). VBIAS = 16V, EXTVCC = 0V, VRUN0 = 1.8V, VRUN1 = 1.8V fSYNC = 250kHz (externally driven), and all programmable parameters at factory default unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Output Current Readback N Resolution LSB Step Size, Full-Scale Range = 16mV LSB Step Size, Full-Scale Range = 32mV LSB Step Size, Full-Scale Range = 64mV (Note 5) 8x Gain, 0V ≤ |IOUT+ – IOUT–| ≤ 5mV 4x Gain, 0V ≤ |IOUT+ – IOUT–| ≤ 20mV 2x Gain, 0V ≤ |IOUT+ – IOUT–| ≤ 50mV 15.26 30.52 Bits µV µV µV IOUT_TUE Total Unadjusted Error (Note 8) 8x Gain, 2.5mV ≤ |IOUT+ – IOUT–| ≤ 5mV 4x Gain, 4mV ≤ |IOUT+ – IOUT–| ≤ 20mV 2x Gain, 6mV ≤ |IOUT+ – IOUT–| ≤ 50mV l l l ±2.3 ±2.0 ±1.9 V OS Zero-Code Offset Voltage ±50 µV tCONVERT Conversion Time (Note 6) 90 ms Temperature Readback (T0, T1) TRES_T Resolution 0.25 °C T0_TUE External TSNS TUE (Note 8) MFR_PWM_MODE_LTC7880[5] = 0 MFR_PWM_MODE_LTC7880[5] = 1 V TSNS = 72mV (Note 17) VTSNS ≤ 1.85mV (Note 17) l l TI_TUE Internal TSNS TUE V RUN = 0.0V, fSYNC = 0kHz (Note 8) ±1 °C tCONVERT_T Update Rate (Note 6) 90 ms DRVCC Regulator VDRVCC_VBIAS DRVCC Voltage No Load 8V < VBIAS < 60V, DRVSET = 0 11V < VBIAS < 60V, DRVSET = 2 6.1 8.6 6.3 6.5 9.4 V V VLDO_VBIAS DRVCC Load Regulation ICC = 0mA to 50mA, EXTVCC = 0, DRVSET = 2 0.5 ±2 % VDRVCC_EXT DRVCC Voltage No Load 7V < EXTVCC < 14V, DRVSET = 0 11V < EXTVCC < 14V, DRVSET = 2 6.1 8.6 6.3 6.5 9.4 V V VLDO_EXT DRVCC Load Regulation ICC = 0mA to 50mA, EXTVCC = 12V, DRVSET = 2 0.5 ±2 % VEXT_THRES EXTVCC Switchover Voltage EXTVCC Ramping Positive, DRVSET = 0 EXTVCC Ramping Positive, DRVSET = 1, 2 l l 5.0 7.4 5.3 7.7 5.6 8.0 V V VEXT_HYS EXTVCC Hysteresis Voltage 80 mV VDD33 Regulator VDD33 Internal VDD33 Voltage 5.0V < VDRVCC 3.2 3.3 3.4 V ILIM VDD33 Current Limit VDD33 = GND, VIN = DRVCC = 5.0V 100 mA VDD33_OV VDD33 Overvoltage Threshold 3.5 V VDD33_UV VDD33 Undervoltage Threshold 3.1 V VDD25 Regulator VDD25 Internal VDD25 Voltage 2.5 V ILIM VDD25 Current Limit VDD25 = GND, VIN = DRVCC = 5.0V 80 mA Oscillator and Phase-Locked Loop fOSC Oscillator Frequency Accuracy 50kHz < fSYNC < 500kHz Measured Falling Edge-to-Falling Edge of SYNC with FREQUENCY_SWITCH = 100.0 and 500.0 l ±10 % VTH(SYNC) SYNC Input Threshold VCLKIN Falling VCLKIN Rising 1.5 V V VOL(SYNC) SYNC Low Output Voltage ILOAD = 3mA l 0.2 0.4 V ILEAK(SYNC SYNC Leakage Current in Slave Mode 0V ≤ V PIN ≤ 3.6V ±5 µA θSYNC-θ0 SYNC to Channel 0 Phase Relationship Based on the Falling Edge of Sync and Rising Edge of TG0 MFR_PWM_CONFIG_LTC7880[2:0] = 0,2,3 MFR_PWM_CONFIG_LTC7880[2:0] = 5 MFR_PWM_CONFIG_LTC7880[2:0] = 1 MFR_PWM_CONFIG_LTC7880[2:0] = 4,6 120 Deg Deg Deg Deg

Rev 0 For more information www.analog.com ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). VBIAS = 16V, EXTVCC = 0V, VRUN0 = 1.8V, VRUN1 = 1.8V fSYNC = 250kHz (externally driven), and all programmable parameters at factory default unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS θSYNC-θ1 SYNC to Channel 1 Phase Relationship Based on the Falling Edge of Sync and Rising Edge of TG1 MFR_PWM_CONFIG_LTC7880[2:0] = 3 MFR_PWM_CONFIG_LTC7880[2:0] = 0 MFR_PWM_CONFIG_LTC7880[2:0] = 2,4,5 MFR_PWM_CONFIG_LTC7880[2:0] = 1 MFR_PWM_CONFIG_LT C7880[2:0] = 6 120 180 240 270 300 Deg Deg Deg Deg Deg EEPROM Characteristics Endurance (Note 13) 0 °C < TJ < 85°C During EEPROM Write Operations l 10,000 Cycles Retention (Note 13) TJ < 125°C l 10 Years Mass_Write Mass Write Operation Time STORE_USER_ALL, 0°C < TJ ≤ 85°C During EEPROM Write Operations l 440 4100 ms Digital Inputs SCL, SDA, RUNn, FAUL Tn V IH Input High Threshold Voltage SCL, SDA, RUN, FAUL T l 1.35 V VIL Input Low Threshold Voltage SCL, SDA, RUN, FAUL T l 0.8 V VHYST Input Hysteresis SCL, SDA 0.08 V CPIN Input Capacitance 10 pF Digital Input WP I PUWP Input Pull-Up Current WP 10 µA Open-Drain Outputs SCL, SDA, FAUL Tn, ALERT, RUNn, SHARE_CLK, PGOODn V OL Output Low Voltage ISINK = 3mA l 0.4 V Digital Inputs SHARE_CLK, WP V IH Input High Threshold Voltage l 1.5 1.8 V VIL Input Low Threshold Voltage l 0.6 1.0 V Leakage Current SDA, SCL, ALERT, RUN I OL Input Leakage Current 0V ≤ VPIN ≤ 5.5V l ±5 µA Leakage Current FAUL Tn, PGOODn I GL Input Leakage Current 0V ≤ VPIN ≤ 3.6V l ±2 µA Digital Filtering of FAUL Tn t FAUL T Input Digital Filtering FAUL Tn 3 µs Digital Filtering of PGOODn t PGOOD Output Digital Filtering PG00Dn 60 µs Digital Filtering of RUNn t RUN Input Digital Filtering RUNn 10 µs PMBus Interface Timing Characteristics f SCL Serial Bus Operating Frequency l 10 400 kHz tBUF Bus Free Time Between Stop and Start l 1.3 µs tHD(STA) Hold Time After Start Condition. After This Period, the First Clock Is Generated l 0.6 µs tSU(STA) Repeated Start Condition Setup Time l 0.6 10000 µs tSU(STO) Stop Condition Setup Time l 0.6 µs tHD(DAT) Data Hold Time Receiving Data T ransmitting Data l l 0.3 0.9 µs µs tSU,DAT Data Setup Time Receiving Data l 0.1 µs

Rev 0For more information www.analog.com ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). VBIAS = 16V, EXTVCC = 0V, VRUN0 = 1.8V, VRUN1 = 1.8V fSYNC = 250kHz (externally driven), and all programmable parameters at factory default unless otherwise specified. Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC7880 is tested under pulsed load conditions such that T J ≈ TA. The LTC7880E is guaranteed to meet performance specifications from 0°C to 85°C. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC7880I is guaranteed over the –40°C to 125°C operating junction temperature range. TJ is calculated from the ambient temperature, TA, and power dissipation, PD, according to the following formula: TJ = TA + (PD • θJA) The maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. Note 3: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified. Note 4: Rise and fall times are measured using 10% and 90% levels. Delay times are measured using 50% levels. Note 5: The data format in PMBus is 5 bits exponent (signed) and 11 bits mantissa (signed). This limits the output resolution to 10 bits though the internal ADC is 16 bits and the calculations use 32-bit words. Note 6: The data conversion is done in round robin fashion. All inputs signals are continuously converted for a typical latency of 90ms unless the MFR_ADC_CONTROL command is utilized. Note 7: The IOUT_CAL_GAIN = 1.0mΩ and MFR_IOUT_TC = 0.0. Value as read from READ_IOUT in amperes. Note 8: Part tested with PWM disabled. Evaluation in application demonstrates capability. TUE (%) = ADC Gain Error (%) + 100 • [Zero Code Offset + ADC Linearity Error]/Actual Value. Note 9 : All VOUT commands assume the ADC is used to auto-zero the output to achieve the stated accuracy. LTC7880 is tested in a feedback loop that servos VOUT to a specified value. Note 10: The maximum programmable VOUT voltage is 60V. Note 11: The maximum VIN1 voltage is 40V. Note 12: When VBIAS < 6V, DRVCC must be tied to VBIAS. Note 13: EEPROM endurance is guaranteed by design, characterization and correlation with statistical process controls. Data retention is production tested via a high temperature bake at wafer level.The minimum retention specification applies for devices whose EEPROM has been cycled less than the minimum endurance specification. The RESTORE_USER_ALL command (EEPROM read) is valid over the entire operating temperature range. Note 14: The LTC7880 quiescent current (I Q) equals the IQ of VBIAS plus the IQ of EXTVCC. Note 15: The LTC7880 includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 16: Write operations above T J = 85°C or below 0°C are possible although the Electrical Characteristics are not guaranteed and the EEPROM will be degraded. Read operations performed at temperatures between –40°C and 125°C will not degrade the EEPROM. Writing to the EEPROM above 85°C will result in a degradation of retention characteristics. Note 17: Limits guaranteed by TSNS voltage and current measurements during test, including ADC readback. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS tTIMEOUT_SMB Stuck PMBus Timer Non-Block Reads Stuck PMBus Timer Block Reads Measured from the Last PMBus Start Event 32/255 255 ms ms tLOW Serial Clock Low Period l 1.3 10000 µs tHIGH Serial Clock High Period l 0.6 µs

Rev 0 For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS EXTVCC Switchover vs Temperature (DRVSET = 0) Load Step (Forced Continuous Mode) Load Step (Pulse-Skipping Mode) Inductor Current at Light Load Start-Up into a Pre-Biased Load Soft-Start Ramp Efficiency and Power Loss vs Load Current Efficiency and Power Loss vs Load Current Efficiency and Power Loss vs Input Voltage V IN = 12V V OUT = 24V f SW = 150kHz L = 6.8µH DCR = 1.86mΩ LOAD CURRENT (A) EFFICIENCY (%) POWER LOSS (W)

7880 G01

LOAD CURRENT (A) EFFICIENCY (%) POWER LOSS (W)

7880 G02

V IN = 12V V OUT = 48V f SW = 150kHz L = 6.8µH DCR = 1.86mΩ EFFICIENCY POWER LOSS V IN (V) 100 EFFICIENCY (%) POWER LOSS (W)

7880 G03

V OUT = 48V I LOAD = 5A f SW = 150kHz L = 6.8µH DCR = 1.86mΩ EFFICIENCY POWER LOSS FORCED CONTINUOUS MODE 2A/DIV PULSE-SKIPPING MODE 2A/DIV 1µs/DIVVIN = 12V VOUT = 24V ILOAD = 100µA

7880 G07

100µs/DIVVIN = 12V VOUT = 24V 0.2A TO 2A STEP

7880 G05

100µs/DIVVIN = 12V VOUT = 24V 0.2A TO 2A STEP

7880 G06

5ms/DIVtRISE = 10ms tDELAY = 5ms

7880 G08

5ms/DIVtRISE = 10ms tDELAY = 5ms

7880 G09

TA = 25C, VBIAS = 16V, EXTVCC = 0V, unless otherwise noted. TEMPERATURE (°C) –50 –25 100 125 5.34 5.35 5.36 5.37 5.38 5.39 5.40 EXTV CC (V)

7880 G04

Rev 0For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS SHARE_CLK Frequency vs Temperature Quiescent Current vs Temperature V OUT Measurement Error vs VOUT VOUT Command INL VOUT Command DNL DRVCC Line Regulation Soft-Off Ramp Regulated 12V Output Voltage vs Temperature Maximum Current Sense Threshold vs Duty Cycle, V OUT = 0V RUN 2V/DIV VOUT 10V/DIV 5ms/DIVtFALL = 5ms tDELAY = 10ms

7880 G10

TEMPERATURE (°C) –50 –25 100 125 11.980 11.984 11.988 11.992 11.996 12.000 12.004 V OUT (V)

7880 G11

DUTY CYCLE (%) 100 46.0 47.0 48.0 49.0 50.0 51.0 52.0 MAXIMUM CURRENT SENSE THRESHOLD (mV)

7880 G12

TEMPERATURE (°C) –50 SHARE_CLK FREQUENCY (kHz) 100 105 110 –25 0 25 50

7880 G13

(°C) –50 –25 100 125 21.4 21.6 21.8 22.0 22.2 22.4 CURRENT (mA)

7880 G14

V OUT (V) –5.0 –3.0 –1.0 1.0 3.0 5.0 ERROR (mV)

7880 G15

V OUT (V) –0.6 –0.2 0.2 0.6 1.0 1.4 INL (LSB)

7880 G16

V OUT (V) –0.4 –0.2 –0.1 0.1 0.2 0.4 DNL (LSB)

7880 G17

V IN (V) 5.0 5.3 5.6 5.9 6.2 6.5 DR VCC (V)

7880 G18

TA = 25C, VBIAS = 16V, EXTVCC = 0V, unless otherwise noted.

Rev 0 For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS External Temperature Error vs Temperature BOOST Charge Pump Output Voltage vs SW Voltage IOUT Error vs IOUT BOOST Charge Pump Charging Current vs Frequency I IN Error vs IIN BOOST Charge Pump Charging Current vs SW Voltage V OUT OV Threshold vs Temperature (12V Target) VOUT OV Threshold vs Temperature (24V Target) VOUT OV Threshold vs Temperature (48V Target) TEMPERATURE (°C) –50 –25 100 125 11.8 11.9 12.0 12.1 12.2 12V OV THRESHOLD (V)

7880 G19

(°C) –50 –25 100 125 23.8 23.9 24.0 24.1 24.2 24V OV THRESHOLD (V)

7880 G20

(°C) –50 –25 100 125 47.8 47.9 48.0 48.1 48.2 48V OV THRESHOLD (V)

7880 G21

TEMPERATURE (°C) –50 –1.0 MEASUREMENT ERROR (°C) –0.8 –0.4 –0.2 1.0 0.4 0 50 75

7880 G22

–0.6 0.6 0.8 0.2 –25 25 100 125 OUTPUT CURRENT (A) –20.0 –12.0 –4.0 4.0 12.0 20.0 MEASUREMENT ERROR (mA)

7880 G23

INPUT CURRENT (A) –20.0 –12.0 –4.0 4.0 12.0 20.0 MEASUREMENT ERROR (mA)

7880 G24

10MΩ Load Between BOOST and SW f SW = 250kHz 125°C –50°C 25°C SW VOL TAGE (V) 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 BOOST – SW VOL TAGE (V)

7880 G25

25°C 125°C –40°C V SW = 12V V BOOST = 16.5V OPERATING FREQUENCY (kHz) 100 200 300 400 500 20.0 40.0 60.0 80.0 100.0 CHARGE PUMP CHARGING CURRENT (µA)

7880 G26

f SW = 250kHz V BOOST – V SW = 7.0V V BOOST – V SW = 4.5V 125°C 25°C –40°C SW VOL TAGE (V) 12.0 24.0 36.0 48.0 60.0 72.0 84.0 96.0 108.0 120.0 CHARGE PUMP CHARGING CURRENT (µA)

7880 G27

TA = 25C, VBIAS = 16V, EXTVCC = 0V, unless otherwise noted.

Rev 0For more information www.analog.com PIN FUNCTIONS SW0/SW1 (Pins 1, 39): Switch Node Connections to Inductors. Voltage swings at the pins are from a diode voltage drop below ground to a diode voltage drop above V OUT. TG0/TG1 (Pins 2, 38): Top Gate Driver Outputs. These are the outputs of floating drivers with a voltage swing equal to DRV CC superimposed on the switch node voltages. VSENSE1+/VSENSE0+ (Pins 3, 45): Positive Output Voltage Sense Inputs. ISENSE0+/ISENSE1+ (Pins 4, 9): Current Sense Comparator Inputs. The (+) input to the current comparator is con - nected to the input voltage. I SENSE0–/ISENSE1– (Pins 5, 10): Current Sense Comparator Inputs. The (–) input to the current comparator is normally connected to the DCR sensing network or current sensing resistor . TSNS0/TSNS1 (Pins 6, 36): External Diode Temperature Sense. Connect to the anode of a diode-connected PNP transistor in order to sense remote temperature. Directly connect the cathode using a seperate ground return path to Pin 53 of the LTC7880. A bypass capacitor between the anode and cathode must be located in close proximity to the transistor . If external temperature sense elements are not installed, short pin to ground and set the UT_FAULT_LIMIT to –275°C and the UT_FAULT_RESPONSE to ignore. V IN0+/VIN1+ (Pins 7, 35): Input Voltage Sense Inputs. NC (Pin 8): No Connection. I THR0/ITHR1 (Pins 11, 32): Loop Compensation Nodes. ITH0/ITH1 (Pins 12, 31): Current Control Threshold and Error Amplifier Compensation Nodes. Each associated channel’s current comparator tripping threshold increases with its ITH voltage. SYNC (Pin 13): External Clock Synchronization Input and Open-Drain Output Pin. If an external clock is present at this pin, the switching frequency will be synchronized to the external clock. If clock master mode is enabled, this pin will pull low at the switching frequency with a 500ns pulse width to ground. A resistor pull-up to 3.3V is required in the application. SCL (Pin 14): Serial Bus Clock Input. Open-drain output, can hold the output low if clock stretching is enabled. A pull-up resistor to 3.3V is required in the application. SDA (Pin 15): Serial Bus Data Input and Output. A pull-up resistor to 3.3V is required in the application. ALERT (Pin 16): Open-Drain Digital Output. Connect the SMBALERT signal to this pin. A pull-up resistor to 3.3V is required in the application. FAUL T0/FAUL T1 (Pins 17, 18): Digital Programmable General Purpose Inputs and Outputs. Open-drain output. A pull-up resistor to 3.3V is required in the application. RUN0/RUN1 (Pins 19, 20): Enable Run Input and Output. Logic high on this pin enables the controller . Open-drain output holds the pin low until the LTC7880 is out of reset. This pin should be driven by an open-drain digital output. A pull-up resistor to 3.3V is required in the application. ASEL0/ASEL1 (Pin 21/Pin 22): Serial Bus Address Select Inputs. Connect optional 1% resistor dividers between V DD25 and GND to these pins to select the serial bus interface address. Refer to the Applications Information section for more detail. Minimize capacitance when the pin is open to assure accurate detection of the pin state. V OUT0_CFG/VOUT1_CFG (Pins 23, 24): Output Voltage Select Pins. Connect a ±1% resistor divider between the chip VDD25, VOUT_CFG and GND in order to select output voltage. If the pin is left open, the IC will use the value programmed in the EEPROM. Refer to the Applications Information section for more detail. Minimize capacitance when the pin is open to assure accurate detection of the pin state. FREQ_CFG (Pin 25): Frequency Select Pin. Connect a ±1% resistor divider between the chip V DD25 FREQ_CFG and GND in order to select switching frequency. If the pin is left open, the IC will use the value programmed in the EEPROM. Refer to the Applications Information section for more detail. Minimize capacitance when the pin is open to assure accurate detection of the pin state.

Rev 0 For more information www.analog.com PIN FUNCTIONS PHAS_CFG (Pin 26): Phase Configuration Input. Connect an optional 1% resistor divider between VDD25 and GND to this pin to configure the phase of each PWM channel relative to SYNC. Refer to the Applications Information section for more detail. Minimize capacitance when the pin is open to assure accurate detection of the pin state. V DD25 (Pin 27): Internally Generated 2.5V Power Sup - ply Output. Bypass this pin to GND with a low ESR 1μF capacitor . Do not load this pin externally except for the resistor dividers needed for the LTC7880 resistor con- figuration pins. WP (Pin 28): Write Protect Pin Active High. An internal 10µA current source pulls the pin to VDD33. If WP is high, the PMBus writes are restricted. SHARE_CLK (Pin 29): Share Clock, Bidirectional Open- Drain Clock Sharing Pin. Nominally 100kHz. Used to synchronize the timing between multiple L TC controllers. Tie all the SHARE_CLK pins together . All L TC controllers will synchronize to the fastest clock. A pull-up resistor of 5.49k to 3.3V is required in the application. V DD33 (Pin 30): Internally Generated 3.3V Power Supply Output. Bypass this pin to GND with a low ESR 1μF capaci- tor . Do not load this pin with external current. PGOO D0/PGOOD1 (Pins 34, 33): Power Good Indicator Outputs. Open-drain logic output that is pulled to ground when the output exceeds OV/UV thresholds. The output is deglitched by an internal 60μs filter. A pull-up resistor to 3.3V is required in the application. BOOST1/BOOST0 (Pins 40, 52): Boosted Floating Driver Supplies. The (+) terminal of the booststrap capacitor connects to this pin. This pin swings from a diode voltage drop below DRV CC up to VOUT + DRVCC. BG0/BG1 (Pins 50, 42): Bottom Gate Driver Outputs. This pin drives the gates of the bottom N-channel MOSFET between GND and DRV CC. EXTVCC (Pin 43): External power input to an internal LDO connected to DRV CC. This LDO supplies DRV CC power bypassing the internal LDO powered from VBIAS whenever EXTVCC is higher than 5.3V (7.7V if DRVSET = 1, 2). See EXTVCC connection in the Applications Information Sec - tion. Do not float or exceed 14V on this pin. Decouple this pin to GND with a minimum of 4.7μF low ESR tantalum or ceramic capacitor . If the EXTVCC pin is not used, tie the pin to GND. The EXTVCC pin may be connected to a higher voltage than the VBIAS pin. DRVCC (Pin 44): Output of the V BIAS or EXTV CC Low Dropout (LDO) Regulators. The gate drivers are powered from this voltage source. The DRV CC output voltage is set by the DRVSET command. The DRV CC pin must be decoupled to ground with a minimum of 4.7µF ceramic or other low ESR capacitor. Do not use the DRV CC pin for any other purpose. IOUT– (Pin 46): Negative Input of the channel 0 output current sense amplifier. Connect to the output voltage. I OUT+ (Pin 47): Positive Input of the channel 0 output current sense amplifier. Connect to the output current sense resistor. VBIAS (Pin 48): Main Input Supply. Decouple this pin to GND with a capacitor (0.1µF to 1µF). GND (Exposed Pad Pin 53): Ground. All small-signal and compensation components should connect to this ground, at one point.

7880 F01

Figure 1. Block Diagram, One of T wo Channels (CH0) Shown

Rev 0 For more information www.analog.com OPERATION OVERVIEW The LTC7880 is a dual channel/PolyPhase, constant fre- quency, analog current mode controller for DC/DC step-up applications with a digital inter face. The LTC7880 digital interface is compatible with PMBus which supports bus speeds of up to 400kHz. A typical application circuit is shown on the first page of this data sheet. Major features include: n Programmable Output V oltage n Programmable Input V oltage Comparator n Programmable Current Limit n Programmable Switching Frequency n Programmable OV and UV Comparators n Programmable On and Off Delay T imes n Programmable Output Rise/Fall T imes n Programmable Loop Compensation n Dedicated Power Good Pin for Each Channel n Phase-Locked Loop for Synchronous, PolyPhase Operation (2, 3, 4 or 6 Phases) n Input and Output V oltage/Current, and Temperature Telemetry n Fully Differential Remote Sense on Channel 0 n Integrated Gate Drivers n Nonvolatile Configuration Memor y with ECC n O ptional External Configuration Resistors for Key Operating Parameters n Optional T ime-Base Interconnect for Synchronization Between Multiple Controllers n Fault Logging n WP Pin to Protect Internal EEPROM Configuration n Standalone Operation After User Factor y Configuration n PMBus V ersion1.2, 400kHz Compliant Interface The PMBus interface provides access to important power management data during system operation including: n Internal Die T emperature n External System T emperature via Optional Diode Sense Elements n Average Output Current n Average Output V oltage n Average Input V oltage n Average Input Current n Configurable, Latched and Unlatched Individual Fault and W arning Status Individual channels are accessed through the PMBus using the PAGE command, i.e., PAGE 0 or 1. Fault reporting and shutdown behavior are fully configu- rable using the FAUL Tn outputs. A dedicated pin for ALERT is provided. The shutdown operation also allows all faults to be individually masked and can be operated in either unlatched (retr y) or latched modes. Individual status commands enable fault reporting over the serial bus to identify the specific fault event. Fault or warning detection includes the following: n Output Under voltage/Overvoltage n Input Under voltage/Overvoltage n Input and Output Over current n Internal Overtemperature n External Overtemperature n Communication, Memor y or Logic (CML) Fault MAIN CONTROL LOOP The LTC7880 is a constant-frequency, current-mode step-up controller that operates at a user-defined relative phasing. During normal operation the bottom MOSFET is turned on when the clock for that channel sets the RS latch, and is turned off when the main current comparator , I CMP , resets the RS latch. The peak inductor current at which I CMP resets the RS latch is controlled by the voltage on the

Rev 0For more information www.analog.com OPERATION ITH pin which is the output of the error amplifier , EA. The EA negative terminal is equal to the VSENSE voltage divided by 52 (26 if range = 1). The positive terminal of the EA is connected to the output of a 12-bit DAC with values ranging from 0V to 1.22V. The output voltage, through feedback of the EA, will be regulated to 52 times the DAC output (26 if range = 1). The DAC value is calculated by the part to synthesize the users desired output voltage. The output voltage is programmed by the user either with the resistor configuration pins detailed in Table 3 or by the V OUT command (either from EEPROM, or by PMBus command). Refer to the PMBus command section of the data sheet or the PMBus specification for more details. The output voltage can be modified by the user at any time with a PMBus VOUT_COMMAND. This command will typically have a latency less than 10ms. The current mode controller will turn off BG when the peak current is reached. If the load current increases, V SENSE will slightly droop with respect to the DAC reference. This causes the I TH voltage to increase until the average inductor current matches the new load current. After the bottom MOSFET has turned off, the top MOSFET is turned on. In continuous conduction mode, the top MOSFET stays on until the end of the switching cycle. EEPROM The LTC7880 contains internal EEPROM with error correc- tion coding (ECC) to store user configuration settings and fault log information. EEPROM endurance and retention for user space and fault log pages are specified in the Absolute Maximum Ratings and Electrical Characteristics table. The LTC7880 EEPROM also contains a manufacturing section that has internal redundancy. The integrity of the entire onboard EEPROM is checked with a CRC calculation each time its data is to be read, such as after a power-on reset or execution of a RESTORE_USER_ ALL command. If a CRC error occurs, the CML bit is set in the STATUS_BYTE and STATUS_WORD commands, the EEPROM CRC Error bit in the STATUS_MFR_SPECIFIC command is set, and the ALERT and RUN pins pulled low (PWM channels off). At that point the device will respond at special address 0x7C, which is activated only after an invalid CRC has been detected. The chip will also respond at the global addresses 0x5A and 0x5B, but use of these addresses when attempting to recover from a CRC issue is not recommended. All power supply rails associated with either PWM channel of a device reporting an invalid CRC will remain disabled until the issue is resolved. Contact the factory if EEPROM repair is unsuccessful. L TC recommends that the EEPROM not be written when die temperature is greater than 85°C. If internal die tem- perature exceeds 130°C, all EEPROM operations except RESTORE_USER_ALL and MFR_RESET are disabled. Full EEPROM operation is not re-enabled until die temperature falls below 125°C. Refer to the Applications Information section for equations to predict retention degradation due to elevated operating temperatures. See the Applications Information section or contact the factory for details on efficient in-system EEPROM program- ming, including bulk EEPROM programming, which the LT C7880 also supports. CRC Protection The integrity of the EEPROM memory is checked after a power-on reset. A CRC error will prevent the controller from leaving the reset state. If a CRC error occurs, the CML bit is set in the STATUS_BYTE and STATUS_WORD commands, the appropriate bit is set in the STATUS_MFR_SPECIFIC command, and the ALERT pin will be pulled low. EEPROM repair can be attempted by writing the desired configura- tion to the controller and executing a STORE_USER_ALL command followed by a CLEAR_FAULTS command. The LTC7880 protects the integrity of the manufacturing data and the user data by implementing ECC and CRC checks in the EEPROM. If the ECC cannot correct the con- tents of a single bit fault in the EEPROM, a CRC failure will occur . This assures that all double bit faults are detected. If the CRC checks fail in either the manufacturing or user data sections of the EEPROM, the “EEPROM CRC Fault” in the STATUS_MFR_SPECIFIC command is set. If this bit remains set after attempting to rewrite the user space and issuing a CLEAR_FAULTS or writing a 1 to this bit, an irrecoverable fault has occurred. There are no provisions for field repair of the EEPROM for these types of faults.

Rev 0 For more information www.analog.com OPERATION POWER-UP AND INITIALIZATION The LTC7880 is designed to provide standalone supply sequencing and controlled turn-on and turn-off operation. As shown in the Figure 1 block diagram, the LTC7880 can operate from a single V BIAS bias supply (5V to 40V) while two on-chip linear regulators generate internal 2.5V and 3.3V. If V BIAS does not exceed 6V, and the EXTVCC pin is not driven by an external supply, the DRV CC and V BIAS pins must be tied together . The LTC7880 EXTVCC pin can driven by an external supply to improve efficiency of the circuit and minimize power on the LTC7880. The EXTV CC pin must exceed approximately 5.3V (7.7V if DRVSET = 1, 2) before the DRV CC voltage LDO operates from the EXTVCC pin. To minimize application power , the EXTVCC pin can be supplied by a switching regulator , or an output of the LTC7880. The EXTV CC pin voltage may exceed the VBIAS pin voltage. The DRVCC voltage LDO operates from the EXTVCC pin if the EXTVCC voltage exceeds the VBIAS voltage by approximately 200mV. The controller configu- ration is initialized by an internal threshold based UVLO where V BIAS must be approximately 4.2V and the 3.3V and 2.5V linear regulators must be within approximately 20% of the regulated values. A PMBus RESTORE_USER_ALL or MFR_RESET command forces this same initialization. During initialization, the external configuration resistors are identified and/or contents of the EEPROM are read into the controller’s RAM. The BGn, TGn, PGOODn and RUNn pins are held low. The FAUL Tn pins are in high impedance mode. The LTC7880 will use the contents of Tables 3 to 6 to determine the resistor defined parameters. See the Resistor Configuration section for more detail. The resistor configuration pins only control some of the preset values of the controller . The remaining values are programmed in EEPROM either at the factory or by the user . If the configuration resistors are not inserted or if the ignore RCONFIG bit is asserted (bit 6 of the MFR_CONFIG_ ALL_LTC7880 configuration command), the LTC7880 will use only the contents of EEPROM to determine the configuration. The ASEL0 and ASEL1 values read at power- up or reset are always respected unless the pins are open. See the Applications Information section for more detail. After the part has initialized, an additional comparator moni- tors VIN1. The VIN_ON threshold must be exceeded before the output power sequencing can begin. After VBIAS power is initially applied, the part will typically require 35ms to initialize and begin the TON_DELAY timer . The read back of voltages and currents may require an additional 200ms to 300ms. SOFT-START The part must enter the run state prior to soft-start. The RUN pin is released by the LTC7880 after the part initial- izes and V IN1 is greater than the VIN_ON threshold. If multiple LTC7880s are used in an application, they all hold their respective run pins low until all devices initialize and V IN1 exceeds the VIN_ON threshold for every device. The SHARE_CLK pin assures all the devices connected to the signal use the same time base. The SHARE_CLK pin is held low until the part has initialized after V BIAS is applied and VIN1 exceeds the VIN_ON threshold. The LTC7880 can be set to turn off (or remain off) if SHARE_CLK is low (set bit 2 of MFR_CHAN_CONFIG_LTC7880 to a 1). This allows the user to assure synchronization across numerous ADI ICs even if the RUN pins can not be connected together due to board constraints. In general, if the user cares about synchronization between chips it is best to connect all the respective RUN pins together and to connect all the respective SHARE_CLK pins together and pull up to V DD33 with a 5.49k resistor . This assures all chips begin sequencing at the same time and use the same time base. After the RUNn pin releases and prior to entering a constant output voltage regulation state, the LTC7880 performs a monotonic initial ramp or “soft-start”. Refer to Figure 29 in the applications section for more detail. Soft-start is performed by actively regulating the load voltage while digitally ramping the target voltage from the MFR_VOUT_START command voltage value to the commanded voltage set-point. The boost voltage will start at VIN-VBE of the external FET . Set MFR_VOUT_START to the expected VIN voltage to assure the desired ramp characteristics. Once the LTC7880 is commanded to turn on, (after power up and initialization) the controller waits for the user specified turn-on delay (TON_DELAY) prior to initiating this output voltage ramp. The rise time of the voltage ramp can be programmed us- ing the TON_RISE command to minimize inrush currents associated with the start-up voltage ramp. The soft-start feature is disabled by setting the value of TON_RISE to any value less than 0.25ms. The LTC7880 PWM always uses

OUT is charged to approximately VIN. remain on unless commanded off.

7880 F02

Figure 2. Event (Voltage) Based Sequencing time will be set by the output capacitance and load current. the transfer of energy to the load as quickly as possible.

Rev 0 For more information www.analog.com OPERATION of the output is too long, it is possible to remove the volt- age requirement of the MFR_RETRY_DELAY command by asserting bit 0 of MFR_CHAN_CONFIG_LTC7880. Alternatively, the controller can be configured so that it remains latched-off following a fault and re-enabling the outputs requires user intervention such as toggling RUN or commanding the part OFF then ON. LIGHT-LOAD CURRENT OPERATION The LTC7880 has two PWM modes of operation, discon- tinuous conduction mode or forced continuous conduc- tion mode. Mode selection is done using the MFR_PWM_ MODE_LT C7880 command (discontinuous conduction is always the start-up mode, forced continuous is the default running mode). If a controller is enabled for discontinuous conduction operation, the inductor current is not allowed to reverse. The reverse current comparator , I REV , turns off the top gate external MOSFET just before the inductor current reaches zero, preventing it from reversing and going negative. In forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. The peak inductor current is determined solely by the voltage on the I TH pin. In this mode, the efficiency at light loads is lower than in discontinuous conduction operation. However , continuous mode exhibits lower output ripple and less interference with audio circuitry. OPERATION WHEN V IN > VOUT When the channel input voltage rises above the regulated VOUT voltage, the controller can behave differently depend- ing on the mode, inductor current and VIN voltage. In forced continuous mode, the loop works to keep the top MOSFET on continuously once V IN rises above VOUT. If VIN is above VOUT and the top gate is not asserted, VOUT will be pulled high by the parasitic diode in the top FET . To protect the FET an internal charge pump delivers current to the boost capacitor from the BOOST pin to maintain a sufficiently high TG voltage. In discontinuous mode, if V IN is above the regulated VOUT voltage, and below the input and output overvoltage thresholds, TG turns on if the inductor current rises above approximately 3% of the programmed I LIM current. If VIN rises above the input or output overvoltage thresholds in either continuous or discontinuous mode, the controller will respond according to the programmed input or output overvoltage fault response. BOOST Refresh and Internal Charge Pump Each top MOSFET driver is biased from the floating bootstrap capacitor , C BOOST, which normally recharges during each cycle through an external diode when the bottom MOSFET turns on. During start-up, if the bottom MOSFET is not turned on within 100µs after the channel is enabled, the bottom MOSFET will be forced to turn on for ~400ns. This forced refresh generates enough BOOST-SW voltage to allow the top MOSFET to be fully enhanced. The internal charge pump keeps the required bias on BOOSTn pin. The charge pump always operates in both continuous and discontinous mode. Operation at Low SENSE Pin Common Mode Voltage The I SENSE+and ISENSE– pins can operate at a common mode voltage as low as 2.5V, which is below the UVLO threshold of the V BIAS pin. The figure on the first page shows a typical application in which V BIAS is powered from VOUT while the VIN supply can go as low as 2.5V. An example of this situation is cold cranking in an automobile where the battery is loaded by the engine starting require- ments. If the voltage on I SENSE+ pin drops below 2.5V, the PWM operation will be disabled. In this configuration, the VIN_OFF command value must be set below 2.5V to prevent the part from stopping power conversion at low V IN1 voltages. PWM LOOP COMPENSATION The internal PWM loop compensation resistors R ITHn of the LTC7880 can be adjusted using bit[4:0] of the MFR_PWM_COMP command. The transcondutance of the LTC7880 PWM error amplifier can be adjusted using bit[7:5] of the MFR_PWM_COMP command. Refer to the Programmable Loop Compensation subsection in the Applications Information section for further details.

Rev 0For more information www.analog.com OPERATION SWITCHING FREQUENCY AND PHASE The switching frequency of the PWM can be established with an internal oscillator or an external time base. The internal phase-locked loop (PLL) synchronizes PWM control to this timing reference with proper phase rela - tion, whether the clock is provided internally or externally. The device can also be configured to provide the master clock to other ICs through PMBus command, EEPROM setting, or external configuration resistors as outlined in T ables 4 and 5. As clock master , the LTC7880 will drive its open-drain SYNC pin at the selected rate with a pulse width of 500ns. An external pull-up resistor between SYNC and V DD33 is required in this case. Only one device connected to SYNC should be designated to drive the pin. If multiple LTC7880s programmed as clock masters are wired to the same SYNC line with a pull-up resistor , just one of the devices is automatically elected to provide clocking, and the others disable their SYNC outputs. The LTC7880 will automatically accept an external SYNC input, disabling its own SYNC drive if necessary. Whether configured to drive SYNC or not, the LTC7880 can continue PWM operation using its own internal oscillator if an external clock signal is subsequently lost. The device can also be programmed to always require an external oscillator for PWM operation by setting bit 4 of MFR_CONFIG_ALL_LTC7880. The status of the SYNC driver circuit is indicated by bit 10 of MFR_PADS. The MFR_PWM_CONFIG_LTC7880 command can be used to configure the phase of each channel. Desired phase can also be set from EEPROM or external configuration resistors as outlined in Table 5. Designated phase is the relationship between the falling edge of SYNC and the internal clock edge that sets the PWM latch to turn on the top power switch. Additional small propagation delays to the PWM control pins will also apply. Both channels must be off before the FREQUENCY_SWITCH and MFR_PWM_CONFIG_LTC7880 commands can be written to the LTC7880. The phase relationships and frequency are independent of each other, providing numerous application options. Multiple LTC7880 ICs can be synchronized to realize a PolyPhase array. In this case the phases should be separated by 360/n degrees, where n is the number of phases driving the output voltage rail. OUTPUT VOL TAGE SENSING In high and low range, both the channel 0 sense pin (VSENSE0+) and channel 1 sense pin (VSENSE1+) are refer- enced to GND. The (telemetry) ADC is fully differential and makes measurements of channels 0 and 1 output voltages at the VSENSE0/GND and VSENSE1/GND pins, respectively. OUTPUT CURRENT SENSING To sense the total output current of the the power stage, a sense resistor is placed between the IOUT+ and IOUT– pins which are connected at the output of the power stage The filtered voltage is amplified by the internal high side current sense amplifier and digitized by the LTC7880’s telemetry ADC. The maximum differential sense voltage is 50mV. The LTC7880 computes the input current using the R value stored in the IOUT_CAL_GAIN command. The resulting measured powerstage current is returned by the READ_IOUT command. INPUT CURRENT SENSING The input current is sensed by the LTC7880 at the I SENSE0+ /ISENSE0- and ISENSE1+ /ISENSE1- pins. The LTC7880 sup- ports RSENSE or inductor DCR current sensing. Refer to the Low V alue Resistor Current Sensing and Inductor DCR Current Sensing subsections in the Applications Informa- tion section for further details. PolyPhase LOAD SHARING Multiple LTC7880’s can be connected in parallel in order to provide a balanced load-share solution by connecting the necessary pins. Figure 3 illustrates the shared con - nections required for load sharing. The SYNC pin should only be enabled on one of the LT C7880s. The other(s) should be programmed to dis - able SYNC with the oscillator frequency set to the nominal value. When bit [7] of the MFR_PWM_CONFIG command is set, Channel 1 will use the feedback node of Chan -

ITH pins are tied together . diode-connected PNP transistor such as the MMBT3906. BE measurement and calculation.

7880 F03

Figure 3. Load Sharing Connections for 3-Phase Operation

Rev 0For more information www.analog.com OPERATION the MFR_CONFIG_ALL_LTC7880 configuration command is asserted in EEPROM, the resistor inputs are ignored upon power-up except for ASEL0 and ASEL1 which are always respected. The resistor configuration pins are only measured during power-up and an execution of a RESTORE_USER_ALL or MFR_RESET command. The V OUTn_CFG pin settings are described in Table 3. These pins select the output voltages for the LTC7880’s analog PWM controllers. If the pin is open, the VOUT_COMMAND command is loaded from EEPROM to determine the output voltage. The default setting is to have the switcher off. If the VOUTn_CFG resistors are installed, the PWM opera- tion is set to the ON state. Otherwise the part defaults to the OFF state. The FREQ_CFG pin settings are described in Table 4. This pin selects the switching frequency. The phase relationships between the two channels and SYNC pin is determined by the PHAS_CFG pin described in Table 5. To synchronize to an external clock, the part should be put into external clock mode (SYNC output disabled but frequency set to the nominal value). If no external clock is supplied, the part will clock at the programmed frequency. If the applica- tion is multi-phase and the SYNC signal between chips is lost, the parts will not be at the same frequency increas- ing the ripple voltage on the output, possibly producing undesirable operation. If the external SYNC signal is being generated internally and external SYNC is not selected, bit 10 of MFR_PADS_LTC7880 will be asserted. If no frequency is selected and the external SYNC frequency is not present, a PLL_FAULT will occur . If the user does not wish to see the ALERT from a PLL_FAULT even if there is not a valid synchronization signal at power-up, the ALERT mask for PLL_FAULT must be written. See the description on SMBALERT_MASK for more details. If the SYNC pin is connected between multiple ICs only one of the ICs should have the SYNC pin enabled, all other ICs should be configured to SYNC pin disabled. The ASEL0 and ASEL1 pin settings are described in Table 6. ASEL1 selects the top 3 bits of the slave address for the LTC7880. ASEL0 selects the bottom 4 bits of the slave address for the LTC7880. If ASEL1 is floating, the 3 most significant bits are retrieved from the EEPROM MFR_ADDRESS command. If ASEL0 is floating, the 4 LSB bits stored in EEPROM MFR_ADDRESS command are used to determine the 4 LSB bits of the slave address. For more detail, refer to Table 6. Note: Per the PMBus specification, pin programmed pa- rameters can be overridden by commands from the digital inter face with the exception of the ASELn pins which are always honored. Do not set any part address to 0x5A or 0x5B because these are global addresses and all parts will respond to them. Refer to Application Note 152 for more information on power system management addressing. FAUL T HANDLING A variety of fault and warning reporting and handling mechanisms are available. Fault and warning detection capabilities include: n Input OV Fault Protection and UV W arn n Output OV /UV Fault and Warn Protection n Internal and External Overtemperature Fault and Warn Protection n External under -temperature, or UT , Fault Protection n CML Fault (Communication, Memor y or Logic) n External Fault Detection via the Bidirectional FAUL Tn Pins. The MFR_FAULT_PROPAGATE_LT C7880 command determines if the FAUL Tn pin is pulled low when a fault is detected. The LTC7880 can map any combination of fault indicators to the FAUL Tn pin using the propagate FAUL Tn response bits, MFR_FAULT_PROPAGATE_LTC7880. The FAUL Tn pin can be used as an input to detect external faults downstream of the controller that require an immediate response.

Rev 0 For more information www.analog.com OPERATION Any fault or warning event will cause the ALERT pin to assert low unless the fault or warning is masked by the SMBALERT_MASK. The pin will remain asserted low until the CLEAR_FAULTS command is issued, the device acknowledges the ARA, the fault bit is written to a 1, bias power is cycled or a MFR_RESET command is issued, the RUN pin is toggled OFF/ON, or the part is commanded OFF/ON via PMBus. Output and input fault event handling is controlled by the corresponding fault response byte as specified in Tables to 11. Shutdown from these types of faults can either be retr y or latched. For retry, the faults are not latched, so if the fault condition is not present after the retry interval has elapsed, a new soft-start is attempted. If the fault persists, the controller will continue to retry. The retry interval is specified by the MFR_RETRY_DELAY command and pre- vents damage to the regulator components by repetitive power cycling, assuming the fault condition itself is not immediately destructive. The MFR_RETRY_DELAY must be greater than 120ms. It can not exceed 83.88 seconds. Status Registers and ALERT Masking Figure 4 summarizes the internal LTC7880 status reg - isters accessible by PMBus command. These contain indication of various faults, warnings and other important operating conditions. As shown, the STATUS_BYTE and STATUS_WORD commands also summarize contents of other status registers. Refer to PMBus Command Details for specific information. NONE OF THE ABOVE in STATUS_BYTE indicates that one or more of the bits in the most-significant byte of STATUS_WORD are also set. In general, any asserted bit in a STATUS_x register also pulls the ALERT pin low. The SMBALERT_MASK command can be used to prevent the LTC7880 from asserting ALERT low with some minor exceptions. STATUS_ events that cause ALERT to be as- serted low can be masked by setting the corresponding ST ATUS_ bit in the SMBALERT_MASK command. These mask settings apply to STATUS_WORD and STATUS_BYTE in the same fashion as the status bits themselves. For example, if ALERT is masked for all bits in Channel 0 STATUS_VOUT, then ALERT is effectively masked for the V OUT bit in STATUS_WORD for PAGE 0. The BUSY bit in STATUS_BYTE also asserts ALERT low and can be masked. This bit can be set as a result of vari- ous internal interactions with PMBus communication. This fault occurs when a command is received that cannot be safely executed with one or both channels enabled. As discussed in Application Information, BUSY faults can be avoided by polling MFR_COMMON before executing some commands. If the user’s PMBus system can tolerate clock stretching, most, if not all, BUSY faults can be avoided by enabling CLOCK STRETCHING by setting bit 1 of the MFR_CONFIG_ ALL to a value of 1. If masked faults occur immediately after power up, ALERT may still be pulled low because there has not been time to retrieve all of the programmed masking information from EEPROM. Status information contained in MFR_COMMON and MFR_PADS can be used to further debug or clarify the contents of STATUS_BYTE or STATUS_WORD as shown, but the contents of these registers may not affect the state of the ALERT pin and may not directly influence bits in STATUS_BYTE or STATUS_WORD.

7880 F04

Figure 4. LTC7880 Status Register Summary

Rev 0 For more information www.analog.com OPERATION Mapping Faults to FAUL T Pins The FAUL Tn pins of the LTC7880 can share faults between channels and with all L TC PMBus products including the LTC3880, LTC2974, LTC2977, LTM4676 µModule®, etc. In the event of an internal fault, one or more of the LTC7880s is configured to pull the bussed FAUL Tn pins low. The other LTC7880s are then configured to shut down when the FAUL Tn pin bus is pulled low. For autonomous group retry, the faulted LTC7880 channel is configured to release the FAUL Tn pin bus after a retry interval, assuming the original fault has cleared. All the channels in the group then begin a soft-start sequence. If the fault response is LATCH_OFF, the FAUL Tn pin remains asserted low until either the RUN pin is toggled OFF/ON or the part is commanded OFF/ON. The toggling of the RUN either by the pin or OFF/ON com- mand will clear faults associated with the LTC7880. If it is desired to have all faults cleared when either RUN pin is toggled, set bit 0 of MFR_CONFIG_ALL_LTC7880 to a 1. The status of all faults and warnings is summarized in the STATUS_WORD and STATUS_BYTE commands. Power Good Pins The PGOODn pins of the LTC7880 are connected to the open drains of internal MOSFETs. The MOSFETs pull the PGOODn pins low when the channel output voltage is not within the channels UV and OV voltage thresholds. During TON_DELAY and TON_RISE sequencing, the PGn pin is held low. The PGOODn pin is also pulled low when the respective RUNn pin is low. The PGOODn pin response is deglitched by an internal 60µs digital filter . The PGOODn pin and PGOOD status may be different at times due to internal communication latency of up to 10µs. SERIAL INTERFACE The LTC7880 serial interface is a PMBus compliant slave device and can operate at any frequency between 10kHz and 400kHz. The address is configurable using either the EEPROM or an external resistor divider . In addition the LTC7880 always responds to the global broadcast address of 0x5A (7-bit address) or 0x5B (7-bit address). The serial interface supports the following protocols de- fined in the PMBus specifications: 1) send command, 2) write byte, 3) write word, 4) group, 5) read byte, 6) read word, 7) read block, 8) write block, 9) PAGE_PLUS_READ, 10) PAGE_PLUS_WRITE, 11) SMBALERT_MASK read and 12) SMBALERT_MASK. All read operations will return a valid PEC if the PMBus master requests it. If the PEC_ REQUIRED bit is set in the MFR_CONFIG_ALL_LTC7880 command, the PMBus write operations will not be acted upon until a valid PEC has been received by the LTC7880. Communication Protection PEC write errors (if PEC_REQUIRED is active), will re - sult in a CML fault. If PEC is active, the communication must have the correct PEC byte or the command will be ignored. If PEC is not active but the communication is sent with PEC, the LTC7880 will process the command correctly. If there is a PEC error the part will respond with a CML Packet Error Check Failed. The CML bit is set in the STATUS_BYTE and STATUS_WORD commands, the appropriate bit is set in the STATUS_CML command, and the ALERT pin is pulled low. DEVICE ADDRESSING The LTC7880 offers four different types of addressing over the PMBus interface, specifically: 1) global, 2) device, 3) rail addressing and 4) alert response address (ARA). Global addressing provides a means of the PMBus master to address all LTC7880 devices on the bus. The LTC7880 global address is fixed 0x5A (7-bit address), 0xB4 (8-bit address) is not paged and cannot be disabled. Commands sent to the global address act the same as if PAGE is set to a value of 0xFF . Commands sent are written to both channels simultaneously. Global command 0x5B (7-bit address), 0xB6 (8-bit address) is paged and allows channel specific command of all LTC7880 devices on the bus. Other L TC device types may respond at one or both of these global addresses; therefore do not read from global addresses. Rail addressing provides a means for the bus master to simultaneously communicate with all channels connected together to produce a single output voltage (PolyPhase). While similar to global addressing, the rail address can be dynamically assigned with the paged MFR_RAIL_ ADDRESS command, allowing for any logical grouping of channels that might be required for reliable system

Rev 0For more information www.analog.com control. Do not read from rail addresses since multiple L TC devices may respond. Device addressing provides the standard means of the PMBus master communicating with a single instance of an LTC7880. The value of the device address is set by a combination of the ASEL0 and ASEL1 configuration pins and the MFR_ADDRESS command. Device address - ing can be disabled by writing a value of 0x80 to the MFR_ADDRESS. All four means of PMBus addressing require the user to employ disciplined planning to avoid addressing conflicts. Communication to LTC7880 devices at global and rail ad- dresses should be limited to command write operations. RESPONSES TO VOUT FAUL TS VOUT OV and UV conditions are monitored by comparators. The OV and UV limits are set in three ways. n As a Per centage of the V OUT if Using the Resistor Con- figuration Pins n In EEPROM if Either Programmed at the Factor y or Through the GUI n By PMBus Command The digital processor within the LTC7880 provides the ability to ignore the fault, shut down and latch off or shut down and retry indefinitely (retry). The hardware response to an OV cannot be disabled see the next section for more detail. The retry interval is set in MFR_RETRY_DELAY and can be from 120ms to 83.88 seconds in 1ms increments. The shutdown for V OUT OV/UV can be done immediately or after a user selectable deglitch time. OPERATION Output Overvoltage Fault Response A programmable overvoltage comparator (OV) guards against transient overshoots as well as long-term over- voltages at the output. In such cases, the bottom MOSFET is turned off and the top MOSFET is turned on until the overvoltage condition is cleared. The analog OV response of asserting the top gate cannot be ignored but the digital response can disable the channel if an OV fault is detected. This minimizes the power dissipation in the body diode of the top MOSFET . This hardware level fault response delay is typically 2µs from the overvoltage condition to TG asserted high. Using the VOUT_OV_FAULT_RESPONSE command, the user can select any of the following behaviors: n Ignore (Recommended) This will turn on the TG signal. n Shut Down (Stop Switching) Immediately —Latch Off This will turn off the TG signal. n Shut Down Immediately —Retry Indefinitely Using the Time Interval Specified in MFR_RETRY_DELAY Either the Latch Off or Retry fault responses can be deglitched in increments of (0-7) • 10µs. See Table 7. Output Under voltage Response The response to an undervoltage comparator output can be either: n Ignore n Shut Down Immediately —Latch Off n Shut Down Immediately —Retry Indefinitely Using the Time Interval Specified in MFR_RETRY_DELAY The UV responses can be deglitched. See Table 8.

Rev 0 For more information www.analog.com OPERATION Peak Input Overcurrent Response Due to the current mode control algorithm, peak output current across the inductor is always limited on a cycle by cycle basis. The value of the peak current limit is specified as the voltage across the I SENSEn+ and ISENSEn− pins. The current limit circuit operates by limiting the ITH maximum voltage. If DCR sensing is used, the ITH maximum voltage has a temperature dependency directly proportional to the TC of the DCR of the inductor . The LTC7880 automatically monitors the external temperature sensors and modifies the maximum allowed I TH to compensate for this term. RESPONSES TO TIMING FAUL TS TON_MAX_FAULT_LIMIT is the time allowed for VOUT to rise and settle at start-up. The TON_MAX_FAULT_LIMIT condition depends on crossing the VOUT_UV_FAULT_ LIMIT as the output is undergoing a soft-start sequence. The TON_MAX_FAULT_LIMIT time is started after TON_DELAY has been reached and a soft-start sequence is started. The resolution of the TON_MAX_FAULT_LIMIT is 10µs. If the VOUT_UV_FAULT_LIMIT is not reached within the TON_MAX_FAULT_LIMIT time, the response of this fault is determined by the value of the TON_MAX_ FAULT_RESPONSE command value. This response may be one of the following: n Ignore n Shut Down (Stop Switching) Immediately —Latch Off n Shut Down Immediately —Retry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY This fault response is not deglitched. A value of 0 in TON_MAX_FAULT_LIMIT means the fault is ignored. The TON_MAX_FAULT_LIMIT should be set longer than the TON_RISE time. See Table 10. RESPONSES TO V IN OV FAUL TS VIN overvoltage is measured with the ADC. The response is deglitched by the 90ms typical response time of the ADC. The fault responses are: n Ignore (Recommended) n Shut Down Immediately —Latch Off n Shut Down Immediately —Retry Indefinitely Using the Time Interval Specified in MFR_RETRY_DELAY See Table 10. RESPONSES TO OT/UT FAUL TS Internal Overtemperature Fault/Warn Response An internal temperature sensor protects against EEPROM damage. Above 85°C, no writes to EEPROM are recom - mended. Above 130°C , the internal overtemperature warn threshold is exceeded and the part will NACK any EEPROM related command except RESTORE_USER_ALL or MFR_RESET and issue a CML fault for Invalid/Unsup- ported Command. Full EEPROM operation is re-enabled when the internal temperature has dropped below 125°C. When the die temperature exceeds 160°C the internal overtemperature fault response is enabled and the PWM is disabled until the die temperature drops below 150°C. Temperature is measured by the ADC. Internal tempera- ture faults cannot be ignored. Internal temperature limits cannot be adjusted by the user See Table 9. External Overtemperature and Undertemperature Fault Response An external temperature sensor can be used to sense critical cir cuit elements like the inductor and power MOSFETs. The OT_FAULT_RESPONSE and UT_FAULT_

Rev 0For more information www.analog.com OPERATION RESPONSE commands are used to determine the appropri- ate response to an overtemperature and undertemperature condition, respectively . If no external sense element is used (not recommended) set the UT_FAULT_RESPONSE to ignore and set the UT_FAULT_LIMIT to –275°C. However , not using an external temperature sense element is not recommended. The fault responses are: n Ignore n Shut Down Immediately —Latch Off n Shut Down Immediately —Retry Indefinitely Using the Time Interval Specified in MFR_RETRY_DELAY See Table 10. RESPONSES TO EXTERNAL FAUL TS When either FAUL Tn pin is pulled low, the respective FAUL Tn bit is deasserted in the MFR_PADS command, the FAUL Tn bit is set in the STATUS_MFR_SPECIFC command, the NONE_OF_THE_ABOVE bit is set in the STATUS_BYTE command, and the ALERT pin is pulled low. Responses are not deglitched. Each channel can be configured to ignore or shut down then retry in response to its FAUL Tn pin going low by modifying the MFR_FAULT_RESPONSE command. To avoid the ALERT pin asserting low when FAUL T is pulled low, assert bit 1 of MFR_CHAN_CONFIG_LTC7880, or mask the ALERT using the SMBALERT_MASK command. FAUL T LOGGING The LTC7880 has fault logging capability. Data is logged into memory in the order shown in Table 12. The data is stored in a continuously updated buffer in RAM. When a fault event occurs, the fault log buffer is copied from the RAM buffer into EEPROM. Fault logging is allowed at temperatures above 85°C; however , retention of 10 years is not guaranteed. When the die temperature exceeds 130°C, the fault logging is delayed until the die temperature drops below 125°C. The fault log data remains in EEPROM until a MFR_FAULT_LOG_CLEAR command is issued. Issuing this command re-enables the fault log feature. Before re-enabling fault log, be sure no faults are present and a CLEAR_FAULTS command has been issued. When the LTC7880 powers-up or exits reset state, it checks the EEPROM for a valid fault log. If a valid fault log exists in EEPROM, the “Valid Fault Log” bit in the STATUS_MFR_SPECIFIC command will be set and an ALERT event will be generated. Also, fault log - ging will be blocked until the LTC7880 has received a MFR _FAULT_LOG_CLEAR command before fault logging will be re-enabled. The information is stored in EEPROM in the event of any fault that disables the controller . The FAUL Tn pin being externally pulled low will not trigger a fault logging event. BUS TIMEOUT PROTECTION The LTC7880 implements a timeout feature to avoid per- sistant faults on the serial interface. The data packet timer begins at the first ST ART event before the device address write byte. Data packet information must be completed within 30ms or the LTC7880 will three-state the bus and ignore the given data packet. If more time is required, assert bit 3 of MFR_CONFIG_ALL_LTC 7880 to allow typical bus timeouts of 255ms. Data packet information includes the device address byte write, command byte, repeat start event (if a read operation), device address byte read (if a read operation), all data bytes and the PEC byte if applicable. The LTC7880 allows for PMBus timeouts proportional to the length of the block read data packets. The part will add 1ms for every byte of length in excess of 32 bytes. The additional block read timeout applies primarily to the MFR_FAULT_LOG command. The timeout period defaults to 30ms. The user is encouraged to use as high a clock rate as possible to maintain efficient data packet transfer between all devices sharing the serial bus interface. The LTC7880 supports the full PMBus frequency range from 10kHz to 400kHz.

Figure 5. Timing Diagram Table 1. Abbreviations of Supported Data Formats two’s compliment binary integers. where Y = b[15:0], an unsigned integer .

Figure 6. PMBus Packet Protocol Diagram Element Key Figure 7. Quick Command Protocol Figure 8. Send Byte Protocol Figure 9. Send Byte Protocol with PEC Figure 10. Write Byte Protocol Figure 11. Write Byte Protocol with PEC Figure 12. Write Word Protocol Figure 13. Write Word Protocol with PEC

7880 F06

7880 F07

7880 F08

7880 F09

7880 F10

7880 F11

7880 F12

7880 F13

7880 F19

Figure 14. Read Byte Protocol Figure 15. Read Byte Protocol with PEC Figure 16. Read Word Protocol Figure 17. Read Word Protocol with PEC Figure 18. Block Read Protocol Figure 19. Block Read Protocol with PEC

7880 F14

7880 F15

7880 F16

7880 F17

7880 F18

Figure 20. Block Write – Block Read Process Call Figure 21. Block Write – Block Read Process Call with PEC Figure 22. Alert Response Address Protocol Figure 23. Alert Response Address Protocol with PEC

7880 F20

7880 F21

7880 F22

7880 F23

Table 2. Summary (Note: The Data Format abbreviations are detailed at the end of this table.) protocols supported by this device.

Rev 0 For more information www.analog.com PMBus COMMAND SUMMARY COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS EEPROM DEFAUL T VALUE PAGE VOUT_MARGIN_LOW 0x26 Margin low output voltage set point. Must be less than VOUT_COMMAND. R/W Word Y L16 V Y 22.8 0x5B33 VOUT_TRANSITION_ RATE 0X27 Rate the output changes when VOUT commanded to a new value. R/W Word Y L11 V/ms Y 0.25 0xAA00 FREQUENCY_SWITCH 0x33 Switching frequency of the controller . R/W Word N L11 kHz Y 250 0xF3E8 VIN_ON 0x35 Input voltage at which the unit should start power conversion. R/W Word N L11 V Y 6.5 0xCB40 VIN_OFF 0x36 Input voltage at which the unit should stop power conversion. R/W Word N L11 V Y 6.0 0xCB00 IOUT_CAL_GAIN 0x38 The ratio of the voltage at the current sense pins to the sensed current. For devices using a fixed current sense resistor , it is the resistance value in mΩ. R/W Word N L11 mΩ Y 5.0 0xCA80 VOUT_OV_FAULT_LIMIT 0x40 Output overvoltage fault limit. R/W Word Y L16 V Y 26.4 0x699A VOUT_OV_FAULT_ RESPONSE 0x41 Action to be taken by the device when an output overvoltage fault is detected. R/W Byte Y Reg Y 0x00 VOUT_OV_WARN_LIMIT 0x42 Output overvoltage warning limit. R/W Word Y L16 V Y 25.8 0x6733 VOUT_UV_WARN_LIMIT 0x43 Output undervoltage warning limit. R/W Word Y L16 V Y 22.2 0x58CD VOUT_UV_FAULT_LIMIT 0x44 Output undervoltage fault limit. R/W Word Y L16 V Y 21.6 0x5666 VOUT_UV_FAULT_ RESPONSE 0x45 Action to be taken by the device when an output undervoltage fault is detected. R/W Byte Y Reg Y 0xB8 OT_FAULT_LIMIT 0x4F External overtemperature fault limit. R/W Word Y L11 C Y 100.0 0xEB20 OT_FAULT_RESPONSE 0x50 Action to be taken by the device when an external overtemperature fault is detected, R/W Byte Y Reg Y 0xB8 90 OT_WARN_LIMIT 0x51 External overtemperature warning limit. R/W Word Y L11 C Y 85.0 0xEAA8 UT_FAULT_LIMIT 0x53 External undertemperature fault limit. R/W Word Y L11 C Y –40.0 0xE580 UT_FAULT_RESPONSE 0x54 Action to be taken by the device when an external undertemperature fault is detected. R/W Byte Y Reg Y 0xB8 91 VIN_OV_FAULT_LIMIT 0x55 Input supply overvoltage fault limit. R/W Word N L11 V Y 40 0xE280 VIN_OV_FAULT_ RESPONSE 0x56 Action to be taken by the device when an input overvoltage fault is detected. R/W Byte Y Reg Y 0x00 VIN_UV_WARN_LIMIT 0x58 Input supply undervoltage warning limit. R/W Word N L11 V Y 6.3 0xCB26 IIN_OC_FAULT_LIMIT 0x5B Input Overcurrent Fault Limit R/W Word Y L11 A Y 25 0xDB20 TON_DELAY 0x60 Time from RUN and/or Operation on to output rail turn-on. R/W Word Y L11 ms Y 0.0 0x8000 TON_RISE 0x61 Time from when the output starts to rise until the output voltage reaches the VOUT commanded value. R/W Word Y L11 ms Y 8.0 0xD200

Rev 0For more information www.analog.com PMBus COMMAND SUMMARY COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS EEPROM DEFAUL T VALUE PAGE TON_MAX_FAULT_LIMIT 0x62 Maximum time from the start of TON_RISE for VOUT to cross the VOUT_UV_FAULT_LIMIT. R/W Word Y L11 ms Y 10.00 0xD280 TON_MAX_FAULT_ RESPONSE 0x63 Action to be taken by the device when a TON_ MAX_FAULT event is detected. R/W Byte Y Reg Y 0xB8 89 TOFF_DELAY 0x64 Time from RUN and/or Operation off to the start of TOFF_FALL ramp. R/W Word Y L11 ms Y 0.0 0x8000 TOFF_FALL 0x65 Time from when the output starts to fall until the output reaches zero volts. R/W Word Y L11 ms Y 8.00 0xD200 TOFF_MAX_WARN_ LIMIT 0x66 Maximum allowed time, after TOFF_FALL completed, for the unit to decay below 12.5%. R/W Word Y L11 ms Y 150.0 0xF258 STATUS_BYTE 0x78 One byte summary of the unit’s fault condition. R/W Byte Y Reg NA 98 STATUS_WORD 0x79 T wo byte summary of the unit’s fault condition. R/W Word Y Reg NA 98 STATUS_VOUT 0x7A Output voltage fault and warning status. R/W Byte Y Reg NA 99 STATUS_INPUT 0x7C Input supply fault and warning status. R/W Byte N Reg NA 99 STATUS_TEMPERATURE 0x7D External temperature fault and warning status for READ_TEMERATURE_1. R/W Byte Y Reg NA 100 STATUS_CML 0x7E Communication and memory fault and warning status. R/W Byte N Reg NA 100 STATUS_MFR_SPECIFIC 0x80 Manufacturer specific fault and state information. R/W Byte Y Reg NA 101 READ_VIN 0x88 Measured input supply voltage at the V IN1 pin. R Word N L11 V NA 103 READ_IIN 0x89 Measured input supply current. R Word Y L11 A NA 103 READ_VOUT 0x8B Measured output voltage. R Word Y L16 V NA 103 READ_IOUT 0x8C Measured channel 0 output current. R Word N L11 A NA 104 READ_TEMPERATURE_1 0x8D External temperature sensor temperature. This is the value used for all temperature related processing, including MFR_IIN_CAL_GAIN. R Word Y L11 C NA 104 READ_TEMPERATURE_2 0x8E Internal die junction temperature. Does not affect any other commands. R Word N L11 C NA 104 READ_FREQUENCY 0x95 Measured PWM switching frequency. R Word N L11 kHz NA 104 READ_POUT 0x96 Calculated output power . R Word N L11 W NA 104 READ_PIN 0x97 Calculated input power R Word Y L11 W NA 104 PMBUS_REVISION 0x98 PMBus revision supported by this device. Current revision is 1.2. R Byte N Reg 0x22 95 MFR_ID 0x99 The manufacturer ID of the LTC7880 in ASCII. R String N ASC LT C 95 MFR_MODEL 0x9A Manufacturer part number in ASCII. R String N ASC LTC7880 95 MFR_VOUT_MAX 0xA5 Maximum allowed output voltage including VOUT_OV_FAULT_LIMIT. R Word Y L16 V 60 0xF000 IC_DEVICE_ID 0xAD Identification of the IC R String N ASC LTC7880 95 IC_DEVICE_REV 0xAE Revision of the IC R String N ASC ACA0 95 USER_DATA_00 0xB0 OEM RESERVED. Typically used for part serialization. R/W Word N Reg Y NA 94 USER_DATA_01 0xB1 Manufacturer reserved for L TpowerPlay. R/W Word Y Reg Y NA 94

Rev 0 For more information www.analog.com PMBus COMMAND SUMMARY COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS EEPROM DEFAUL T VALUE PAGE USER_DATA_02 0xB2 OEM RESERVED. Typically used for part serialization R/W Word N Reg Y NA 94 USER_DATA_03 0xB3 An EEPROM word available for the user . R/W Word Y Reg Y 0x0000 94 USER_DATA_04 0xB4 An EEPROM word available for the user . R/W Word N Reg Y 0x0000 94 MFR_INFO 0xB6 Manufacturing specific information. R Word N Reg NA 102 MFR_EE_UNLOCK 0xBD Contact factory. NA 112 MFR_EE_ERASE 0xBE Contact factory. NA 112 MFR_EE_DATA 0xBF Contact factory. NA 112 MFR_CHAN_CONFIG_ LTC7880 0xD0 Configuration bits that are channel specific. R/W Byte Y Reg Y 0x1D 70 MFR_CONFIG_ALL_ LTC7880 0xD1 General configuration bits. R/W Byte N Reg Y 0x21 MFR_FAULT_ PROPAGATE_LTC7880 0xD2 Configuration that determines which faults are propagated to the FAUL T pin. R/W Word Y Reg Y 0x6993 MFR_PWM_COMP 0xD3 PWM loop compensation configuration R/W Byte Y Reg Y 0x70 73 MFR_PWM_MODE_ LTC7880 0xD4 Configuration for the PWM engine. R/W Byte Y Reg Y 0xC1 MFR_FAULT_RESPONSE 0xD5 Action to be taken by the device when the FAUL T pin is externally asserted low. R/W Byte Y Reg Y 0xC0 93 MFR_OT_FAULT_ RESPONSE 0xD6 Action to be taken by the device when an internal overtemperature fault is detected. R Byte N Reg 0xC0 MFR_IOUT_PEAK 0xD7 Report the maximum measured value of READ_IOUT since last MFR_CLEAR_PEAKS. R Word N L11 A NA 104 MFR_ADC_CONTROL 0xD8 ADC telemetry parameter selected for repeated fast ADC read back R/W Byte N Reg 0x00 105 MFR_VOUT_START 0xDA Start voltage of rising output voltage ramp. Stop voltage of falling output voltage ramp. R/W Word Y L16 V Y 18 0x4800 MFR_RETRY_DELAY 0xDB Retry interval during FAUL T retry mode. R/W Word Y L11 ms Y 350.0 0xFABC MFR_RESTART_DELAY 0xDC Minimum time the RUN pin is held low by the LTC7880. R/W Word Y L11 ms Y 500.0 0xFBE8 MFR_VOUT_PEAK 0xDD Maximum measured value of READ_VOUT since last MFR_CLEAR_PEAKS. R Word Y L16 V NA 105 MFR_VIN_PEAK 0xDE Maximum measured value of READ_VIN since last MFR_CLEAR_PEAKS. R Word N L11 V NA 105 MFR_TEMPERATURE_1_ PEAK 0xDF Maximum measured value of external Temperature (READ_TEMPERATURE_1) since last MFR_CLEAR_PEAKS. R Word Y L11 C NA 106 MFR_IIN_PEAK 0xE1 Maximum measured value of READ_IIN command since last MFR_CLEAR_PEAKS R Word Y L11 A NA 106 MFR_CLEAR_PEAKS 0xE3 Clears all peak values. Send Byte N NA 98 MFR_PADS 0xE5 Digital status of the I/O pads. R Word N Reg NA 101 MFR_ADDRESS 0xE6 Sets the 7-bit I 2C address byte. R/W Byte N Reg Y 0x4F 69 MFR_SPECIAL_ID 0xE7 Manufacturer code representing the LTC7880 and revision R Word N Reg 0x49EX 95

Rev 0For more information www.analog.com PMBus COMMAND SUMMARY COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS EEPROM DEFAUL T VALUE PAGE MFR_IIN_CAL_GAIN 0xE8 The resistance value of the input current sense element in mΩ. R/W Word Y L11 mΩ Y 3.0 0xC300 MFR_FAULT_LOG_ STORE 0xEA Command a transfer of the fault log from RAM to EEPROM. Send Byte N NA 108 MFR_FAULT_LOG_ CLEAR 0xEC Initialize the EEPROM block reserved for fault logging. Send Byte N NA 112 MFR_FAULT_LOG 0xEE Fault log data bytes. R Block N Reg Y NA 108 MFR_COMMON 0xEF Manufacturer status bits that are common across multiple L TC chips. R Byte N Reg NA 102 MFR_COMPARE_USER_ ALL 0xF0 Compares current command contents with EEPROM. Send Byte N NA 107 MFR_TEMPERATURE_2_ PEAK 0xF4 Peak internal die temperature since last MFR_ CLEAR_PEAKS. R Word N L11 C NA 106 MFR_PWM_CONFIG_ LTC7880 0xF5 Set numerous parameters for the DC/DC controller including phasing. R/W Byte N Reg Y 0x10 MFR_IIN_CAL_GAIN_TC 0xF6 Temperature coefficient of the current sensing element. R/W Word Y CF ppm/ Y 0 0x0000 MFR_TEMP_1_GAIN 0xF8 Sets the slope of the external temperature sensor . R/W Word Y CF Y 1.0 0x4000 MFR_TEMP_1_OFFSET 0xF9 Sets the offset of the external temperature sensor with respect to –273.1°C R/W Word Y L11 C Y 0.0 0x8000 MFR_RAIL_ADDRESS 0xFA Common address for PolyPhase outputs to adjust common parameters. R/W Byte Y Reg Y 0x80 MFR_RESET 0xFD Commanded reset without requiring a power down. Send Byte N NA 71 Note 1: Commands indicated with Y in the EEPROM column indicate that these commands are stored and restored using the STORE_USER_ALL and RESTORE_USER_ALL commands, respectively. Note 2: Commands with a default value of NA indicate “not applicable”. Commands with a default value of FS indicate “factory set on a per part basis”. Note 3: The LTC7880 contains additional commands not listed in this table. Reading these commands is harmless to the operation of the IC; however , the contents and meaning of these commands can change without notice. Note 4: Some of the unpublished commands are read-only and will generate a CML bit 6 fault if written. Note 5: Writing to commands not published in this table is not permitted. Note 6: The user should not assume compatibility of commands between different parts based upon command names. Always refer to the manufacturer’s data sheet for each part for a complete definition of a command’s function. L TC strives to keep command functionality compatible between all L TC devices. Differences may occur to address specific product requirements.

SENSE (if RSENSE is used) and inductor value. RANGE is set with bit 1 of MFR_PWM_MODE_LTC7880. ing the transient response to load changes. IIN_OC_FAULT_LIMIT section of the PMBus commands. adjust the current limit when indutor temperature changes. MFR_IIN_CAL_GAIN_TC command. For the best current limit accuracy, use the 75mV setting. sensing. Do not float these pins during normal operation. Figure 24. Optimal Sense Line Placement

Rev 0For more information www.analog.com APPLICATIONS INFORMATION between the ISENSE+ and ISENSE– signal paths can result in loss of accuracy in the current reading of the ADC. The current reading accuracy can be improved by matching the impedance of the two signal paths. To accomplish this add a series resistor R3 between V IN and I SENSE+ equal to R1. A capacitor of 1µF or greater should be placed in parallel with this resistor . If the peak voltage is <75mV at room temperature, R2 is not required. LOW VALUE RESISTOR CURRENT SENSING A typical sensing circuit using a discrete resistor is shown in Figure 25b. R SENSE is chosen based on the required output current. The current comparator has a maximum threshold V SENSE(MAX) determined by the ILIMIT setting. The current comparator threshold sets the peak of the inductor current, yielding a maximum average output current I MAX equal to the peak value less half the peak-to-peak ripple current L. To calculate the sense resistor value, use the equation: RSENSE = VSENSE(MAX) IMAX + ∆IL Due to possible PCB noise in the current sensing loop, the AC current sensing ripple of ∆V SENSE = ∆IL • RSENSE also needs to be checked in the design to get a good signal-to- noise ratio. In general, for a reasonably good PCB layout, a 15mV minimum ∆V SENSE voltage is recommended as a conservative number to start with, either for RSENSE or DCR sensing applications. A typical sensing circuit using a discrete resistor is shown in Figure 25b. An RC filter placed near the IC is commonly used to reduce the effects of the capacitive and inductive noise coupled in the sense traces on the PCB. A typical filter consists of two series 100Ω resistors connected to a parallel 1000pF capacitor , resulting in a time constant of 200ns. VOUTDRVCC BOOST TG SW BG GND *PLACE C1 NEAR SENSE+, SENSE– PINS INDUCTOR DCR OPTIONAL >1µF L ISENSE– ISENSE+ LTC7880 VIN

7880 F25a

R2 C1* DCR IOUT_CAL_GAIN = DCR × R2 R1 + R2 + R3 R3 = R1 VOUTDRVCC BOOST TG SW BG GND FILTER COMPONENTS PLACED NEAR SENSE PINS ISENSE– ISENSE+ LTC7880 VIN

7880 F25b

CF • 2RF ≤ ESL/RS POLE-ZERO CANCELLATION SENSE RESISTOR PLUS PARASITIC INDUCTANCE RS ESL CF RF RF Figure 25a. Inductor DCR Current Sense Circuit Figure 25b. Resistor Current Sense Circuit

• tON • tOFF tON + tOFF (1) If the RC time constant is chosen to be close to the para- sitic inductance divided by the sense resistor (L/R), the resultant waveform looks resistive, as shown in Figure 27. For applications using low maximum sense voltages, check the sense resistor manufacturer ’s data sheet for information about parasitic inductance. In the absence of data, measure the voltage drop directly across the sense resistor to extract the magnitude of the ESL step and use Equation 1 to determine the ESL. However , do not overfilter the signal. Keep the RC time constant less than or equal to the inductor time constant to maintain a sufficient ripple voltage on V RSENSE for optimal operation of the current loop controller . INDUCTOR DCR CURRENT SENSING For applications requiring the highest possible efficiency at high load currents, the LTC7880 is capable of sensing the voltage drop across the inductor DCR, as shown in Figure 25a . The DCR of the inductor represents the small amount of DC winding resistance of the copper , which can be less than 1mΩ for today’s low value, high current inductors. In a high current application requiring such an inductor , conduction loss through a sense resistor would reduce the efficiency by a few percent compared to DCR sensing. If R1 = R3 and the external (R1 + R3)||R2 • C1 time con- stant is chosen to be exactly equal to the 2 • L/DCR time constant, assuming R1 = R3, the voltage drop across the external capacitor ,C1, is equal to the drop across the inductor DCR multiplied by R2/(R1 + R2 + R3). R2 scales the voltage across the sense terminals for applications where the DCR is greater than the target sense resistor value. The DCR value is entered as the IOUT_CAL_GAIN in mΩ unless R2 is required. If R2 is used: IOUT _ CAL _ GAIN = DCR • R2 R1+ R2 + R3 R2 can be removed if there is no need to attenuate the current sense signal in order to remain within the desired current sense range. To properly select the external filter components, the DCR of the inductor must be known. It can be measured using an accurate RLC meter , but the DCR tolerance is not always the same and varies with temperature. Consult the inductor manufacturers’ data sheets for detailed information. The LTC7880 will correct for temperature variation if the correct temperature coef- ficient value is entered into the MFR_IIN_CAL_GAIN_TC command. T ypically the resistance has a 3900ppm/°C coefficient. 500ns/DIV VSENSE 20mV/DIV

7880 F26

7880 F27

Figure 26. Voltage Measured Directly Across RSENSE Figure 27. Voltage Measured After the RSENSE Filter

Rev 0For more information www.analog.com APPLICATIONS INFORMATION Assuming R1 = R3, C2 can be optimized for a flat frequency response using the following equation: C2 = 2R1•R2 • C1– L DCR 2R1+ R2( ) R12 Using the inductor ripple current value from the Inductor Value Calculation section, the target sense resistor value is: RSENSE(EQUIV) = VSENSE(MAX) IMAX + ∆IL To ensure that the application will deliver full load current over the full operating temperature range, be sure to pick the optimum I LIMIT value accounting for tolerance in the DCR versus the MFR_IOUT_CAL_GAIN parameter entered. Next, determine the DCR of the inductor . Use the manu- facturer’s maximum value, which is usually specified at °C. Increase this value to account for tolerances in the temperature sensing element of 3°C to 5°C and any additional temperature differences associated with the proximity of the temperature sensor element to the inductor . C1 is usually selected to be in the range of 0.047µF to 4.7µF. This forces (R1 + R3)||R2 to be approximately 2k. Adding optional elements R3 and C2 shown in Figure 25a will minimize offset errors associated with the I SENSE leak- age currents. Set R3 equal to the value of R1. Set C2 to a value of 1µF or greater to ensure adequate noise filtering. The equivalent resistance (R1 + R3)||R2 is scaled to the room temperature inductance and maximum DCR: DCR at 20 °C( ) • C1 The maximum power loss in R1 is related to the duty cycle, and will occur in continuous mode at V IN = 1/2VOUT: PLOSS R1= VOUT – VIN( ) • VIN Ensure that R1 has a power rating higher than this value. If high efficiency is necessary at light loads, consider this power loss when deciding whether to use DCR sensing or sense resistors. Light load power loss can be modestly higher with a DCR network than with a sense resistor due to the extra switching losses incurred through R1. However , DCR sensing eliminates a sense resistor , reduc- ing conduction losses and provides higher efficiency at heavy loads. Peak efficiency is about the same with either method. Selecting discontinuous mode will improve the converter efficiency at light loads regardless of the current sensing method. To maintain a good signal-to-noise ratio for the current sense signal, use a minimum ∆VISENSE of 10mV to 15mV. For a DCR sensing application, the actual ripple voltage will be determined by the equation: ∆VISENSE = VIN – VOUT R1• C1

• VOUT VIN • fOSC SLOPE COMPENSATION AND INDUCTOR PEAK CURRENT Slope compensation provides stability in constant frequen- cy current mode architectures by preventing sub-harmonic oscillations at high duty cycles. This is accomplished internally by adding a compensation ramp to the induc - tor current signal. The LT C7880 uses a patented current limit technique that cancels the effect of the compensating ramp. This allows the maximum inductor peak current to remain unaffected throughout all duty cycles. INDUCTOR VALUE CALCULATION Given the desired input and output voltages, the inductor value and operating frequency, f OSC, directly determine the inductor peak-to-peak ripple current: IRIPPLE = VIN fOSC •L 1– VIN VOUT Lower ripple current reduces core losses in the inductor , ESR losses in the output capacitors, and output voltage ripple. Thus, highest efficiency operation is obtained at the lowest frequency with a small ripple current. Achieving this, however , requires a large inductor . A reasonable starting point for setting ripple current is ΔI L = 0.3(IMAX). The maximum ΔIL occurs at VIN = 1/2VOUT.

Rev 0 For more information www.analog.com APPLICATIONS INFORMATION INDUCTOR CORE SELECTION Once the inductor value is determined, the type of induc- tor must be selected. Core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance. As the inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses increase. Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can con - centrate on copper loss and preventing saturation. Ferrite core materials saturate hard, which means that the induc- tance collapse abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! POWER MOSFET AND OP TIONAL SCHOTTKY DIODE SELECTION Two external power MOSFETs must be selected for each output channel in the LTC7880: one N-channel MOSFET for the bottom (main) switch, and one N-channel MOSFET for the top (synchronous) switch. The peak-to-peak gate drive levels are set by the DRV CC voltage. Pay close attention to the BVDSS specification for the MOSFETs as well; most of the logic-level MOSFETs are limited to 30V or less. Selection criteria for the power MOSFETs include the on-resistance, R DS(ON) , Miller capacitance, C MILLER, input voltage and maximum output current. Miller ca - pacitance, CMILLER, can be approximated from the gate charge curve usually provided on the MOSFET manu - facturers’ data sheet. CMILLER is equal to the increase in gate charge along the horizontal axis while the curve is approximately flat divided by the specified change in VDS. This result is then multiplied by the ratio of the applica - tion applied VDS to the gate charge curve specified V DS. When the IC is operating in continuous mode the duty cycles for the top and bottom MOSFETs are given by: Main Switch Duty Cycle = 1– VIN VOUT Synchronous Switch Duty Cycle = VIN VOUT The MOSFET power dissipations at maximum output current are given by: PMAIN = (VOUT −VIN)VOUT VIN 2 • IOUT(MAX)

• 1+δ( )
• RDS(ON)+k •VOUT VIN
• IOUT(MAX) 2• VIN
• CMILLER • f PSYNC = VIN VOUT
• IOUT(MAX)
• 1+δ( ) •RDS(ON) where d is the temperature dependency of R DS(ON) (ap- proximately 1Ω ). The constant k, which accounts for the loss caused by reverse recovery current, is inversely proportional to the gate drive current and has an empiri- cal value of 1.7. Both MOSFET s have I2R losses while the topside N-channel equation includes an additional term for transition losses, which are highest at high input voltages. For high VIN the high current efficiency generally improves with larger MOSFETs, while for low V IN the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower C MILLER actually provides higher efficiency. The synchronous MOSFET losses are greatest at high input voltage when the bottom switch duty factor is low or during an overvoltage when the synchronous switch is on close to 100% of the period. The term (1 + d) is generally given for a MOSFET in the form of a normalized R DS(ON) vs Temperature curve, but d = 0.005/°C can be used as an approximation for low voltage MOSFETs. The optional Schottky diodes connected from SWn to VOUTn conduct during the dead time between the conduc- tion of the two power MOSFETs. These prevent the body di odes of the top MOSFETs from turning on, storing charge during the dead time and requiring a reverse recovery period. A 1A to 3A Schottky is generally a good compro- mise for both regions of operation due to the relatively small average current. Larger diodes result in additional transition losses due to their larger junction capacitance.

age conditions, aluminum electrolytic capacitors are not. impedance, the higher the required input capacitance. based on the output voltage and range of input voltage.

7880 F28

Figure 28. Normalized Output Capacitor The LTC7880 must enter the run state prior to soft-start. the same time base for time delay operations.

Rev 0 For more information www.analog.com APPLICATIONS INFORMATION MFR_VOUT_START value when the ramp is initialized, the effective ramp time will be reduced by: TRAMP = TON_RISE •MFR_VOUT_START VIN Multiple LTC7880s and other L TC parts can be configured to start with equal or unique delay times. To work within a desired synchronization scheme all devices must use the same timing clock (SHARE_CLK) and all devices must share the RUNn pin. This allows the relative delay of all parts to be synchronized. The actual variation in the delays will be dependent on the highest clock rate of the devices connected to the SHARE_CLK pin (all Linear Technology ICs are configured to allow the fastest SHARE_CLK signal to control the timing of all devices). The SHARE_CLK signal can be ±10% in frequency, thus the actual time delays will have proportional variance. Soft-start is performed by actively regulating the load voltage while digitally ramping the target voltage from MFR_VOUT_START value to the commanded voltage set point. The rise time of the voltage ramp can be programmed using the TON_RISE command to minimize inrush currents associated with the start-up voltage ramp. The soft-start feature is disabled by setting TON_RISE to any value less than 0.250ms. The LTC7880 will perform the necessary math to assure the voltage ramp is controlled to the desired slope. However , the voltage slope can not be any faster than the fundamental limits of the power stage. The shorter TON_RISE time is set, the larger the discrete steps in the TON_RISE ramp will appear . The number of steps in the ramp is equal to TON_RISE/0.1ms. The LTC7880 PWM will always use discontinuous mode during the TON_RISE operation. In discontinuous mode, the bottom gate is turned off as soon as reverse current is detected in the inductor . This will allow the regulator to start up into a pre-biased load. The LTC7880 does not include a traditional tracking feature. However , two outputs can be given the same TON_RISE and TON_DELAY times to effectively ramp up at the same time. If the RUN pin is released at the same time and both LTC7880s use the same time base, the outputs will track very closely. If the circuit is in a PolyPhase configuration, all timing parameters for that rail must be the same. The previously described method of start-up sequencing is time based. For concatenated events it is possible to control the RUNn pins based on the PGOODn pin of a different con- troller , or the PGOODn pin(s) of the LTC7880. The FAUL Tn pins can be configured to release when the output voltage of the converter is greater than the VOUT_UV_FAULT_LIMIT. It is recommended to use the deglitched V OUT UV fault limit because there is little appreciable time delay between the converter crossing the UV threshold and the FAUL Tn pin releasing. The deglitched output can be enabled by setting the MFR_FAULT_PROPAGATE_VOUT_UVUF bit in the MFR_FAULT_PROPAGATE_LTC7880 command. Refer to the MFR section of the PMBus commands in this document. The UV comparator output signal may have some glitching as the V OUT signal transitions through the comparator threshold. The LTC7880 includes a 70µs digital deglitch filter to greatly reduce the probability of multiple transitions. To minimize the risk of FAUL Tn pins glitching, make the TON_RISE times less than 100ms. If unwanted transitions still occur on FAUL Tn, place a capacitor to ground on the FAUL Tn pin to filter the waveform. The RC time-constant of the filter should be set sufficiently fast to assure no appreciable delay is incurred. A delay of 300µs to 500µs will provide some additional filtering without significantly delaying the trigger event. DIGITAL SERVO MODE For maximum accuracy in the regulated output voltage, enable the digital servo loop by asserting bit 6 of the MFR_PWM_MODE_LTC7880 command. In digital servo mode the LTC7880 will adjust the regulated output volt- age based on the ADC voltage reading. Every 90ms the digital ser vo loop will step the LSB of the DAC (nominally 15.4mV or 7.7mV depending on the voltage range bit) until the output is at the correct ADC reading. At power-up this mode engages after TON_MAX_FAULT_LIMIT unless the limit is set to 0 (infinite). If the TON_MAX_FAULT_LIMIT is set to 0 (infinite), the servo begins after TON_RISE is com- plete and V OUT has exceeded the VOUT_UV_FAULT_LIMIT. This same point in time is when the output changes from discontinuous to the programmed mode as indicated in MFR_PWM_MODE_LTC7880 bit 0. Refer to Figure 29 for details on the V OUT waveform under time-based sequencing.

ramp is typically TOFF_FALL/0.1ms.

7880 F29

Figure 29. Timing Controlled VOUT Rise Figure 30. TOFF_DELAY and TOFF_FALL TON_MAX_FAULT_LIMIT time is reached. and the IIN_OC_FAULT_LIMIT is not exceeded. FAULT_LIMIT is not exceeded. The maximum rise time is limited to 1.3 seconds. servo to the same output regulation point. plies power to DRVCC from the V BIAS or EXTVCC supply.

required by the MOSFET gate drivers. an external supply or an output derived source. Figure 31. To minimize the voltage drop caused by the gate Figure 31. Setup for a 6V Input

7880 F31

and valid ADC conversions to be read. specification for more details regarding fault responses. is detected, TGn is asserted and BGn is held low. or larger is generally recommended.

7880 F32

Figure 32. Boost Circuit to Minimize PWM Jitter CML fault is detected, ALERT is asserted low. DD33 supply is externally driven.

Rev 0 For more information www.analog.com APPLICATIONS INFORMATION For high speed signals such as the SDA, SCL and SYNC, a lower value resistor may be required. The RC time con- stant should be set to 1/3 to 1/5 the required rise time to avoid timing issues. For a 100pF load and a 400kHz PMBus communication rate, the rise time must be less than 300ns. The resistor pull-up on the SDA and SCL pins with the time constant set to 1/3 the rise time: RPULLUP = tRISE 3 • 100pF = 1k Minimize parasitic capacitance on the SDA and SCL pins to avoid communication problems. To estimate the loading capacitance, monitor the signal in question and measure how long it takes for the desired signal to reach approximately 63% of the output value. This is one time constant. The SYNC pin has an on-chip pull-down transistor with the output held low for nominally 500ns. If the internal oscillator is set for 500kHz and the load is 100pF and a 3x time constant is required, the resistor calculation is as follows: RPULLUP = 2µs – 500ns 3 • 100pF = 5k If timing errors are occurring or if the SYNC frequency is not as fast as desired, monitor the waveform and determine if the RC time constant is too long for the application. If possible reduce the parasitic capacitance. If not reduce the pull up resistor sufficiently to assure proper timing. The SHARE_CLK pull-up resistor has a similar equation with a period of 10us and a pull-down time of 1µs. The RC time constant should be approximately 3µs or faster . PHASE-LOCKED LOOP AND FREQUENCY SYNCHRONIZATION The LTC7880 has a phase-locked loop (PLL) comprised of an internal voltage-controlled oscillator (VCO) and a phase detector . The PLL is locked to the falling edge of the SYNC pin. The phase relationship between the PWM controller and the falling edge of SYNC is controlled by the lower 3 bits of the MFR_PWM_CONFIG_LTC7880 com - mand. For PolyPhase applications, it is recommended all the phases be spaced evenly . Thus for a 2-phase system the signals should be 180° out of phase and a 4-phase system should be spaced 90°. The phase detector is an edge-sensitive digital type that provides a known phase shift between the external and internal oscillators. This type of phase detector does not exhibit false lock to harmonics of the external clock. The output of the phase detector is a pair of complemen- tary current sources that charge or discharge the internal filter network. The PLL lock range is guaranteed between 85kHz to 500kHz. Nominal parts will have a range beyond this; however , operation to a wider frequency range is not guaranteed. The PLL has a lock detection circuit. If the PLL should lose lock during operation, bit 4 of the STATUS_MFR_SPECIFIC command is asserted and the ALERT pin is pulled low. The fault can be cleared by writing a 1 to the bit. If the user does not want the ALERT pin to assert if a PLL_FAULT occurs, the SMBALERT_MASK command can be used to prevent the alert. If there is no external signal applied to the SYNC pin in the application, the nominal programmed frequency will control the PWM circuitry. If FREQUENCY_SWITCH is programmed to external oscillator , and no external SYNC signal is present, the LTC7880 PWM engine will run at the lowest free running frequency of the PLL oscillator . This may result in excess inductor current and undesirable operation. If multiple parts share the SYNC signal and the external SYNC signal is not present, the parts will not be synchronized and excess voltage ripple on the output may be present. Multiple LTC7880s are required to share one SYNC signal in PolyPhase configurations, for other configurations connecting the SYNC pins to form a single SYNC signal is optional. If the SYNC pin is shared between LTC7880s, only one LTC7880 should be programmed with a frequency output. All the other LTC7880s should be programmed to disable their SYNC output. However their frequency should be programmed to the nominal desired value.If the LTC7880 is programmed with a frequency output, and an external signal is present. Bit 10 of MFR_PADS_LTC7880 will be asserted low if this condition exists.

the gate charge required to turn off the bottom MOSFET . but the ripple voltage and current will increase. between the transistor and capacitor . BE approach with its lower signal levels.

7880 F33

Figure 33. External ΔVBE Temperature Sense Figure 34. 2D+R Temperature Sense

7880 F34

using the direct p-n junction measurement method. set to ignore, and the IOUT_CAL_GAIN_TC to a value of 0. MOSFET to supply high frequency transient input current. higher output voltage levels. VSENSE0+, IOUT+ and IOUT– and pins together .

7880 F35

Figure 35. Low Noise Output Current Sense Circuit

PMBus interface or purchasing custom programmed parts. tion. If VOUT is set to 28V or lower , low range is used. Table 3. VOUTn_CFG The PWM switching frequency is set according to Table 4. DD33 is required on the SYNC pin. respect to the falling edge of SYNC.

Table 4. FREQ_CFG Resistor Programming of SYNC is set using the values in Table 5. Table 5. PHAS_CFG Resistor Programming are global addresses and all parts will respond to them.

Table 6. ASELn Resistor Programming the output power divided by the input power times 100%. tion losses, 5) body diode conduction losses. results in a small (<0.1%) loss.

1. DRVCC current is the sum of the MOSFET driver and

of the topside and bottom side MOSFETs.

1. DC I2R losses. These arise from the resistances of the
2. T ransition losses apply only to the bottom MOSFET(s),

• CRSS • f 5. Body diode conduction losses are more significant at higher switching frequency. During the dead time, the loss in the top MOSFETs is I OUT • VDS, where VDS is approximately 0.7V. At higher switching frequency, the dead time becomes a good percentage of switching cycle and causes the efficiency to drop. Other “hidden” losses such as copper trace and internal battery resistances can account for an additional 5% to 10% efficiency degradation in portable systems. It is very important to include these “system” level losses during the design phase. The internal battery and fuse resistance losses can be minimized by making sure that C IN has ad- equate charge storage and very low ESR at the switching frequency . Other losses including Schottky conduction losses during dead time and inductor core losses.

7880 F36

Figure 36. Programmable Loop Compensation location, as shown in Figure 37.

7880 F37

Figure 37. . Error Amp gm Adjust

7880 F38

Figure 38. RITH Adjust or ringing, which would indicate a stability problem. prior to compensation calculation.

Rev 0For more information www.analog.com APPLICATIONS INFORMATION The ITH series internal R ITH - external C C filter sets the dominant pole-zero loop compensation. The internal RITH value can be modified (from 0Ω to 62kΩ) using bits[4:0] of the MFR_PWM_COMP command. Adjust the value of R ITH to optimize transient response once the final PC layout is done and the particular C C filter capacitor and output capacitor type and value have been determined. The output capacitors need to be selected because the various types and values determine the loop gain and phase. An output current pulse of 20% to 80% of full-load current having a rise time of 1µs to 10µs will produce output volt- age and I TH pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. Placing a power MOSFET with a resistor to ground directly across the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce a load step. The MOSFET + R SERIES will produce output currents approximately equal to V OUT/RSERIES. R SERIES values from 0.1Ω to 2Ω are valid depending on the current limit settings and the programmed output voltage. The initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. This is why it is better to look at the I TH pin signal which is in the feedback loop and is the filtered and compensated control loop response. The gain of the loop will be increased by increasing R ITH and the bandwidth of the loop will be increased by decreasing CC. If RITH is increased by the same factor that CC is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. The gain of the loop will be proportional to the transconductance of the error amplifier which is set using bits[7:5] of the MFR_PWM_COMP command. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. A second, more severe transient is caused by switching in loads with large (>1µF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with C OUT, causing a rapid drop in VOUT. No regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. If the ratio of C LOAD to COUT is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 • C LOAD. Thus a 10µF capacitor would require a 250µs rise time, limiting the charging current to about 200mA. PolyPhase CONFIGURATION When configuring a PolyPhase rail with multiple LTC7880s, the user must share the SYNC, ITH, SHARE_CLK, FAUL Tn, PGOODn and ALERT pins of both parts. Be sure to use pull-up resistors on FAUL Tn, PGOODn, SYNC, SHARE_CLK and ALERT. One of the LTC7880’s SYNC pin must be set to the desired switching frequency, and all other FREQUENCY_SWITCH commands must be set to External Clock. If an external oscillator is provided, set the FREQUENCY_SWITCH command to External Clock for all LTC7880s. The relative phasing of all the channels should be spaced equally. The MFR_RAIL_ADDRESS of all the devices should be set to the same value. When connecting a PolyPhase rail with LTC7880s, connect the V IN pins of the LTC7880s directly back to the supply voltage through the VIN pin filter networks. PC BOARD LAYOUT CHECKLIST When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the IC. These items are also illustrated graphically in the layout diagram of Figure 39. Figure 40 illustrates the cur- rent waveforms present in the various branches of the synchronous regulator operating in the continuous mode. Check the following in your layout Is the top N-channel MOSFET , M1, located within 1cm of COUT? 2. Are signal ground and power ground kept separate ? The ground return of CDRVCC must return to the combined COUT (–) terminals. The ITH trace should be as short as possible.

7880 F39

Figure 39. Recommended Printed Circuit Layout Diagram

7880 F40

Figure 40. Branch Current Waveforms

Rev 0 For more information www.analog.com APPLICATIONS INFORMATION 4. The loop formed by the top N-channel MOSFET, bottom N-channel MOSFET, and the C OUT capacitor should have short leads and PC trace lengths. 5. T he output capacitor (–) terminals should be connected as close as possible to the (–) terminals of the input capacitor by placing the capacitors next to each other and away from the Schottky loop described in item 4. Are the I SENSE+ and I SENSE– leads routed together with minimum PC trace spacing? The filter capacitor between I SENSE+ and I SENSE– should be as close as possible to the IC. Ensure accurate current sensing with Kelvin connections at the sense resistor or inductor, whichever is used for current sensing. Is the DRVCC decoupling capacitor connected close to the IC, between the DRVCC and the power ground pins? This capacitor carries the MOSFET driver current peaks. An additional 1µF ceramic capacitor placed immediately next to the DRV CC and GND pins can help improve noise performance substantially. 8. Keep the switching nodes (SW n), top gate nodes (TGn), and boost nodes (BOOSTn) away from sensitive small-signal nodes, especially from the voltage and current sensing feedback pins. All of these nodes have very large and fast moving signals and therefore should be kept on the “output side” of the LTC7880 and occupy minimum PC trace area. If DCR sensing is used, place the top resistor (Figure 25a, R1) close to the switching node. Use a modified “star ground” technique: a low imped- ance, large copper area central grounding point on the same side of the PC board as the input and output capacitors with tie-ins for the bottom of the DRV CC and EXTVCC decoupling capacitors, the bottom of the voltage feedback resistive divider and the GND pin of the IC. 10. Are the IOUT+ and IOUT– pins Kelvin connected to the RSENSEOUT sense resistor? This will prevent the PCB trace resistance from causing errors in the input current measurement. These traces should be as short as possible and routed away from any noisy nodes such as the switching or boost nodes. PC BOARD LAYOUT DEBUGGING It is helpful to use a DC-50MHz current probe to monitor the current in the inductor while testing the circuit. Monitor the output switching node (SWn pin) to synchronize the oscil- loscope to the internal oscillator and probe the actual output voltage as well. Check for proper per formance over the oper- ating voltage and current range expected in the application. The frequency of operation should be maintained over the input voltage range down to dropout and until the output load drops below the low current operation threshold. T he duty cycle percentage should be maintained from cycle to cycle in a well-designed, low noise PCB implementation. Variation in the duty cycle at a subharmonic rate can sug- gest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. Over compensation of the loop can be used to tame a poor PC layout if regulator bandwidth optimization is not required. Check the operation of the undervoltage lockout circuit by lowering V IN while monitoring the outputs to verify operation. Investigate whether any problems exist only at higher out- put currents or only at higher input voltages. If problems coincide with high input voltages and low output currents, look for capacitive coupling between the BOOST n, SWn, TGn, and possibly BGn connections and the sensitive volt- age and current pins. The capacitor placed across the cur- rent sensing pins needs to be placed immediately adjacent to the pins of the IC. This capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. If problems are encountered with high current output loading at lower input voltages, look for inductive coupling between C IN, Schottky and the top MOSFET components to the sensitive current and voltage sensing traces. In addition, investigate common ground path voltage pickup between these components and the GND pin of the IC.

7880 F41

Figure 41. Dual Phase 250kHz 12V/36V Boost Converter

Rev 0 For more information www.analog.com APPLICATIONS INFORMATION The following parameters are set as a percentage of the output voltage if the resistor configuration pins are used to determined output voltage: All other user defined parameters must be programmed into the EEPROM. L TPP can be utilized to quickly set up the part with the desired operating parameters. The components are designed based on single channel operation. The inductance values are based on a 40% maximum ripple current assumption (2A). The minimum inductance for 30% ripple current can be calculated using the following equation: ∆IL = VIN f •L ⎠⎟ 1– VIN VOUT The largest current ripple occurs when V IN = 0.5VOUT = 18V. The maximum inductor current for each channel is: IL(MAX) = ∆IL IOUT(MAX) 1−D( ) Both channels will have 3.5A (35%) ripple. The peak inductor current will be the maximum average value plus one-half the ripple current or which is 11.125A. Wurth 7443641000 (2.4mΩ typical DCR at 25 °C) is the chosen inductor. The maximum current sense resistor value must be small enough to not exceed the 75mV maximum current sense threshold. Set R SENSE = 5mΩ for both channels: RSENSE(MAX) = 75mV IOUT(MAX) VILIMIT = IL(MAX) • RSENSE = 11.75•5mΩ = 58.75mV The VILIMIT should be set to 75mV to assure variation in components and noise in the system do not limit the average current. COUT is chosen to filter the square current in the output. A low ESR (5mΩ) capacitor is suggested. This capacitor will limit output voltage ripple to 55.6mV assuming ESR dominates the ripple. ADDITIONAL DESIGN CHECKS Tie FAUL T0 and FAUL T1 together and pull up to V DD33 with a 10k resistor . Tie RUN0 and RUN1 together and pull up to V DD33 with a 10k resistor . If there are other L TC PSM parts, connect the RUN pins between chips and connect the FAUL T pins between chips. Be sure all PMBus pins have resistor pull-up to V DD33 and connect these inputs across all L TC PSM parts in the application. Tie SHARE_CLK high with a 10k resistor to V DD33 and share between all L TC PSM parts in the application. Be sure a unique address for each chip can be decoded with the ASEL0 and ASEL1 pins. Refer to Table 6. For maximum flexibility, allow board space for R TOP and RBOTTOM for any parameter that is set with resistors such as ASEL0 and ASEL1.

board for programming, telemetry and system debug. provides a powerful way to debug an entire power system. be quickly developed and stored to the LTC7880 EEPROM. to be enabled and valid ADCs to be read. EXTVCC pins. Normally this is not an issue if VBIAS is open.

7880 F42

Figure 42. L TC Controller Connection

provides unprecedented diagnostic and debug features. Figure 43. L TpowerPlay Screen Shot

as shown in Figure 44; Write Command Data Processing. its internal format so that it can be executed. ensure the last data written to any command is never lost. executing commands marked for processing.

7880 F44

Figure 44. Write Command Data Processing Figure 45. Example of a Command Write of VOUT_COMMAND abled by asserting bit 1 of MFR_CONFIG_ALL_LTC7880.

Rev 0 For more information www.analog.com APPLICATIONS INFORMATION unwanted ALERT notification. A simple way to achieve this is to create a SAFE_WRITE_BYTE() and SAFE_WRITE_ WORD() subroutine. The above polling mechanism allows your software to remain clean and simple while robustly communicating with the part. For a detailed discussion of these topics and other special cases please refer to the application note section located at: designtools When communicating using bus speeds at or below 100kHz, the polling mechanism shown here provides a simple solution that ensures robust communication without clock stretching. At bus speeds in excess of 100kHz, it is strongly recommended that the part be configured to en- able clock stretching. This requires a PMBus master that supports clock stretching. System software that detects and properly recovers from the standard PMBus NACK/ BUSY faults is required. The LTC7880 is not recommended in applications with bus speeds in excess of 400kHz The three hand shaking status bits are in the MFR_ COMMON register . When the part is busy executing an internal operation, it will clear bit 6 of MFR_COMMON (‘chip not busy’). When the part is busy specifically be - cause it is in a transitional VOUT state (margining hi/lo, power off/on, moving to a new output voltage set point, etc.) it will clear bit 4 of MFR_COMMON (‘output not in transition’). When internal calculations are in process, the part will clear bit 5 of MFR_COMMON (‘calculations not pending’). These three status bits can be polled with a PMBus read byte of the MFR_COMMON register until all three bits are set. A command immediately following the status bits being set will be accepted without NACKing or generating a BUSY fault/ALERT notification. The part can NACK commands for other reasons, however , as required by the PMBus spec (for instance, an invalid command or data). An example of a robust command write algorithm for the VOUT_COMMAND register is provided in Figure 45. It is recommended that all command writes (write byte, write word, etc. ) be preceded with a polling loop to avoid the extra complexity of dealing with busy behavior and

Pages 0x00 and 0x01 correspond to Channel 0 and Channel 1, respectively, in this device. set to 0xFF is not recommended. This command has one data byte. may be sent with PAGE_PLUS_WRITE. a non-paged command, the Page Number byte is ignored. mand that has two data bytes is shown in Figure 46. Figure 46. Example of PAGE_PLUS_WRITE

7880 F46

the data returned by the command, all in one communication packet . data from a non-paged command, the Page Number byte is ignored. with PEC is shown in Figure 47. Figure 47. Example of PAGE_PLUS_READ

7880 F47

fault for Invalid/Unsupported Data. EE_UNLOCK, and STORE_USER_ALL command. respective bits in the STATUS commands.

Rev 0For more information www.analog.com PMBus COMMAND DETAILS When WRITE_PROTECT is set to 0x00, writes to all commands are enabled. If WP pin is high, PAGE, OPERATION, MFR_CLEAR_PEAKS, MFR_EE_UNLOCK, WRITE_PROTECT and CLEAR_FAULTS commands are supported. Individual fault bits can be cleared by writing a 1 to the respective bits in the STATUS commands. MFR_ADDRESS The MFR_ADDRESS command byte sets the 7 bits of the PMBus slave address for this device. Setting this command to a value of 0x80 disables device addressing. The GLOBAL device address, 0x5A and 0x5B, cannot be deactivated. If RCONFIG is set to ignore, the ASEL0 and ASEL1 pins are still used to determine the LSB and MSB, respectively, of the channel address. If the ASEL0 and ASEL1 pins are both open, the LTC7880 will use the ad- dress value stored in EEPROM. If the ASEL0 pin is open, the LTC7880 will use the lower 4 bits of the MFR_ADDRESS value stored in EEPROM to construct the effective address of the part. If the ASE L1 pin is open, the LTC7880 will use the upper 3 bits of the MFR_ADDRESS value stored in EEPROM to construct the effective address of the part. This command has one data byte. MFR_RAIL_ADDRESS The MFR_RAIL_ADDRESS command enables direct device address access to the PAGE activated channel. The value of this command should be common to all devices programmed to that rail address.. The user should only perform command writes to this address. If a read is performed from this address and the rail devices do not respond with EXACTL Y the same value, the LTC7880 will detect bus contention and may set a CML communications fault. Setting this command to a value of 0x80 disables rail device addressing for the channel. This command has one data byte. GENERAL CONFIGURATION COMMANDS COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS EEPROM DEFAUL T VALUE MFR_CHAN_CONFIG_LTC7880 0xD0 Configuration bits that are channel specific. R/W Byte Y Reg Y 0x1D MFR_CONFIG_ALL_LTC7880 0xD1 General configuration bits. R/W Byte N Reg Y 0x21

Rev 0 For more information www.analog.com PMBus COMMAND DETAILS MFR_CHAN_CONFIG_LTC7880 General purpose configuration command common to multiple L TC products. BIT MEANING

7 Reserved

6 Reserved

5 Reserved

4 Disable RUN Low. When asserted the RUN pin is not pulsed low if commanded OFF . 3 Short Cycle. When asserted the output will immediate off if commanded ON while waiting for TOFF_DELAY or TOFF_FALL. TOFF_MIN of 120ms is honored then the part will command ON. 2 SHARE_CLOCK control. If SHARE_CLOCK is held low, the output is disabled. 1 ALERT is not pulled low if FAUL T is pulled low externally.

0 Disables the V

OUT decay value requirement for MFR_RETRY_TIME processing. When this bit is set to a 0, the output must decay to less than 12.5% of the programmed value before the PWM will restart. This applies to any action that turns off the PWM including a fault, an OFF/ON command, or a RUN pin transition from high to low. A TOFF_MAX warning status will not be generated when this bit is set to a 1. This command has one data byte. MFR_CONFIG_ALL_LTC7880 General purpose configuration command common to multiple L TC products. BIT MEANING

7 Enable Fault Logging

6 Ignore Resistor Configuration Pins

5 Disable CML Fault for Quick Command Message.

4 Disable SYNC output

3 Enable 255ms PMBus timeout

2 A valid PEC required for PMBus writes to be accepted. If this bit is not set, the part will not accept commands with invalid PEC.

1 Enable the use of PMBus clock stretching

0 Execute CLEAR_FAULTS on rising edge of either RUN pin. This command has one data byte. ON/OFF/MARGIN COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS EEPROM DEFAUL T VALUE OPERATION 0x01 Operating mode control. On/off, margin high and margin low. R/W Byte Y Reg Y 0x40 ON_OFF_CONFIG 0x02 RUN pin and PMBus bus on/off command configuration. R/W Byte Y Reg Y 0x1E MFR_RESET 0xFD Commanded reset without requiring a power-down. Send Byte N NA

Rev 0For more information www.analog.com PMBus COMMAND DETAILS ON_OFF_CONFIG The ON_OFF_CONFIG command specifies the combination of RUNn pin input state and PMBus commands needed to turn the PWM channel on and off. Supported Values: VALUE MEANING 0x1F OPERATION value and RUNn pin must both command the device to start/run. Device executes immediate off when commanded off. 0x1E OPERATION value and RUNn pin must both command the device to start/run. Device uses TOFF_XXXX command values when commanded off. 0x17 RUNn pin control with immediate off when commanded off. OPERATION on/off control ignored. 0x16 RUNn pin control using TOFF_XXXX command values when commanded off. OPERATION on/off control ignored. Programming an unsupported ON_OFF_CONFIG value will generate a CML fault and the command will be ignored. This command has one data byte. OPERATION The OPERATION command is used to turn the unit on and off in conjunction with the input from the RUNn pins. It is also used to cause the unit to set the output voltage to the upper or lower MARGIN VOL TAGEs. The unit stays in the commanded operating mode until a subsequent OPERATION command or change in the state of the RUNn pin instructs the device to change to another mode. If the OPERATION command value in EEPROM is set to the MARGIN_LOW/ HIGH state, the next RESET or POWER_ON cycle will ramp to that state. If the OPERATION command is modified, for example ON is changed to MARGIN_LOW, the output will move at a fixed slope set by the VOUT_TRANSITION_RATE. The default operation command is soft off. If V BIAS is applied to a part with factory default programming and the VOUT_CONFIG resistor configuration pins are not installed, the outputs will be commanded off. The part defaults to the Sequence Off state. This command has one data byte. Supported Values: VALUE MEANING 0xA8 Margin high. 0x98 Margin low. 0x80 On (V OUT back to nominal even if bit 3 of ON_OFF_CONFIG is not set). 0x40* Soft off (with sequencing). 0x00* Immediate off (no sequencing). *Device does not respond to these commands if bit 3 of ON_OFF_CONFIG is not set. Programming an unsupported OPERATION value will generate a CML fault and the command will be ignored. This command has one data byte. MFR_RESET This command provides a means to reset the LTC7880 from the serial bus. This forces the LTC7880 to turn off both PWM channels, load the operating memory from internal EEPROM, clear all faults and then perform a soft-start of both PWM channels, if enabled. This write-only command has no data bytes.

Rev 0 For more information www.analog.com PMBus COMMAND DETAILS PWM CONFIGURATION COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS EEPROM DEFAUL T VALUE MFR_PWM_COMP 0xD3 PWM loop compensation configuration R/W Byte Y Reg Y 0x70 MFR_PWM_MODE_ LTC7880 0xD4 Configuration for the PWM engine. R/W Byte Y Reg Y 0xC1 MFR_PWM_CONFIG_ LTC7880 0xF5 Set numerous parameters for the DC/DC controller including phasing. R/W Byte N Reg Y 0x10 FREQUENCY_SWITCH 0x33 Switching frequency of the controller . R/W Word N L11 kHz Y 250 0xF3E8 MFR_PWM_MODE_LTC7880 The MFR_PWM_MODE_LTC7880 command sets important PWM controls for each channel. Bits [0] and [6] may be changed when the addressed channel(s) is on,however the channel(s) must be turned off if any other bits are changed when the command is issued. The LTC7880 will issue a CML fault and ignore the command and its data if the channel is on and any bits other than [0] and [6] are changed. The MFR_PWM_MODE_LTC7880 command allows the user to program the PWM controller to use discontinuous (pulse-skipping mode), or forced continuous conduction mode. BIT MEANING [7] Use High Range of ILIMIT Low Current Range High Current Range [6] Enable Servo Mode [5] External temperature sense: 0: ΔV BE measurement. 1: Direct voltage measurement. [4] Reserved [3:2]* 00b 01b 10b DRV CC select and EXTVCC switch over threshold DRVCC = 6.3V, EXTVCC threshold = 5.3V DRVCC = 8.3V, EXTVCC threshold = 7.7V DRVCC = 10V, EXTVCC threshold = 7.7V [1] V OUT Range The maximum output voltage is 60V The maximum output voltage is 30V [0] Mode Discontinuous Forced Continuous * Page 0 only. Page 1 bits[3:2] are reserved Bit [7] of this command determines if the part is in high range or low range of the IIN_OC_FAULT_LIMIT command. Changing this bit value changes the PWM loop gain and compensation. This bit value cannot be changed when the channel output is active. Writing this bit when the channel is active will generate a CML fault.

Rev 0For more information www.analog.com PMBus COMMAND DETAILS Bit [6] The LTC7880 will not servo while the part is OFF , ramping on or ramping off. When set to a one, the output servo is enabled. The output set point DAC will be slowly adjusted to minimize the difference between the READ_VOUT_ADC and the VOUT_COMMAND (or the appropriate margined value). When Bit[5] is cleared, the LTC7880 computes temperature in °C from ∆V BE measured by the ADC at the TSNSn pin as T = (G • ΔVBE • q/(K • ln(16))) – 273.15 + O When Bit[5] is set, the LTC7880 computes temperature in °C from TSNSn voltage measured by the ADC as For both equations, G = MFR_TEMP_1_GAIN • 2–14, and O = MFR_TEMP_1_OFFSET Bit[3:2] determine the DRVCC voltage and EXTVCC switchover voltage. Bit[1] of this command determines if the part is in high range or low voltage range. Changing this bit value changes the PWM loop gain and compensation. This bit value cannot be changed when the channel output is active. Writing this bit when the channel is active will generate a CML fault. Bit[0] determines if the PWM mode of operation is discontinuous (pulse-skipping mode), or forced continuous conduction mode. This command has one data byte.Whenever the channel is ramping on, the PWM mode will be discontinuous, regardless of the value of this command. MFR_PWM_COMP The MFR_PWM_COMP command sets the gm of the PWM channel error amplifiers and the value of the internal R ITHn compensation resistors. This command affects the loop gain of the PWM output which may require modifications to the external compensation network. BIT MEANING BIT [7:5] EAgm (mS) 000b 1.00 001b 1.68 010b 2.35 011b 3.02 100b 3.69 101b 4.36 110b 5.04 111b 5.73 BIT [4:0] RITH (kΩ) 00000b 0 00001b 0.25 00010b 0.5 00011b 0.75 00100b 1

Rev 0 For more information www.analog.com PMBus COMMAND DETAILS BIT MEANING 00101b 1.25 00110b 1.5 00111b 1.75 01000b 2 01001b 2.5 01010b 3 01011b 3.5 01100b 4 01101b 4.5 01110b 5 01111b 5.5 10000b 6 10001b 7 10010b 8 10011b 9 10100b 11 10101b 13 10110b 15 10111b 17 11000b 20 11001b 24 11010b 28 11011b 32 11100b 38 11101b 46 11110b 54 11111b 62 This command has one data byte. MFR_PWM_CONFIG_LTC7880 The MFR_PWM_CONFIG_LTC7880 command sets the switching frequency phase offset with respect to the falling edge of the SYNC signal. The part must be in the OFF state to process this command. Either the RUN pins must be low or the part must be commanded off. If either channel is in the RUN state and this command is written, the command will be NACK’d and a BUSY fault will be asserted.

Rev 0For more information www.analog.com PMBus COMMAND DETAILS BIT MEANING Use VFBO Feedback nodes of both channels are independent. Channel 1 uses the Channel 0 feedback node. [6:5] 00b 01b 10b 11b Output current sense gain. 2x gain. 0mV to 50mV range. 4x gain. 0mV to 20mV range. 8x gain. 0mV to 5mV range. Reserved. Do not use.

4 Share Clock Enable : If this bit is 1, the

SHARE_CLK pin will not be released until V IN1 > VIN_ON. The SHARE_CLK pin will be pulled low when VIN1 < VIN_OFF. If this bit is 0, the SHARE_CLK pin will not be pulled low when VIN1 < VIN_OFF except for the initial application of VIN1. BIT [2:0] CHANNEL 0 (DEGREES) CHANNEL 1 (DEGREES) 000b 0 180 001b 90 270 010b 0 240 011b 0 120 100b 120 240 101b 60 240 110b 120 300 111b Reserved. Do not use. Do not assert Bit[7] except for use in a PolyPhase configuration. The V SENSEn+n, ITHn, PGOODn and RUNn must be shared between channels when this bit is asserted. FREQUENCY_SWITCH The FREQUENCY_SWITCH command sets the switching frequency, in kHz, of the LTC7880. This command can be set to any value between 85 and 500. The part must be in the OFF state to process this command. The RUN pin must be low or both channels must be commanded off. If the part is in the RUN state and this command is written, the command will be NACK'd and a BUSY fault will be asserted. When the part is commanded off and the frequency is changed, a PLL_UNLOCK status may be detected as the PLL locks onto the new frequency.

Rev 0 For more information www.analog.com PMBus COMMAND DETAILS This command has two data bytes and is formatted in Linear_5s_11s format. VOL TAGE Input Voltage and Limits COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS EEPROM DEFAUL T VALUE VIN_OV_FAULT_LIMIT 0x55 Input supply overvoltage fault limit. R/W Word N L11 V Y 40 0xE280 VIN_UV_WARN_LIMIT 0x58 Input supply undervoltage warning limit. R/W Word N L11 V Y 6.3 0xCB26 VIN_ON 0x35 Input voltage at which the unit should start power conversion. R/W Word N L11 V Y 6.5 0xCB40 VIN_OFF 0x36 Input voltage at which the unit should stop power conversion. R/W Word N L11 V Y 6.0 0xCB00 VIN_OV_FAULT_LIMIT The VIN_OV_FAULT_LIMIT command sets the value of the input voltage measured by the ADC, at the VIN1 pin in volts, that causes an input overvoltage fault. This command has two data bytes in Linear_5s_11s format. Sets the INPUT Bit Is the STATUS_WORD Sets the VIN Fault Bit in the STATUS_INPUT Command Notifies the Host by Asserting ALERT, Unless Masked VIN_UV_WARN_LIMIT The VIN_UV_WARN_LIMIT command sets the value of input voltage measured by the ADC at the V IN1 pin that causes an input undervoltage warning. This warning is disabled until the input exceeds the input startup threshold value set by the VIN_ON command and the unit has been enabled. If the VIN_UV_WARN_LIMIT is then exceeded, the device: Sets the INPUT Bit in STATUS_WORD Sets the VIN Undervoltage Warning Bit in the STATUS_INPUT Command Notifies the Host by Asserting ALERT, Unless Masked VIN_ON The VIN_ON command sets the input voltage, at the V IN1 pin in volts, at which the unit should start power conversion. This command has two data bytes and is formatted in Linear_5s_11s format. VIN_OFF The VIN_OFF command sets the input voltage, at the VIN1 pin in volts, at which the unit should stop power conversion. This command has two data bytes and is formatted in Linear_5s_11s format.

Rev 0For more information www.analog.com PMBus COMMAND DETAILS Output Voltage and Limits COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS EEPROM DEFAUL T VALUE VOUT_MODE 0x20 Output voltage format and exponent R Byte Y Reg 2–10 0x16 VOUT_MAX 0x

24 Upper limit on the output voltage the unit

can command regardless of any other commands. R/W Word Y L16 V Y 60 0xF000 VOUT_OV_FAULT _ LIMIT 0x40 Output overvoltage fault limit. R/W Word Y L16 V Y 26.4 0x699A VOUT_OV_WARN_ LIMIT 0x42 Output overvoltage warning limit. R/W Word Y L16 V Y 25.8 0x6733 VOUT_MARGIN_HIGH 0x25 Margin high output voltage set point. Must be greater than VOUT_COMMAND. R/W Word Y L16 V Y 25.2 0x64CD VOUT_COMMAND 0x21 Nominal output voltage set point. R/W Word Y L16 V Y 24 0x6000 MFR_VOUT_START 0x DA Start voltage of rising output voltage ramp Stop voltage of falling output voltage ramp R/W W ord Y L16 V Y 18 0x4800 VOUT_MARGIN_LOW 0x 26 Margin low output voltage set point. Must be less than VOUT_COMMAND. R/W Word Y L16 V Y 22.8 0x5B33 VOUT_UV_WARN_ LIMIT 0x43 Output undervoltage warning limit. R/W Word Y L16 V Y 22.2 0x58CD VOUT_UV_FAULT_ LIMIT 0x44 Output undervoltage fault limit. R/W Word Y L16 V Y 21.6 0x5666 MFR_VOUT_MAX 0xA5 Maximum allowed output voltage. R Word Y L16 V 60 0xF000 VOUT_MODE The data byte for VOUT_MODE command, used for commanding and reading output voltage, consists of a 3-bit mode (only linear format is supported) and a 5-bit parameter representing the exponent used in output voltage Read/Write commands. This read-only command has one data byte. VOUT_MAX The VOUT_MAX command sets an upper limit on any voltage, including VOUT_MARGIN_HIGH, the unit can com - mand regardless of any other commands or combinations. The maximum allowed value of this command is 60 volts. The maximum output voltage the LTC7880 can produce is 60 volts including VOUT_MARGIN_HIGH. However , the VOUT_OV_FAULT_LIMIT can only be commanded as high as 60 volts. This command has two data bytes and is formatted in Linear_16u format. VOUT_OV_FAULT_LIMIT The VOUT_OV_FAULT_LIMIT command sets the value of the output voltage measured by the OV supervisor compara- tor at the sense pins, in volts, which causes an output overvoltage fault.

Rev 0 For more information www.analog.com PMBus COMMAND DETAILS If the VOUT_OV_FAULT_LIMIT is modified and the part is in the RUN state, allow 10ms after the command is modified to assure the new value is being honored. The part indicates if it is busy making a calculation. Monitor bits 5 and 6 of MFR_COMMON. Either bit is low if the part is busy. If this wait time is not met, and the VOUT_COMMAND is modified above the old overvoltage limit, an OV condition might temporarily be detected resulting in undesirable behavior and possible damage to the switcher . If VOUT_OV_FAULT_RESPONSE is set to OV_PULLDOWN or 0x00, the FAUL T pin will not assert if VOUT_OV_FAULT is propagated. The LTC7880 will assert TG and force BG low as soon as the overvoltage condition is detected. This command has two data bytes and is formatted in Linear_16u format. VOUT_OV_WARN_LIMIT The VOUT_OV_WARN_LIMIT command sets the value of the output voltage measured by the ADC at the sense pins, in volts, which causes an output voltage high warning. In response to the VOUT_OV_WARN_LIMIT being exceeded, the device:

• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the VOUT Overvoltage Warning bit in the STATUS_VOUT command
• Notifies the host by asserting ALERT pin, unless masked This condition is detected by the ADC so the response time may be up to 120ms. This command has two data bytes and is formatted in Linear_16u format. VOUT_MARGIN_HIGH The VOUT_MARGIN_HIGH command loads the unit with the voltage to which the output is to be changed, in volts, when the OPERATION command is set to “Margin High”. The value must be greater than VOUT_COMMAND. The maximum guaranteed value on VOUT_MARGIN_HIGH is 60V. This command will not be acted on during TON_RISE and TOFF_FALL output sequencing. The VOUT_TRANSITION_RATE will be used if this command is modified while the output is active and in a steady-state condition. This command has two data bytes and is formatted in Linear_16u format. VOUT_COMMAND The VOUT_COMMAND consists of two bytes and is used to set the output voltage, in volts. The maximum guaranteed value on VOUT is 60 volts. This command will not be acted on during TON_RISE and TOFF_FALL output sequencing. The VOUT_TRANSITION_RATE will be used if this command is modified while the output is active and in a steady-state condition. This command has two data bytes and is formatted in Linear_16u format.

Rev 0For more information www.analog.com PMBus COMMAND DETAILS MFR_VOUT_START The MFR_VOUT_START command consists of two bytes and is used to set the starting point of the output voltage TON_RISE ramp in volts. The MFR_VOUT_START command also sets the end point of the output voltage TOFF_FALL ramp in volts. The value of MFR_VOUT_START should be set to higher than the maximum input voltage. This command will not be acted on during TON_RISE and TOFF_FALL output sequencing. This command has two data bytes and is formatted in Linear_16u format. VOUT_MARGIN_LOW The VOUT_MARGIN_LOW command loads the unit with the voltage to which the output is to be changed, in volts, when the OPERATION command is set to “Margin Low”. The value must be less than VOUT_COMMAND. This command will not be acted on during TON_RISE and TOFF_FALL output sequencing. The VOUT_TRANSITION_RATE will be used if this command is modified while the output is active and in a steady-state condition. This command has two data bytes and is formatted in Linear_16u format. VOUT_UV_WARN_LIMIT The VOUT_UV_ WARN_LIMIT command reads the value of the output voltage measured by the ADC at the sense pins, in volts, which causes an output voltage low warning. In response to the VOUT_UV_WARN_LIMIT being exceeded, the device:

• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the VOUT Undervoltage Warning bit in the STATUS_VOUT command
• Notifies the host by asserting ALERT pin, unless masked This command has two data bytes and is formatted in Linear_16u format. VOUT_UV_FAULT_LIMIT The VOUT_UV_FAULT_LIMIT command reads the value of the output voltage measured by the UV supervisor com - parator at the sense pins, in volts, which causes an output undervoltage fault. This command has two data bytes and is formatted in Linear_16u format. Sets the VOUT bit in the STATUS_WORD
• Sets the VOUT_UV Fault bit in the STATUS_VOUT command
• Notifies the host by asserting ALERT pin, unless masked

Rev 0 For more information www.analog.com PMBus COMMAND DETAILS MFR_VOUT_MAX The MFR_VOUT_MAX command is the maximum output voltage in volts for each channel, including VOUT_OV_FAULT_ LIMIT. If the output voltages are set to high range (Bit 1 of MFR_PWM_CONFIG_LTC7880 set to a 0) MFR_VOUT_MAX is 60V. If the output voltage is set to low range (Bit 1 of MFR_PWM_CONFIG_LTC7880 set to a 1) the MFR_VOUT_MAX is 30V. Entering a VOUT_COMMAND value greater than this will result in a CML fault and the output voltage setting will be clamped to the maximum level. This will also result in Bit 3 VOUT_MAX_Warning in the STATUS_VOUT com- mand being set. This read only command has 2 data bytes and is formatted in Linear_16u format. CURRENT AND LIMITS COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS EEPROM DEFAUL T VALUE IOUT_CAL_GAIN 0x38 The ratio of the voltage at the output current sense pins to the sensed current. For devices using a fixed current sense resistor , it is the resistance value in mΩ. R/W Word N L11 mΩ Y 5.0 0xCA80 MFR_IIN_CAL_GAIN_TC 0xF6 Temperature coefficient of the current sensing element. R/W Word Y CF Y 0 0x0000 IIN_OC_FAULT_LIMIT 0x 5B Input overcurrent fault limit. R/W Word Y L11 A Y 25 0xDB20 IOUT_CAL_GAIN The IOUT_CAL_GAIN command is used to set the resistance value of the channel 0 output current sense resistor in milliohms. This command has two data bytes and is formatted in Linear_5s_11s format. MFR_IIN_CAL_GAIN_TC The MFR_IIN_CAL_GAIN_TC command allows the user to program the temperature coefficient of the IIN_CAL_GAIN sense resistor or inductor DCR in ppm/°C. This command has two data bytes and is formatted in 16-bit 2’s complement integer ppm. N = –32768 to 32767 • 10–6. Nominal temperature is 27°C. The IIN_CAL_GAIN is multiplied by: 1.0 + MFR_IIN_CAL_GAIN_TC • (READ_TEMPERATURE_1 27)]. DCR sensing will have a typical value of 3900. The MFR_IIN_CAL_GAIN and MFR_IIN_CAL_GAIN_TC impact all current parameters including: READ_IIN.

Rev 0For more information www.analog.com PMBus COMMAND DETAILS IIN_OC_FAULT_LIMIT The IIN_OC_FAULT_LIMIT command sets the value of the peak input current limit, in amperes. When the controller is in current limit, the overcurrent detector will indicate an overcurrent fault condition. The programmed overcurrent fault limit value is rounded up to the nearest one of the following set of discrete values: 25mV/MFR_IIN_CAL_GAIN Low Range (1.5x Nominal Loop Gain) MFR_PWM_MODE_LTC7880 [7]=028.6mV/MFR_IIN_CAL_GAIN 32.1mV/MFR_IIN_CAL_GAIN 35.7mV/MFR_IIN_CAL_GAIN 39.3mV/MFR_IIN_CAL_GAIN 42.9mV/MFR_IIN_CAL_GAIN 46.4mV/MFR_IIN_CAL_GAIN 50mV/MFR_IIN_CAL_GAIN 37.5mV/MFR_IIN_CAL_GAIN High Range (Nominal Loop Gain) MFR_PWM_MODE_LTC7880 [7]=142.9mV/MFR_IIN_CAL_GAIN 48.2mV/MFR_IIN_CAL_GAIN 53.6mV/MFR_IIN_CAL_GAIN 58.9mV/MFR_IIN_CAL_GAIN 64.3mV/MFR_IIN_CAL_GAIN 69.6mV/MFR_IIN_CAL_GAIN 75mV/MFR_IIN_CAL_GAIN Note: This is the peak of the current waveform. The READ_IIN command returns the average current. The peak input current limits are adjusted with temperature based on the MFR_IIN_CAL_GAIN_TC using the equation: Peak Current Limit = MFR_IIN_CAL_GAIN • (1 + MFR_IIN_CAL_GAIN_TC • (READ_TEMPERTURE_1-27.0)). The L TpowerPlay GUI automatically convert the voltages to currents. The IIN range is set with bit 7 of the MFR_PWM_MODE_LTC7880 command. This command has two data bytes and is formatted in Linear_5s_11s format. Input Current and Limits COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS EEPROM DEFAUL T VALUE MFR_IIN_CAL_GAIN 0xE8 The resistance value of the input current sense element in mΩ. R/W Word Y L11 mΩ Y 3.0 0xC300 MFR_IIN_CAL_GAIN The IIN_CAL_GAIN command is used to set the resistance value of the input current sense resistor in milliohms. (see also READ_IIN). This command has two data bytes and is formatted in Linear_5s_11s format.

Rev 0 For more information www.analog.com PMBus COMMAND DETAILS TEMPERATURE External Temperature Calibration COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS EEPROM DEFAUL T VALUE MFR_TEMP_1_GAIN 0xF8 Sets the slope of the external temperature sensor . R/W Word Y CF Y 1.0 0x4000 MFR_TEMP _1_OFFSET 0xF9 Sets the offset of the external temperature sensor . R/W Word Y L11 C Y 0.0 0x8000 MFR_TEMP_1_GAIN The MFR_TEMP_1_GAIN command will modify the slope of the external temperature sensor to account for non-idealities in the element and errors associated with the remote sensing of the temperature in the inductor . This command has two data bytes and is formatted in 16-bit 2’s complement integer . The effective gain adjustment is N • 2–14. The nominal value is 1. MFR_TEMP_1_OFFSET The MFR_TEMP_1_OFFSET command will modify the offset of the external temperature sensor to account for non- idealities in the element and errors associated with the remote sensing of the temperature in the inductor . This command has two data bytes and is formatted in Linear_5s_11s format. External Temperature Limits COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS EEPROM DEFAUL T VALUE OT_FAULT_LIMIT 0x4F External overtemperature fault limit. R/W Word Y L11 C Y 100.0 0xEB20 OT_WARN_LIMIT 0x51 External overtemperature warning limit. R/W Word Y L11 C Y 85.0 0xEAA8 UT_FAULT_LIMIT 0x53 External undertemperature fault limit. R/W Word Y L11 C Y –40.0 0xE580 OT_FAULT_LIMIT The OT_FAULT_LIMIT command sets the value of the external sense temperature measured by the ADC, in degrees Celsius, which causes an overtemperature fault. The READ_TEMPERATURE_1 value will be used to determine if this limit has been exceeded. This command has two data bytes and is formatted in Linear_5s_11s format.

• Sets the TEMPERATURE Fault bit in the STATUS_BYTE
• Sets the OT Fault bit in the STATUS_TEMPERATURE command
• Notifies the host by asserting ALERT pin, unless masked

Rev 0For more information www.analog.com PMBus COMMAND DETAILS OT_WARN_LIMIT The OT_WARN_LIMIT command sets the value of the external sense temperature measured by the ADC, in degrees Celsius, which causes an overtemperature warning. The READ_TEMPERATURE_1 value will be used to determine if this limit has been exceeded. In response to the OT_WARN_LIMIT being exceeded, the device:

• Sets the TEMPERATURE bit in the STATUS_BYTE
• Sets the Overtemperature Warning bit in the STATUS_TEMPERATURE command, and
• Notifies the host by asserting ALERT pin, unless masked This command has two data bytes and is formatted in Linear_5s_11s format. UT_FAULT_LIMIT The UT_FAULT_LIMIT command sets the value of the external sense temperature measured by the ADC, in degrees Celsius, which causes an undertemperature fault. The READ_TEMPERATURE_1 value will be used to determine if this limit has been exceeded. Note : If the temp sensors are not installed, the UT_FAULT_LIMIT can be set to –275°C and UT_FAULT_LIMIT response set to ignore to avoid ALERT being asserted. This command has two data bytes and is formatted in Linear_5s_11s format.
• Sets the TEMPERATURE Fault bit in the STATUS_BYTE
• Sets the UT Fault bit in the STATUS_TEMPERATURE command
• Notifies the host by asserting ALERT pin, unless masked TIMING Timing—On Sequence/Ramp COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS EEPROM DEFAUL T VALUE TON_DELAY 0x60 Time from RUN and/or Operation on to output rail turn-on. R/W Word Y L11 ms Y 0.0 0x8000 TON_RISE 0x61 Time from when the output starts to rise until the output voltage reaches the VOUT commanded value. R/W Word Y L11 ms Y 8.0 0xD200 TON_MAX_FAULT_LIMIT 0x62 Maximum time from the start of TON_ RISE for VOUT to cross the VOUT_UV_ FAULT_LIMIT. R/W Word Y L11 ms Y 10.0 0xD280 VOUT_TRANSITION_RATE 0x27 Rate the output changes when VOUT commanded to a new value. R/W Word Y L11 V/ms Y 0.25 0xAA00 TON_DELAY The TON_DELAY command sets the time, in milliseconds, from when a start condition is received until the output voltage starts to rise. Values from 0ms to 83 seconds are valid. The resulting turn-on delay will have a typical delay of 270µs for TON_DELAY = 0 and an uncertainty of ±50µs for all values of TON_DELAY. This command has two data bytes and is formatted in Linear_5s_11s format.

Rev 0 For more information www.analog.com PMBus COMMAND DETAILS TON_RISE The TON_RISE command sets the time, in milliseconds, from the time the output starts to rise to the time the output enters the regulation band. Values from 0 to 1.3 seconds are valid. The part will be in discontinuous mode during TON_RISE events. If TON_RISE is less than 0.25ms, the LTC7880 digital slope will be bypassed and the output voltage transition will only be controlled by the analog performance of the PWM switcher . The number of steps in TON_RISE is equal to TON_RISE (in ms)/0.1ms with an uncertainty of ±0.1ms. This command has two data bytes and is formatted in Linear_5s_11s format. TON_MAX_FAULT_LIMIT The TON_MAX_FAULT_LIMIT command sets the value, in milliseconds, on how long the unit can attempt to power up the output without reaching the output undervoltage fault limit, or output overcurrent limit. A data value of 0ms means that there is no limit and that the unit can attempt to bring up the output voltage indefinitely. The maximum limit is 83 seconds. This command has two data bytes and is formatted in Linear_5s_11s format.

• Sets the VOUT Fault bit in the STATUS_WORD
• Sets the TON_MAX Fault bit in the STATUS_VOUT command
• Notifies the host by asserting ALERT pin, unless masked VOUT_TRANSITION_RATE When a PMBus device receives either a VOUT_COMMAND or OPERATION (Margin High, Margin Low) that causes the output voltage to change this command set the rate in V/ms at which the output voltage changes. This commanded rate of change does not apply when the unit is commanded on or off. The maximum allowed slope is 4V/ms. This command has two data bytes and is formatted in Linear_5s_11s format. Timing—Off Sequence/Ramp COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS EEPROM DEFAUL T VALUE TOFF_DELAY 0x64 Time from RUN and/or Operation off to the start of TOFF_FALL ramp. R/W Word Y L11 ms Y 0.0 0x8000 TOFF_FALL 0x

65 Time from when the output starts to fall

until the output reaches zero volts. R/W Word Y L11 ms Y 8.0 0xD200 TOFF_MAX_WARN_LIMIT 0x

66 Maximum allowed time, after TOFF_FALL

completed, for the unit to decay below 12.5%. R/W Word Y L11 ms Y 150 0xF258 TOFF_DELAY The TOFF_DELAY command sets the time, in milliseconds, from when a stop condition is received until the output voltage starts to fall. Values from 0 to 83 seconds are valid. The resulting turn off delay will have a typical delay of 270µs for TOFF_DELAY = 0 and an uncertainty of ±50µs for all values of TOFF_DELAY. TOFF_DELAY is not applied when a fault event occurs This command has two data bytes and is formatted in Linear_5s_11s format.

Rev 0For more information www.analog.com PMBus COMMAND DETAILS TOFF_FALL The TOFF_FALL command sets the time, in milliseconds, from the end of the turn-off delay time until the output volt- age is commanded to zero. It is the ramp time of the VOUT DAC. When the VOUT DAC is zero, the PWM output will be set to high impedance state. The part will maintain the mode of operation programmed. For defined TOFF_FALL times, the user should set the part to continuous conduction mode. Loading the max value indicates the part will ramp down at the slowest possible rate. fall time is 1.3 seconds. The number of steps in TOFF_FALL is equal to TOFF_FALL (in ms)/0.1ms with an uncertainty of ±0.1ms. In discontinuous conduction mode, the controller will not draw current from the load and the fall time will be set by the output capacitance and load current. This command has two data bytes and is formatted in Linear_5s_11s format. TOFF_MAX_WARN_LIMIT The TOFF_MAX_WARN_LIMIT command sets the value, in milliseconds, on how long the unit can attempt to turn off the output until a warning is asserted. The output is considered off when the V OUT voltage is less than 12.5% of the programmed VOUT_COMMAND value. The calculation begins after TOFF_FALL is complete. A data value of 0ms means that there is no limit and that the unit can attempt to turn off the output voltage indefinitely. Other than 0, values from 120ms to 524 seconds are valid. This command has two data bytes and is formatted in Linear_5s_11s format.

• Sets the VOUT Fault bit in the STATUS_WORD
• Sets the TOFF_MAX Warning bit in the STATUS_VOUT command
• Notifies the host by asserting ALERT pin, unless masked Precondition for Restart COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS EEPROM DEFAUL T VALUE MFR_RESTART_ DELAY 0xDC Minimum time the RUN pin is held low by the LTC7880. R/W Word Y L11 ms Y 500 0xFBE8 MFR_RESTART_DELAY This command specifies the minimum RUN off time in milliseconds. This device will pull the RUN pin low for this length of time once a falling edge of RUN has been detected. The minimum recommended value is 136ms. Note: The restart delay is different than the retry delay. The restart delay pulls RUN low for the specified time, after which a standard start-up sequence is initiated. The minimum restart delay should be equal to TOFF_DELAY + TOFF_ FALL + 136ms. Valid values are from 136ms to 65.52 seconds in 16ms increments. To assure a minimum off time, set the MFR_RESTART_DELAY 16ms longer than the desired time. The output rail can be off longer than the MFR_ RESTART_DELAY after the RUN pin is pulled high by an external resistor if the output decay bit 0 is enabled in MFR_ CHAN_CONFIG_LT C7880 and the output takes a long time to decay below 12.5% of the programmed value. This command has two data bytes and is formatted in Linear_5s_11s format.

Rev 0 For more information www.analog.com PMBus COMMAND DETAILS FAUL T RESPONSE Fault Responses All Faults COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS EEPROM DEFAUL T VALUE MFR_RETRY_ DELAY 0xDB Retry interval during FAUL T retry mode. R/W Word Y L11 ms Y 350 0xFABC MFR_RETRY_DELAY This command sets the time in milliseconds between retries if the fault response is to retry turn on after a fault has occured. This command value is used for all fault responses that require retry. The retry time starts once the fault has been detected by the offending channel. Valid values are from 120ms to 83.88 seconds in 1ms increments. Note: The retry delay time is determined by the longer of the MFR_RETRY_DELAY command or the time required for the regulated output to decay below 12.5% of the programmed value. If the natural decay time of the output is too long, it is possible to remove the voltage requirement of the MFR_RETRY_DELAY command by asserting bit 0 of MFR_CHAN_CONFIG_LTC7880. This command has two data bytes and is formatted in Linear_5s_11s format. Fault Responses Input Voltage COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS EEPROM DEFAUL T VALUE VIN_OV_FAULT_RESPONSE 0x56 Action to be taken by the device when an input supply overvoltage fault is detected. R/W Byte Y Reg Y 0x00 VIN_OV_FAULT_RESPONSE The VIN_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an input over - voltage fault. The data byte is in the format given in Table 7. The device also

• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Set the INPUT bit in the upper byte of the STATUS_WORD
• Sets the VIN Overvoltage Fault bit in the STATUS_INPUT command, and
• Notifies the host by asserting ALERT pin, unless masked This command has one data byte.

Rev 0For more information www.analog.com PMBus COMMAND DETAILS Fault Responses Output Voltage COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS EEPROM DEFAUL T VALUE VOUT_OV_FAULT_RESPONSE 0x41 Action to be taken by the device when an output overvoltage fault is detected. R/W Byte Y Reg Y 0x00 VOUT_UV_FAULT_RESPONSE 0x45 Action to be taken by the device when an output undervoltage fault is detected. R/W Byte Y Reg Y 0xB8 TON_MAX_FAULT_ RESPONSE 0x63 Action to be taken by the device when a TON_MAX_FAULT event is detected. R/W Byte Y Reg Y 0xB8 VOUT_OV_FAULT_RESPONSE The VOUT_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an output overvoltage fault. The data byte is in the format given in Table 7. The device also:

• Sets the VOUT_OV bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the VOUT Overvoltage Fault bit in the STATUS_VOUT command
• Notifies the host by asserting ALERT pin, unless masked The only values recognized for this command are: 0x00–Part forces TG high. 0x80–The device shuts down (disables the output) and the unit does not attempt to retry. (PMBus, Part II, Section 10.7). 0xB8–The device shuts down (disables the output) and device attempts to retry continuously, without limitation, until it is commanded OFF (by the RUN pin or OPERATION command or both), bias power is removed, or another fault condition causes the unit to shut down. 0x4n The device shuts down and the unit does not attempt to retry. The output remains disabled until the part is com- manded OFF then ON or the RUN pin is asserted low then high or RESET through the command or removal of VIN. The OV fault must remain active for a period of n
• 10µs, where n is a value from 0 to 7. 0x78+n The device shuts down and the unit attempts to retry continuously until either the fault condition is cleared or the part is commanded OFF then ON or the RUN pin is asserted low then high or RESET through the command or removal of VIN. The OV fault must remain active for a period of n • 10µs, where n is a value from 0 to 7. Any other value will result in a CML fault and the write will be ignored. This command has one data byte.

Table 7. VOUT_OV_FAULT_RESPONSE , VIN_OV_FAULT_RESPONSE Data Byte Contents

• Sets the corresponding fault bit in the status commands and
• Notifies the host by asserting ALERT pin, unless masked. The fault bit, once set, is cleared only when one or more of the following events occurs:
• The device receives a CLEAR_FAULTS command.
• The output is commanded through the RUN pin, the OPERATION command, or the combined action of the RUN pin and OPERATION command, to turn off and then to turn back on, or
• Bias power is removed and reapplied to the LTC7880. 00 Part forces TG high. (Recommended to minimize power dissipation and prevent damage to the top MOSFET).

01 The PMBus device continues operation for the delay time

10 The device shuts down immediately (disables the output) and

responds according to the retry setting in bits [5:3]. 11 Not supported. Writing this value will generate a CML fault.

111 The PMBus device attempts to restart continuously, without

detected. Only valid for deglitched off state. undervoltage fault. The data byte is in the format given in Table 8.

• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the VOUT undervoltage fault bit in the STATUS_VOUT command
• Notifies the host by asserting ALERT pin, unless masked The UV fault and warn are masked until the following criteria are achieved: 1) The TON_MAX_FAULT_LIMIT has been reached 2) The TON_DELAY sequence has completed 3) The TON_RISE sequence has completed 4) The VOUT_UV_FAULT_LIMIT threshold has been reached The UV fault and warn are masked whenever the channel is not active. The UV fault and warn are masked during TON_RISE and TOFF_FALL sequencing. This command has one data byte.

Table 8. VOUT_UV_FAULT_RESPONSE Data Byte Contents

• Sets the corresponding fault bit in the status commands and
• Notifies the host by asserting ALERT pin, unless masked. The fault bit, once set, is cleared only when one or more of the following events occurs:
• The device receives a CLEAR_FAULTS command.
• The output is commanded through the RUN pin, the OPERATION command, or the combined action of the RUN pin and OPERATION command, to turn off and then to turn back on, or
• The device receives a RESTORE_USER_ALL command.
• The device receives a MFR_RESET command.
• The device supply power is cycled. 00 The PMBus device continues operation without interruption. (Ignores the fault functionally)

10 The device shuts down (disables the output) and responds

according to the retry setting in bits [5:3]. 11 Not supported. Writing this value will generate a CML fault. detected. Only valid for deglitched off state. fault. The data byte is in the format given in Table 11.

• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the TON_MAX_FAULT bit in the STATUS_VOUT command, and
• Notifies the host by asserting ALERT pin, unless masked A value of 0 disables the TON_MAX_FAULT_RESPONSE. It is not recommended to use 0. This command has one data byte. Fault Responses IC Temperature COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS EEPROM DEFAUL T VALUE MFR_OT_FAULT_ RESPONSE 0xD6 Action to be taken by the device when an internal overtemperature fault is detected. R Byte N Reg 0xC0

overtemperature fault. The data byte is in the format given in Table 9.

• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the MFR bit in the STATUS_WORD, and
• Sets the Overtemperature Fault bit in the STATUS_MFR_SPECIFIC command
• Notifies the host by asserting ALERT pin, unless masked This command has one data byte.

Table 9. Data Byte Contents MFR_OT_FAULT_RESPONSE

• Sets the corresponding fault bit in the status commands and
• Notifies the host by asserting ALERT pin, unless masked. The fault bit, once set, is cleared only when one or more of the following events occurs:
• The device receives a CLEAR_FAULTS command.
• The output is commanded through the RUN pin, the OPERATION command, or the combined action of the RUN pin and OPERATION command, to turn off and then to turn back on, or
• Bias power is removed and reapplied to the LTC7880. 00 Not supported. Writing this value will generate a CML fault. 01 Not supported. Writing this value will generate a CML fault

responds according to the retry setting in bits [5:3]. 11 The device’s output is disabled while the fault is present. disabled until the fault is cleared. 001-111 Not supported. Writing this value will generate CML fault. external undertemperature fault is detected. perature fault on the external temp sensors. The data byte is in the format given in Table 10.

• Sets the TEMPERATURE bit in the STATUS_BYTE
• Sets the Overtemperature Fault bit in the STATUS_TEMPERATURE command, and
• Notifies the host by asserting ALERT pin, unless masked This command has one data byte. UT_FAULT_RESPONSE The UT_FAULT_RESPONSE command instructs the device on what action to take in response to an external under - temperature fault on the external temp sensors. The data byte is in the format given in Table 11. The device also
• Sets the TEMPERATURE bit in the STATUS_BYTE
• Sets the Undertemperature Fault bit in the STATUS_TEMPERATURE command, and
• Notifies the host by asserting ALERT pin, unless masked This condition is detected by the ADC so the response time may be up to 90ms. This command has one data byte.

Table 10. Data Byte Contents: TON_MAX_FAULT_RESPONSE, OT_FAULT_RESPONSE, UT_FAULT_RESPONSE

• Sets the corresponding fault bit in the status commands, and
• Notifies the host by asserting ALERT pin, unless masked. The fault bit, once set, is cleared only when one or more of the following events occurs:
• The device receives a CLEAR_FAULTS command.
• The output is commanded through the RUN pin, the OPERATION command, or the combined action of the RUN pin and OPERATION command, to turn off and then to turn back on, or
• The device receives a RESTORE_USER_ALL command.
• The device receives a MFR_RESET command.
• The device supply power is cycled. 00 The PMBus device continues operation without interruption. 01 Not supported. Writing this value will generate a CML fault.

responds according to the retry setting in bits [5:3]. 11 Not supported. Writing this value will generate a CML fault.

Rev 0 For more information www.analog.com PMBus COMMAND DETAILS FAUL T SHARING Fault Sharing Propagation COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS EEPROM DEFAUL T VALUE MFR_FAULT_ PROPAGATE_LTC7880 0xD2 Configuration that determines which faults are propagated to the FAUL T pins. R/W Word Y Reg Y 0x6993 MFR_FAULT_PROPAGATE_LTC7880 The MFR_FAULT_PROPAGATE_LTC7880 command enables the faults that can cause the FAUL Tn pin to assert low. The command is formatted as shown in Table 11. Faults can only be propagated to the FAUL Tn pin if they are programmed to respond to faults. This command has two data bytes. Table 11: FAUL Tn Propagate Fault Configuration The FAUL T0 and FAUL T1 pins are designed to provide electrical notification of selected events to the user . Some of these events are common to both output channels. Others are specific to an output channel. They can also be used to share faults between channels. BIT(S) SYMBOL OPERATION B[15] VOUT disabled while not decayed. This is used in a PolyPhase configuration when bit 0 of the MFR_CHAN_CONFIG_LTC7880 is a zero. If the channel is turned off, by toggling the RUN pin or commanding the part OFF , and then the RUN is reasserted or the part is commanded back on before the output has decayed, VOUT will not restart until the 12.5% decay is honored. The FAUL T pin is asserted during this condition if bit 15 is asserted. B[14] Mfr_FAULT_propagate_short_CMD_ cycle 0: No action 1: Asserts low if commanded off then on before the output has sequenced off. Re-asserts high 120ms after sequence off. b[13] Mfr_FAULT_propagate_ton_max_fault 0: No action if a TON_MAX_FAULT fault is asserted 1: Associated output will be asserted low if a TON_MAX_FAULT fault is asserted FAUL T0 is associated with page 0 TON_MAX_FAULT faults FAUL T1 is associated with page 1 TON_MAX_FAULT faults b[12] Reserved Must be 0 b[11] Mfr_FAULT0_propagate_int_ot, Mfr_FAULT1_propagate_int_ot 0: No action if the MFR_OT_FAULT_LIMIT fault is asserted 1: Associated output will be asserted low if the MFR_OT_FAULT_LIMIT fault is asserted b[10] Reserved Must be 0 b[9] Reserved Must be 0

Rev 0For more information www.analog.com BIT(S) SYMBOL OPERATION b[8] Mfr_FAULT0_propagate_ut, Mfr_FAULT1_propagate_ut 0: No action if the UT_FAULT_LIMIT fault is asserted 1: Associated output will be asserted low if the UT_FAULT_LIMIT fault is asserted FAUL T0 is associated with page 0 UT faults FAUL T1 is associated with page 1 UT faults b[7] Mfr_FAULT0_propagate_ot, Mfr_FAULT1_propagate_ot 0: No action if the OT_FAULT_LIMIT fault is asserted 1: Associated output will be asserted low if the OT_FAULT_LIMIT fault is asserted FAUL T0 is associated with page 0 OT faults FAUL T1 is associated with page 1 OT faults b[6] Reserved b[5] Reserved b[4] Mfr_FAULT0_propagate_input_ov, Mfr_FAULT1_propagate_input_ov 0: No action if the VIN_OV_FAULT_LIMIT fault is asserted 1: Associated output will be asserted low if the VIN_OV_FAULT_LIMIT fault is asserted b[3] Reserved b[2] Reserved b[1] Mfr_FAULT0_propagate_vout_uv, Mfr_FAULT1_propagate_vout_uv 0: No action if the VOUT_UV_FAULT_LIMIT fault is asserted 1: Associated output will be asserted low if the VOUT_UV_FAULT_LIMIT fault is asserted FAUL T0 is associated with page 0 UV faults FAUL T1 is associated with page 1 UV faults b[0] Mfr_FAULT0_propagate_vout_ov, Mfr_FAULT1_propagate_vout_ov 0: No action if the VOUT_OV_FAULT_LIMIT fault is asserted 1: Associated output will be asserted low if the VOUT_OV_FAULT_LIMIT fault is asserted FAUL T0 is associated with page 0 OV faults FAUL T1 is associated with page 1 OV faults Fault Sharing Response COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS EEPROM DEFAUL T VALUE MFR_FAULT_RESPONSE 0xD5 Action to be taken by the device when the FAUL T pin is asserted low. R/W Byte Y Reg Y 0xC0 MFR_FAULT_RESPONSE The MFR_FAULT_RESPONSE command instructs the device on what action to take in response to the FAUL Tn pin being pulled low by an external source. Supported Values: VALUE MEANING 0xC0 FAULT_INHIBIT The LTC7880 will three-state the output in response to the FAUL T pin pulled low. 0x00 FAULT_IGNORE The LTC7880 continues operation without interruption. PMBus COMMAND DETAILS

Rev 0 For more information www.analog.com The device also: Sets the MFR_SPECIFIC Bit in the STATUS_WORD. Sets Bit 0 in the STATUS_MFR_SPECIFIC Command to Indicate FAUL Tn Is Being Pulled Low Notifies the Host by Asserting ALERT, Unless Masked This command has one data byte. SCRATCHPAD COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS EEPROM DEFAUL T VALUE USER_DATA_00 0xB0 OEM reserved. Typically used for part serialization. R/W Word N Reg Y NA USER_DATA_01 0xB1 Manufacturer reserved for L TpowerPlay. R/W Word Y Reg Y NA USER_DATA_02 0xB2 OEM reserved. Typically used for part serialization. R/W Word N Reg Y NA USER_DATA_03 0xB3 A EEPROM word available for the user . R/W Word Y Reg Y 0x0000 USER_DATA_04 0xB4 A EEPROM word available for the user . R/W Word N Reg Y 0x0000 USER_DATA_00 through USER_DATA_04 These commands are non-volatile memory locations for customer storage. The customer has the option to write any value to the USER_DATA_nn at any time. However , the L TpowerPlay software and contract manufacturers use some of these commands for inventory control. Modifying the reserved USER_DATA_nn commands may lead to undesirable inventory control and incompatibility with these products. These commands have 2 data bytes and are in register format. IDENTIFICATION COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS EEPROM DEFAUL T VALUE PMBUS_REVISION 0x98 PMBus revision supported by this device. Current revision is 1.2. R Byte N Reg FS 0x22 CAPABILITY 0x19 Summary of PMBus optional communication protocols supported by this device. R Byte N Reg 0xB0 MFR_ID 0x99 The manufacturer ID of the LTC7880 in ASCII. R String N ASC LT C MFR_MODEL 0x9A Manufacturer part number in ASCII. R String N ASC LTC7880 IC_DEVICE_ID 0xAD Identification of the IC R String N ASC LTC7880 IC_DEVICE_REV 0xAE Revision of the IC R String N ASC ACA0 MFR_SPECIAL_ID 0xE7 Manufacturer code representing the LTC7880. R Word N Reg 0x49EX PMBus COMMAND DETAILS

Rev 0For more information www.analog.com PMBus COMMAND DETAILS PMBus_REVISION The PMBUS_REVISION command indicates the revision of the PMBus to which the device is compliant. The LTC7880 is PMBus Version 1.2 compliant in both Part I and Part II. This read-only command has one data byte. CAPABILITY This command provides a way for a host system to determine some key capabilities of a PMBus device. The LTC7880 supports packet error checking, 400kHz bus speeds, and ALERT pin. This read-only command has one data byte. MFR_ID The MFR_ID command indicates the manufacturer ID of the LTC7880 using ASCII characters. This read-only command is in block format. MFR_MODEL The MFR_MODEL command indicates the manufacturer’s part number of the LTC7880 using ASCII characters. This read-only command is in block format. MFR_SPECIAL_ID The 16-bit word representing the part name and revision. 0x49EX denotes the part is an LTC7880, X is adjustable by the manufacturer . This read-only command has two data bytes. IC_DEVICE_ID The IC_DEVICE_ID command indicates the manufacturer’s ID of the LTC7880 using ASCII characters. This read-only command is in block format. IC_DEVICE_REV The IC_DEVICE_REV command indicates the revision of the LTC7880 using ASCII characters. This read-only command is in block format.

Rev 0 For more information www.analog.com PMBus COMMAND DETAILS FAUL T WARNING AND STATUS COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED FORMAT UNITS EEPROM DEFAUL T VALUE CLEAR_FAULTS 0x03 Clear any fault bits that have been set. Send Byte N NA SMBALERT_MASK 0x1B Mask activity. Block R/W Y Reg Y See CMD Details MFR_CLEAR_PEAKS 0xE3 Clears all peak values. Send Byte N NA STATUS_BYTE 0x78 One byte summary of the unit’s fault condition. R/W Byte Y Reg NA STATUS_WORD 0x79 T wo byte summary of the unit’s fault condition. R/W Word Y Reg NA STATUS_VOUT 0x7A Output voltage fault and warning status. R/W Byte Y Reg NA STATUS_INPUT 0x7C Input supply fault and warning status. R/W Byte N Reg NA STATUS_ TEMPERATURE 0x7D External temperature fault and warning status for READ_TEMERATURE_1. R/W Byte Y Reg NA STATUS_CML 0x7E Communication and memory fault and warning status. R/W Byte N Reg NA STATUS_MFR_ SPECIFIC 0x80 Manufacturer specific fault and state information. R/W Byte Y Reg NA MFR_PADS 0xE5 Digital status of the I/O pads. R Word N Reg NA MFR_COMMON 0xEF Manufacturer status bits that are common across multiple L TC chips. R Byte N Reg NA MFR_INFO 0xB6 Manufacturing specific information. R Word N Reg NA CLEAR_FAULTS The CLEAR_FAULTS command is used to clear any fault bits that have been set. This command clears all bits in all status commands simultaneously. At the same time, the device negates (clears, releases) its ALERT pin signal output if the device is asserting the ALERT pin signal. If the fault is still present when the bit is cleared, the fault bit will remain set and the host notified by asserting the ALERT pin low. CLEAR_FAULTS can take up to 10µs to process. If a fault occurs within that time frame it may be cleared before the status register is set. This write-only command has no data bytes. The CLEAR_FAULTS does not cause a unit that has latched off for a fault condition to restart. Units that have shut down for a fault condition are restarted when: The output is commanded through the RUN pin, the OPERA TION command, or the combined action of the RUN pin and OPERATION command, to turn off and then to turn back on, or MFR_RESET command is issued. Bias power is removed and reapplied to the integrated cir cuit

bits would continue to assert ALERT if set. of any supported status register , again without PEC. SMBALERT_MASK cannot be applied to STATUS_BYTE, STATUS_WORD, MFR_COMMON or MFR_PADS_LTC7880. SMBALERT_MASK will generate a CML for Invalid/Unsupported Data. Figure 48. Example of Setting SMBALERT_MASK

7880 F48

Figure 49. Example of Reading SMBALERT_MASK

7880 F49

Rev 0 For more information www.analog.com PMBus COMMAND DETAILS MFR_CLEAR_PEAKS The MFR_CLEAR_PEAKS command clears the MFR_*_PEAK data values. A MFR_RESET command will also clear the MFR_*_PEAK data values. This write-only command has no data bytes. STATUS_BYTE The STATUS_BYTE command returns one byte of information with a summary of the most critical faults. This is the lower byte of the status word. STATUS_BYTE Message Contents: BIT STATUS BIT NAME MEANING 7* BUSY A fault was declared because the LTC7880 was unable to respond. 6 OFF This bit is set if the channel is not providing power to its output, regardless of the reason, including simply not being enabled. 5 VOUT_OV An output overvoltage fault has occurred.

4 IOUT_OC Not supported (LTC7880 returns 0)

3 VIN_UV Not supported (LTC7880 returns 0). 2 TEMPERATURE A temperature fault or warning has occurred. 1 CML A communications, memory or logic fault has occurred. 0* NONE OF THE ABOVE A fault Not listed in bits[7:1] has occurred. *ALERT can be asserted if either of these bits is set. They may be cleared by writing a 1 to their bit position in the STATUS_BYTE, in lieu of a CLEAR_ FAULTS command. This command has one data byte. STATUS_WORD The STATUS_WORD command returns a two-byte summary of the channel's fault condition. The low byte of the STATUS_WORD is the same as the STATUS_BYTE command. STATUS_WORD High Byte Message Contents: BIT STATUS BIT NAME MEANING 15 VOUT An output voltage fault or warning has occurred.

14 IOUT Not supported (LTC7880 returns 0)

13 INPUT An input voltage fault or warning has occurred. 12 MFR_SPECIFIC A fault or warning specific to the LTC7880 has occurred. 11 POWER_GOOD# The POWER_GOOD state is false if this bit is set. 10 FANS Not supported (LTC7880 returns 0). 9 OTHER Not supported (LTC7880 returns 0). 8 UNKNOWN Not supported (LTC7880 returns 0). If any of the bits in the upper byte are set, NONE_OF_THE_ABOVE is asserted. This command has two data bytes.

Rev 0For more information www.analog.com PMBus COMMAND DETAILS STATUS_VOUT The STATUS_VOUT command returns one byte of VOUT status information. STATUS_VOUT Message Contents: BIT MEANING 7 V OUT overvoltage fault. 6 V OUT overvoltage warning. 5 V OUT undervoltage warning. 4 V OUT undervoltage fault. 3 V OUT max warning. 2 TON max fault. 1 TOFF max fault. 0 Not supported (LTC7880 returns 0). The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear status by means other than using the CLEAR_FAULTS command. Any supported fault bit in this command will initiate an ALERT event. This command has one data byte. STATUS_INPUT The STATUS_INPUT command returns one byte of VIN (VINSNS) status information. STATUS_INPUT Message Contents: BIT MEANING 7 V IN overvoltage fault. 6 Not supported (LTC7880 returns 0). 5 V IN undervoltage warning. 4 Not supported (LTC7880 returns 0).

3 Unit off for insufficient V

IN. 2 Not supported (LTC7880 returns 0).

1 Not supported (LTC7880 returns 0)

0 Not supported (LTC7880 returns 0). The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear status by means other than using the CLEAR_FAULTS command. Any supported fault bit in this command will initiate an ALERT event. Bit 3 of this command is not latched and will not generate an ALERT even if it is set. This command has one data byte.

Rev 0 For more information www.analog.com PMBus COMMAND DETAILS STATUS_TEMPERATURE The STATUS_TEMPERATURE commands returns one byte with status information on temperature. This is a paged command and is related to the respective READ_TEMPERATURE_1 value. STATUS_TEMPERATURE Message Contents: BIT MEANING 7 External overtemperature fault. 6 External overtemperature warning. 5 Not supported (LTC7880 returns 0). 4 External undertemperature fault. 3:0 Not supported (LTC7880 returns 0). The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear status by means other than using the CLEAR_FAULTS command. This command has one data byte. STATUS_CML The STATUS_CML command returns one byte of status information on received commands, internal memory and logic. STATUS_CML Message Contents: BIT MEANING 7 Invalid or unsupported command received. 6 Invalid or unsupported data received. 5 Packet error check failed. 4 Memory fault detected. 3 Processor fault detected. 2 Reserved (LTC7880 returns 0). 1 Other communication fault. 0 Other memory or logic fault. If either bit 3 or bit 4 of this command is set, a serious and significant internal error has been detected. Continued operation of the part is not recommended if these bits are continuously set. The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear status by means other than using the CLEAR_FAULTS command. Any supported fault bit in this command will initiate an ALERT event. This command has one data byte.

Rev 0For more information www.analog.com PMBus COMMAND DETAILS STATUS_MFR_SPECIFIC The STATUS_MFR_SPECIFIC commands returns one byte with the manufacturer specific status information. The format for this byte is: BIT MEANING 7 Internal Temperature Fault Limit Exceeded. 6 Internal Temperature Warn Limit Exceeded. 5 Factory T rim Area EEPROM CRC Fault.

4 PLL is Unlocked

3 Fault Log Present

0 FAUL T Pin Asserted Low by External Device

If any of these bits are set, the MFR bit in the STATUS_WORD will be set, and ALERT may be asserted. The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear status by means other than using the CLEAR_FAULTS command. However , the fault log present bit can only be cleared by issuing the MFR_FAULT_LOG_CLEAR command. Any supported fault bit in this command will initiate an ALERT event. This command has one data byte. MFR_PADS This command provides the user a means of directly reading the digital status of the I/O pins of the device. The bit assignments of this command are as follows: BIT ASSIGNED DIGITAL PIN

15 V DD33 OV Fault

14 V DD33 UV Fault

13 Reserved

12 Reserved

11 ADC Values Invalid, Occurs During Start-Up. May Occur Briefly on Current Measurement Channels During Normal Operation

10 SYNC clocked by external device (when LTC7880 configured to drive SYNC pin)

9 Channel 1 Power Good

8 Channel 0 Power Good

7 LTC7880 Driving RUN1 Low

6 LTC7880 Driving RUN0 Low

5 RUN1 Pin State

4 RUN0 Pin State

3 LTC7880 Driving FAUL T1 Low

2 LTC7880 Driving FAUL T0 Low

1 FAUL T1 Pin State

0 FAUL T0 Pin State

A 1 indicates the condition is true. This read-only command has two data bytes.

Rev 0 For more information www.analog.com PMBus COMMAND DETAILS MFR_COMMON The MFR_COMMON command contains bits that are common to all L TC digital power and telemetry products. BIT MEANING

7 Chip Not Driving ALERT Low

6 LTC7880 Not Busy

5 Calculations Not Pending

4 LTC7880 Outputs Not in T ransition

3 EEPROM Initialized

2 Reserved

1 SHARE_CLK Timeout

0 WP Pin Status

This read-only command has one data byte. MFR_INFO The MFR_INFO command contains the EEPROM status bit. MFR_INFO Data Contents BIT MEANING 15:6 Reserved

5 EEPROM ECC status

0b Corrections made in the EEPROM user space 1b No corrections made in the EEPROM user space 4:0 Reserved EEPROM ECC status is updated after each RESTORE_USER_ALL or RESET command, a power-on reset or a EEPROM bulk read operation. This read-only command has two data bytes.

Rev 0For more information www.analog.com PMBus COMMAND DETAILS TELEMETRY COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED FORMAT UNITS EEPROM DEFAUL T VALUE READ_VIN 0x88 Measured input supply voltage at the V IN1 pin. R Word N L11 V NA READ_IIN 0x89 Measured input supply current. R Word Y L11 A NA READ_VOUT 0x8B Measured output voltage. R Word Y L16 V NA READ_IOUT 0x8C Measured output current. R Word N L11 A NA READ_TEMPERATURE_1 0x8D External diode junction temperature. This is the value used for all temperature related processing, including IOUT_CAL_GAIN. R Word Y L11 C NA READ_TEMPERATURE_2 0x8E Internal junction temperature. Does not affect any other commands. R Word N L11 C NA READ_FREQUENCY 0x95 Measured PWM switching frequency. R Word N L11 kHz NA READ_POUT 0x96 Calculated output power . R Word N L11 W NA READ_PIN 0x97 Calculated input power . R Word Y L11 W NA MFR_IOUT_PEAK 0xD7 Report the maximum measured value of READ_IOUT since last MFR_CLEAR_PEAKS. R Word N L11 A NA MFR_ADC_CONTROL 0xD8 ADC telemetry parameter selected for repeated fast ADC read back R/W Byte N Reg 0x00 MFR_VOUT_PEAK 0xDD Maximum measured value of READ_VOUT since last MFR_CLEAR_PEAKS. R Word Y L16 V NA MFR_VIN_PEAK 0xDE Maximum measured value of READ_VIN since last MFR_CLEAR_PEAKS. R Word N L11 V NA MFR_TEMPERATURE_1_PEAK 0xDF Maximum measured value of external Temperature (READ_TEMPERATURE_1) since last MFR_CLEAR_PEAKS. R Word Y L11 C NA MFR_IIN_PEAK 0xE1 Maximum measured value of READ_IIN command since last MFR_CLEAR_PEAKS. R Word Y L11 A NA MFR_TEMPERATURE_2_PEAK 0xF4 Peak internal die temperature since last MFR_CLEAR_PEAKS. R W ord N L11 C NA READ_VIN The READ_VIN command returns the measured VIN1 pin voltage. This read-only command has two data bytes and is formatted in Linear_5s_11s format. READ_VOUT The READ_VOUT command returns the measured output voltage in the same format as set by the VOUT_MODE command. This read-only command has two data bytes and is formatted in Linear_16u format. READ_IOUT The READ_IOUT command returns the input current, in Amperes, as measured across the output current sense resis- tor (see also IOUT_CAL_GAIN). This read-only command has two data bytes and is formatted in Linear_5s_11s format.

Rev 0 For more information www.analog.com PMBus COMMAND DETAILS READ_IIN The READ_IIN command returns the average input current in amperes. The IIN value is a function of: a) the differential voltage measured across the ISENSE pins b) the IIN_CAL_GAIN value c) the MFR_IIN_CAL_GAIN_TC value, and d) READ_TEMPERATURE_1 value e) The MFR_TEMP_1_GAIN and the MFR_TEMP_1_OFFSET This read-only command has two data bytes and is formatted in Linear_5s_11s format. READ_TEMPERATURE_1 The READ_TEMPERATURE_1 command returns the temperature, in degrees Celsius, of the external sense element. This read-only command has two data bytes and is formatted in Linear_5s_11s format. READ_TEMPERATURE_2 The READ_TEMPERATURE_2 command returns the LTC7880’s die temperature, in degrees Celsius, of the internal sense element. This read-only command has two data bytes and is formatted in Linear_5s_11s format. READ_FREQUENCY The READ_FREQUENCY command is a reading of the PWM switching frequency in kHz measured at the input to the PWL PLL. This read-only command has 2 data bytes and is formatted in Linear_5s_11s format. READ_POUT The READ_POUT command is a reading of the DC/DC converter output power in Watts. POUT is calculated based on the most recent correlated output voltage and current reading. This read-only command has 2 data bytes and is formatted in Linear_5s_11s format. READ_PIN The READ_PIN command is a reading of the DC/DC converter input power in Watts. PIN is calculated based on the most recent input voltage and current reading. This read-only command has 2 data bytes and is formatted in Linear_5s_11s format. MFR_IOUT_PEAK The MFR_IOUT_PEAK command reports the highest current, in amperes, reported by the READ_IOUT measurement. This command is cleared using the MFR_CLEAR_PEAKS command. This read-only command has two data bytes and is formatted in Linear_5s_11s format.

Rev 0For more information www.analog.com PMBus COMMAND DETAILS MFR_ADC_CONTROL The MFR_ADC_CONTROL command determines the ADC read back selection. A default value of 0 in the command runs the standard telemetry loop with all parameters updated in a round robin fashion with a typical latency of 90ms. The user can command a non-zero value to monitored a single parameter with an approximate update rate of 8ms. This command has a latency of up to 2 ADC conversions or approximately 16ms (external temperature conversions may have a latency of up to 3 ADC conversion or approximately 24ms). It is recommended the part remain in standard telemetry mode except for special cases where fast ADC updates of a single parameter is required. The part should be commanded to monitor the desired parameter for a limited period of time (less then 1 second) then set the command back to standard round robin mode. If this command is set to any value except standard round robin telemetry (0) all warnings and faults associated with telemetry other than the selected parameter are effectively disabled and voltage servoing is disabled. When round robin is reasserted, all warnings and faults and servo mode are re-enabled. COMMANDED VALUE TELEMETRY COMMAND NAME DESCRIPTION 0x0F Reserved 0x0E Reserved 0x0D Reserved 0x0C READ_TEMPERATURE_1 Channel 1 external temperature 0x0B Reserved 0x0A READ_IIN Channel 1 measured input current 0x09 READ_VOUT Channel 1 measured output voltage 0x08 READ_TEMPERATURE_1 Channel 0 external temperature 0x07 Reserved 0x06 READ_IIN Channel 0 measured input current 0x05 READ_VOUT Channel 0 measured output voltage 0x04 READ_TEMPERATURE_2 Internal junction temperature 0x03 READ_IOUT Channel 0 measured output current 0x02 Reserved 0x01 READ_VIN Measured input supply voltage at the VIN1 pin 0x00 Standard ADC round robin telemetry If a reserved command value is entered, the telemetry will default to Internal IC Temperature and issue a CML fault. CML faults will continue to be issued by the LTC7880 until a valid command value is entered. The accuracy of the measured input supply voltage is only guaranteed if the MFR_ADC_CONTROL command is set to standard round robin telemetry. This write-only command has 1 data byte and is formatted in register format. MFR_VOUT_PEAK The MFR_VOUT_PEAK command reports the highest voltage, in volts, reported by the READ_VOUT measurement. This command is cleared using the MFR_CLEAR_PEAKS command. This read-only command has two data bytes and is formatted in Linear_16u format. MFR_VIN_PEAK The MFR_VIN_PEAK command reports the highest voltage, in volts, reported by the READ_VIN measurement. This command is cleared using the MFR_CLEAR_PEAKS command. This read-only command has two data bytes and is formatted in Linear_5s_11s format.

Rev 0 For more information www.analog.com PMBus COMMAND DETAILS MFR_TEMPERATURE_1_PEAK The MFR_TEMPERATURE_1_PEAK command reports the highest temperature, in degrees Celsius, reported by the READ_TEMPERATURE_1 measurement. This command is cleared using the MFR_CLEAR_PEAKS command. This read-only command has two data bytes and is formatted in Linear_5s_11s format. MFR_IIN_PEAK The MFR_READ_IIN_PEAK command reports the highest current, in Amperes, reported by the READ_IIN measurement. This command is cleared using the MFR_CLEAR_PEAKS command. This command has two data bytes and is formatted in Linear_5s_11s format. MFR_TEMPERATURE_2_PEAK The MFR_TEMPERATURE_2_PEAK command reports the highest temperature, in degrees Celsius, reported by the READ_TEMPERATURE_2 measurement. This command is cleared using the MFR_CLEAR_PEAKS command. This read-only command has two data bytes and is formatted in Linear_5s_11s format. EEPROM MEMORY COMMANDS Store/Restore COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED FORMAT UNITS EEPROM DEFAUL T VALUE STORE_USER_ALL 0x15 Store user operating memory to EEPROM. Send Byte N NA RESTORE_USER_ALL 0x16 Restore user operating memory from EEPROM. Send Byte N NA MFR_COMPARE_USER_ALL 0xF0 Compares current command contents with EEPROM. Send Byte N NA STORE_USER_ALL The STORE_USER_ALL command instructs the PMBus device to copy the non-volatile user contents of the Operating Memory to the matching locations in the non-volatile User EEPROM memory. Executing this command if the die temperature exceeds 85°C or is below 0°C is not recommended and the data reten- tion of 10 years cannot be guaranteed. If the die temperature exceeds 130°C, the STORE_USER_ALL command is disabled. The command is re-enabled when the IC temperature drops below 125°C. Communication with the LTC7880 and programming of the EEPROM can be initiated when VDD33 is available and VIN is not applied. To enable the part in this state, using global address 0x5B write MFR_EE_UNLOCK to 0x2B followed by 0xC4. The LTC7880 will now communicate normally, and the project file can be updated. To write the updated project file to the EEPROM issue a STORE_USER_ALL command. When VIN is applied, a MFR_RESET must be issued to allow the PWM to be enabled and valid ADCs to be read.

abled if the die exceeds 130°C and are not re-enabled until the die temperature drops below 125°C. This write-only command has no data bytes. This write-only command has no data bytes. what is stored in non-volatile memory. If the compare operation detects differences, a CML fault will be generated. This write-only command has no data bytes. A conceptual diagram of the fault log is shown in Figure 50. The fault log provides black box capability for the LTC7880. voltage readings, as well as the peak values of these quantities, are stored in a continuously updated buffer in RAM.

7880 F50

Figure 50. Fault Logging

Rev 0 For more information www.analog.com PMBus COMMAND DETAILS You can think of the operation as being similar to a strip chart recorder . When a fault occurs, the contents are written into EEPROM for non volatile storage. The EEPROM fault log is then locked. The part can be powered down with the fault log available for reading at a later time. MFR_FAULT_LOG The MFR_FAULT_LOG command allows the user to read the contents of the FAULT_LOG after the first fault occur - rence since the last MFR_FAULT_LOG_CLEAR command was written. The contents of this command are stored in non-volatile memor y, and are cleared by the MFR_FAULT_LOG_CLEAR command. The length and content of this command are listed in Table 13. If the user accesses the MFR_FAULT_LOG command and no fault log is present, the command will return a data length of 0. If a fault log is present, the MFR_FAULT_LOG will return a block of data 147 bytes long. The area available for the fault log in EEPROM is smaller than the area in RAM. When reading the fault log from RAM, all six events of cyclical data remain. However , when the fault log is read from EEPROM (after a reset), the last two events are lost. The read length of 147 bytes remains the same, but the fifth and sixth events are a repeat of the fourth event. If a fault occurs within the first second of applying power , some of the earlier pages in the fault log may not contain valid data. NOTE: The approximate transfer time for this command is 3.4ms using a 400kHz clock. This read-only command is in block format. MFR_FAULT_LOG_STORE The MFR_FAULT_LOG_STORE command forces the fault log operation to be written to EEPROM just as if a fault event occurred. This command will set bit 3 of the STATUS_MFR_SPECIFIC fault if bit 7 “Enable Fault Logging” is set in the MFR_CONFIG_ALL_LTC7880 command. If the die temperature is in excess of 130°C when the MFR_FAULT_LOG_STORE command is issued, the fault log is captured in the device's volatile RAM, but it is not written to the EEPROM. If and when the die temperature drops below 125°C, the part will then transfer the contents of the fault log from the device's volatile RAM into the partition of the EEPROM reserved for the fault log. This is also applicable to a standard fault log event if the fault log is enabled. This limitation in operation is to protect the EEPROM circuits from damage which may occur when the die temperature is in excess of 130°C. This write-only command has no data bytes.

Table 12. Fault Logging This table outlines the format of the block data from a read block data of the MFR_FAULT_LOG command. Fault Log Preface [7:0] ASC 0 Returns L Txx beginning at byte 0 if a partial or complete fault log exists. Fault Source [7:0] Reg 4 Refer to Table 13a. MFR_REAL_TIME [7:0] Reg 5 48 bit share-clock counter value when fault occurred (200µs resolution). MFR_VIN_PEAK [15:8] L11 19 Peak READ_VIN since last power-on or CLEAR_PEAKS command. READ_TEMPERATURE1 (PAGE 0) [15:8] L11 21 External temperature sensor 0 during last event. READ_TEMPERATURE1 (PAGE 1) [15:8] L11 23 External temperature sensor 1 during last event. READ_TEMPERATURE2 [15:8] L11 25 LTC7880 die temperature sensor during last event.

Rev 0 For more information www.analog.com CYCLICAL DATA EVENT n (Data at Which Fault Occurred; Most Recent Data) Event “n” represents one complete cycle of ADC reads through the MUX at time of fault. Example: If the fault occurs when the ADC is processing step 15, it will continue to take readings through step 25 and then store the header and all 6 event pages to EEPROM READ_VOUT (PAGE 0) [15:8] LIN 16 27 [7:0] LIN 16 28 READ_VOUT (PAGE 1) [15:8] LIN 16 29 [7:0] LIN 16 30 READ_IIN (PAGE 0) [15:8] LIN 11 31 [7:0] LIN 11 32 READ_IIN(PAGE 1) [15:8] LIN 11 33 [7:0] LIN 11 34 READ_VIN [15:8] LIN 11 35 [7:0] LIN 11 36 Reserved [15:8] LIN 11 37 [7:0] LIN 11 38 STATUS_VOUT (PAGE 0) BYTE 39 STATUS_VOUT (PAGE 1) BYTE 40 STATUS_WORD (PAGE 0) [15:8] WORD 41 [7:0] WORD 42 STATUS_WORD (PAGE 1) [15:8] WORD 43 [7:0] WORD 44 STATUS_MFR_SPECIFIC (PAGE 0) BYTE 45 STATUS_MFR_SPECIFIC (PAGE 1) BYTE 46 EVENT n-1 (data measured before fault was detected) READ_VOUT (PAGE 0) [15:8] LIN 16 47 [7:0] LIN 16 48 READ_VOUT (PAGE 1) [15:8] LIN 16 49 [7:0] LIN 16 50 READ_IIN (PAGE 0) [15:8] LIN 11 51 [7:0] LIN 11 52 READ_IIN (PAGE 1) [15:8] LIN 11 53 [7:0] LIN 11 54 READ_VIN [15:8] LIN 11 55 [7:0] LIN 11 56 Reserved [15:8] LIN 11 57 [7:0] LIN 11 58 STATUS_VOUT (PAGE 0) BYTE 59 STATUS_VOUT (PAGE 1) BYTE 60 STATUS_WORD (PAGE 0) [15:8] WORD 61 [7:0] WORD 62 PMBus COMMAND DETAILS

Rev 0For more information www.analog.com PMBus COMMAND DETAILS STATUS_WORD (PAGE 1) [15:8] WORD 63 [7:0] WORD 64 STATUS_MFR_SPECIFIC (PAGE 0) BYTE 65 STATUS_MFR_SPECIFIC (PAGE 1) BYTE 66 EVENT n-5 (Oldest Recorded Data) READ_VOUT (PAGE 0) [15:8] LIN 16 127 [7:0] LIN 16 128 READ_VOUT (PAGE 1) [15:8] LIN 16 129 [7:0] LIN 16 130 READ_IIN (PAGE 0) [15:8] LIN 11 131 [7:0] LIN 11 132 READ_IIN (PAGE 1) [15:8] LIN 11 133 [7:0] LIN 11 134 READ_VIN [15:8] LIN 11 135 [7:0] LIN 11 136 Reserved [15:8] LIN 11 137 [7:0] LIN 11 138 STATUS_VOUT (PAGE 0) BYTE 139 STATUS_VOUT (PAGE 1) BYTE 140 STATUS_WORD (PAGE 0) [15:8] WORD 141 [7:0] WORD 142 STATUS_WORD (PAGE 1) [15:8] WORD 143 [7:0] WORD 144 STATUS_MFR_SPECIFIC (PAGE 0) BYTE 145 STATUS_MFR_SPECIFIC (PAGE 1) BYTE 146

Rev 0 For more information www.analog.com PMBus COMMAND DETAILS Table 13a: Explanation of Position_Fault Values POSITION_FAULT VALUE SOURCE OF FAUL T LOG 0xFF MFR_FAULT_LOG_STORE 0x00 TON_MAX_FAULT Channel 0 0x01 VOUT_OV_FAULT Channel 0 0x02 VOUT_UV_FAULT Channel 0 0x05 TEMP_OT_FAULT Channel 0 0x06 TEMP_UT_FAULT Channel 0 0x07 VIN_OV_FAULT 0x0A MFR_TEMPERATURE_2_OT_FAULT 0x10 TON_MAX_FAULT Channel 1 0x11 VOUT_OV_FAULT Channel 1 0x12 VOUT_UV_FAULT Channel 1 0x15 OT_FAULT Channel 1 0x16 UT_FAULT Channel 1 0x17 VIN_OV_FAULT 0x1A MFR_TEMPERATURE_2_OT_FAULT MFR_FAULT_LOG_CLEAR The MFR_FAULT_LOG_CLEAR command will erase the fault log file stored values. It will also clear bit 3 in the STATUS_MFR_SPECIFIC command. After a clear is issued, the status can take up to 8ms to clear . This write-only command is send bytes. Block Memory Write/Read COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS EEPROM DEFAUL T VALUE MFR_EE_UNLOCK 0xBD Unlock user EEPROM for access by MFR_EE_ERASE and MFR_EE_DATA commands. R/W Byte N Reg NA MFR_EE_ERASE 0xBE Initialize user EEPROM for bulk programming by MFR_EE_DATA. R/W Byte N Reg NA MFR_EE_DATA 0xBF Data transferred to and from EEPROM using sequential PMBus word reads or writes. Supports bulk programming. R/W Word N Reg NA All the EEPROM commands are disabled if the die temperature exceeds 130°C. EEPROM commands are re-enabled when the die temperature drops below 125°C. MFR_EE_xxxx The MFR_EE_xxxx commands facilitate bulk programming of the LTC7880 internal EEPROM. Contact the factory for details.

Rev 0For more information www.analog.com TYPICAL APPLICATIONS 2-CHANNEL 150kHz/24V and 36V Boost Converter VDD33 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 20k 15k 24.9k 11.3k 10k 23.2k 24.9k 7.32k 24.9k 5.76k VDD25 DRVCC TG0 TG1 BOOST0 BOOST1 SW0 SW1 BG0 SYNC PGOOD0 PGOOD1 SDA SCL VOUT0_CFG VOUT1_CFG ASEL0 ASEL1 FREQ_CFG ALERT FAUL T0 FAUL T1 SHARE_CLK RUN0 RUN1 WP PHAS_CFG TSNS0 ITH0 ITHR0 EXTVCC TSNS1 ITH1 ITHR1 BG1 1000pF 1µF 10nF 10nF VIN 12V

7880 TA02

6.8nF ISENSE0+ ISENSE1+ ISENSE0– ISENSE1– 5m/uni03A9 10µF 10µF VOUT0 36V 0.1µF 10µH 5m/uni03A9 4m/uni03A9 1k10nF10nF VBIAS L TC7880 GNDVDD33 VDD25 IIOUT- IOUT+ 10µH 1µF 220pF 30/uni03A9 30/uni03A91000pF 30/uni03A9 30/uni03A9 22µF 220µF VIN1 VSENSE1+ VSENSE0+ VIN0 220µF 0.1µF 10µF VOUT1 24V 220µF 6.8nF 220pF L0, L1: Würth 7443631000 10/uni03BCH M1, M2: INFINEON BSC034N06NS M3, M4: INFINEON BSC034N06NS

Rev 0 For more information www.analog.com TYPICAL APPLICATIONS L0, L1, L2, L3: Würth 7443640330 3.3uH L0, L2, L3: Würth 7443630140 1.4/uni03BCH M1, M2, M5, M6: INFINEON BSC034N06NS M3, M4, M7, M8: INFINEON BSC034N06NS 24.9k 11.3k 24.9k 11.3k 10k 23.2k 24.9k 7.32k 20k 12.7k VDD25 DRVCC TG0 TG1 BOOST0 BOOST1 SW0 SW1 BG0 SYNC PGOOD0 PGOOD1 SDA SCL VOUT0_CFG VOUT1_CFG ASEL0 ASEL1 FREQ_CFG ALERT FAUL T0 FAUL T1 SHARE_CLK RUN0 RUN1 WP PHAS_CFG TSNS0 ITH0 ITHR0 EXTVCC TSNS1 ITH1 ITHR1 BG1 1000pF 1µF 10nF 10nF 6.8nF ISENSE0+ ISENSE1+ ISENSE0– ISENSE1– 2m/uni03A9 1k10nF10nF 10µF 10µF 0.1µF 3.3µH 4m/uni03A9 4m/uni03A9 VBIAS L TC7880 GNDVDD33 VDD25 IOUT+IIOUT- 3.3µH 1µF 220pF 30/uni03A9 30/uni03A91000pF 30/uni03A9 30/uni03A9 VIN1 VSENSE1+ VSENSE0+ VIN0 220µF 0.1µF 10k 10k 10k 10k 10k 10k 10k 24.9k 11.3k 24.9k 11.3k 10k 15.8k 24.9k 9.09k 20k 12.7k VDD25 DRVCC TG0 TG1 BOOST0 BOOST1 SW0 SW1 BG0 SYNC PGOOD0 PGOOD1 SDA SCL VOUT0_CFG VOUT1_CFG ASEL0 ASEL1 FREQ_CFG ALERT FAUL T0 FAUL T1 SHARE_CLK RUN0 RUN1 WP PHAS_CFG TSNS0 ITH0 ITHR0 EXTVCC TSNS1 ITH1 ITHR1 BG1 1000pF 1µF 10nF 10nF VIN 12V

7880 TA03

6.8nF ISENSE0+ ISENSE1+ ISENSE0– ISENSE1– 2m/uni03A9 10µF 10µF VOUT 24V 20A 0.1µF 10nF 10nF 3.3µH 4m/uni03A9 4m/uni03A9 VBIAS L TC7880 GNDVDD33 VDD25 IOUT+IIOUT- 3.3µH 1µF 220pF 30/uni03A9 30/uni03A91000pF 30/uni03A9 30/uni03A9 22µF 220µF VIN1 VSENSE1+ VSENSE0+ VIN0 220µF 0.1µF VDD33 20k 11k High Efficiency 350kHz 4-phase 24V Step-Up Converter

Rev 0For more information www.analog.com Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. PACKAGE DESCRIPTION 7.00 ±0.10 (2 SIDES) NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT , SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONL Y A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 TOP MARK (SEE NOTE 6) PIN 1 NOTCH R = 0.30 TYP OR 0.35 × 45°C CHAMFER 0.40 ±0.10 52 51 BOTTOM VIEW—EXPOSED PAD TOP VIEW SIDE VIEW

6.50 REF

(2 SIDES) 8.00 ±0.10 (2 SIDES)

5.50 REF

(2 SIDES)0.75 ±0.05 0.75 ±0.05 R = 0.115 TYP R = 0.10 TYP 0.25 ±0.05

0.50 BSC

0.200 REF

0.00 – 0.05 6.45 ±0.10 5.41 ±0.10 0.00 – 0.05 (UKG52) QFN REV Ø 0306 (2 SIDES) 5.41 ±0.05 6.45 ±0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPL Y SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.70 ±0.05 6.10 ±0.05 7.50 ±0.05 0.25 ±0.05 52-Lead Plastic QFN (7mm × 8mm) (Reference LTC DWG # 05-08-1729 Rev Ø)

Rev 0 For more information www.analog.com  ANALOG DEVICES, INC. 2019 www.analog.com RELATED PARTS TYPICAL APPLICATION 250kHz 2-Phase 12V to 48V Boost Converter with Sense Resistors 10k 10k 10k 10k 10k 10k 10k 16.2k 20.5k 16.2k 20.5k 10k 23.2k 24.9k 7.32k 24.9k 9.09k VDD25 DRVCC TG0 TG1 BOOST0 BOOST1 SW0 SW1 BG0 SYNC PGOOD0 PGOOD1 SDA SCL VOUT0_CFG VOUT1_CFG ASEL0 ASEL1 FREQ_CFG ALERT FAUL T0 FAUL T1 SHARE_CLK RUN0 RUN1 WP PHAS_CFG TSNS0 ITH0 ITHR0 EXTVCC TSNS1 ITH1 ITHR1 BG1 1000pF 1µF 10nF 10nF VIN 12V

7880 TA05

6.8nF L0, L1: Würth 7443631000 10/uni03BCH M1, M2: INFINEON BSC034N06NS M3, M4: INFINEON BSC034N06NS I SENSE0+ ISENSE1+ ISENSE0– ISENSE1– 5m/uni03A9 10nF 1k 10nF 10µF 10µF VOUT 48V 0.1µF 10µH 5m/uni03A9 5m/uni03A9 VBIAS L TC7880 GNDVDD33 VDD25 IOUT+IIOUT- 10µH 1µF 220pF 30/uni03A9 30/uni03A91000pF 30/uni03A9 30/uni03A9 22µF 220µF VIN1 VSENSE1+ VSENSE0+ VIN0 220µF 0.1µF VDD33 PART NUMBER DESCRIPTION COMMENTS LTM4676A Dual 13A or Single 26A Step-Down DC/DC µModule Regulator with Digital Power System Management VIN Up to 26.5V; 0.5V ≤ VOUT (±0.5%) ≤ 5.4V, ±2% IOUT Accuracy, Fault Logging, I2C/PMBus Interface, 16mm × 16mm × 5mm, BGA Package LTM4677 Dual 18A or Single 36A μModule Regulator with Digital Power System Management 4.5V ≤ V IN ≤16V; 0.5V ≤ VOUT (±0.5%) ≤ 1.8V, I2C/PMBus Interface, 16mm × 16mm × 5.01mm, BGA Package LTC3889 60V Dual Output Step-Down Controller with PSM 5V < VIN < 60V, 0.5V ≤ VOUT (±0.5%) ≤ 40V, Input Current Sense, I2C/PMBus Interface with EEPROM and 16-Bit ADC LTC3884 Dual Output Multiphase Step-Down Controller with Sub MilliOhm DCR Sensing Current Mode Control and Digital Power System Management 4.5V ≤ V IN ≤ 38V, 0.5V ≤ VOUT (±0.5%) ≤ 5.5V, I2C/PMBus Interface, Programmable Analog Loop Compensation, Input Current Sense LTC3887/ LTC3887-1 Dual Output Multiphase Step-Down DC/DC Controller with Digital Power System Management V IN Up to 24V, 0.5V ≤ VOUT0,1 ≤ 5.5V, Analog Control Loop, I2C/PMBus Interface with EEPROM and 16-Bit ADC LTC3882/ LTC3882-1 Dual Output Multiphase Step-Down DC/DC Voltage Mode Controller with Digital Power System Management V IN Up to 38V, 0.5V ≤ VOUT1,2 ≤ 5.25V, ±0.5% VOUT Accuracy I2C/PMBus Interface with EEPROM and 16-Bit ADC LTC3886/ LTC3886-1 60V Dual Output Step-Down Controller with PSM 4.5V < V IN < 60V, 0.5V ≤ VOUT (±0.5%) ≤ 13.8V, Input Current Sense, I2C/PMBus Interface with EEPROM and 16-Bit ADC LTC2977 8-Channel PMBus Power System Manager Featuring Accurate Output Voltage Measurement Fault Logging to Internal EEPROM Monitors Eight Output Voltages, Input Voltage and Die Temperature