DAP018A ONSEMI | Alldatasheet
Document overview
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Technical content
Features
- Fixed−frequency 65 kHz (A and B versions) or 100 kHz (C and D versions) Current−mode Control Operation
- Internal and Adjustable Over Power Protection (OPP) Circuit
- Frequency Foldback down to 25 kHz and Skip−cycle in Light Load Conditions
- Reduced Internal Bias Currents for Improved Standby Performance
- Adjustable Brown−out Protection (B and D versions)
- Internal Ramp Compensation
- Internal Fixed 5 ms Soft−Start
- Adjustable Frequency Jittering for Better EMI Signature
- Auto−recovery internal output short−circuit protection for A, B, C and D versions. F is latched
- Adjustable Timer for Improved Short−circuit Protection
- OTP and OVP Inputs for Improved Robustness
- +500 mA / −800 mA Peak Current Capability
- Up to 28 V VCC Operation
- Improved Creepage Distance between High−voltage and Adjacent Pin
- Extremely Low No−load Standby Power
- This is a Pb−Free Device
- This Device uses Halogen−Free Molding Compound Typical Applications
- High Power ac−dc Converters for TVs, Set−top Boxes etc.
- Offline Adapters for Notebooks MARKING DIAGRAM PIN CONNECTIONS SOIC−14 D SUFFIX CASE 751A (Top View) DAP018x AWLYWWG 14x = Device Version A = Assembly Location WL = Wafer Lot Y = Year WW = Work Week G = Pb −Free Package CTimer OVP OPP Jittering Fold FB CS HV NC OTP BO(B&D) V CC DRV GND †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet.
ORDERING INFORMATION
Figure 1. Typical Application Example 2 OVP Input voltage to latch comparator This pin offers an over−voltage protection input. 3 CTimer Timer Wiring a capacitor to ground helps selecting the timer duration. 4 Jitter Frequency jittering speed This pin offers a way to adjust the frequency modulation pace.
5 Foldback / skip Frequency foldback /
duce the level at which frequency foldback occurs. 6 FB Feedback pin Hooking an optocoupler collector to this pin will allow regulation.
7 CS Current sense +
means to introduce ramp compensation. 8 GND − The controller ground. 9 DRV Driver output The driver’s output to an external MOSFET gate. 10 VCC Supplies the controller This pin is connected to an external auxiliary voltage. 11 BO Brown−out, B and D versions For B and D versions, this pin offers a brown−out input.
12 OTP NTC connection This pin connects to a pulldown NTC resistor for over temperat-
13 NC − Non−connected for improved creepage.
14 HV High−voltage input Connected to the bulk capacitor, this pin powers the internal
current source to deliver a startup current.
http://onsemi.com Delta Device ON Semiconductor Device Frequency Brown− Out Short− Circuit Package Shipping† DAP018ADR2G SCY99079ADR2G 65 kHz No Auto− Recovery SOIC−14 (Pb−Free) 2500 / Tape & Reel DAP018BDR2G SCY99079BDR2G 65 kHz Yes Auto− Recovery SOIC−14 (Pb−Free) 2500 / Tape & Reel DAP018CDR2G SCY99079CDR2G 100 kHz No Auto− Recovery SOIC−14 (Pb−Free) 2500 / Tape & Reel DAP018DDR2G SCY99079DDR2G 100 kHz Yes Auto− Recovery SOIC−14 (Pb−Free) 2500 / Tape & Reel DAP018FDR2G SCY99079FDR2G 65 kHz Yes Latched SOIC−14 (Pb−Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
5 V on
10 VCC
9 Drv
Figure 2. Internal Circuit Architecture
5 V reset
http://onsemi.com MAXIMUM RATINGS TABLE Symbol Rating Value Unit VCCmax Maximum Power Supply Voltage, VCC Pin, Continuous Voltage −0.3 to 28 V ICCmax Maximum Current for VCC Pin /C003630 mA Maximum Voltage on Low Power Pins (Except Pins 9, 10 and 14) −0.3 to 10 V IOPP Maximum Injected Negative Current into the OPP Pin (Pin 1) −2 mA RθJ−A Thermal Resistance Junction−to−Air 120 °C/W TJMAX Maximum Junction Temperature 150 °C Storage Temperature Range −60 to +150 °C ESD Capability, Human Body Model (All pins except HV) 2 kV ESD Capability, Machine Model 180 V Maximum Voltage on Pin 14 (HV) −0.3 to 500 V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above t he Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. NOTES:This device(s) contains ESD protection and exceeds the following tests: Human Body Model 2000V per JEDEC Standard JESD22−A114E Machine Model 200V per JEDEC Standard JESD22−A115−A This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78 except pin 12.
ELECTRICAL CHARACTERISTICS
(For typical values TJ = 25°C, for min/max values TJ = −25°C to +125°C, Max TJ = 150°C, VCC = 12 V unless otherwise noted) Symbol Rating Pin Min Typ Max Unit SUPPLY SECTION VCCON VCC increasing level at which the current source turns−off 10 14 15 16 V VCC(min) VCC level below which output pulses are stopped 10 8 9 10 V VCClatch VCC decreasing level at which the latch−off phase ends 10 7.2 7.5 8.0 V VCCreset Internal latch reset level 10 5 V resetHyst Minimum voltage difference between VCClatch and VCCreset, TJ > 0°C − 0.8 V VCCTSD VCC voltage when the TSD is activated (Note 2) − 6.5 7.1 V ICC1 Internal IC consumption, no output load on pin 9 10 1.9 mA ICC1light ICC1 for a feedback voltage equal to Vfold (internal bias reduction) 10 1.5 mA ICC2 Internal IC consumption, 1 nF output load on pin 9 10 2.7 mA ICC3 Internal IC consumption, latch−off phase 10 0.6 mA ITSD Current consumption in TSD mode − 400 /C0109A INTERNAL START−UP CURRENT SOURCE – High−voltage pin biased to 60 Vdc. Symbol Rating Pin Min Typ Max Unit IC2 High−voltage current source, VCC = 10 V 14 3 6 9 mA IC1 High−voltage current source, VCC = 0, TJ = 25°C 14 150 650 1200 /C0109A VTh VCC transition level for IC1 to IC2 toggling point 14 0.9 V Ileak Leakage current for the high voltage source, Vpin 14 = 500 Vdc, VCC = 12 V, TJ > 0°C 14 1 15 30 /C0109A DRIVE OUTPUT Symbol Rating Pin Min Typ Max Unit Tr Output voltage rise−time @ CL = 1 nF, 10−90% of a 12 V output signal 9 − 40 − ns 1. See characterization table for linearity over negative bias voltage. 2. Guaranteed by design. 3. The OTP parameters are selected to cope with a TTC03−474 which offers a resistance of 8.8 k/C0087 when heated to a temperature of 110°C. 4. The brown −out circuitry is disabled on versions A & C and operates on versions B & D.
http://onsemi.com (For typical values TJ = 25°C, for min/max values TJ = −25°C to +125°C, Max TJ = 150°C, VCC = 12 V unless otherwise noted) DRIVE OUTPUT Symbol UnitMaxTypMinPinRating Tf Output voltage fall−time @ CL = 1 nF, 10−90% of a 12 V output signal 9 − 25 − ns Isource Source current capability at VDRV = 10.5 V 9 − 500 − mA Isink Sink current capability at VDRV = 0 V 9 − 800 − mA VDRVlow DRV pin level at VCC close to VCC(min) with a 33 k/C0087 resistor to GND 9 7.6 − − V VDRVhigh DRV pin level at VCC = 28 V 9 10 15 17 V CURRENT COMPARATOR Symbol Rating Pin Min Typ Max Unit IIB Input Bias Current @ 0.8 V input level on pin 7 7 0.02 /C0109A VLimit Maximum internal current setpoint – pin1 grounded 7 0.76 0.8 0.84 V TDEL Propagation delay from current detection to gate off−state 7 100 150 ns TLEB Leading Edge Blanking Duration 7 140 ns TSS Internal soft−start duration activated upon startup, auto−recovery and BO release for versions B & D, pin 1 grounded. − 5 ms IOPPo Setpoint decrease for pin 1 biased to –300 mV (Note 1) 1 37.5 % IOOPv Voltage setpoint for pin 1 biased to −300 mV (Note 1) 1 0.46 0.5 0.54 V IOPPs Setpoint decrease for pin 1grounded 1 0 % INTERNAL OSCILLATOR Symbol Rating Pin Min Typ Max Unit fOSC Oscillation frequency (65 kHz version, A & B) − 60 65 70 kHz fOSC Oscillation frequency (100 kHz version, C & D) − 92 100 108 kHz Dmax Maximum duty−cycle − 76 80 84 % fjitter Frequency jittering in percentage of fOSC − ±5 % fswing Swing frequency with a 22 nF capacitor to pin 4 4 300 Hz ICjit Jittering modulator charging current 4 18 /C0109A VCjitP Jittering capacitor peak voltage 4 2.2 V VCjitV Jittering capacitor valley voltage 4 0.8 V FEEDBACK SECTION Symbol Rating Pin Min Typ Max Unit Rup Internal pull−up resistor 6 20 k/C0087 RFB Equivalent resistor on FB pin 16 k/C0087 Iratio Pin 6 to current setpoint division ratio − 4.2 k/C0087 FREQUENCY FOLDBACK Symbol Rating Pin Min Typ Max Unit Ifold Internal foldback reference current 5 8.5 10 11.5 /C0109A Vfold Frequency folback level with a 100 k/C0087 resistor to ground 5 1 V Iskip Skip current in percentage of the maximum excursion, for Vfold = 1 V 30 % Ftrans Transition frequency below which skip−cycle occurs for TJ = 25°C – 21 25 29 kHz Vskip Skip−cycle level voltage on the feedback pin 6 320 mV 1. See characterization table for linearity over negative bias voltage. 2. Guaranteed by design. 3. The OTP parameters are selected to cope with a TTC03−474 which offers a resistance of 8.8 k/C0087 when heated to a temperature of 110°C. 4. The brown −out circuitry is disabled on versions A & C and operates on versions B & D.
http://onsemi.com (For typical values TJ = 25°C, for min/max values TJ = −25°C to +125°C, Max TJ = 150°C, VCC = 12 V unless otherwise noted) INTERNAL RAMP COMPENSATION Symbol Rating Pin Min Typ Max Unit Vramp Internal ramp level @ 25°C (Note 2) 7 3.0 V Rramp Internal ramp resistance to CS pin (Note 2) 7 20 k/C0087 PROTECTIONS Symbol Rating Pin Min Typ Max Unit Vlatch Latching level input 2 2.85 3 3.25 V Tlatch−del Delay before latch confirmation − 20 /C0109s VtimFault Timer level completion 3 4.3 V Itim Timer capacitor charging current 3 12 /C0109A TimerL Timer length, Ctimer = 0.22 /C0109F typical 3 100 ms VBO Brown−Out level – B & D versions 11 0.95 1 1.05 V IBO Hysteresis current, Vpin 11 < VBO – B & D versions, TJ = 25°C 11 9 10 11 /C0109A IBO Hysteresis current, Vpin 11 < VBO – B & D versions, −25°C < TJ < 25°C 11 8.6 10 11 /C0109A IBObias Brown−Out input bias current – B & D versions 11 0.02 /C0109A TBO−del Delay before brown−out confirmation − 20 /C0109s IOTP Over temperature shutdown current (Note 3) 12 101 113 124 /C0109A VOTP Over temperature latching voltage (Note 3) 12 0.95 1 1.05 V TSD Temperature shutdown − 140 °C TSD_hys Temperature shutdown hysteresis − 40 °C 1. See characterization table for linearity over negative bias voltage. 2. Guaranteed by design. 3. The OTP parameters are selected to cope with a TTC03−474 which offers a resistance of 8.8 k/C0087 when heated to a temperature of 110°C. 4. The brown −out circuitry is disabled on versions A & C and operates on versions B & D.
http://onsemi.com
Application Information
SpeedKing II implements a standard current mode architecture where the switch −off event is dictated by the peak current setpoint. This component represents the ideal candidate where low part −count is the key parameter, particularly in low−cost ac−dc adapters, open−frame power supplies etc. Thanks to its High −V oltage technology, the DAP−018X incorporates all the necessary components normally needed in today modern power supply designs, bringing several enhancements such as an adjustable EMI jittering and a fault timer...
- Current−mode operation with internal ramp compensation: implementing peak current mode control, the DAP−018X offers an internal ramp compensation signal that can easily by summed up to the sensed current. Subharmonic oscillations can thus be fought via the inclusion of a simple resistor in series with the current−sense information.
- Internal OPP: by routing a portion of the negative voltage present during the on−time on the auxiliary winding to the dedicated OPP pin, the user has a simple and non−dissipative option to alter the maximum peak current setpoint as the bulk voltage increases. If the pin is grounded, no OPP compensation occurs. If the pin receives a negative voltage down to –300 mV , then a peak current reduction down to 40% typical can be achieved. For an improved performance, the maximum voltage excursion on the sense resistor is limited to 0.8 V .
- Internal high−voltage startup switch: reaching a low no−load standby power represents a difficult exercise when the controller requires an external, lossy, resistor connected to the bulk capacitor. Thanks to an internal logic, the controller disables the high−voltage current source after startup which no longer hampers the consumption in no−load situations.
- EMI jittering: a dedicated pin offers the ability to vary the pace at which the oscillator frequency is modulated. This helps spreading out energy in conducted noise analysis. To avoid modulation conflicts, the jittering will be disabled as soon as the controller enters frequency folback (light load conditions).
- Frequency foldback capability: a continuous flow of pulses in not compatible with no−load standby power requirements. The controller observes the feedback pin and when it reaches a level determined by pin 5, the peak current freezes. The oscillator then starts to reduce its switching frequency as the feedback level continues to decrease. It can decrease down to 26 kHz (typical). At this point, if the power continues to drop, the controller enters classical skip−cycle mode at a peak current set by pin 5 level. The point at which the foldback occurs can be adjusted to any level, we recommend to put it in the vicinity of 1 V or slightly above.
- Bias reduction: the controller detects that standby mode is entered by monitoring the feedback pin level. When this occurs, the circuit significantly reduces its bias current by shutting down un−necessary blocks. This improves the standby power further.
- Brown−out: versions B & D include a brown−out (BO) detector. When the voltage sensed on this pin is below the BO level, the controller does not operate. When the voltage reaches the threshold, the controller pulses and open the internal hysteresis current source. By connecting a divider network between the bulk voltage and the BO pin, the designer has the flexibility to adjust the turn−on and turn−off levels. For versions A & C, the brown−out circuitry is disabled and pin 11 is not internally connected.
- Internal soft−start: a soft−start precludes the main power switch from being stressed upon start−up. In this controller, the soft−start is internally fixed to 5 ms. The soft−start is activated when a) a new startup sequence occurs – fresh startup or during an auto−recovery hiccup b) when the controller recovers from a brown−out condition (B & D versions).
- OVP input: the Speedking II includes a latch input that can be used to sense an overvoltage condition on the adapter. If this pin is brought higher than the internal reference voltage Vlatch, then the circuit permanently latches off. The VCC pin swings up and down, keeping the controller latched. The latch reset occurs when a) the user disconnects the adapter from the mains and lets the V CC falls below the VCCreset value b) for versions B & D, if the internal BO circuitry senses a bulk / mains reset, then the controller is also reset. In this case, if the controller is within a hiccup cycle: the hiccup cycle is immediately reset and driving pulses only re−appear on the output when V CC reaches VCC(on).
- OTP input: the controller incorporates an Over Temperature Protection circuitry (OTP) which allows the direct connection of a Negative Temperature Coefficient (NTC) sensor from pin 12 to GND. When the temperature increases, the NTC resistor falls down. When the NTC reaches a 8.8 k/C0087 value (T = 110°C), the voltage developed across its terminal is V OTP. The internal comparator trips and latches−off the part. Reset occurs in similar conditions as described in the OVP section.
- Short−circuit protection: short−circuit and especially over−load protection are difficult to implement when a strong leakage inductance between auxiliary and power
drops below VCC(min) (7.9 V typical). Figure 32. The Current Source Brings VCC Above
15 V (typical) and then Turns Off
J), the device would dissipate 370 x 2m = 740 mW. Figure 33. The Startup Source Now Features a
Figure 34. An Error Flag gets Asserted a 0.22 /C0109F capacitor being connected to pin 3.
- the converter regulates but the auxiliary winding
closed because of the output current monitoring.
Figure 35. First Fault Mode Case
- In the second case, the converter operates in
regulation, but the output is severely overloaded. to the maximum and the timer starts to count. goes away, the SMPS resumes operation.
Figure 38. The Burst Period is Ensured by the VCC Capacitor becomes easy to evaluate the burst period and its duty−cycle.
- t1: I = ICC3 = 600 /C0109A, ΔV = 9 – 6.5 = 2.5 V /C0179 t1 = 91 ms
- t2: I = 3 mA, ΔV = 15 – 6.5 = 8.5 V /C0179 t1 = 62 ms
- t3: I = 600 /C0109A, ΔV = 15 – 6.5 = 8.5 V /C0179 t1 = 311 ms
- t′1 = t1 = 91 ms
- t′2 = t2 = 62 ms The total period duration is thus the sum of all these events which leads to Tfault = 617 ms. If the timer lasts 100 ms, then our duty−cycle in auto −recovery burst equals 100/(617 + 100) ≈ 13%, which is good. Should the user like to further decrease or, to the contrary, increase this duty −cycle, changing the VCC capacitor is an easy job. Latch−off and Over Voltage Protection Speedking II features a fast comparator that permanently monitors pin 2 level. Figure 39 details how it is internally arranged:
Figure 39. A Comparator Monitors Pin 2 and
Figure 45. A Brown−out Event Immediately Stops the Driving Pulses then performs a fresh re−start before pulsing again. Where VBO = 1 V typical and IBO = 10 /C0109A typical.
100 Vdc and a turn−off voltage of 50 Vdc, then the upper
resistor would be 4.9 M/C0087 and the lower side resistor 100 k/C0087. current reaches a level set via the original skip pin (pin 5).
Figure 48. A Pulldown Resistor Adjusts the Foldback Level
2 V swing on the jitter capacitor, then we calculate the
Figure 52. The OPP Circuitry Affects the Maximum Peak Current Setpoint by
0.8 V ±5%
Figure 53. The Peak Current Regularly Reduces string placed between the bulk rail and the current sense pin. changes the circuit power capability at high line only.
Figure 54. The Zener Diode can Introduce a Threshold which Figure 55. The Addition of the Zener Diode series with the zener to block the positive excursion.
http://onsemi.com PACKAGE DIMENSIONS SOIC−14 D SUFFIX CASE 751A−03 ISSUE H NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. −A− −B− G P 7 PL 14 8 M0.25 (0.010) B M SBM0.25 (0.010) A ST −T− FR X 45 SEATING PLANE D 14 PL K C JM /C0095 DIM MIN MAX MIN MAX INCHESMILLIMETERS A 8.55 8.75 0.337 0.344 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049 G 1.27 BSC 0.050 BSC J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009 M 0 7 0 7 P 5.80 6.20 0.228 0.244 R 0.25 0.50 0.010 0.019 /C0095/C0095/C0095/C0095 7.04 14X 0.58 14X 1.52 1.27 DIMENSIONS: MILLIMETERS PITCH SOLDERING FOOTPRINT ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. DAP018/D PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative