DAP005 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 39
Technical content
Datasheet sections
- 1 Description
- 1.1 Pin connection
- 1.2 Pin description
- 2 Absolute maximum ratings
- 3 Thermal data
- 4 Electrical characteristics
- 5 Typical electrical performance
- 6 Application information
- 6.1 Overvoltage protection
- 6.2 Feedback Failure Protection (FFP)
- 6.3 Voltage Feedforward
- 6.4 THD optimizer circuit
- 6.5 Tracking Boost function
- 6.6 Inductor saturation detection
- 6.7 Power management/housekeeping functions
- 7 Brownout protection
- 7.1 Summary of DAP005 idle states
- 8 Application examples and ideas
- 9 Package mechanical data
- 10 Revision history
Features
■ Transition-mode control of PFC pre-regulators ■ Very precise adjustable output overvoltage protection ■ Tracking boost function ■ Protection against feedback loop failure (Latched shutdown) ■ Interface for cascaded converter's PWM controller ■ Input voltage feedforward (1/V2) ■ AC brownout protection ■ Low (≤ 90µA) start-up current ■ < 5mA quiescent current ■ 1.4% (@ TJ = 25°C) internal reference voltage ■ -600/+800 mA totem pole gate driver with active pull-down during UVLO ■ SO14 package
Applications
PFC pre-regulators for: ■ HI-END AC-DC adapter/charger ■ Desktop PC, server, WEB server ■ IEC61000-3-2 OR JEIDA-MITI compliant SMPS, in excess of 250W Table 1. Device summary Figure 1. Block diagram
1 Description
THD even over a large load range. consumption (≤ 90 µA before start-up and ≤ 5 mA running). where the PFC pre-regulator works as a master and in those where it works as a slave. Figure 2. Typical system block diagram
1.1 Pin connection
Figure 3. Pin connection (top view)
1.2 Pin description
Table 2. Pin description regulator is fed into the pin through a resistor divider. pin to change the output voltage so that it tracks the mains voltage. this pin is used also to derive the information on the RMS mains voltage. to determine MOSFET’s turn-off. the start-up level and asserts PWM_LATCH (pin 8) high. the mains voltage. Never connect the pin directly to GND.
function is not used leave this pin open. almost to the start-up level and this condition is latched. PWM_LATCH pin is asserted high. protection in case the feedback loop fails. functions are not needed, tie the pin to a voltage between 0.26 and 2.5 V. controller. If not used, the pin will be left floating. the pin will be left floating.
10 AC_OK
protection, tie to INV (pin 1) if the function is not used. going edge triggers MOSFET’s turn-on. 12 GND Ground. Current return for both the signal part of the IC and the gate driver. this pin is clamped at about 12V to avoid excessive gate voltages. 14 VCC Supply Voltage of both the signal part of the IC and the gate driver. Table 2. Pin description (continued)
2 Absolute maximum ratings
3 Thermal data
Table 3. Absolute maximum ratings Table 4. Thermal data
4 Electrical characteristics
Table 5. Electrical characteristics
Table 5. Electrical characteristics (continued)
(4) Parameters guaranteed by design, functionality tested in production.
5 Typical electrical performance
Figure 4. Supply current vs supply voltage Figure 5. V CC Zener voltage vs TJ Figure 6. IC consumption vs T J Figure 7. Feedback reference vs T J Figure 8. Start-up & UVLO vs T J Figure 9. E/A output clamp levels vs T J
6 Application information
6.1 Overvoltage protection
Normally, the voltage control loop keeps the output voltage VO of the PFC pre-regulator close to its nominal value, set by the ratio of the resistors R1 and R2 of the output divider. Neglecting the ripple components, under steady state conditions the current through R1 equals that through R2. Considering that the non-inverting input of the error amplifier is internally biased at 2.5V, the voltage at pin INV will be 2.5V as well, then: Equation 1 If the output voltage experiences an abrupt change ∆Vo the voltage at pin INV is kept at 2.5V by the local feedback of the error amplifier, a network connected between pins INV and COMP that introduces a long time constant. Then the current through R2 remains equal to 2.5/R2 but that through R1 becomes: Equation 2 The difference current ∆I R1 = I’R1 - I’R1 = ∆VO/R1 will flow through the compensation network and enter the error amplifier (pin COMP). This current is monitored inside the IC and when it reaches about 18 µA the output voltage of the multiplier is forced to decrease, thus reducing the energy drawn from the mains. If the current exceeds 20 µA, the OVP is triggered (Dynamic OVP), and the external power transistor is switched off until the current falls approximately below 5 µA. However, if the overvoltage persists (e.g. in case the load is completely disconnected), the error amplifier will eventually saturate low hence triggering an internal comparator (Static OVP) that will keep the external power switch turned off until the output voltage comes back close to the regulated value. The output overvoltage that is able to trigger the OVP function is then: Equation 3 ∆VO = R1 · 20 · 10-6 IR2 IR1 2.5 I'R1 VO 2.5– VO∆+
much smaller than Vo, the tolerance on the absolute value will be proportionally reduced. The tolerance on the OVP level due to the DAP005 will be 40·0.125 = 5 V, that is ± 1.14 %. discharge of the Vcc capacitor. Figure 34. Output voltage setting, OVP and FFP functions: internal block diagram
6.2 Feedback Failure Protection (FFP)
The OVP function above described is able to handle "normal" overvoltage conditions, i.e. those resulting from an abrupt load/line change or occurring at start-up. It cannot handle the overvoltage generated, for instance, when the upper resistor of the output divider (R1) fails open: the voltage loop can no longer read the information on the output voltage and will force the PFC pre-regulator to work at maximum ON-time, causing the output voltage to rise with no control. A pin of the device (PFC_OK) has been dedicated to provide an additional monitoring of the output voltage with a separate resistor divider (R3 high, R4 low, see Figure 34). This divider is selected so that the voltage at the pin reaches 2.5V if the output voltage exceeds a preset value, usually larger than the maximum Vo that can be expected, also including worst-case load/line transients. Example: V O = 400 V, Vox = 475V. Select: R3 = 3MΩ; When this function is triggered, the gate drive activity is immediately stopped, the device is shut down, its quiescent consumption is reduced below 250 µA and the condition is latched as long as the supply voltage of the IC is above the UVLO threshold. At the same time the pin PWM_LATCH is asserted high. PWM_LATCH is an open source output able to deliver 3.7V min. with 0.5 mA load, intended for tripping a latched shutdown function of the PWM controller IC in the cascaded DC-DC converter, so that the entire unit is latched off. To restart the system it is necessary to recycle the input power, so that the Vcc voltages of both the DAP005 and the PWM controller go below their respective UVLO thresholds. The PFC_OK pin doubles its function as a not-latched IC disable: a voltage below 0.2V will shut down the IC, reducing its consumption below 1 mA. In this case both PWM_STOP and PWM_LATCH keep their high impedance status. To restart the IC simply let the voltage at the pin go above 0.26 V. Note that this function offers a complete protection against not only feedback loop failures or erroneous settings, but also against a failure of the protection itself. Either resistor of the PFC_OK divider failing short or open or a PFC_OK pin floating will result in shutting down the IC and stopping the pre-regulator.
6.3 Voltage Feedforward
The power stage gain of PFC pre-regulators varies with the square of the RMS input voltage. So does the crossover frequency f c of the overall open-loop gain because the gain has a single pole characteristic. This leads to large trade-offs in the design. For example, setting the gain of the error amplifier to get fc = 20 Hz @ 264 Vac means having fc ≅ 4 Hz @ 88 Vac, resulting in a sluggish control dynamics. Additionally, the slow control loop causes large transient current flow during rapid line or load changes that are limited by the dynamics of the multiplier output. This limit is considered when selecting the sense resistor to let the full load power pass under minimum line voltage conditions, with some margin. But a fixed current limit allows excessive power input at high line, whereas a fixed power limit requires the current limit to vary inversely with the line voltage. Voltage Feedforward can compensate for the gain variation with the line voltage and allow overcoming all of the above-mentioned issues. It consists of deriving a voltage proportional to the input RMS voltage, feeding this voltage into a squarer/divider circuit (1/V 2 corrector) and providing the resulting signal to the multiplier that generates the current reference for the inner current control loop (see Figure 35).
Figure 35. Voltage feedforward: squarer-divider (1/V 2) block diagram and transfer range, which improves significantly dynamic behavior at low line and simplifies loop design. voltage changes. Clearly a trade-off is required. in systems with no feedforward compensation.
6.4 THD optimizer circuit
current flow to temporarily stop. near the line voltage zero-crossings as compared to that commanded by the control loop. discharging the high-frequency filter capacitor after the bridge. Figure 37. THD optimizer
Figure 38. THD optimization: standard TM PFC controller (left side) and DAP005 offset added to the output of the multiplier in the proximity of the line voltage zero-crossings. larger offset at high line where the energy transfer gets worse. PFC controller are compared to those of this chip.
6.5 Tracking Boost function
In some applications it may be advantageous to regulate the output voltage of the PFC pre- regulator so that it tracks the RMS input voltage rather than at a fixed value like in conventional boost pre-regulators. This is commonly referred to as "tracking boost" or "follower boost" approach. With this IC the function can be realized by connecting a resistor (R T) between the TBO pin and ground. The TBO pin presents a DC level equal to the peak of the MULT pin voltage and is then representative of the mains RMS voltage. The resistor defines a current, equal to V(TBO)/R T, that is internally 1:1 mirrored and sunk from pin INV (pin 1) input of the error amplifier. In this way, when the mains voltage increases the voltage at TBO pin will increase as well and so will do the current flowing through the resistor connected between TBO and GND. Then a larger current will be sunk by INV pin and the output voltage of the PFC pre- regulator will be forced to get higher. Obviously, the output voltage will move in the opposite direction if the input voltage decreases. To avoid undesired output voltage rise should the mains voltage exceed the maximum specified value, the voltage at the TBO pin is clamped at 3V. By properly selecting the multiplier bias it is possible to set the maximum input voltage above which input-to-output tracking ends and the output voltage becomes constant. If this function is not used, leave the pin open: the device will regulate a fixed output voltage. Starting from the following data:
- Vin1 = minimum specified input RMS voltage;
- Vin2 = maximum specified input RMS voltage;
- Vo1 = regulated output voltage @ Vin = Vin1;
- Vo2 = regulated output voltage @ Vin = Vin2;
- Vox = absolute maximum limit for the regulated output voltage;
- ∆Vo = OVP threshold, to set the output voltage at the desired values use the following design procedure: 1. Determine the input RMS voltage Vin clamp that produces Vo = Vox: Equation 6 and choose a value Vinx such that Vin2 = Vinx < Vinclamp. This will result in a limitation of the output voltage range below Vox (it will equal Vox if one chooses Vinx = Vinclamp) 2. Determine the divider ratio of the MULT pin (pin 3) bias: Equation 7 Vin clamp Vox Vo 1– Vox Vo 2– k 3 2V i n x⋅
and check that at minimum mains voltage Vin1 the peak voltage on pin 3 is greater than 0.65V. 3. Determine R1, the upper resistor of the output divider: Equation 8 4. Calculate the lower resistor R 2 of the output divider and the adjustment resistor RT: Equation 9 5. Check that the maximum current sourced by the TBO pin (pin 6) does not exceed the maximum specified (0.25mA): Equation 10 In the following Mathcad® sheet, as an example, the calculation is shown for the circuit illustrated in Figure 40. Figure 41 shows the internal block diagram of the tracking boost function. R1 Vo∆ R2 2.5 R1 Vin 2 Vin 1– RT 2kR 1 Vin 2 Vin 1– ITBOmax RT
Vin1 := 88V Vo 1:= 200V Vin2 := 264V Vo 2:= 385V Vox ;= 400V ∆Vo ;= 40V Step 1 choose: Vinx: = 270V Step 2 Step 3 Step 4 Vin clamp : Vox Vo 1– Vox Vo 2– k: 3 2V i n x⋅ R1: Vo∆ R2: 2.5 R1 Vin 2 Vin 1– RT:k2 R 1 Vin 2 Vin 1–
Figure 39. V OUT vs VIN characteristics
6.6 Inductor saturation detection
which leads to a catastrophic failure after few switching cycles.
6.7 Power management/housekeeping functions
Figure 42. Effect of boost inductor saturation on the MOSFET current and detection method
enables/disables the operation of the PFC stage. operation of the DC-DC stage. Figure 43. Interface circuits that let DC-DC converter’s controller IC disable the DAP005 at light
8.2 V DAP005PFC_OK
14 PFC_STOP
Brownout protection DAP005
7 Brownout protection
As already seen, the DAP005 is provided with an ON/OFF control pin (AC_OK, 10) internally connected to the inverting input of a comparator. The non-inverting input is internally referenced to 0.52V, so that the IC is disabled if the voltage applied at the AC_OK pin is below the internal reference. In this case, the voltage on the PWM_STOP pin is asserted low and the consumption of the IC is reduced below 1 mA as well. For good noise immunity, hysteresis is also provided, so that the IC is re-enabled as the voltage on the pin exceeds 0.6V. This function, in systems where the PFC pre-regulator acts as the master stage, can be used to implement what is commonly called “brownout protection”. Brownout Protection is basically a not-latched device shutdown function that must be activated when a condition of mains undervoltage is detected. This condition may cause overheating of the primary power section due to an excess of RMS current. Brownout can also cause the PFC pre-regulator to work open loop and this could be dangerous to the PFC stage itself and the downstream converter, should the input voltage return abruptly to its rated value. Another problem is the spurious restarts that may occur during converter power down and that cause the output voltage of the converter not to decay to zero monotonically. For these reasons it is usually preferable to shutdown the unit in case of brownout. IC shutdown upon brownout can be easily realized as shown in Figure 46. The scheme on the left is of general use, the one on the right can be used if the bias levels of the multiplier and the R FF·CFF time constant are compatible with the specified brownout level and with the specified holdup time respectively. It is worth noticing one point: this brownout protection works correctly only in systems where the PFC stage is the master and the cascaded DC-DC converter is the slave or, in other words, where the PFC stage starts first and enables/disables the operation of the DC-DC stage. One reason is that in case of brownout the whole converter must be switched off, not operate as long as brownout lasts and restart as brownout disappears. This kind of operation cannot be achieved if the PFC stage is slave to the DC-DC converter (that is, the DC-DC converter starts first and determines start-up and shutdown of the PFC stage) because the DAP005 could detect brownout only after it has started, that is after the DC-DC converter has started. This would result in an intermittent operation, not in a complete shutdown. The second reason is that in case of a master DC-DC stage a turn-off signal coming from the slave PFC may interfere during converter power-off and give origin to a not well-defined power-off sequence or even to spurious restarts. Therefore, while the AC_OK pin can be used to switch off the PFC stage only, if acceptable, the use of the PWM_STOP pin is not recommended in systems with a master DC-DC stage. This function is quite flexible and can be used for different purposes. In systems comprising an auxiliary converter and a main converter (e.g. desktop PC’s silver box or hi-end LCD-TV), where the auxiliary converter also powers the controllers of the main converter, the pin AC_OK can be used to start and stop the main converter. In the simplest case, to enable/disable the PWM controller the PWM_STOP pin can be connected to either the output of the error amplifier (Figure 44 a) or, if the chip is provided with it, to its soft-start pin (Figure 44 b). The use of the soft-start pin allows the designer to delay the start-up of the DC-DC stage with respect to that of the PFC stage, which is often desired. An underlying assumption in order for that to work properly is that the UVLO thresholds of the PWM controller are certainly higher than those of the DAP005.
Figure 46. Brownout protection (master PFC)
7.1 Summary of DAP005 idle states
Table 6. Summary of DAP005 idle states
8 Application examples and ideas
Note: Measurements done with the line filter shown in Figure 49. Note: Measurements done with the line filter shown in Figure 49. Figure 47. Test board 80W, Wide-range, Tracking Boost: Electrical schematic Table 7. Test board evaluation results at full load Table 8. Test board evaluation results at half load
9 Package mechanical data
conditions are also marked on the inner box label. ECOPACK is an ST trademark. Table 9. SO-14 Mechanical data Figure 54. Package dimensions
Table 10. Revision history