DAP011

DAP011 ONSEMI | Alldatasheet

Document overview

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Technical content

Features

• Current−Mode Control with Adjustable Skip−Cycle Capability
• Internal Ramp Compensation
• Adjustable Frequency Jittering for Better EMI Signature
• Auto−Recovery Internal Output Short−Circuit Protection
• Adjustable Timer for Improved Short−Circuit Protection
• Dedicated Latch Input
• +500 mA/−800 mA Peak Current Capability
• Fixed Frequency Versions at 65/100 kHz
• 5.0 V – 5.0 mA Reference V oltage
• Internal Temperature Shutdown
• Direct Optocoupler Connection
• Extremely Low No−Load Standby Power
• Adjustable Soft−Start
• This is a Pb−Free Device* Typical Applications
• High Power AC/DC Converters for TVs, Set−Top Boxes, etc.
• Offline Adapters for Notebooks
• All Power Supplies Device Package Shipping †

ORDERING INFORMATION

SO−14 (Pb−Free) 2500 / Tape & Reel MARKING DIAGRAM PIN CONNECTIONS DAP011 DAP011C SOIC−14 D SUFFIX CASE 751A (Top View)

14 DAP011/DAP011C

A = Assembly Location WL = Wafer Lot Y = Year WW = Work Week G = Pb−Free Package CTIMER LATCH NC JITTER SKIP FB CS HV NC NC REF VCC DRV GND †For information on tape and reel specifications, including par t orientation and tape sizes, please refer to our Tape and Ree l Packaging Specifications Brochure, BRD8011/D. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. (65 kHz) (100 kHz) fosc DAP011/DAP011C

http://onsemi.com DAP011/DAP011C *See Note OVP Freq. Jitter Skip Adj. HV−Bulk 5 V Ref. Vout Gnd Ramp Gnd Timer Delay *This resistor prevents from negatively biasing the HV pin (14) at power−off. Typical value is 4.7 k/C0087. Figure 1. Typical Application Example

Description

1 NC − −

2 Latch Input voltage to latch comparator By bringing this pin above 3.0 V, e.g. via a Zener or an NTC, the circuit permanently latches−off. 3 CTimer Timer/soft−start delay Wiring a capacitor to ground helps selecting the timer duration. 10% of this duration fixes the soft−start period. 4 Jitter Frequency jittering speed This pin offers a way to adjust the frequency modulation pace.

5 Skip Skip cycle adjustment By connecting a resistor to ground, it becomes possible to alter the

default skip cycle level. 6 FB Feedback pin Hooking an optocoupler collector to this pin will allow regulation.

7 CS Current sense + ramp

This pin monitors the primary peak current but also offers a mean to introduce ramp compensation. 8 GND − The controller ground. 9 DRV Driver output The driver’s output to an external MOSFET. 10 VCC Supplies the controller This pin is connected to an external auxiliary voltage. 11 Ref. Reference voltage This pin delivers 5.0 V and sources up to 5.0 mA. 12 NC − Non−connected for improved creepage. 13 NC − Non−connected for improved creepage.

14 HV High−voltage input Connected to the bulk capacitor, this pin powers the internal current

source to deliver a startup current.

4 V Reset

10 VCC

9 Drv

Figure 2. Internal Circuit Architecture

http://onsemi.com MAXIMUM RATINGS Rating Symbol Value Unit Power Supply Voltage, VCC Pin, Continuous Voltage VCC 20 V Transient Power Supply Voltage, Duration < 10 ms, IVCC < 20 mA − 25 V Maximum Voltage on Low Power Pins (Except Pin 9, Pin 10, Pin 5 and Pin 14) − −0.3 to 10 V Maximum Voltage on Pin 5 − 5.0 V Thermal Resistance, Junction−to−Air R/C0113JA 120 °C/W Thermal Reference Junction−to−Lead (Note 3) Psi JL 40 °C/W Maximum Junction Temperature TJMAX 150 °C Storage Temperature Range − −60 to +150 °C ESD Capability, HBM Model (All Pins Except HV) − 2.0 kV ESD Capability, Machine Model − 200 V Maximum Voltage on Pin 14 (HV) − −0.3 to 500 V Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. This device series contains ESD protection and exceeds the following tests: Human Body Model 2000 V per Mil−Std−883, Method 3 015. Machine Model Method 200 V 2. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78. 3. Minimum Pad FR4 Board 1 oz Copper.

http://onsemi.com ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −5°C to +125°C, Max TJ = 150°C, VCC = 12 V unless otherwise noted.) Characteristic Symbol Pin Min Typ Max Unit SUPPLY SECTION VCC Increasing Level at which the Current Source Turns−Off VCCON 10 11.8 12.8 13.8 V VCC Level at which Output Pulses are Stopped VCC(min) 10 8.0 9.0 10 V VCC Decreasing Level at which the Latch−Off Phase Ends VCClatch 10 − 6.5 − V Internal Latch Reset Level VCCreset 10 − 5.0 − V Minimum Voltage Difference between VCClatch and VCCReset resetHyst − 1.0 − − V Internal IC Consumption, No Output Load on Pin 9 DAP011 DAP011C ICC1 10 − 1.2 1.3 mA Internal IC Consumption, 1.0 nF Output Load on Pin 9 DAP011 DAP011C ICC2 10 − 1.9 2.5 mA Internal IC Consumption, Latch−Off Phase ICC3 10 − 0.6 mA Reference Voltage, Iout = 1.0 mA, TJ = 25°C Vref1 11 4.9 5.0 5.1 V Reference Voltage, Iout = 5.0 mA Vref2 11 4.8 − 5.13 V Maximum Output Current Capability IrefOut 11 5.0 − − mA Decoupling Capacitor Connected to Pin 11 Cref 11 100 − − nF INTERNAL STARTUP CURRENT SOURCE (TJ > −5°C) – High−voltage pin biased to 60 V DC. High−Voltage Current Source, VCC = 10 V (Note 4) IC2 14 2.0 4.0 − mA High−Voltage Current Source, VCC = 0 IC1 14 200 500 650 /C0109A VCC Transition Level for IC1 to IC2 Toggling Point VTh 14 − 1.8 − V Leakage Current for the High Voltage Source, Vpin 14 = 250 Vdc Ileak 14 − 35 − /C0109A DRIVE OUTPUT (Lothar like) Output Voltage Rise−Time @ CL = 1.0 nF, 10−90% of a 12 V Output Signal Tr 9 − 40 − ns Output Voltage Fall−Time @ CL = 1.0 nF, 10−90% of a 12 V Output Signal Tf 9 − 15 − ns Source Resistance ROH 9 − 12 − /C0087 Sink Resistance ROL 9 − 7.0 − /C0087 CURRENT COMPARATOR Input Bias Current @ 1.0 V Input Level on Pin 7 IIB 7 − 0.02 − /C0109A Maximum Internal Current Setpoint – TJ = 25°C ILimit1 7 0.95 1.0 1.05 V Maximum Internal Current Setpoint – TJ from −5° to 125°C ILimit2 7 0.93 1.0 1.07 V Default Internal Voltage Setpoint for Skip Cycle Operation VLskip 7 − 350 − mV Propagation Delay from Current Detection to Gate OFF State TDEL 7 − 100 150 ns Leading Edge Blanking Duration TLEB 7 − 200 − ns Soft−Start Duration, Ctimer = 0.22 /C0109F TSS − − 10 − ms INTERNAL OSCILLATOR Oscillation Frequency DAP011 DAP011C fOSC − 60 100 108 kHz Maximum Duty−Cycle Dmax − 76 80 84 % Frequency Jittering in Percentage of fOSC DAP011 DAP011C fjitter − − /C00345.0 /C00346.0 Swing Frequency with a 22 nF Capacitor to Pin 4 fswing 4 − 300 − Hz Jittering Modulator Charging Current ICjit 4 − 20 − /C0109A Jittering Capacitor Peak Voltage VCjitP 4 − 2.15 − V Jittering Capacitor Valley Voltage VCjitV 4 − 0.75 − V 4. Min. value for T J = 125°C (See Figure 10).

http://onsemi.com ELECTRICAL CHARACTERISTICS (continued) (For typical values TJ = 25°C, for min/max values TJ = −5°C to +125°C, Max TJ = 150°C, VCC = 12 V unless otherwise noted.) Characteristic Symbol Pin Min Typ Max Unit FEEDBACK SECTION Internal Pullup Resistor Rup 6 − 20 − k/C0087 Pin 6 to Current Setpoint Division Ratio Iratio − − 3.0 − − SKIP CYCLE GENERATION Internal Skip Reference Current Iskip 5 − 40 − /C0109A Pin 5 Internal Output Impedance (Note 5) Zout 5 − 25 − k/C0087 Default Skip Mode Level Vskip 5 − 1.0 − V INTERNAL RAMP COMPENSATION Internal Ramp Level @ 25°C (Note 6) Vramp 7 − 1.8 − V Internal Ramp Resistance to CS Pin Rramp 7 − 20 − k/C0087 PROTECTIONS Latching Level Input Vlatch 2 2.85 3.05 3.25 V Delay before Latch Confirmation Tlatch−del − − 20 − /C0109s Timer Level Completion VtimFault 3 − 4.3 − V Timer Capacitor Charging Current Itim 3 − 10 − /C0109A Timer Length, Ctimer = 0.22 μF Typical TimerL 3 − 100 − ms Temperature Shutdown TSD − 140 − − °C Temperature Shutdown Hysteresis TSD_hys − − 40 − °C 5. Maximum voltage on Pin 5 is 5.0 V. 6. A 15 k /C0087 resistor is connected from Pin 7 to the ground for the measurement.

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APPLICATION INFORMATION

SpeedKing implements a standard current mode architecture where the switch−off event is dictated by the peak current setpoint. This component represents the ideal candidate where low part−count is the key parameter, particularly in low−cost AC/DC adapters, open−frame power supplies etc. Due to its high voltage technology, the DAP011/DAP011C incorporates all the necessary components normally needed in today modern power supply designs, bringing several enhancements such as an adjustable EMI jittering and a fault timer.

• Current−mode operation with internal ramp compensation: implementing peak current mode control, the DAP011/DAP011C offers an internal ramp compensation signal that can easily by summed up to the sensed current. Subharmonic oscillations can thus be fought via the inclusion of a simple resistor.
• Internal high−voltage startup switch: reaching a low no−load standby power represents a difficult exercise when the controller requires an external, lossy, resistor connected to the bulk capacitor. Thanks to an internal logic, the controller disables the high−voltage current source after startup which no longer hampers the consumption in no−load situations.
• EMI jittering: a dedicated pin offers the ability to vary the pace at which the oscillator frequency is modulated. This helps spreading out energy in conducted noise analysis.
• Skip−cycle capability: a continuous flow of pulses in not compatible with no−load standby power requirements. Slicing the switching pattern in bunch of pulses drastically reduces overall losses but can, in certain cases, bring acoustic noise in the transformer. Thanks to a skip operation taking place at low peak currents only, no mechanical noise appears in the transformer. Also, activating the soft−start during skip cycle brings so−called SoftSkip benefits, greatly reducing acoustical noise in the transformer.
• Internal soft−start: a soft−start precludes the main power switch from being stressed upon startup. Its duration is equal to 10% of the fault timer, e.g. 10ms for a 100 ms timer duration.
• Latch input: by monitoring pin 2, the controller detects when it is brought above a latching level via a zener (OVP) or a NTC (OTP), or both. When the latch is detected, all pulses are permanently disabled and VCC goes up and down, maintaining the latch condition. When the user cycles V CC below 5.0 V , the controller gets reset and attempts to restart.
• Short−circuit protection: short−circuit and especially over−load protection are difficult to implement when a strong leakage inductance between auxiliary and power windings affects the transformer (the auxiliary winding level does not properly collapse in presence of an output short). Here, every time the internal 1.0 V maximum peak current limit is activated, an error flag, Ip Flag, is asserted and a time period starts, thanks to an adjustable timer. If the timer reaches completion while the error flag is still present, the controller stops the pulses and goes into a latch−off phase, operating in a low−frequency burst−mode. To limit the fault output power, a divide−by−two circuitry is installed on the V CC pin and requires twice a startup sequence before another attempt to restart is. As soon as the fault disappears, the SMPS resumes operation. The latch−off phase can also be initiated, more classically, when V CC drops below VCC(min) (9.0 V typical).

1. the converter regulates but the auxiliary winding

goes away, the SMPS resumes operation. Figure 23. First Fault Mode Case, the Auxiliary Winding Collapses but Feedback is Still There

1. In the second case, the converter operates in

regulation, but the output is severely overloaded. to the maximum and the timer starts to count. away, the SMPS resumes operation. Figure 24. This Case is Similar to a Short−circuit Where VAUX Does Not Collapse

1. A second case exists where the short−circuit

fault is removed, the SMPS resumes operation. Figure 25. This Case is Similar to a Short−circuit Where VAUX Does Collapse

either reducing the timer or increasing the V CC capacitor. Figure 26. The Burst Period is Ensured by the VCC Capacitor Charge/Discharge Cycle becomes easy to evaluate the burst period and its duty−cycle.

• t1: I = ICC3 = 600 /C0109A, /C0068V = 9 – 6.5 = 2.5 V /C0179 t1 = 91 ms
• t2: I = 3 mA, /C0068V = 12.8 – 6.5 = 6.3 /C0179 t1 = 46 ms
• t3: I = 600 /C0109A, /C0068V= 12.8 – 6.5 = 6.3 V /C0179 t1 = 231ms
• t’1 = t1 = 91 ms
• t’2 = t2 = 46 ms The total period duration is thus the sum of all these events which leads to Tfault = 505 ms. If Tpulse = 100 ms, then our burst duty−cycle equals 100/(505+100) ≈ 16.5%, which is good. Should the user like to further decrease or, to the contrary, increase this duty−cycle, changing the V CC capacitor is an easy job. Latch−off and Overvoltage Protection Speedking features a fast comparator that permanently monitors Pin 2 level. Figure 27 details how it is internally arranged:

Figure 27. A Comparator Monitors Pin 2 and Latches

5 V reset

Figure 28. The Part is Reset when VCC Reaches 5.0 V double hiccup mode to keep the consumption to the lowest. order to improve the noise immunity. Figure 29. The Reference Voltage is used with the

5.0 V, FB Pin open

3.0 V upper dynamic range

default), the peak current cannot exceed 1.0 V / R sense. cannot go below 1.0 V / 3 or around 350 mV / R sense. Figure 37. Output Pulses at Various Power Levels (X = 5 /C0109s/div) P1 < P2 < P3

Figure 40. Due to Pin 4, it is Easy to Alter the Default Skip Level

http://onsemi.com PACKAGE DIMENSIONS SOIC−14 D SUFFIX CASE 751A−03 ISSUE G NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. −A− −B− G P 7 PL 14 8 M0.25 (0.010) B M SBM0.25 (0.010) A ST −T− FR X 45 SEATING PLANE D 14 PL K C JM /C0095 DIM MIN MAX MIN MAX INCHESMILLIMETERS A 8.55 8.75 0.337 0.344 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049 G 1.27 BSC 0.050 BSC J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009 M 0 7 0 7 P 5.80 6.20 0.228 0.244 R 0.25 0.50 0.010 0.019 /C0095/C0095/C0095/C0095 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 DAP011/D LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative.