DALC208 STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
Features
■ Protection of 4 lines ■ Peak reverse voltage: VRRM = 9 V per diode ■ Very low capacitance per diode: C < 5 pF ■ Very low leakage current: IR < 1 µA Benefits ■ Cost-effective solution compared with discrete solution ■ High efficiency in ESD suppression ■ No significant signal distortion thanks to very low capacitance ■ High reliability offered by monolithic integration ■ Lower PCB area consumption versus discrete solution Complies with the following standards ■ IEC61000-4-2 level 4 ■ MIL STD 883G-Method 3015-7: class 3, human body model
Applications
Where ESD and/or over and undershoot protection for datalines is required: ■ Sensitive logic input protection ■ Microprocessor based equipment ■ Audio / video inputs ■ Portable electronics ■ Networks ■ ISDN equipment ■ USB interface Figure 1. Functional diagram
Description
The DALC208SC6 diode array is designed to protect components which are connected to data and transmission lines from over voltages caused by electrostatic discharge (ESD) or other transients. It is a rail-to-rail protection device also suited for overshoot and undershoot suppression on sensitive logic inputs. The low capacitance of the DALC208SC6 prevents significant signal distortion. SOT23-6L (Plastic) I/O 1 I/O 2 I/O 3 I/O 4 REF 2 REF 1
1 Characteristics
Figure 2. Input capacitance measurement Table 1. Absolute maximum ratings (T amb = 25 °C) Table 2. Thermal resistance
- Device mounted on FR4 PCB with recommended footprint dimensions.
Table 3. Electrical characteristics (T amb = 25 °C)
Technical information DALC208
2 Technical information
2.1 Surge protection
The DALC208SC6 is particularly optimized to perform surge protection based on the rail to rail topology. The clamping voltage VCL can be calculated as follow : VCL+ = VREF2 + VF for positive surges VCL- = VREF1 - VF for negative surges with V F = VT + Rd.Ip (VF forward drop voltage) / (VT forward drop threshold voltage) According to the curve Figure 7 we assume that the value of the dynamic resistance of the clamping diode is typically Rd = 0.7 Ω and VT = 1.2 V. For an IEC 61000-4-2 surge Level 4 (Contact Discharge: Vg=8 kV, Rg=330 Ω), VREF2 = +5 V, VREF1 = 0 V, and if in first approximation, we assume that : Ip = Vg / Rg ′ 24 A. So, we find: –V CL+′ +23V –V CL-′ -18V Note: The calculations do not take into account phenomena due to parasitic inductances.
2.2 Surge protection application example
If we consider that the connections from the pin REF2 to VCC and from REF1 to GND are done by two tracks of 10 mm long and 0.5 mm large; we assume that the parasitic inductances of these tracks are about 6 nH. So when an IEC 61000-4-2 surge occurs, due to the rise time of this spike (tr = 1 ns), the voltage V CL has an extra value equal to Lw.dI/dt. The dI/dt is calculated as: dI/dt = Ip/tr ′ 24 A/ns The overvoltage due to the parasitic inductances is: Lw.dI/dt = 6 x 24 ′ 144V By taking into account the effect of these parasitic inductances due to unsuitable layout, the clamping voltage will be : –V CL+ = +23 + 144 ′ 167V We can reduce as much as possible these phenomena with simple layout optimization. It’s the reason why some recommendations have to be followed (See Section 2.3: How to ensure good ESD protection).
Figure 8. ESD behavior: parasitic phenomena due to unsuitable layout
2.3 How to ensure good ESD protection
as possible to avoid over voltages due to parasitic phenomena. See Figure 8. thanks to the ground plane that allows a short connection. REF2 and ground, to prevent these kinds of overvoltage disturbances. to the recommendations described above.
3 Crosstalk behavior
3.1 Crosstalk phenomena
Figure 13. Crosstalk phenomena
3.2 Digital crosstalk
Figure 14. Digital crosstalk measurements Figure 15. Digital crosstalk results
3.3 Analog crosstalk
Figure 16. Analog crosstalk measurements range of analog signals (up to 100MHz) the effect on disturbed line is less than -45 dBm. transmission of operating signals. The attenuation curve give such an information. 100 Mbit/s while it works as a filter for undesirable signals such as GSM carrier (900 MHz). Figure 17. Analog crosstalk results Figure 18. DALC208SC6 attenuation
4 Application examples
Figure 19. Video line protection Figure 22. Another way to connect the DALC208SC6
1 RED VIDEO
2 GREEN VIDEO
3 BLUE VIDEO
4 GROUND
5 DDC (Display Data Channel) GROUND
6 RED GROUND
7 GREEN GROUND
8 BLUE GROUND
10 SYNC GROUND
11 GROUND
12 SDA (Sérial Data)
13 HORIZONTAL SYNC
14 VERTICAL SYNC (VCLK)
15 SCL (Serial Clock)
Figure 20. T1/E1 protection Figure 21. USB port protection
5 PSpice model
defined by the PSpice parameters given in Table 4. Figure 23. PSpice model of one DALC208SC6 Figure 24. PSpice model simulation: surge > 0 Figure 25. PSpice model simulation: surge < 0 Figure 26. Attenuation comparison
Table 4. PSpice parameter
6 Package information
- Epoxy meets UL94, V0 In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com.
Figure 27. Footprint (dimensions in mm) Table 5. SOT23-6L dimensions
7 Ordering information
8 Revision history
Table 6. Ordering information Table 7. Document revision history millimeters (0.118 inches) to 3.05 millimeters (0.120 inches). 20-Mar-2008 7 Reformatted to current standard. Added ECOPACK paragraph.