DAC91001PFBT

Texas Instruments

DACx1001 20-Bit, 18-Bit, and 16-Bit, Low-Noise, Ultra-Low Harmonic Distortion, Fast-Settling, High-Voltage Output, Digital-to-Analog Converters (DACs)

Manufacturer: Texas Instruments

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DAC11001A_V02 TI1 | Alldatasheet

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Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA. DAC11001A, DAC91001, DAC81001 SLASEL0A – OCTOBER 2019– REVISED DECEMBER 2019 DACx100120-Bit,18-Bit,and16-Bit,Low-Noise,Ultra-LowHarmonicDistortion,Fast- Settling,High-VoltageOutput,Digital-to-AnalogConverters(DACs)

1 Features

1• 20-bit monotonic: 1-LSB DNL (max)

Integral linearity: 4-LSB INL (max)
Low noise: 7nV/√Hz
Code independent low glitch: 1 nV-s
Excellent THD: –105 dB at 1-kHz fOUT
Fast settling: 1 µs
Flexible output ranges: VREFPF to VREFNF
Integrated, precision feedback resistors
50-MHz, 4-wire SPI-compatible interface – Readback – Daisy-chain
Temperature range: –40°C to +125˚C
Package: 48-pin TQFP

2 Applications

Lab and field instrumentation
Spectrometer
Analog output module
Battery Test
Semiconductor test
Arbitrary waveform generator (AWG)
MRI
X-ray systems
Professional audio amplifier (rack mount)

3 Description

The 20-bit DAC11001A, 18-bit DAC91001, and 16-bit DAC81001 (DACx1001) are highly accurate, low- noise, voltage-output, single-channel, digital-to- analog converters (DACs). The DACx1001 are specified monotonic by design, and offer excellent linearity of less than 4 LSB (max) across all ranges. The unbuffered voltage output offers low noise performance (7 nV/√Hz) in combination with a fast settling time (1µs), making this device an excellent choice for low-noise, fast control-loop, and waveform generation applications. The DACx1001 integrates an enhanced deglitch circuit with code-independent ultra-low glitch (1 nV-s) to enable clean waveform ramps with ultra-low total harmonic distortion (THD). The DACx1001 devices incorporate a power-on-reset circuit so that the DAC powers with known values in the registers. With external references, DAC output ranges from VREFPF to VREFNF can be achieved, including asymmetric output ranges. The DACx1001 use a versatile 4–wire serial interface that operates at clock rates of up to 50 MHz. The DACx1001 is specified over the industrial temperature range of –40°C to +125°C. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) DAC11001 TQFP (48) 7.00 mm × 7.00 mmDAC91001 (preview) DAC81001 (preview) (1) For all available packages, see the package option addendum at the end of the data sheet. Functional Block Diagram High-Precision, Control-Loop Circuit

DAC11001A, DAC91001, DAC81001 SLASEL0A – OCTOBER 2019– REVISED DECEMBER 2019 www.ti.com Product Folder Links: DAC11001A DAC91001 DAC81001 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Table of Contents 7.6 Timing Requirements: Write, 4.5 V ≤ DVDD ≤ 5.5 7.7 Timing Requirements: Write, 2.7 V ≤ DVDD < 4.5

7.8 Timing Requirements: Read and Daisy-Chain

7.9 Timing Requirements: Read and Daisy-Chain Write,

12.4 Receiving Notification of Documentation Updates 46

13 Mechanical, Packaging, and Orderable

4 Revision History

Changes from Original (October 2019) to Revision A Page

48 NC13NC

47 AGND14AGND-TnH

46 AGND15NC

45 VCC16DGND

44 VSS17DGND

43 AGND18LDAC

42 AGND19ALARM

41 AVDD20DGND

40 AGND21DGND

39 AVDD22DGND

38 AGND23DGND

37 NC24NC

5 Device Comparison Table

DAC91001 (preview) 18-bit DAC81001 (preview) 16-bit

6 Pin Configuration and Functions

DAC11001A, DAC91001, DAC81001 SLASEL0A – OCTOBER 2019– REVISED DECEMBER 2019 www.ti.com Product Folder Links: DAC11001A DAC91001 DAC81001 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Pin Functions PIN TYPE DESCRIPTION NAME NO. AGND 2, 35, 38, 40, 42, 43, 46, 47 Analog ground Connect to 0 V. AGND-OUT 8 Analog ground Connect to 0 V. Measure DAC output voltage with respect to this node. AGND-TnH 14 Analog ground Connect to 0 V. Integrated deglitcher clock ground.. ALARM 19 Output Alarm output AVDD 39, 41 Power Positive low voltage analog power supply CLR 30 Input DAC registers clear pin, active low DGND 16, 17, 20, 21, 22, 23, Digital ground Connect to 0 V. DVDD 27 Power Digital power supply pin RFB 9 Input Integrated precision resistor feedback node IOVDD 28 Power Interface power supply pin LDAC 18 Input Load DAC pin, active low NC 1, 12, 13, 15, 24, 25, 29, 36, 37, — No connection, leave floating OUT 7 Output Unbuffered voltage output RCM 11 Input Integrated precision resistor common-mode node REFNF 5 Input External negative reference input. Connect to 0 V for unipolar DAC output. REFNS 6 Input External negative reference sense node REFPF 3 Input External positive reference input REFPS 4 Input External positive reference sense node ROFS 10 Input Integrated precision resistor offset node SCLK 31 Input Serial clock input of serial peripheral interface (SPI). Schmitt-trigger logic input. Data are transferred at rates of up to 50 MHz. SDIN 32 Input Serial data input. Schmitt-trigger logic input. Data are clocked into the input shift register on the falling edge of the serial clock input. SDO 34 Output Serial data output. Data are valid on the falling edge of SCLK. SYNC 33 Input SPI bus chip select input (active low). Data bits are not clocked into the serial shift register unless SYNC is low. When SYNC is high, the SDO pin is in high-impedance status. VCC 45 Power Analog positive power supply VSS 44 Power Analog negative power supply

DAC11001A, DAC91001, DAC81001 www.ti.com SLASEL0A – OCTOBER 2019– REVISED DECEMBER 2019 Product Folder Links: DAC11001A DAC91001 DAC81001 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Positive supply voltage AVDD to AGND –0.3 7 VVCC to VSS –0.3 40 VCC to AGND –0.3 40 Negative supply voltage VSS to AGND –19 0.3 V Positive reference voltage VREFPF to VREFNF –0.3 40 VVREFPF to VCC –0.3 VCC + 0.3 VREFPF to AGND –0.3 40 Negative reference voltage VREFNF to AGND –19 0.3 V VREFNF to VSS VSS – 0.3 0.3 Digital and IO power supply DVDD, IOVDD to DGND –0.3 7 V Digital input(s) to DGND DGND – 0.3 IOVDD + 0.3 V VOUT, VRFB, VRCM, VROFS to AGND (VSS = AGND) VSS VCC V to VSS 0 VCC Alarm pin voltage, ALARM to DGND –0.3 DVDD + 0.3 V Digital output, SDO to DGND –0.3 DVDD + 0.3 V Current into any pin –10 10 mA TJ Junction temperature 150 °C Tstg Storage temperature –65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±1000 V Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±250

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT AVDD to AGND 4.5 5.5 V VSS to AGND –18 –3 V VCC to AGND 8 33 V VCC to VSS 11 36 V DVDD to DGND 2.7 5.5 V IOVDD to DGND 1.7 5.5 V AGND to DGND –0.3 0.3 V VIH digital input high voltage 0.7 × IOVDD V VIL digital input low voltage 0.3 × IOVDD V VREFPF to AGND 3 15 V VREFNF to AGND –15 0 V VREFPF to VREFNF 3 30 V TA Operating temperature –40 125 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.4 Thermal Information Package

THERMAL METRIC(1) DAC11001A, DAC91001, DAC81001 UNITPFB (TQFP)

48 PINS

RθJA Junction-to-ambient thermal resistance 51.0 °C/W RθJC(top) Junction-to-case (top) thermal resistance 10.3 °C/W RθJB Junction-to-board thermal resistance 16.2 °C/W ΨJT Junction-to-top characterization parameter 0.3 °C/W ΨJB Junction-to-board characterization parameter 16.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W

DAC11001A, DAC91001, DAC81001 www.ti.com SLASEL0A – OCTOBER 2019– REVISED DECEMBER 2019 Product Folder Links: DAC11001A DAC91001 DAC81001 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated (1) Specified for the following pairs: VREFPF = 5 V and VREFNF = 0 V; VREFPF = 10 V and VREFNF = 0 V; VREFPF = +5 V and VREFNF = –5 V; VREFPF = +10 V and VREFNF = –10 V. (2) Calculated between code 0d to 1048575d. (3) With device temperature calibration mode enabled and used. (4) Specified by design, not production tested.

7.5 Electrical Characteristics

at TA = –40°C to +125°C, VCC = +15 V, VSS = –15 V, AVDD = 5.5 V, DVDD = 3.3 V, IOVDD = 1.8 V, see note(1) for VREFPF and VREFNF, 20-bit orderable used, OUT pin buffered with unity gain OPA827, ROFS, RCM, RFB unconnected, and all typical specifications at TA = 25°C, (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STATIC PERFORMANCE Resolution DAC11001A 20 BitsDAC91001 18 DAC81001 16 INL Relative accuracy(2) –4 4 LSBRelative accuracy(2)(3)(4) –2.6 2.6 Relative accuracy(2)(4) DACx1001A TA = 25°C –2 2 Relative accuracy drift over time(2) TA = 25°C, 1000 hrs 0.1 LSB DNL Differential nonlinearity(2)(3) –1 1 LSB Zero code error(4) TA = 0°C to 70°C, code 0d into DAC, unipolar ranges only –4 4 LSBTA = –40°C to +125°C, code 0d into DAC, unipolar ranges only –4 4 TA = 25°C, unipolar ranges only ±2 Zero code error temperature coefficient TA = 0°C to 70°C, code 0d into DAC, unipolar ranges only ±0.04 ppm FSR/°CTA = –40°C to +125°C, code 0d into DAC, unipolar ranges only ±0.04 Gain error(2)(4) TA = 0°C to 70°C –8 8 ppm of FSR TA = 0°C to 70°C, VREFPF = 3 V, VREFNF = –10 V –8 8 TA = –40°C to +125°C –10 10 TA = 25°C ±2 Gain error temperature coefficient TA = 0°C to 70°C ±0.04 ppm FSR/°C TA = 0°C to 70°C, VREFPF = 3 V, VREFNF = –10 V ±0.04 Positive full-scale error(4) TA = 0°C to 70°C, code 1048575d into DAC –8 8 LSB TA = 0°C to 70°C, code 1048575d into DAC, VREFPF = 3 V, VREFNF = –10 V –6 6 TA = –40°C to +125°C, code 1048575d into DAC –10 10 TA = 25°C ±2 Full-scale error temperature coefficient TA = 0°C to 70°C ±0.04 ppm FSR/°C TA = 0°C to 70°C, VREFPF = 3 V, VREFNF = –10 V ±0.04 OUTPUT CHARACTERISTICS Headroom From VREFPF to VCC 3 V Footroom From VREFNF to VSS 3 V DC impedance From ROFS to RCM 5 kΩ From RCM to RFB 5 ZO DC output impedance 2.5 kΩ

DAC11001A, DAC91001, DAC81001 SLASEL0A – OCTOBER 2019– REVISED DECEMBER 2019 www.ti.com Product Folder Links: DAC11001A DAC91001 DAC81001 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Electrical Characteristics (continued) at TA = –40°C to +125°C, VCC = +15 V, VSS = –15 V, AVDD = 5.5 V, DVDD = 3.3 V, IOVDD = 1.8 V, see note(1) for VREFPF and VREFNF, 20-bit orderable used, OUT pin buffered with unity gain OPA827, ROFS, RCM, RFB unconnected, and all typical specifications at TA = 25°C, (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (5) Adaptive TnH mode. TnH action is disabled for large code steps. For small steps, TnH action happens with a hold time of 1.2µs. Power supply rejection ratio (dc) TA = 25°C, VCC = 15 V ± 20%, VSS = –15 V 1.5 µV/V TA = 25°C, VCC = 15 V, VSS = –15 V ± 20% 1 VOLTAGE REFERENCE INPUT Reference input impedance (REFPF) DAC at midscale, VREFPF = 10 V, VREFNF = 0 V 5.5 kΩ Reference input impedance (REFNF) DAC at midscale, VREFPF = 10 V, VREFNF = 0 V 7 DYNAMIC PERFORMANCE ts Output voltage settling time(5) VREFPF = 10 V, VREFNF = 0 V, full-scale settling to 0.1%FSR 1 µsVREFPF = 10 V, VREFNF = 0 V, full-scale settling to ±1 LSB 2.5 VREFPF = 10 V, VREFNF = 0 V, 1-mV step settling to ±1 LSB 2.5 SR Slew rate VREFPF = 10 V, VREFNF = 0 V, full-scale step, measured at OUT pin 50 V/µs Power-on glitch magnitude Measured at unbuffered DAC voltage output, VREFPF = 10 V, VREFNF = 0 V –0.2 V Vn Output noise 0.1-Hz to 10-Hz, DAC at midscale, VREFPF = 10 V, VREFNF = 0 V 0.4 µVpp 100-kHz bandwidth, DAC at midscale, VREFPF = 10 V, VREFNF = 0 V 3 µVrms Output noise density Measured at 1 kHz, 10 kHz, 100 kHz, DAC at mid scale, VREFPF = 10 V, VREFNF = 0 V 7 nV/√Hz SFDR Spurious free dynamic range DAC update rate = 400 kHz, fOUT = 1 kHz, VOUTPP = 0 V to 10 V –105 dB DAC update rate = 400 kHz, fOUT = 1 kHz, VOUTPP = 3 V to –10 V –105 dB THD Total harmonic distortion DAC update rate = 400 kHz, fOUT = 1 kHz, VOUTPP = 0 V to 10 V –105 dB DAC update rate = 400 kHz, fOUT = 1 kHz, VOUTPP = 3 V to –10 V –105 dB Power supply rejection ratio (ac) 200-mV 50-Hz or 60-Hz sine wave superimposed on VSS, VCC = 15 V 95 dB 200-mV 50 Hz or 60 Hz sine wave superimposed on VCC, VSS = –15 V 95 dB Code change glitch impulse ±1 LSB change around mid code (including feedthrough), VREFPF = 10 V, VREFNF = 0 V, measured at output of buffer op amp 1 nV-s Code change glitch impulse magnitude ±1 LSB change around mid code (including feedthrough), VREFPF = 10 V, VREFNF = 0 V, measured at output of buffer op amp 5 mV Reference feedthrough VREFPF = 10 V ± 10%, VREFNF = 0 V, frequency = 100 Hz, DAC at zero scale –90 dB Reference feedthrough VREFNF = –10 V ± 10%, VREFPF = 10 V, frequency = 100 Hz, DAC at full scale –90 dB

DAC11001A, DAC91001, DAC81001 www.ti.com SLASEL0A – OCTOBER 2019– REVISED DECEMBER 2019 Product Folder Links: DAC11001A DAC91001 DAC81001 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated Electrical Characteristics (continued) at TA = –40°C to +125°C, VCC = +15 V, VSS = –15 V, AVDD = 5.5 V, DVDD = 3.3 V, IOVDD = 1.8 V, see note(1) for VREFPF and VREFNF, 20-bit orderable used, OUT pin buffered with unity gain OPA827, ROFS, RCM, RFB unconnected, and all typical specifications at TA = 25°C, (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Digital feedthrough At SCLK = 1 MHz, DAC output static at midscale, 10-V range 1 nV-s DIGITAL INPUTS Hysteresis voltage 0.4 V Input current ±5 µA Pin capacitance Per pin 10 pF DIGITAL OUTPUTS VOL Output low voltage sinking 200 µA 0.4 V VOH Output high voltage sourcing 200 µA IOVDD – 0.5 V High impedance leakage ±5 µA High impedance output capacitance 10 pF POWER IAVDD Current flowing into AVDD VREFPF = 10 V, VREFNF = 0 V, midscale code 1.5 mA IVCC Current flowing into VCC VREFPF = 10 V, VREFNF = 0 V, midscale code 7 mA IVSS Current flowing into VSS VREFPF = 10 V, VREFNF = 0 V, midscale code 7 mA IDVDD Current flowing into DVDD VREFPF = 10 V, VREFNF = 0 V, midscale code 0.5 mA IIOVDD Current flowing into IOVDD VREFPF = 10 V, VREFNF = 0 V, midscale code, all digital input pins static at IOVDD 0.1 mA IREFPF Reference input current (VREFPF) VREFPF = 10 V, VREFNF = 0 V, midscale code 5 mA IREFNF Reference input current (VREFNF) VREFPF = 10 V, VREFNF = 0 V, midscale code 5 mA

DAC11001A, DAC91001, DAC81001 SLASEL0A – OCTOBER 2019– REVISED DECEMBER 2019 www.ti.com Product Folder Links: DAC11001A DAC91001 DAC81001 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated 7.6 Timing Requirements: Write, 4.5 V ≤ DVDD ≤ 5.5 V all input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed from a voltage level of (VIL + VIH) / 2, SDO loaded with 20 pF, and TA = –40°C to +125°C (unless otherwise noted) MIN NOM MAX UNIT fSCLK SCLK frequency, 1.7 V ≤ IOVDD < 2.7 V 33 MHz SCLK frequency, 2.7 V ≤ IOVDD ≤ 5.5 V 50 tSCLKHIGH SCLK high time, 1.7 V ≤ IOVDD < 2.7 V 15 ns SCLK high time, 2.7 V ≤ IOVDD ≤ 5.5 V 10 tSCLKLOW SCLK low time, 1.7 V ≤ IOVDD < 2.7 V 15 ns SCLK low time, 2.7 V ≤ IOVDD ≤ 5.5 V 10 tSDIS SDI setup, 1.7 V ≤ IOVDD < 2.7 V 13 ns SDI setup, 2.7 V ≤ IOVDD ≤ 5.5 V 8 tSDIH SDI hold, 1.7 V ≤ IOVDD < 2.7 V 13 ns SDI hold, 2.7 V ≤ IOVDD ≤ 5.5 V 8 tCSS SYNC falling edge to SCLK falling edge, 1.7 V ≤ IOVDD < 2.7 V 23 ns SYNC falling edge to SCLK falling edge, 2.7 V ≤ IOVDD ≤ 5.5 V 18 tCSH SCLK falling edge to SYNC rising edge, 1.7 V ≤ IOVDD < 2.7 V 15 ns SCLK falling edge to SYNC rising edge, 2.7 V ≤ IOVDD ≤ 5.5 V 10 tCSHIGH SYNC high time, 1.7 V ≤ IOVDD < 2.7 V 55 ns SYNC high time, 2.7 V ≤ IOVDD ≤ 5.5 V 50 tCSIGNORE SCLK falling edge to SYNC ignore, 1.7 V ≤ IOVDD < 2.7 V 10 ns SCLK falling edge to SYNC ignore, 2.7 V ≤ IOVDD ≤ 5.5 V 5 tLDACSL Synchronous update: SYNC rising edge to LDAC falling edge, 1.7 V ≤ IOVDD < 2.7 V 50 ns Synchronous update: SYNC rising edge to LDAC falling edge, 2.7 V ≤ IOVDD ≤ 5.5 V 50 tLDACW LDAC low time, 1.7 V ≤ IOVDD < 2.7 V 20 ns LDAC low time, 2.7 V ≤ IOVDD ≤ 5.5 V 20 tCLRW CLR low time, 1.7 V ≤ IOVDD < 2.7 V 20 ns CLR low time, 2.7 V ≤ IOVDD ≤ 5.5 V 20

DAC11001A, DAC91001, DAC81001 www.ti.com SLASEL0A – OCTOBER 2019– REVISED DECEMBER 2019 Product Folder Links: DAC11001A DAC91001 DAC81001 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated 7.7 Timing Requirements: Write, 2.7 V ≤ DVDD < 4.5 V all input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed from a voltage level of (VIL + VIH) / 2, SDO loaded with 20 pF, and TA = –40°C to +125°C (unless otherwise noted) MIN NOM MAX UNIT fSCLK SCLK frequency, 1.7 V ≤ IOVDD < 2.7 V 20 MHz SCLK frequency, 2.7 V ≤ IOVDD ≤ 5.5 V 25 tSCLKHIGH SCLK high time, 1.7 V ≤ IOVDD < 2.7 V 25 ns SCLK high time, 2.7 V ≤ IOVDD ≤ 5.5 V 20 tSCLKLOW SCLK low time, 1.7 V ≤ IOVDD < 2.7 V 25 ns SCLK low time, 2.7 V ≤ IOVDD ≤ 5.5 V 20 tSDIS SDI setup, 1.7 V ≤ IOVDD < 2.7 V 21 ns SDI setup, 2.7 V ≤ IOVDD ≤ 5.5 V 16 tSDIH SDI hold, 1.7 V ≤ IOVDD < 2.7 V 21 ns SDI hold, 2.7 V ≤ IOVDD ≤ 5.5 V 16 tCSS SYNC falling edge to SCLK falling edge, 1.7 V ≤ IOVDD < 2.7 V 41 ns SYNC falling edge to SCLK falling edge, 2.7 V ≤ IOVDD ≤ 5.5 V 36 tCSH SCLK falling edge to SYNC rising edge, 1.7 V ≤ IOVDD < 2.7 V 25 ns SCLK falling edge to SYNC rising edge, 2.7 V ≤ IOVDD ≤ 5.5 V 20 tCSHIGH SYNC high time, 1.7 V ≤ IOVDD < 2.7 V 100 ns SYNC high time, 2.7 V ≤ IOVDD ≤ 5.5 V 100 tCSIGNORE SCLK falling edge to SYNC ignore, 1.7 V ≤ IOVDD < 2.7 V 10 ns SCLK falling edge to SYNC ignore, 2.7 V ≤ IOVDD ≤ 5.5 V 5 tLDACSL Synchronous update: SYNC rising edge to LDAC falling edge, 1.7 V ≤ IOVDD < 2.7 V 100 ns Synchronous update: SYNC rising edge to LDAC falling edge, 2.7 V ≤ IOVDD ≤ 5.5 V 100 tLDACW LDAC low time, 1.7 V ≤ IOVDD < 2.7 V 40 ns LDAC low time, 2.7 V ≤ IOVDD ≤ 5.5 V 40 tCLRW CLR low time, 1.7 V ≤ IOVDD < 2.7 V 40 ns CLR low time, 2.7 V ≤ IOVDD ≤ 5.5 V 40

DAC11001A, DAC91001, DAC81001 SLASEL0A – OCTOBER 2019– REVISED DECEMBER 2019 www.ti.com Product Folder Links: DAC11001A DAC91001 DAC81001 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated 7.8 Timing Requirements: Read and Daisy-Chain Write, 4.5 V ≤ DVDD ≤ 5.5 V all input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed from a voltage level of (VIL + VIH) / 2, SDO loaded with 20 pF, and TA = –40°C to +125°C (unless otherwise noted) MIN NOM MAX UNIT fSCLK SCLK frequency 1.7 V ≤ IOVDD < 2.7 V, FSDO = 0 10 MHz 1.7 V ≤ IOVDD < 2.7 V, FSDO = 1 20 2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 0 15 2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 1 30 tSCLKHIGH SCLK high time 1.7 V ≤ IOVDD < 2.7 V, FSDO = 0 50 ns 1.7 V ≤ IOVDD < 2.7 V, FSDO = 1 25 2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 0 33 2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 1 16 tSCLKLOW SCLK low time 1.7 V ≤ IOVDD < 2.7 V, FSDO = 0 50 ns 1.7 V ≤ IOVDD < 2.7 V, FSDO = 1 25 2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 0 33 2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 1 16 tSDIS SDI setup, 1.7 V ≤ IOVDD < 2.7 V 13 ns SDI setup, 2.7 V ≤ IOVDD ≤ 5.5 V 8 tSDIH SDI hold, 1.7 V ≤ IOVDD < 2.7 V 13 ns SDI hold, 2.7 V ≤ IOVDD ≤ 5.5 V 8 tCSS SYNC falling edge to SCLK falling edge, 1.7 V ≤ IOVDD < 2.7 V 30 ns SYNC falling edge to SCLK falling edge, 2.7 V ≤ IOVDD ≤ 5.5 V 20 tCSH SCLK falling edge to SYNC rising edge, 1.7 V ≤ IOVDD < 2.7 V 15 ns SCLK falling edge to SYNC rising edge, 2.7 V ≤ IOVDD ≤ 5.5 V 10 tCSHIGH SYNC high time, 1.7 V ≤ IOVDD < 2.7 V 55 ns SYNC high time, 2.7 V ≤ IOVDD ≤ 5.5 V 50 tCSIGNORE SCLK falling edge to SYNC ignore, 1.7 V ≤ IOVDD < 2.7 V 10 ns SCLK falling edge to SYNC ignore, 2.7 V ≤ IOVDD ≤ 5.5 V 5 tLDACSL Synchronous update: SYNC rising edge to LDAC falling edge, 1.7 V ≤ IOVDD <

2.7 V 50

Synchronous update: SYNC rising edge to LDAC falling edge, 2.7 V ≤ IOVDD ≤

5.5 V 50

LDAC low time, 1.7 V ≤ IOVDD < 2.7 V 20 ns LDAC low time, 2.7 V ≤ IOVDD ≤ 5.5 V 20 tCLRW CLR low time, 1.7 V ≤ IOVDD < 2.7 V 20 ns CLR low time, 2.7 V ≤ IOVDD ≤ 5.5 V 20 tSDODLY SCLK rising edge to SDO valid data, 1.7 V ≤ IOVDD < 2.7 V, FSDO = 0 0 35 ns SCLK rising edge to SDO valid data, 2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 0 0 25 SCLK falling edge to SDO valid data, 1.7 V ≤ IOVDD < 2.7 V, FSDO = 1 0 35 SCLK falling edge to SDO valid data, 2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 1 0 25 tSDOZ SYNC rising edge to SDO HiZ, 1.7 V ≤ IOVDD < 2.7 V 0 20 ns SYNC rising edge to SDO HiZ, 2.7 V ≤ IOVDD ≤ 5.5 V 0 20

DAC11001A, DAC91001, DAC81001 www.ti.com SLASEL0A – OCTOBER 2019– REVISED DECEMBER 2019 Product Folder Links: DAC11001A DAC91001 DAC81001 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated 7.9 Timing Requirements: Read and Daisy-Chain Write, 2.7 V ≤ DVDD < 4.5 V all input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed from a voltage level of (VIL + VIH) / 2, SDO loaded with 20 pF, and TA = –40°C to +125°C (unless otherwise noted) MIN NOM MAX UNIT fSCLK SCLK frequency 1.7 V ≤ IOVDD < 2.7 V, FSDO = 0 8 MHz 1.7 V ≤ IOVDD < 2.7 V, FSDO = 1 16 2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 0 10 2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 1 20 tSCLKHIGH SCLK high time 1.7 V ≤ IOVDD < 2.7 V, FSDO = 0 62 ns 1.7 V ≤ IOVDD < 2.7 V, FSDO = 1 31 2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 0 50 2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 1 25 tSCLKLOW SCLK low time 1.7 V ≤ IOVDD < 2.7 V, FSDO = 0 62 ns 1.7 V ≤ IOVDD < 2.7 V, FSDO = 1 31 2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 0 50 2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 1 25 tSDIS SDI setup, 1.7 V ≤ IOVDD < 2.7 V 21 ns SDI setup, 2.7 V ≤ IOVDD ≤ 5.5 V 16 tSDIH SDI hold, 1.7 V ≤ IOVDD < 2.7 V 21 ns SDI hold, 2.7 V ≤ IOVDD ≤ 5.5 V 16 tCSS SYNC falling edge to SCLK falling edge, 1.7 V ≤ IOVDD < 2.7 V 41 ns SYNC falling edge to SCLK falling edge, 2.7 V ≤ IOVDD ≤ 5.5 V 36 tCSH SCLK falling edge to SYNC rising edge, 1.7 V ≤ IOVDD < 2.7 V 25 ns SCLK falling edge to SYNC rising edge, 2.7 V ≤ IOVDD ≤ 5.5 V 20 tCSHIGH SYNC high time, 1.7 V ≤ IOVDD < 2.7 V 100 ns SYNC high time, 2.7 V ≤ IOVDD ≤ 5.5 V 100 tCSIGNORE SCLK falling edge to SYNC ignore, 1.7 V ≤ IOVDD < 2.7 V 10 ns SCLK falling edge to SYNC ignore, 2.7 V ≤ IOVDD ≤ 5.5 V 5 tLDACSL Synchronous update: SYNC rising edge to LDAC falling edge, 1.7 V ≤ IOVDD <

2.7 V 100

Synchronous update: SYNC rising edge to LDAC falling edge, 2.7 V ≤ IOVDD ≤

5.5 V 100

LDAC low time, 1.7 V ≤ IOVDD < 2.7 V 40 ns LDAC low time, 2.7 V ≤ IOVDD ≤ 5.5 V 40 tCLRW CLR low time, 1.7 V ≤ IOVDD < 2.7 V 40 ns CLR low time, 2.7 V ≤ IOVDD ≤ 5.5 V 40 tSDODLY SCLK rising edge to SDO valid data, 1.7 V ≤ IOVDD < 2.7 V, FSDO = 0 0 40 ns SCLK rising edge to SDO valid data, 2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 0 0 30 SCLK rising edge to SDO valid data, 1.7 V ≤ IOVDD < 2.7 V, FSDO = 1 0 40 SCLK rising edge to SDO valid data, 2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 1 0 30 tSDOZ SYNC rising edge to SDO HiZ, 1.7 V ≤ IOVDD < 2.7 V 0 20 ns SYNC rising edge to SDO HiZ, 2.7 V ≤ IOVDD ≤ 5.5 V 0 20

7.10 Typical Characteristics

Figure 3. . Integral Linearity Error vs Digital Input Code Figure 4. Differential Linearity Error vs Digital Input Code Figure 5. Integral Linearity Error vs Temperature Figure 6. Differential Linearity Error vs Temperature Figure 7. Zero Code Error vs Temperature Figure 8. Positive Full-Scale Error vs Temperature

CODEV (V V ) V OUTDAC Register Buffer Registers SPI Interface Power On Reset REFPF DGND AVDD DAC DVDD REFNF REFPS REFNSAGNDVSS IOVDD R R RCM ROFS RFB Power Down Logic VCC SCLK SDIN SYNC SDO LDAC CLR ALARM DAC11001A, DAC91001, DAC81001 SLASEL0A – OCTOBER 2019– REVISED DECEMBER 2019 www.ti.com Product Folder Links: DAC11001A DAC91001 DAC81001 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

The 20-bit DAC11001A, 18-bit DAC91001, and 16-bit DAC81001 (DACx1001) are single-channel DACs. The unbuffered DAC output architecture is based on an R2R ladder that is designed to provide monotonicity over wide reference and temperature ranges (1-LSB DNL). This architecture provides a very low-noise (7 nV/√Hz) and fast-settling (1 µs) output. The DACx1001 also implement a deglitch circuit that enables low, code-independent glitch at the DAC output. This is extremely useful for creating ultra low harmonic distortion waveform generation. The DACx1001 requires external reference voltages on REFPF and REFNF pins. The output of the DAC ranges from VREFNF to VREFPF. See the Recommended Operating Conditions for VREFPF and VREFNF voltage ranges. The DACx1001 also includes precision matched gain setting pins (ROFS, RCM, and RFB), Using these pins and an external op amp, the DAC output can be scaled. The DACx1001 incorporate a power-on-reset circuit that makes sure that the DAC output powers up at zero scale, and remains at zero scale until a valid DAC command is issued. The DACx1001 use a 4-wire serial interface that operates at clock rates of up to 50 MHz.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Digital-to-Analog Converter Architecture

The DACx1001 provide 20-bit monotonic outputs using an R2R ladder architecture. The DAC output ranges between VREFNF and VREFPF based on the 20-bit DAC data, as described in Equation 1: where

CODE is the decimal equivalent of the DAC-DATA loaded to the DAC.
N is the bits of resolution; 20 for DAC1101A, 18 for DAC91001, 16 for DAC81001.
VREFPF, VREFNF is the reference voltage (positive and negative). (1)

8.3.2 External Reference

Conditions for VREFPF and VREFNF voltage ranges. VREFPF = 5 V and VREFNF = –5 V. Figure 44. Reference Drive Circuit Table 1. Reference Op Amp Options

8.3.3 Output Buffers

information. Table 2 shows the op amp options for the output drive circuit. Table 2. Output Op Amp Options

8.3.4 Internal Power-On Reset (POR)

Figure 45. Relevant Voltage Levels for the POR Circuit –1.8 V for approximately 1 ms.

DAC11001A, DAC91001, DAC81001 www.ti.com SLASEL0A – OCTOBER 2019– REVISED DECEMBER 2019 Product Folder Links: DAC11001A DAC91001 DAC81001 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated For the IOVDD supply, no internal POR occurs for nominal supply operation from 1.8 V (supply minimum) to 5.5 V (supply maximum). For IOVDD supply voltages between 1.5 V (undefined operation threshold) and 0.8 V (POR threshold), the internal POR circuit may or may not provide a reset over all temperature conditions. For an IOVDD supply less than 0.8 V (POR threshold), the internal POR resets as long as the supply voltage is less than 0.8 V for approximately 1 ms. In case the DVDD, AVDD, IOVDD, VCC, or VSS supply drops to a level where the internal POR signal is indeterminate, power cycle the device followed using a software reset.

8.3.5 Temperature Drift and Calibration

The DACx1001 includes a calibration circuit that significantly reduces the temperature drift on integrated and differential nonlinearities. By default, this feature is disabled. Enable the temperature calibration feature by writing 1 to the EN_TMP_CAL bit (address 02h, B23). After the EN_TMP_CAL bit is set, issue a calibration cycle by writing 1 to RCLTMP (address 04h, B8). At this point, the device enters a calibration cycle. Do not issue any DAC update command during this period. The device has the capability to indicate the end of calibration using two methods: 1. Read the status bit ALM (address 05h, B12) using SPI. 2. Issue an alarm on the ALARM pin by setting logic 0. To enable this feature, write 1 to ENALMP bit (address 02h, B12). After the calibration cycle completes, update the DAC code to observe the impact at the DAC output. If the environmental temperature changes after calibration, then recalibrate the device.

8.3.6 DAC Output Deglitch Circuit

The DACx1001 include a deglitch (track-and-hold) circuit at the output. This circuit is enabled by default. The deglitch circuit minimizes the code-to-code glitch at the DAC output at the expense of the DAC update rate. This circuit is disabled by writing 1 to DIS_TNH (bit 7, address 06h). Disable this circuit to enable faster update of the DAC output, but with higher code-to-code glitches.

8.4 Device Functional Modes

8.4.1 Fast-Settling Mode and THD

The DACx1001 R2R ladder and deglitch circuit reduce the harmonic distortion for waveform generation applications. The fast settling bit (FSET, bit 10, address 02h) is set to 1 by default, so that the DAC is configured for enhanced THD performance. The FSET bit can be reset to 0 using an SPI write to enable fast-settling mode. In this mode, the DAC deglitcher circuit can be configured using TNH_MASK (bits 19:18, address 02h). These bits disable the deglitch circuit for code changes specified in Table 7. These bits are only writable when FSET = 0 (fast settling enabled) and DIS_TNH = 0 (deglitch circuit enabled).

8.4.2 DAC Update Rate Mode

The DACx1001 maximum update rate can be configured up to 1 MHz by using UP_RATE (bits 6:4, address 06h). These bits change the hold timing of the deglitch circuit. The bits are set to a 0.5-MHz DAC update rate by default for enhanced THD performance. Changing the maximum update rate of the DAC impacts THD performance.

8.5 Programming

multiple devices for write operations. address bits B30 to B24. The next 20 bits are data. For all writes, data are clocked on the falling edge of SCLK. Figure 46. Serial Interface Write Bus Cycle: Standalone Mode Figure 47. Serial Interface Read Bus Cycle

8.5.1 Daisy-Chain Operation

For systems that contain several DACx1001 devices, the SDO pin is used to daisy-chain the devices together. register while the SYNC pin is kept low. The DAC is updated with the data on rising edge of SYNC pin. Figure 48. Serial Interface Daisy-Chain Write Cycle If more than 32 clock pulses are applied, the data ripple out of the shift register and appear on the SDO line. constructed. Each device in the system requires 32 clock pulses.

DAC11001A, DAC91001, DAC81001 www.ti.com SLASEL0A – OCTOBER 2019– REVISED DECEMBER 2019 Product Folder Links: DAC11001A DAC91001 DAC81001 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated Programming (continued) As a result, the total number of clock cycles must be equal to 32 × N, where N is the total number of devices in the daisy-chain. When the serial transfer to all devices is complete the SYNC signal is taken high. This action transfers the data from the SPI shift registers to the internal register of each device in the daisy-chain and prevents any further data from being clocked into the input shift register. The DACx1001 implement a bit that enables higher speeds for clocking out data from the SDO pin. Enable this feature by setting FSDO (bit 13, address 02h) to 1. See Timing Requirements: Read and Daisy-Chain Write, 2.7 V ≤ DVDD < 4.5 V and for more information.

8.5.2 CLR Pin Functionality and Software Clear

The CLR pin is an asynchronous input pin to the DAC. When activated, this level-sensitive pin clears the DAC buffers and DAC latches to the DAC-CLEAR-DATA bits (address 03h). The device exits clear mode on the SYNC rising edge of the next valid write to the device. If the CLR pin receives a logic 0 during a write sequence during normal operation, the clear mode is activated and the buffer and DAC registers are immediately cleared. The DAC registers can also be cleared using the SCLR bit (address 04h, B5); the contents are cleared at the rising edge of SYNC.

8.5.3 Output Update (Synchronous and Asynchronous)

The DACx1004 devices offer both a software and hardware simultaneous update and control function. The DAC double-buffered architecture has been designed so that new data can be entered for the DAC without disturbing the analog output. Data updates can be performed either in synchronous or in asynchronous mode, depending on the status of LDAC-MODE bit (address 02h, B14).

8.5.3.1 Synchronous Update

In synchronous mode (LDACMODE = 1), the LDAC pin is used as an active-low signal for simultaneous DAC updates. Data buffers must be loaded with the desired data before an LDAC low pulse. After an LDAC low pulse, the DAC is updated with the last contents of the corresponding data buffers. If the content of a data buffer is not changed, the DAC output remains unchanged after the LDAC pin is pulsed low.

8.5.3.2 Asynchronous Update

In asynchronous mode (LDACMODE = 0), data are updated with the rising edge of the SYNC (when daisy-chain mode is enabled, DSDO = 0), or at the 32nd falling edge of SCLK (When daisy-chain mode is disabled, DSDO = 1). For asynchronous updates, the LDAC pin is not required, and it must be connected to 0 V permanently.

8.5.4 Software Reset Mode

The DACx1001 implements a software reset feature. The software reset function uses the SRST bit (address 04h, B6). When this bit is set to 1, the device resets to the default state.

8.6 Register Map

Table 3. Register Map

Table 4. Access Type Codes

8.6.1 NOP Register (address = 00h) [reset = 0x000000h]

Figure 49. NOP Register Format Table 5. NOP Register Field Descriptions

31 Write W N/A Write when set to 0

8.6.2 DAC-DATA Register (address = 01h) [reset = 0x000000h]

Figure 50. DAC-DATA Register Format Table 6. DAC-DATA Register Field Descriptions

31 Read/Write R/W N/A Read when set to 1 or write when set to 0

MSB aligned straight binary format.

8.6.3 CONFIG1 Register (address = 02h) [reset = 004C80h for bits [23:0]]

Figure 51. CONFIG1 Register Format Table 7. CONFIG1 Register Field Descriptions

23 EN_TMP_CAL R/W 0h Enables and disables the temperature calibration feature

14 LDACMODE R/W 1 Synchronous or asynchronous mode select bit

13 FSDO R/W 0h Enable Fast SDO

12 ENALMP R/W 0h Enable ALARM pin to be pulled low, end of temperature calibration cycle

1 : Indicates end of temperature calibration cycle. ALARM pin pulled low.

11 DSDO R/W 1h Enable SDO (for readback and daisy-chain)

10 FSET R/W 1h Fast-settling vs enhanced THD mode

4 PDN R/W 0h Powers down and power up the DAC

8.6.4 DAC-CLEAR-DATA Register (address = 03h) [reset = 000000h for bits [23:0]]

Figure 52. DAC-CLEAR-DATA Register Format Table 8. DAC-CLEAR-DATA Register Field Descriptions

8.6.5 TRIGGER Register (address = 04h) [reset = 000000h for bits [23:0]]

Figure 53. TRIGGER Register Format Table 9. TRIGGER Register Field Descriptions

8 RCLTMP R/W 0h Trigger temperature recalibration DAC Codes

6 SRST R/W 0h Software reset

5 SCLR R/W 0h Software clear

8.6.6 STATUS Register (address = 05h) [reset = 000000h for bits [23:0]]

Figure 54. STATUS Register Format Table 10. STATUS Register Field Descriptions

31 Read/Write R N/A Read when set to 1 , read only

12 ALM R 0 Alarm indicator bit, This bit is not masked by ENALMP bit

8.6.7 CONFIG2 Register (address = 06h) [reset = 000040h for bits [23:0]]

Figure 55. CONFIG2 Register Format Table 11. CONFIG2 Register Field Descriptions

7 DIS_TNH R/W 0h Disable track and hold:

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.2 Typical Application

9.2.1 Source Measure Unit (SMU)

under-test (DUT). Figure 56 provides a simplified circuit diagram of the force-DAC in an SMU. Figure 56. Source Measure Unit

9.2.1.1 Design Requirements

Force voltage range: ±10 V
Force current range: ±20 mA

9.2.1.2 Detailed Design Procedure

external resistor is not shown in the drawing for simplicity. The gain resistor is not required for a gain of 1. Equation 2 shows the calculation of the voltage gain when switch SW is in position 1.

and R2 are 1-kΩ each. Equation 3 shows the calculation for the current gain when the switch is in the position 2. value for GI and a smaller resistance value for RSENSE in case the design requires a lower voltage headroom. reference buffers when driving the reference inputs of DACx1001. The values are obtained through simulation.

9.2.1.3 Application Curves

Figure 57. INL at ±10-V Output Figure 58. DNL at ±10-V Output

9.2.2 Battery Test Equipment (BTE)

Figure 59. Battery Test Equipment

9.2.2.1 Design Requirements

Output range: 0 V to 5 V
System level temperature drift: ±2 ppm/°C

9.2.2.2 Detailed Design Procedure

To get unipolar output from DACx1001, connect the negative reference input to ground as shown in Figure 59.

9.2.2.3 Application Curves

Figure 60. INL at 0-V to 5-V Output Figure 61. DNL at 0-V to 5-V Output

9.2.3 High-Precision Control Loop

control circuit, wherein the DACx1001 commands the set point and an analog loop controls the actuator. Figure 62. High-Precision Control Loop

9.2.3.1 Design Requirements

DNL: ±1 LSB max at 20-bits
Settling time: < 2 µs
Code-to-code Glltch: < 2 nV-s

9.2.3.2 Detailed Design Procedure

9.2.3.3 Application Curves

Figure 63. INL at ±5-V Output Figure 64. DNL at ±5-V Output

9.2.4 Arbitrary Waveform Generation (AWG)

AWG circuit using the DACx1001. Figure 65. Arbitrary Waveform Generation

9.2.4.1 Design Requirements

THD at 1 kHz: > –105 dB
Update rate: 100 kHz

9.2.4.2 Detailed Design Procedure

low-distortion amplifier for high-THD applications.

9.2.4.3 Application Curves

Figure 66. THD vs Frequency

9.3 System Examples

This section provides details on the digital interface and the embedded resistor configurations.

9.3.1 Interfacing to a Processor

ac-signal generation applications, the jitter in the LDAC signal contributes to signal-to-noise ratio (SNR). Processor. Typically, 33-Ω resistors work on printed circuit boards (PCBs) with a 50-Ω trace impedance. Figure 67. Interfacing to a Processor

9.3.2 Interfacing to a Low-Jitter LDAC Source

the SPI frame synchronously. Figure 68. Interfacing to an External LDAC Source

9.3.3 Embedded Resistor Configurations

R2R ladder. These resistors can be used in various configurations, as shown in the following subsections.

9.3.3.1 Minimizing Bias Current Mismatch

Figure 69. Minimizing Bias Current Mismatch Figure 70. 2x Gain Configuration

9.3.3.3 Generating Negative Reference

accurate negative reference voltage. Figure 71. Generating Negative Reference

9.4 What to Do and What Not to Do

9.4.1 What to Do

Follow recommended grounding, decoupling, and layout schemes for achieving best accuracy.
Use a low-jitter LDAC source for best ac performance.
Choose the appropriate amplifiers depending on the application requirements as explained in above sections.

9.4.2 What Not to Do

Do not apply the reference before the DAC power supplies are powered on.
Do not use the reference source directly with the DAC reference inputs without using buffers. or else the accuracy drastically degrades.

9.5 Initialization Set Up

The following text shows the pseudocode to get started with the DACx1001: //SPI Settings //Mode: Mode-1 (CPOL: 0, CPHA: 1) //CS Type: Active Low, Per Packet //Frame length: 32 //SYNTAX: WRITE <REGISTER (HEX ADDRESS>, <HEX DATA> //Select VREF, TnH mode (Good THD), LDAC mode and power-up the DAC WRITE CONFIG (0x02), 0x004C80 //Write zero code to the DAC WRITE DACDATA (0x01), 0x000000 //Write mid code to the DAC WRITE DACDATA (0x01), 0x7FFFF0 //Write full code to the DAC WRITE DACDATA (0x01), 0xFFFFF0

10 Power Supply Recommendations

Figure 72. Power and Signal Grounding a ground loop, otherwise. The resulting connection that avoids the ground loop is shown in Figure 73. Figure 73. Grounding Scheme When AGND is Load Ground

Filtering: Filter out noise and ripple from power supplies
Bypassing: Supply switching or load transient currents locally by avoiding trace inductances
Decoupling: Stop local transient currents from impacting other circuits To achieve these objectives, use the following 3-element scheme. Place a decoupling capacitor close to every power supply pin to provide the local current path for load and circuit switching transients. This capacitor must be referenced to the respective load ground for best load transient suppression. Use a 0.1-µF to 1-µF, X7R, multilayer ceramic capacitor (MLCC) for this purpose. For analog power supplies, a 10-Ω series resistor provides the best decoupling. For filtering the power supply noise and ripple, 10-µF capacitors work best when placed at the power entry point of the board. An example decoupling scheme is shown in Figure 76.

Figure 76. Power-Supply Decoupling

10.1 Power-Supply Sequencing

power supplies are ramped up. To avoid this condition, make sure to ramp AVDD before VSS.

11 Layout

11.1 Layout Guidelines

ground reference planes for the digital signal traces, especially for the SPI and LDAC signals.

11.2 Layout Example

Figure 77. Layout Example

12 Device and Documentation Support

12.1 Device Support

12.1.1 Development Support

12.2 Documentation Support

12.2.1 Related Documentation

Texas Instruments, BP-DAC11001EVM user's guide
Texas Instruments, Impact of Code-to-Code Glitch in Precision Applications application brief

12.3 Related Links

tools and software, and quick access to order now. Table 12. Related Links

12.4 Receiving Notification of Documentation Updates

changed. For change details, review the revision history included in any revised document.

12.5 Support Resources

from the experts. Search existing answers or ask your own question to get the quick design help you need. not necessarily reflect TI's views; see TI's Terms of Use.

12.6 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

12.7 Electrostatic Discharge Caution

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.8 Glossary

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 18-Dec-2019 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples DAC11001APFBR ACTIVE TQFP PFB 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU-DCC Level-3-260C-168 HR -40 to 125 DAC11001A DAC11001APFBT ACTIVE TQFP PFB 48 250 Green (RoHS & no Sb/Br) CU NIPDAU-DCC Level-3-260C-168 HR -40 to 125 DAC11001A DAC81001PFBT PREVIEW TQFP PFB 48 250 TBD Call TI Call TI -40 to 125 DAC91001PFBR PREVIEW TQFP PFB 48 1000 TBD Call TI Call TI -40 to 125 DAC91001PFBT PREVIEW TQFP PFB 48 250 TBD Call TI Call TI -40 to 125 PDAC11001APFBT ACTIVE TQFP PFB 48 250 TBD Call TI Call TI -40 to 125 PDAC91001PFBT ACTIVE TQFP PFB 48 250 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.

www.ti.com 18-Dec-2019 Addendum-Page 2 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 19-Dec-2019 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC11001APFBR TQFP PFB 48 1000 350.0 350.0 43.0 DAC11001APFBT TQFP PFB 48 250 213.0 191.0 55.0 PACKAGE MATERIALS INFORMATION www.ti.com 19-Dec-2019 Pack Materials-Page 2

MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 4073176/B 10/96 Gage Plane 0,13 NOM 0,25 0,45 0,75 Seating Plane 0,05 MIN 0,17 0,27 SQ 7,20 6,80 5,50 TYP SQ8,80 9,20 1,05 0,95 1,20 MAX 0,08 0,50 M0,08 0°–7° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026

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Product Information

DAC91001PFBT specifications and overview.

Summary

DACx1001 20-Bit, 18-Bit, and 16-Bit, Low-Noise, Ultra-Low Harmonic Distortion, Fast-Settling, High-Voltage Output, Digital-to-Analog Converters (DACs)

Description

DACx1001 20-Bit, 18-Bit, and 16-Bit, Low-Noise, Ultra-Low Harmonic Distortion, Fast-Settling, High-Voltage Output, Digital-to-Analog Converters (DACs)

Source title DAC91001PFBT Datasheet(PDF) - Texas Instruments

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