DAC904E

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Technical content

14-Bit, 165MSPS DIGITAL-TO-ANALOG CONVERTER

FEATURES

G SINGLE +5V OR +3V OPERATION G HIGH SFDR: 20MHz Output at 100MSPS: 64dBc G LOW GLITCH: 3pV-s G LOW POWER: 170mW at +5V G INTERNAL REFERENCE: Optional Ext. Reference Adjustable Full-Scale Range Multiplying Option

APPLICATIONS

G COMMUNICATION TRANSMIT CHANNELS WLL, Cellular Base Station Digital Microwave Links Cable Modems G WAVEFORM GENERATION Direct Digital Synthesis (DDS) Arbitrary Waveform Generation (ARB) G MEDICAL/ULTRASOUND G HIGH-SPEED INSTRUMENTATION AND CONTROL G VIDEO, DIGITAL TV

DESCRIPTION

The DAC904 is a high-speed, Digital-to-Analog Converter (DAC) offering a 14-bit resolution option within the family of high- performance converters. Featuring pin compatibility among fam- ily members, the DAC908, DAC900, and DAC902 provide a component selection option to an 8-, 10-, and 12-bit resolution, respectively. All models within this family of DACs support update rates in excess of 165MSPS with excellent dynamic performance, and are especially suited to fulfill the demands of a variety of applications. The advanced segmentation architecture of the DAC904 is optimized to provide a high Spurious-Free Dynamic Range (SFDR) for single-tone, as well as for multi-tone signals— essential when used for the transmit signal path of communica- tion systems. The DAC904 has a high impedance (200kΩ ) current output with a nominal range of 20mA and an output compliance of up to 1.25V. The differential outputs allow for both a differential or single-ended analog signal interface. The close matching of the current outputs ensures superior dynamic performance in the differential configuration, which can be implemented with a transformer. Utilizing a small geometry CMOS process, the monolithic DAC904 can be operated on a wide, single-supply range of +2.7V to +5.5V. Its low power consumption allows for use in portable and battery-operated systems. Further optimization can be realized by lowering the output current with the adjustable full-scale option. For noncontinuous operation of the DAC904, a power-down mode results in only 45mW of standby power. The DAC904 comes with an integrated 1.24V bandgap refer- ence and edge-triggered input latches, offering a complete converter solution. Both +3V and +5V CMOS logic families can be interfaced to the DAC904. The reference structure of the DAC904 allows for additional flexibility by utilizing the on-chip reference, or applying an external reference. The full-scale output current can be adjusted over a span of 2-20mA, with one external resistor, while main- taining the specified dynamic performance. The DAC904 is available in SO-28 and TSSOP-28 packages. Current Sources LSB Switches Segmented Switches +1.24V Ref. Latches 14-Bit Data Input D13...D0 DAC904 FSA BW +VD+VA AGND CLK DGND REF IN INT/EXT IOUT IOUT BYP PD DAC904 SBAS095C – MAY 2002 www.ti.com Copyright © 2002, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

SBAS095Cwww.ti.com

ELECTRICAL CHARACTERISTICS

At TA = full specified temperature range, +VA = +5V, +VD = +5V, differential transformer coupled output, 50Ω doubly terminated, unless otherwise specified. DAC904U, E PARAMETER CONDITIONS MIN TYP MAX UNITS RESOLUTION 14 Bits OUTPUT UPDATE RATE 2.7V to 3.3V 125 165 MSPS Output Update Rate (f CLOCK ) 4.5V to 5.5V 165 200 MSPS Full Specified Temperature Range, Operating Ambient, T A –40 +85 °C STATIC ACCURACY (1) TA = +25°C Differential Nonlinearity (DNL) f CLOCK = 25MSPS, fOUT = 1.0MHz ±2.5 LSB Integral Nonlinearity (INL) ±3.0 LSB DYNAMIC PERFORMANCE TA = +25°C Spurious-Free Dynamic Range (SFDR) To Nyquist fOUT = 1.0MHz, fCLOCK = 25MSPS 72 79 dBc fOUT = 2.1MHz, fCLOCK = 50MSPS 76 dBc fOUT = 5.04MHz, fCLOCK = 50MSPS 68 dBc fOUT = 5.04MHz, fCLOCK = 100MSPS 68 dBc fOUT = 20.2MHz, fCLOCK = 100MSPS 64 dBc fOUT = 25.3MHz, fCLOCK = 125MSPS 60 dBc fOUT = 41.5MHz, fCLOCK = 125MSPS 55 dBc fOUT = 27.4MHz, fCLOCK = 165MSPS 60 dBc fOUT = 54.8MHz, fCLOCK = 165MSPS 55 dBc Spurious-Free Dynamic Range within a Window fOUT = 5.04MHz, fCLOCK = 50MSPS 2MHz Span 82 dBc fOUT = 5.04MHz, fCLOCK = 100MSPS 4MHz Span 82 dBc Total Harmonic Distortion (THD) fOUT = 2.1MHz, fCLOCK = 50MSPS –75 dBc fOUT = 2.1MHz, fCLOCK = 125MSPS –74 dBc Two Tone fOUT1 = 13.5MHz, fOUT2 = 14.5MHz, fCLOCK = 100MSPS 63 dBc ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instru- ments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. DEMO BOARD PRODUCT ORDERING NUMBER COMMENT DAC904U DEM-DAC90xU Populated evaluation board without DAC. Order sample of desired DAC90x model separately. DAC904E DEM-DAC904E Populated evaluation board including the DAC904E. DEMO BOARD ORDERING INFORMATION ABSOLUTE MAXIMUM RATINGS SPECIFIED PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE-LEAD DESIGNATOR (1) RANGE MARKING NUMBER MEDIA, QUANTITY DAC904U SO-28 DW –40°C to +85°C DAC904U DAC904U Rails, 28 " """ " DAC904U/1K Tape and Reel, 1000 DAC904E TSSOP-28 PW –40°C to +85°C DAC904E DAC904E Rails, 52 " """ " DAC904E/2K5 Tape and Reel, 2500 NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com. PACKAGE/ORDERING INFORMATION

SBAS095C www.ti.com ELECTRICAL CHARACTERISTICS (Cont.) At TA = +25°C, +VA = +5V, +VD = +5V, differential transformer coupled output, 50Ω doubly terminated, unless otherwise specified. DAC904U, E PARAMETER CONDITIONS MIN TYP MAX UNITS DYNAMIC PERFORMANCE (Cont.) Output Settling Time(2) to 0.1% 30 ns Output Rise Time(2) 10% to 90% 2 ns Output Fall Time(2) 10% to 90% 2 ns Glitch Impulse 3p V - s DC-ACCURACY Full-Scale Output Range(3)(FSR) All Bits HIGH, I OUT 2.0 20.0 mA Output Compliance Range –1.0 +1.25 V Gain Error With Internal Reference –10 ±1 +10 %FSR Gain Error With External Reference –10 ±2 +10 %FSR Gain Drift With Internal Reference ±120 ppmFSR/ °C Offset Error With Internal Reference –0.025 +0.025 %FSR Offset Drift With Internal Reference ±0.1 ppmFSR/ °C Power-Supply Rejection, +VA –0.2 +0.2 %FSR/V Power-Supply Rejection, +VD –0.025 +0.025 %FSR/V Output Noise I OUT = 20mA, RLOAD = 50Ω 50 pA/ √Hz Output Resistance 200 k Ω Output Capacitance I OUT , IOUT to Ground 12 pF REFERENCE Reference Voltage +1.24 V Reference Tolerance ±10 % Reference Voltage Drift ±50 ppmFSR/ °C Reference Output Current 10 µA Reference Input Resistance 1M Ω Reference Input Compliance Range 0.1 1.25 V Reference Small-Signal Bandwidth (4) 1.3 MHz DIGITAL INPUTS Logic Coding Straight Binary Latch Command Rising Edge of Clock Logic HIGH Voltage, VIH +V D = +5V 3.5 5 V Logic LOW Voltage, VIL +V D = +5V 0 1.2 V Logic HIGH Voltage, VIH +V D = +3V 2 3 V Logic LOW Voltage, VIL +V D = +3V 0 0.8 V Logic HIGH Current, IIH(5) +V D = +5V ±20 µA Logic LOW Current, IIL +V D = +5V ±20 µA Input Capacitance 5p F POWER SUPPLY Supply Voltages Supply Current(6) IVA 24 30 mA IVA , Power-Down Mode 1.1 2 mA IVD 81 5 m A Power Dissipation +5V, I OUT = 20mA 170 230 mW +3V, IOUT = 2mA 50 mW Power Dissipation, Power-Down Mode 45 mW Thermal Resistance, θJA SO-28 75 °C/W TSSOP-28 50 °C/W NOTES: (1) At output IOUT , while driving a virtual ground. (2) Measured single-ended into 50Ω Load. (3) Nominal full-scale output current is 32x IREF ; see Application Section for details. (4) Reference bandwidth depends on size of external capacitor at the BW pin and signal level. (5) Typically 45µA for the PD pin, which has an internal pull-down resistor. (6) Measured at fCLOCK = 50MSPS and fOUT = 1.0MHz.

SBAS095Cwww.ti.com Current Sources LSB Switches Segmented MSB Switches +1.24V Ref. Latches 14-Bit Data Input DAC904 FSA BW +VD+VA R SET AGND NOTE: (1) Optional components. CLK DGND REF IN 0.1µF INT/EXT IOUT IOUT BYP PD 20pF(1) 50Ω 50Ω 20pF(1) 1:1 VOUT 0.1µF 0.1µF(1) +5V +5V Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 CLK D DGND NC A BYP I OUT IOUT AGND BW FSA REF IN INT/EXT PD DAC904 PIN DESIGNATOR DESCRIPTION

1 Bit 1 Data Bit 1 (D13), MSB

2 Bit 2 Data Bit 2 (D12)

3 Bit 3 Data Bit 3 (D11)

4 Bit 4 Data Bit 4 (D10)

5 Bit 5 Data Bit 5 (D9)

6 Bit 6 Data Bit 6 (D8)

7 Bit 7 Data Bit 7 (D7)

8 Bit 8 Data Bit 8 (D6)

9 Bit 9 Data Bit 9 (D5)

10 Bit 10 Data Bit 10 (D4)

11 Bit 11 Data Bit 11 (D3)

12 Bit 12 Data Bit 12 (D2)

13 Bit 13 Data Bit 13 (D1)

14 Bit 14 Data Bit 14 (D0), LSB

15 PD Power Down, Control Input; Active

HIGH. Contains internal pull-down circuit; may be left unconnected if not used.

16 INT/EXT Reference Select Pin; Internal ( = 0) or

External ( = 1) Reference Operation 17 REF IN Reference Input/Ouput. See Applications section for further details.

18 FSA Full-Scale Output Adjust

19 BW Bandwidth/Noise Reduction Pin:

Bypass with 0.1µF to +VA for Optimum Performance. (Optional)

20 AGND Analog Ground

OUT Complementary DAC Current Output

22 I OUT DAC Current Output

23 BYP Bypass Node: Use 0.1 µF to AGND 24 +V A Analog Supply Voltage, 2.7V to 5.5V

25 NC No Internal Connection

26 DGND Digital Ground

D Digital Supply Voltage, 2.7V to 5.5V

28 CLK Clock Input

PIN DESCRIPTIONSPIN CONFIGURATION Top View SO, TSSOP TYPICAL CONNECTION CIRCUIT

SBAS095C www.ti.com TIMING DIAGRAM t2 t1 tS tH tSETtPD CLOCK D13 D0 Iout or Iout Data Changes Stable Valid Data Data Changes SYMBOL DESCRIPTION MIN TYP MAX UNITS t1 Clock Pulse HIGH Time 3 ns t2 Clock Pulse LOW Time 3 ns tS Data Setup Time 1.0 ns tH Data Hold Time 1.5 ns tPD Propagation Delay Time 1 ns tSET Output Settling Time to 0.1% 30 ns

SBAS095Cwww.ti.com TYPICAL CHARACTERISTICS: V D = VA = +5V At TA = +25°C, Differential IOUT = 20mA, 50Ω double-terminated load, SFDR up to Nyquist, unless otherwise specified. DAC Code TYPICAL DNL Error (LSBs) –10 10k 12k 14k 16k 16384 TYPICAL INL Error (LSBs) –10 DAC Code 10k 12k 14k 16k 16384 SFDR vs fOUT AT 25MSPS Frequency (MHz) SFDR (dBc) 0dBFS –6dBFS SFDR vs fOUT AT 50MSPS Frequency (MHz) SFDR (dBc) –6dBFS 0dBFS SFDR vs fOUT AT 100MSPS Frequency (MHz) SFDR (dBc) 0dBFS –6dBFS SFDR vs fOUT AT 125MSPS Frequency (MHz) SFDR (dBc) 0dBFS –6dBFS

SBAS095C www.ti.com TYPICAL CHARACTERISTICS: V D = VA = +5V (Cont.) At TA = +25°C, Differential IOUT = 20mA, 50Ω double-terminated load, SFDR up to Nyquist, unless otherwise specified. SFDR vs fOUT AT 165MSPS Frequency (MHz) SFDR (dBc) –6dBFS 0dBFS SFDR vs fOUT AT 200MSPS Frequency (MHz) SFDR (dBc) –6dBFS 0dBFS DIFFERENTIAL vs SINGLE-ENDED SFDR vs fOUT AT 100MSPS Frequency (MHz) SFDR (dBc) Diff (0dBFS) IOUT (–6dBFS) IOUT (0dBFS) Diff (–6dBFS) X X X X X X X SFDR vs IOUTFS and fOUT AT 100MSPS, 0dBFS IOUTFS (mA) SFDR (dBc) 51 0 2 02 X X X X 2.1MHz 20.2MHz 10.1MHz 5.04MHz 40.4MHz *** * THD vs fCLOCK AT fOUT = 2.1MHz fCLOCK (MSPS) THD (dBc) –70 –75 –80 –85 –90 –95 –100 25 50 100 125 1500 2HD 4HD 3HD X X X X SFDR vs TEMPERATURE AT 100MSPS, 0dBFS Temperature (°C) SFDR (dBc) –20 0 25 70 50 85–40 2.1MHz 10.1MHz 40.4MHz XXXXXXX

SBAS095Cwww.ti.com TYPICAL CHARACTERISTICS: V D = VA = +5V (Cont.) At TA = +25°C, Differential IOUT = 20mA, 50Ω double-terminated load, SFDR up to Nyquist, unless otherwise specified. DUAL-TONE OUTPUT SPECTRUM Frequency (MHz) Magnitude (dBm) –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 5 1 01 52 02 53 03 54 04 55 0 fCLOCK = 100MSPS fOUT1 = 13.5MHz fOUT2 = 14.5MHz SFDR = 63dBc Amplitude = 0dBFS FOUR-TONE OUTPUT SPECTRUM Frequency (MHz) Magnitude (dBm) –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 51 0 1 5 2 0 2 5 fCLOCK = 50MSPS fOUT1 = 6.25MHz fOUT2 = 6.75MHz fOUT3 = 7.25MHz fOUT4 = 7.75MHz SFDR = 66dBc Amplitude = 0dBFS SFDR vs fOUT AT 25MSPS Frequency (MHz) SFDR (dBc) 0dBFS –6dBFS SFDR vs fOUT AT 50MSPS Frequency (MHz) SFDR (dBc) –6dBFS 0dBFS SFDR vs fOUT AT 100MSPS Frequency (MHz) SFDR (dBc) –6dBFS 0dBFS SFDR vs fOUT AT 125MSPS Frequency (MHz) SFDR (dBc) 0dBFS –6dBFS TYPICAL CHARACTERISTICS: V D = VA = +3V At TA = +25°C, Differential IOUT = 20mA, 50Ω double-terminated load, SFDR up to Nyquist, unless otherwise specified.

SBAS095C www.ti.com SFDR vs fOUT AT 165MSPS Frequency (MHz) SFDR (dBc) –6dBFS 0dBFS DIFFERENTIAL vs SINGLE-ENDED SFDR vs fOUT AT 100MSPS Frequency (MHz) SFDR (dBc) Diff (0dBFS) IOUT (–6dBFS) IOUT (0dBFS) Diff (–6dBFS) TYPICAL CHARACTERISTICS: V D = VA = +3V (Cont.) At TA = +25°C, Differential IOUT = 20mA, 50Ω double-terminated load, SFDR up to Nyquist, unless otherwise specified. IOUTFS (mA) SFDR (dBc) 51 0 2 02 X X *** * X X SFDR vs IOUTFS and fOUT AT 100MSPS 2.1MHz 5.04MHz 20.2MHz 10.1MHz 40.4MHz THD vs fCLOCK AT fOUT = 2.1MHz fCLOCK (MSPS) THD (dBc) –70 –75 –80 –85 –90 –95 –100 25 50 100 125 1500 2HD 4HD 3HD SFDR vs TEMPERATURE AT 100MSPS, 0dBFS Temperature (°C) SFDR (dBc) –20 0 25 70 50 85–40 2.1MHz 10.1MHz 40.4MHz XX XX XX X DUAL-TONE OUTPUT SPECTRUM Frequency (MHz) Magnitude (dBm) –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 5 1 01 52 02 53 03 54 04 55 0 fCLOCK = 100MSPS fOUT1 = 13.5MHz fOUT2 = 14.5MHz SFDR = 64dBc Amplitude = 0dBFS

SBAS095Cwww.ti.com

APPLICATION INFORMATION

The architecture of the DAC904 uses the current steering technique to enable fast switching and a high update rate. The core element within the monolithic DAC is an array of seg- mented current sources that are designed to deliver a full-scale output current of up to 20mA, as shown in Figure 1. An internal decoder addresses the differential current switches each time the DAC is updated and a corresponding output current is formed by steering all currents to either output summing node, I OUT or IOUT . The complementary outputs deliver a differential output signal that improves the dynamic performance through reduction of even-order harmonics, common-mode signals (noise), and double the peak-to-peak output signal swing by a factor of two, compared to single-ended operation. FIGURE 1. Functional Block Diagram of the DAC904. NOTE: Supply bypassing not shown. NOTE: (1) Optional. At TA = +25°C, Differential IOUT = 20mA, 50Ω double-terminated load, SFDR up to Nyquist, unless otherwise specified. output impedance of greater than 200kΩ .

FIGURE 8. External Reference Configuration.FIGURE 7. Internal Reference Configuration. be chosen within their specified limits. operate over a supply range of 2.7V to 5.5V. signal layers by ground layers, etc. verter output can be adjusted from 20mA down to 2mA. output compliance voltage limitations for a given load condition. ability of dynamic gain control.

SBAS095C www.ti.com The DAC904 uses separate pins for its analog and digital supply and ground connections. The placement of the decou- pling capacitor should be such that the analog supply (+V is bypassed to the analog ground (AGND), and the digital supply bypassed to the digital ground (DGND). In most cases 0.1µF ceramic chip capacitors at each supply pin are ad- equate to provide a low impedance decoupling path. Keep in mind that their effectiveness largely depends on the proximity to the individual supply and ground pins. Therefore, they should be located as close as physically possible to those device leads. Whenever possible, the capacitors should be located immediately under each pair of supply/ground pins on the reverse side of the pc-board. This layout approach will minimize the parasitic inductance of component leads and pcb runs. Further supply decoupling with surface mount tantalum ca- pacitors (1µF to 4.7µF) may be added as needed in proximity of the converter. Low noise is required for all supply and ground connections to the DAC904. It is recommended to use a multilayer pc- board utilizing separate power and ground planes. Mixed signal designs require particular attention to the routing of the different supply currents and signal traces. Generally, analog supply and ground planes should only extend into analog signal areas, such as the DAC output signal and the refer- ence signal. Digital supply and ground planes must be confined to areas covering digital circuitry, including the digital input lines connecting to the converter, as well as the clock signal. The analog and digital ground planes should be joined together at one point underneath the DAC. This can be realized with a short track of approximately 1/8 inch (3mm). The power to the DAC904 should be provided through the use of wide pcb runs or planes. Wide runs will present a lower trace impedance, further optimizing the supply decou- pling. The analog and digital supplies for the converter should only be connected together at the supply connector of the pc-board. In the case of only one supply voltage being available to power the DAC, ferrite beads along with bypass capacitors may be used to create an LC filter. This will generate a low-noise analog supply voltage that can then be connected to the +V A supply pin of the DAC904. While designing the layout, it is important to keep the analog signal traces separate from any digital line, in order to prevent noise coupling onto the analog signal path.

www.ti.com 25-Feb-2012 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) DAC904E ACTIVE TSSOP PW 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR DAC904E/2K5 ACTIVE TSSOP PW 28 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR DAC904E/2K5G4 ACTIVE TSSOP PW 28 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR DAC904EG4 ACTIVE TSSOP PW 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR DAC904U ACTIVE SOIC DW 28 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR DAC904U/1K ACTIVE SOIC DW 28 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR DAC904U/1KG4 ACTIVE SOIC DW 28 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR DAC904UG4 ACTIVE SOIC DW 28 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

www.ti.com 25-Feb-2012 Addendum-Page 2 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC904E/2K5 TSSOP PW 28 2500 367.0 367.0 38.0 DAC904U/1K SOIC DW 28 1000 367.0 367.0 55.0 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 2

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