DAC902E1G4.B

DAC902 TI | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 25

Technical content

12-Bit, 165MSPS DIGITAL-TO-ANALOG CONVERTER

FEATURES

G SINGLE +5V OR +3V OPERATION G HIGH SFDR: 5MHz Output at 100MSPS: 67dBc G LOW GLITCH: 3pV-s G LOW POWER: 170mW at +5V G INTERNAL REFERENCE: Optional Ext. Reference Adjustable Full-Scale Range Multiplying Option

APPLICATIONS

G COMMUNICATION TRANSMIT CHANNELS: WLL, Cellular Base Station Digital Microwave Links Cable Modems G WAVEFORM GENERATION: Direct Digital Synthesis (DDS) Arbitrary Waveform Generation (ARB) G MEDICAL/ULTRASOUND G HIGH-SPEED INSTRUMENTATION AND CON- TROL G VIDEO, DIGITAL TV

DESCRIPTION

The DAC902 is a high-speed, Digital-to-Analog Converter (DAC) offering a 12-bit resolution option within the SpeedPlus Family of high-performance converters. Featuring pin compatibility among family members, the DAC908, DAC900, and DAC904 provide a component selection option to an 8-, 10-, and 14-bit resolution, respectively. All models within this family of DACs support update rates in excess of 165MSPS with excellent dynamic performance, and are especially suited to fulfill the demands of a variety of applications. The advanced segmentation architecture of the DAC902 is opti- mized to provide a high Spurious-Free Dynamic Range (SFDR) for single-tone, as well as for multi-tone signals—essential when used for the transmit signal path of communication systems. The DAC902 has a high impedance (200kΩ ) current output with a nominal range of 20mA and an output compliance of up to 1.25V. The differential outputs allow for both a differential or single- ended analog signal interface. The close matching of the current outputs ensures superior dynamic performance in the differential configuration, which can be implemented with a transformer. Utilizing a small geometry CMOS process, the monolithic DAC902 can be operated on a wide, single-supply range of +2.7V to +5.5V. Its low power consumption allows for use in portable and battery- operated systems. Further optimization can be realized by lowering the output current with the adjustable full-scale option. For noncontinuous operation of the DAC902, a power-down mode results in only 45mW of standby power. The DAC902 comes with an integrated 1.24V bandgap reference and edge-triggered input latches, offering a complete converter solution. Both +3V and +5V CMOS logic families can be inter- faced to the DAC902. The reference structure of the DAC902 allows for additional flexibility by utilizing the on-chip reference, or applying an exter- nal reference. The full-scale output current can be adjusted over a span of 2mA to 20mA, with one external resistor, while maintain- ing the specified dynamic performance. The DAC902 is available in the SO-28 and TSSOP-28 packages. Current Sources LSB Switches Segmented Switches +1.24V Ref. Latches 12-Bit Data Input D11...D0 DAC902 FSA BW +VD+VA AGND CLK DGND REF IN INT/EXT IOUT IOUT BYP PD DAC902 SBAS094B – MAY 2002 www.ti.com Copyright © 2002, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TM PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

ELECTRICAL CHARACTERISTICS

At TA = full specified temperature range, +VA = +5V, +VD = +5V, differential transformer coupled output, 50Ω doubly terminated, unless otherwise specified. DAC902U/E PARAMETER CONDITIONS MIN TYP MAX UNITS RESOLUTION 12 Bits OUTPUT UPDATE RATE 2.7V to 3.3V 125 165 MSPS Output Update Rate (f CLOCK ) 4.5V to 5.5V 165 200 MSPS Full Specified Temperature Range, Operating Ambient, T A –40 +85 °C STATIC ACCURACY (1) TA = +25°C Differential Nonlinearity (DNL) f CLOCK = 25MSPS, fOUT = 1.0MHz –1.75 ±0.5 +1.75 LSB Integral Nonlinearity (INL) –2.5 ±1.0 +2.5 LSB DYNAMIC PERFORMANCE TA = +25°C Spurious-Free Dynamic Range (SFDR) To Nyquist fOUT = 1MHz, fCLOCK = 25MSPS 71 77 dBc fOUT = 2.1MHz, fCLOCK = 50MSPS 75 dBc fOUT = 5.04MHz, fCLOCK = 50MSPS 68 dBc fOUT = 5.04MHz, fCLOCK = 100MSPS 67 dBc fOUT = 20.2MHz, fCLOCK = 100MSPS 61 dBc fOUT = 25.3MHz, fCLOCK = 125MSPS 61 dBc fOUT = 41.5MHz, fCLOCK = 125MSPS 57 dBc fOUT = 27.4MHz, fCLOCK = 165MSPS 60 dBc fOUT = 54.8MHz, fCLOCK = 165MSPS 53 dBc Spurious-Free Dynamic Range within a Window fOUT = 5.04MHz, fCLOCK = 50MSPS 2MHz Span 80 dBc fOUT = 5.04MHz, fCLOCK = 100MSPS 4MHz Span 80 dBc Total Harmonic Distortion (THD) fOUT = 2.1MHz, fCLOCK = 50MSPS –74 dBc fOUT = 2.1MHz, fCLOCK = 125MSPS –75 dBc Two Tone fOUT1 = 13.5MHz, fOUT2 = 14.5MHz, fCLOCK = 100MSPS 64 dBc ABSOLUTE MAXIMUM RATINGS PACKAGE SPECIFIED DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE NUMBER RANGE MARKING NUMBER (1) MEDIA DAC902U SO-28 217 –40°C to +85°C DAC902U DAC902U Rails "" " " " DAC902U/1K Tape and Reel DAC902E TSSOP-28 360 –40°C to +85°C DAC902E DAC902E Rails "" " " " DAC902E/2K5 Tape and Reel NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of “DAC902E/2K5 ” will get a single 2500-piece Tape and Reel. PACKAGE/ORDERING INFORMATION DEMO BOARD PRODUCT ORDERING NUMBER COMMENT DAC902U DEM-DAC90xU Populated evaluation board without the DAC. Order sample of desired DAC90x model separately. DAC902E DEM-DAC902E Populated evaluation board including the DAC902E. DEMO BOARD ORDERING INFORMATION ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instru- ments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PARAMETER CONDITIONS MIN TYP MAX UNITS ELECTRICAL CHARACTERISTICS (Cont.) At TA = full specified temperature range, +VA = +5V, +VD = +5V, differential transformer coupled output, 50Ω doubly terminated, unless otherwise specified. DYNAMIC PERFORMANCE (Cont.) Output Settling Time(2) to 0.1% 30 ns Output Rise Time(2) 10% to 90% 2 ns Output Fall Time(2) 10% to 90% 2 ns Glitch Impulse 3p V - s DC-ACCURACY Full-Scale Output Range(3)(FSR) All Bits High, I OUT 2.0 20.0 mA Output Compliance Range –1.0 +1.25 V Gain Error With Internal Reference –10 ±1 +10 %FSR Gain Error With External Reference –10 ±2 +10 %FSR Gain Drift With Internal Reference ±120 ppmFSR/ °C Offset Error With Internal Reference –0.025 +0.025 %FSR Offset Drift With Internal Reference ±0.1 ppmFSR/ °C Power-Supply Rejection, +VA –0.2 +0.2 %FSR/V Power-Supply Rejection, +VD –0.025 +0.025 %FSR/V Output Noise I OUT = 20mA, RLOAD = 50Ω 50 pA/ √Hz Output Resistance 200 k Ω Output Capacitance I OUT , IOUT to Ground 12 pF REFERENCE Reference Voltage +1.24 V Reference Tolerance ±5% Reference Voltage Drift ±50 ppmFSR/ °C Reference Output Current 10 µA Reference Input Resistance 1M Ω Reference Input Compliance Range 0.1 1.25 V Reference Small-Signal Bandwidth (4) 1.3 MHz DIGITAL INPUTS Logic Coding Straight Binary Latch Command Rising Edge of Clock Logic High Voltage, VIH +V D = +5V 3.5 5 V Logic Low Voltage, VIL +V D = +5V 0 1.2 V Logic High Voltage, VIH +V D = +3V 2 3 V Logic Low Voltage, VIL +V D = +3V 0 0.8 V Logic High Current, IIH(5) +V D = +5V ±20 µA Logic Low Current, IIL +V D = +5V ±20 µA Input Capacitance 5p F POWER SUPPLY Supply Voltages Supply Current(6) IVA 24 30 mA IVA , Power-Down Mode 1.1 2 mA IVD 81 5 m A Power Dissipation +5V, I OUT = 20mA 170 230 mW +3V, IOUT = 2mA 50 mW Power Dissipation, Power-Down Mode 45 mW Thermal Resistance, θJA SO-28 75 °C/W TSSOP-28 50 °C/W NOTES: (1) At output IOUT , while driving a virtual ground. (2) Measured single-ended into 50Ω Load. (3) Nominal full-scale output current is 32 • IREF ; see Application Section for details. (4) Reference bandwidth depends on size of external capacitor at the BW pin and signal level. (5) Typically 45µA for the PD pin, which has an internal pull-down resistor. (6) Measured at fCLOCK = 50MSPS and fOUT = 1.0MHz.

PIN DESIGNATOR DESCRIPTION

1 Bit 1 Data Bit 1 (D11), MSB

2 Bit 2 Data Bit 2 (D10)

3 Bit 3 Data Bit 3 (D9)

4 Bit 4 Data Bit 4 (D8)

5 Bit 5 Data Bit 5 (D7)

6 Bit 6 Data Bit 6 (D6)

7 Bit 7 Data Bit 7 (D5)

8 Bit 8 Data Bit 8 (D4)

9 Bit 9 Data Bit 9 (D3)

10 Bit 10 Data Bit 10 (D2)

11 Bit 11 Data Bit 11 (D1)

12 Bit 12 Data Bit 12 (D0), LSB

13 NC No Connection

14 NC No Connection

15 PD Power Down, Control Input; Active

HIGH. Contains internal pull-down circuit; may be left unconnected if not used.

16 INT/EXT Reference Select Pin; Internal ( = 0) or

External ( = 1) Reference Operation. 17 REF IN Reference Input/Ouput. See Applica- tions section for further details.

18 FSA Full-Scale Output Adjust

19 BW Bandwidth/Noise Reduction Pin:

Bypass with 0.1µF to +VA for Optimum Performance.

20 AGND Analog Ground

21 I OUT Complementary DAC Current Output

22 I OUT DAC Current Output

23 BYP Bypass Node: Use 0.1 µF to AGND 24 +V A Analog Supply Voltage, 2.7V to 5.5V

25 NC No Connection

26 DGND Digital Ground

D Digital Supply Voltage, 2.7V to 5.5V

28 CLK Clock Input

PIN DESCRIPTIONSPIN CONFIGURATION Top View SO, TSSOP TYPICAL CONNECTION CIRCUIT Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 NC NC CLK D DGND NC A BYP I OUT IOUT AGND BW FSA REF IN INT/EXT PD DAC902 Current Sources LSB Switches Segmented MSB Switches +1.24V Ref. Latches 12-Bit Data Input DAC902 FSA BW +VD+VA R SET AGND CLK DGND REF IN 0.1µF INT/EXT IOUT IOUT BYP PD 20pF 50Ω 50Ω 20pF 1:1 0.1µF 0.1µF +5V +5V

SYMBOL DESCRIPTION MIN TYP MAX UNITS t1 Clock Pulse HIGH Time 3.0 ns t2 Clock Pulse LOW Time 3.0 ns tS Data Setup Time 1.0 ns tH Data Hold Time 1.5 ns tPD Propagation Delay Time 1 ns tSET Output Settling Time to 0.1% 30.0 ns t2 t1 tS tH tSETtPD CLOCK D13 D0 Iout or Iout Data Changes Stable Valid Data Data Changes

TYPICAL CHARACTERISTICS: V D = VA = +5V At TA = +25°C, differential transformer coupled output, 50Ω doubly terminated, and SFDR up to Nyquist, unless otherwise noted. SFDR vs fOUT AT 25MSPS Frequency (MHz) SFDR (dBc) 0dBFS –6dBFS SFDR vs fOUT AT 50MSPS Frequency (MHz) SFDR (dBc) –6dBFS 0dBFS SFDR vs fOUT AT 100MSPS Frequency (MHz) SFDR (dBc) 0dBFS –6dBFS SFDR vs fOUT AT 125MSPS Frequency (MHz) SFDR (dBc) 0dBFS –6dBFS DAC Code TYPICAL DNL Error (LSBs) 2.5 2.0 1.5 1.0 0.5 –0.5 –1.0 –1.5 –2.0 –2.5 500 1000 1500 2000 2500 3000 3500 4000 4096 DAC Code TYPICAL INL Error (LSBs) 2.5 2.0 1.5 1.0 0.5 –0.5 –1.0 –1.5 –2.0 –2.5 500 1000 1500 2000 2500 3000 3500 4000 4096

TYPICAL CHARACTERISTICS: V D = VA = +5V (Cont.) At TA = +25°C, differential transformer coupled output, 50Ω doubly terminated, and SFDR up to Nyquist, unless otherwise noted. SFDR vs TEMPERATURE AT 100MSPS, 0dBFS Temperature (°C) SFDR (dBc) –20 0 25 70 50 85–40 2.1MHz 10.1MHz 40.4MHz XXXXXXX SFDR vs IOUTFS and fOUT AT 100MSPS, 0dBFS IOUTFS (mA) SFDR (dBc) 51 0 2 02 X X X X 2.1MHz 20.2MHz 10.1MHz 40.4MHz DIFFERENTIAL vs SINGLE-ENDED SFDR vs fOUT AT 100MSPS Frequency (MHz) SFDR (dBc) Diff (0dBFS) IOUT (–6dBFS) IOUT (0dBFS) Diff (–6dBFS) X X X X X X X SFDR vs fOUT AT 200MSPS Frequency (MHz) SFDR (dBc) –6dBFS 0dBFS SFDR vs fOUT AT 165MSPS Frequency (MHz) SFDR (dBc) –6dBFS 0dBFS THD vs fCLOCK AT fOUT = 2.1MHz fCLOCK (MSPS) THD (dBc) –70 –75 –80 –85 –90 –95 –100 25 50 100 125 1500 2HD 4HD 3HD X X X X

TYPICAL CHARACTERISTICS: V D = VA = +5V (Cont.) At TA = +25°C, differential transformer coupled output, 50Ω doubly terminated, and SFDR up to Nyquist, unless otherwise noted. FOUR-TONE OUTPUT SPECTRUM Frequency (MHz) Magnitude (dBm) –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 51 0 1 5 2 0 2 5 fCLOCK = 50MSPS fOUT1 = 6.25MHz fOUT2 = 6.75MHz fOUT3 = 7.25MHz fOUT4 = 7.75MHz SFDR = 66dBc Amplitude = 0dBFS DUAL-TONE OUTPUT SPECTRUM Frequency (MHz) Magnitude (dBm) –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 5 1 01 52 02 53 03 54 04 55 0 fCLOCK = 100MSPS fOUT1 = 13.5MHz fOUT2 = 14.5MHz SFDR = 64dBc Amplitude = 0dBFS SINGLE-TONE OUTPUT SPECTRUM Frequency (MHz) Magnitude (dBm) –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 5 1 01 52 02 53 03 54 04 55 0 fCLOCK = 100MSPS fOUT = 2.1MHz SFDR = 74dBc Amplitude = 0dBFS

TYPICAL CHARACTERISTICS: V D = VA = +3V At TA = +25°C, differential transformer coupled output, 50Ω doubly terminated, and SFDR up to Nyquist, unless otherwise noted. DIFFERENTIAL vs SINGLE-ENDED SFDR vs fOUT AT 100MSPS Frequency (MHz) SFDR (dBc) Diff (0dBFS) IOUT (–6dBFS) IOUT (0dBFS) Diff (–6dBFS) SFDR vs fOUT AT 165MSPS Frequency (MHz) SFDR (dBc) –6dBFS 0dBFS SFDR vs fOUT AT 125MSPS Frequency (MHz) SFDR (dBc) 0dBFS –6dBFS SFDR vs fOUT AT 100MSPS Frequency (MHz) SFDR (dBc) –6dBFS 0dBFS SFDR vs fOUT AT 50MSPS Frequency (MHz) SFDR (dBc) –6dBFS 0dBFS SFDR vs fOUT AT 25MSPS Frequency (MHz) SFDR (dBc) 0dBFS –6dBFS

TYPICAL CHARACTERISTICS: V D = VA = +3V (Cont.) At TA = +25°C, differential transformer coupled output, 50Ω doubly terminated, and SFDR up to Nyquist, unless otherwise noted. FOUR-TONE OUTPUT SPECTRUM Frequency (MHz) Magnitude (dBm) –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 51 0 1 5 2 0 2 5 fCLOCK = 50MSPS fOUT1 = 6.25MHz fOUT2 = 6.75MHz fOUT3 = 7.25MHz fOUT4 = 7.75MHz SFDR = 66dBc Amplitude = 0dBFS DUAL-TONE OUTPUT SPECTRUM Frequency (MHz) Magnitude (dBm) –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 5 1 01 52 02 53 03 54 04 55 0 fCLOCK = 100MSPS fOUT1 = 13.5MHz fOUT2 = 14.5MHz SFDR = 68dBc Amplitude = 0dBFS SINGLE-TONE OUTPUT SPECTRUM Frequency (MHz) Magnitude (dBm) –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 5 1 01 52 02 53 03 54 04 55 0 fCLOCK = 100MSPS fOUT = 2.1MHz SFDR = 76dBc Amplitude = 0dBFS SFDR vs TEMPERATURE AT 100MSPS, 0dBFS Temperature (°C) SFDR (dBc) –20 0 25 70 50 85–40 2.1MHz 10.1MHz 40.4MHz X X XXXXX THD vs fCLOCK AT fOUT = 2.1MHz fCLOCK (MSPS) THD (dBc) –70 –75 –80 –85 –90 –95 –100 25 50 100 125 1500 2HD 4HD 3HD IOUTFS (mA) SFDR (dBc) 51 0 2 02 X X X X SFDR vs IOUTFS and fOUT AT 100MSPS, 0dBFS 2.1MHz 20.2MHz 10.1MHz 40.4MHz

APPLICATION INFORMATION

The architecture of the DAC902 uses the current steering technique to enable fast switching and a high update rate. The core element within the monolithic DAC is an array of segmented current sources that are designed to deliver a full- scale output current of up to 20mA, as shown in Figure 1. An internal decoder addresses the differential current switches each time the DAC is updated and a corresponding output current is formed by steering all currents to either output summing node, I OUT or IOUT . The complementary outputs deliver a differential output signal that improves the dynamic performance through reduction of even-order harmonics, common-mode signals (noise), and double the peak-to-peak output signal swing by a factor of two, compared to single- ended operation. The segmented architecture results in a significant reduc- tion of the glitch energy, improves the dynamic perfor- mance (SFDR), and DNL. The current outputs maintain a very high output impedance of greater than 200kΩ . The full-scale output current is determined by the ratio of the internal reference voltage (1.24V) and an external resistor, R SET . The resulting IREF is internally multiplied by a factor of 32 to produce an effective DAC output current that can range from 2mA to 20mA, depending on the value of R SET . The DAC902 is split into a digital and an analog portion, each of which is powered through its own supply pin. The digital section includes edge-triggered input latches and the decoder logic, while the analog section comprises the cur- rent source array with its associated switches, and the reference circuitry. DAC TRANSFER FUNCTION The total output current, I OUTFS , of the DAC902 is the summation of the two complementary output currents: IOUTFS = IOUT + IOUT (1) The individual output currents depend on the DAC code and can be expressed as: IOUT = IOUTFS • (Code/4096) (2) IOUT = IOUTFS • (4095 – Code/4096) (3) where ‘Code’ is the decimal representation of the DAC data input word. Additionally, IOUTFS is a function of the refer- ence current IREF , which is determined by the reference voltage and the external setting resistor, RSET . IOUTFS = 32 • IREF = 32 • VREF /RSET (4) In most cases the complementary outputs will drive resistive loads or a terminated transformer. A signal voltage will develop at each output according to: V OUT = IOUT • RLOAD (5) V OUT = IOUT • RLOAD (6) FIGURE 1. Functional Block Diagram of the DAC902. NOTE: Supply bypassing not shown.

ability of dynamic gain control. times may be chosen within their specified limits. operate over a supply range of 2.7V to 5.5V. FIGURE 8. External Reference Configuration. the normal operation of the converter. signal layers by ground layers, etc.

Further supply decoupling with surface mount tantalum capacitors (1uF to 4.7uF) may be added as needed in proximity of the converter. Low noise is required for all supply and ground connections to the DAC902. It is recommended to use a multilayer pc- board utilizing separate power and ground planes. Mixed signal designs require particular attention to the routing of the different supply currents and signal traces. Generally, analog supply and ground planes should only extend into analog signal areas, such as the DAC output signal and the reference signal. Digital supply and ground planes must be confined to areas covering digital circuitry, including the digital input lines connecting to the converter, as well as the clock signal. The analog and digital ground planes should be joined together at one point underneath the DAC. This can be realized with a short track of approximately 1/8" (3mm). The power to the DAC902 should be provided through the use of wide pcb runs or planes. Wide runs will present a lower trace impedance, further optimizing the supply decou- pling. The analog and digital supplies for the converter should only be connected together at the supply connector of the pc-board. In the case of only one supply voltage being available to power the DAC, ferrite beads along with bypass capacitors may be used to create an LC filter. This will generate a low-noise analog supply voltage that can then be connected to the +V A supply pin of the DAC902. While designing the layout, it is important to keep the analog signal traces separate from any digital line, in order to prevent noise coupling onto the analog signal path.

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DAC902E Active Production TSSOP (PW) | 28 50 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 DAC902E DAC902E.B Active Production TSSOP (PW) | 28 50 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 DAC902E DAC902E/2K5 Active Production TSSOP (PW) | 28 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 DAC902E DAC902E/2K5.B Active Production TSSOP (PW) | 28 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 DAC902E DAC902E1G4.B Active Production TSSOP (PW) | 28 50 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 DAC902E DAC902U Active Production SOIC (DW) | 28 20 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 DAC902U DAC902U.B Active Production SOIC (DW) | 28 20 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 DAC902U DAC902U/1K Active Production SOIC (DW) | 28 1000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 DAC902U DAC902U/1K.B Active Production SOIC (DW) | 28 1000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 DAC902U (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative Addendum-Page 1

www.ti.com 23-May-2025 and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC902E/2K5 TSSOP PW 28 2500 367.0 367.0 38.0 DAC902U/1K SOIC DW 28 1000 350.0 350.0 66.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) DAC902E PW TSSOP 28 50 530 10.2 3600 3.5 DAC902E.B PW TSSOP 28 50 530 10.2 3600 3.5 DAC902E1G4.B PW TSSOP 28 50 530 10.2 3600 3.5 DAC902U DW SOIC 28 20 506.98 12.7 4826 6.6 DAC902U.B DW SOIC 28 20 506.98 12.7 4826 6.6 Pack Materials-Page 3

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2025, Texas Instruments Incorporated