DAC902

DAC902 BURR-BROWN | Alldatasheet

Document overview

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Technical content

© 1999 Burr-Brown Corporation PDS-1447B Printed in U.S.A. May, 2000 International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 DAC902 DAC902 For most current data sheet and other product information, visit www.burr-brown.com 12-Bit, 165MSPS DIGITAL-TO-ANALOG CONVERTER

FEATURES

l SINGLE +5V OR +3V OPERATION l HIGH SFDR: 5MHz Output at 100MSPS: 67dBc l LOW GLITCH: 3pV-s l LOW POWER: 170mW at +5V l INTERNAL REFERENCE: Optional Ext. Reference Adjustable Full-Scale Range Multiplying Option

APPLICATIONS

l COMMUNICATION TRANSMIT CHANNELS: WLL, Cellular Base Station Digital Microwave Links Cable Modems l WAVEFORM GENERATION: Direct Digital Synthesis (DDS) Arbitrary Waveform Generation (ARB) l MEDICAL/ULTRASOUND l HIGH-SPEED INSTRUMENTATION AND CONTROL l VIDEO, DIGITAL TV

DESCRIPTION

The DAC902 is a high-speed, digital-to-analog converter (DAC) offering a 12-bit resolution option within the SpeedPlus Family of high-performance converters. Featuring pin compatibility among family members, the DAC908, DAC900, and DAC904 provide a component selection option to an 8-, 10-, and 14-bit resolution, respectively. All models within this family of D/A converters support update rates in excess of 165MSPS with excellent dynamic performance, and are especially suited to fulfill the demands of a variety of applications. The advanced segmentation architecture of the DAC902 is optimized to provide a high Spurious-Free Dynamic Range (SFDR) for single-tone, as well as for multi-tone signals— essential when used for the transmit signal path of communica- tion systems. The DAC902 has a high impedance (200kΩ ) current output with a nominal range of 20mA and an output compliance of up to 1.25V. The differential outputs allow for both a differential, or single-ended analog signal interface. The close matching of the current outputs ensures superior dynamic performance in the differential configuration, which can be implemented with a transformer. Utilizing a small geometry CMOS process, the monolithic DAC902 can be operated on a wide, single-supply range of +2.7V to +5.5V. Its low power consumption allows for use in portable and battery operated systems. Further optimization can be realized by lowering the output current with the adjustable full-scale option. For noncontinuous operation of the DAC902, a power-down mode results in only 45mW of standby power. The DAC902 comes with an integrated 1.24V bandgap refer- ence and edge-triggered input latches, offering a complete converter solution. Both +3V and +5V CMOS logic families can be interfaced to the DAC902. The reference structure of the DAC902 allows for additional flexibility by utilizing the on-chip reference, or applying an external reference. The full-scale output current can be adjusted over a span of 2mA to 20mA, with one external resistor, while maintaining the specified dynamic performance. The DAC902 is available in the SO-28 and TSSOP-28 pack- ages. TM Current Sources LSB Switches Segmented Switches +1.24V Ref. Latches 12-Bit Data Input D11...D0 DAC902 FSA BW +VD+V A AGND CLK DGND REF IN INT/EXT IOUT IOUT BYP PD

At TA = full specified temperature range, +VA = +5V, +VD = +5V, differential transformer coupled output, 50Ω doubly terminated, unless otherwise specified. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. DAC902U/E PARAMETER CONDITIONS MIN TYP MAX UNITS Resolution 12 Bits Output Update Rate (fCLOCK ) 4.5V to 5.5V 165 200 MSPS Output Update Rate 2.7V to 3.3V 125 165 MSPS Full Specified Temperature Range, Operating Ambient, T A –40 +85 °C STATIC ACCURACY (1) TA = +25°C Differential Nonlinearity (DNL) f CLOCK = 25MSPS, fOUT = 1.0MHz –1.75 ±0.5 +1.75 LSB Integral Nonlinearity (INL) –2.5 ±1.0 +2.5 LSB DYNAMIC PERFORMANCE TA = +25°C Spurious Free Dynamic Range (SFDR) To Nyquist fOUT = 1MHz, fCLOCK = 25MSPS 71 77 dBc fOUT = 2.1MHz, fCLOCK = 50MSPS 75 dBc fOUT = 5.04MHz, fCLOCK = 50MSPS 68 dBc fOUT = 5.04MHz, fCLOCK = 100MSPS 67 dBc fOUT = 20.2MHz, fCLOCK = 100MSPS 61 dBc fOUT = 25.3MHz, fCLOCK = 125MSPS 61 dBc fOUT = 41.5MHz, fCLOCK = 125MSPS 57 dBc fOUT = 27.4MHz, fCLOCK = 165MSPS 60 dBc fOUT = 54.8MHz, fCLOCK = 165MSPS 53 dBc Spurious Fee Dynamic Range within a Window fOUT = 5.04MHz, fCLOCK = 50MSPS 2MHz Span 80 dBc fOUT = 5.04MHz, fCLOCK = 100MSPS 4MHz Span 80 dBc Total Harmonic Distortion (THD) fOUT = 2.1MHz, fCLOCK = 50MSPS –74 dBc fOUT = 2.1MHz, fCLOCK = 125MSPS –75 dBc Two Tone fOUT1 = 13.5MHz, fOUT2 = 14.5MHz, fCLOCK = 100MSPS 64 dBc Output Settling Time(2) to 0.1% 30 ns Output Rise Time(2) 10% to 90% 2 ns Output Fall Time(2) 10% to 90% 2 ns Glitch Impulse 3 pV-s DC-ACCURACY Full-Scale Output Range(3)(FSR) All Bits High, I OUT 2.0 20.0 mA Output Compliance Range –1.0 +1.25 V Gain Error With Internal Reference –10 ±1 +10 %FSR Gain Error With External Reference –10 ±2 +10 %FSR Gain Drift With Internal Reference ±120 ppmFSR/ °C Offset Error With Internal Reference –0.025 +0.025 %FSR Offset Drift With Internal Reference ±0.1 ppmFSR/ °C Power Supply Rejection, +VA –0.2 +0.2 %FSR/V Power Supply Rejection, +VD –0.025 +0.025 %FSR/V Output Noise I OUT = 20mA, RLOAD = 50Ω 50 pA/ √Hz Output Resistance 200 k Ω Output Capacitance I OUT , IOUT to Ground 12 pF REFERENCE Reference Voltage +1.24 V Reference Tolerance ±5% Reference Voltage Drift ±50 ppmFSR/ °C Reference Output Current 10 µA Reference Input Resistance 1M Ω Reference Input Compliance Range 0.1 1.25 V Reference Small Signal Bandwidth(4) 1.3 MHz DIGITAL INPUTS Logic Coding Straight Binary Latch Command Rising Edge of Clock Logic High Voltage, VIH +VD = +5V 3.5 5 V Logic Low Voltage, VIL +VD = +5V 0 1.2 V Logic High Voltage, VIH +VD = +3V 2 3 V Logic Low Voltage, VIL +VD = +3V 0 0.8 V Logic High Current, IIH(5) +VD = +5V ±20 µA Logic Low Current, IIL +VD = +5V ±20 µA Input Capacitance 5p F

Supply Current(6) IVA 24 30 mA IVA , Power-Down Mode 1.1 2 mA IVD 81 5 m A Power Dissipation +5V, I OUT = 20mA 170 230 mW +3V, IOUT = 2mA 50 mW Power Dissipation, Power-Down Mode 45 mW Thermal Resistance, θJA SO-28 75 °C/W TSSOP-28 50 °C/W NOTES: (1) At output IOUT , while driving a virtual ground. (2) Measured single-ended into 50Ω Load. (3) Nominal full-scale output current is 32 • IREF ; see Application Section for details. (4) Reference bandwidth depends on size of external capacitor at the BW pin and signal level. (5) Typically 45µA for the PD pin, which has an internal pull-down resistor. (6) Measured at fCLOCK = 50MSPS and fOUT = 1.0MHz. DAC902U/E PARAMETER CONDITIONS MIN TYP MAX UNITS SPECIFICATIONS (Cont.) At TA = full specified temperature range, +VA = +5V, +VD = +5V, differential transformer coupled output, 50Ω doubly terminated, unless otherwise specified. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degrada- tion to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS PACKAGE SPECIFIED DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE NUMBER RANGE MARKING NUMBER (1) MEDIA DAC902U SO-28 217 –40 °C to +85°C DAC902U DAC902U Rails "" " " " DAC902U/1K Tape and Reel DAC902E TSSOP-28 360 –40 °C to +85°C DAC902E DAC902E Rails "" " " " DAC902E/2K5 Tape and Reel NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of “DAC902E/2K5” will get a single 2500-piece Tape and Reel. PACKAGE/ORDERING INFORMATION DEMO BOARD PRODUCT ORDERING NUMBER COMMENT DAC902U DEM-DAC90xU Populated evaluation board without the D/A converter. Order sample of desired DAC90x model separately. DAC902E DEM-DAC902E Populated evaluation board including the DAC902E. DEMO BOARD ORDERING INFORMATION

PIN DESIGNATOR DESCRIPTION

1 Bit 1 Data Bit 1 (D11), MSB

2 Bit 2 Data Bit 2 (D10)

3 Bit 3 Data Bit 3 (D9)

4 Bit 4 Data Bit 4 (D8)

5 Bit 5 Data Bit 5 (D7)

6 Bit 6 Data Bit 6 (D6)

7 Bit 7 Data Bit 7 (D5)

8 Bit 8 Data Bit 8 (D4)

9 Bit 9 Data Bit 9 (D3)

10 Bit 10 Data Bit 10 (D2)

11 Bit 11 Data Bit 11 (D1)

12 Bit 12 Data Bit 12 (D0), LSB

13 NC No Connection

14 NC No Connection

15 PD Power Down, Control Input; Active

High. Contains internal pull-down circuit; may be left unconnected if not used.

16 INT/EXT Reference Select Pin; Internal ( = 0) or

External ( = 1) Reference Operation. 17 REF IN Reference Input/Ouput. See Applica- tions section for further details.

18 FSA Full-Scale Output Adjust

19 BW Bandwidth/Noise Reduction Pin:

Bypass with 0.1µF to +VA for Optimum Performance.

20 AGND Analog Ground

OUT Complementary DAC Current Output

22 I OUT DAC Current Output

23 BYP Bypass Node: Use 0.1 µF to AGND 24 +V A Analog Supply Voltage, 2.7V to 5.5V

25 NC No Connection

26 DGND Digital Ground

D Digital Supply Voltage, 2.7V to 5.5V

28 CLK Clock Input

PIN DESCRIPTIONSPIN CONFIGURATION Top View SOIC, TSSOP TYPICAL CONNECTION CIRCUIT Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 NC NC CLK D DGND NC A BYP I OUT IOUT AGND BW FSA REF IN INT/EXT PD DAC902 Current Sources LSB Switches Segmented MSB Switches +1.24V Ref. Latches 12-Bit Data Input DAC902 FSA BW +V D+VA R SET AGND CLK DGND REF IN 0.1µF INT/EXT IOUT IOUT BYP PD 20pF 50Ω 50Ω 20pF 1:1 0.1µF 0.1µF +5V +5V

SYMBOL DESCRIPTION MIN TYP MAX UNITS t1 Clock Pulse High Time 3.0 ns t2 Clock Pulse Low Time 3.0 ns tS Data Setup Time 1.5 ns tH Data Hold Time 2.5 ns tPD Propagation Delay Time (t 1 + t2) + 1 ns tSET Output Settling Time to 0.1% 30.0 ns tPD tSET tHtS CLK D11 - D0 IOUT or IOUT

TYPICAL PERFORMANCE CURVES, V D = VA = +5V At TA = +25°C, differential transformer coupled output, 50Ω doubly terminated, and SFDR up to Nyquist, unless otherwise noted. SFDR vs fOUT AT 25MSPS Frequency (MHz) SFDR (dBc) 0dBFS –6dBFS SFDR vs fOUT AT 50MSPS Frequency (MHz) SFDR (dBc) –6dBFS 0dBFS SFDR vs fOUT AT 100MSPS Frequency (MHz) SFDR (dBc) 0dBFS –6dBFS SFDR vs fOUT AT 125MSPS Frequency (MHz) SFDR (dBc) 0dBFS –6dBFS DAC Code TYPICAL DNL Error (LSBs) 2.5 2.0 1.5 1.0 0.5 –0.5 –1.0 –1.5 –2.0 –2.5 500 1000 1500 2000 2500 3000 3500 4000 4096 DAC Code TYPICAL INL Error (LSBs) 2.5 2.0 1.5 1.0 0.5 –0.5 –1.0 –1.5 –2.0 –2.5 500 1000 1500 2000 2500 3000 3500 4000 4096

TYPICAL PERFORMANCE CURVES, V D = VA = +5V (Cont.) At TA = +25°C, differential transformer coupled output, 50Ω doubly terminated, and SFDR up to Nyquist, unless otherwise noted. SFDR vs TEMPERATURE AT 100MSPS, 0dBFS Temperature (°C) SFDR (dBc) –20 0 25 70 50 85–40 2.1MHz 10.1MHz 40.4MHz XXXXXXX THD vs fCLOCK AT fOUT = 2.1MHz fCLOCK (MSPS) THD (dBc) –70 –75 –80 –85 –90 –95 –100 25 50 100 125 1500 2HD 4HD 3HD X X X X SFDR vs IOUTFS and fOUT AT 100MSPS, 0dBFS IOUTFS (mA) SFDR (dBc) 51 02 02 X X X X 2.1MHz 20.2MHz 10.1MHz 40.4MHz DIFFERENTIAL vs SINGLE-ENDED SFDR vs fOUT AT 100MSPS Frequency (MHz) SFDR (dBc) Diff (0dBFS) IOUT (–6dBFS) IOUT (0dBFS) Diff (–6dBFS) X X X X X X X SFDR vs fOUT AT 200MSPS Frequency (MHz) SFDR (dBc) –6dBFS 0dBFS SFDR vs fOUT AT 165MSPS Frequency (MHz) SFDR (dBc) –6dBFS 0dBFS

TYPICAL PERFORMANCE CURVES, V D = VA = +5V (Cont.) At TA = +25°C, differential transformer coupled output, 50Ω doubly terminated, and SFDR up to Nyquist, unless otherwise noted. FOUR-TONE OUTPUT SPECTRUM Frequency (MHz) Magnitude (dBm) –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 51 0 1 5 2 0 2 5 fCLOCK = 50MSPS fOUT1 = 6.25MHz fOUT2 = 6.75MHz fOUT3 = 7.25MHz fOUT4 = 7.75MHz SFDR = 66dBc Amplitude = 0dBFS DUAL-TONE OUTPUT SPECTRUM Frequency (MHz) Magnitude (dBm) –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 5 1 01 52 02 53 03 54 04 55 0 fCLOCK = 100MSPS fOUT1 = 13.5MHz fOUT2 = 14.5MHz SFDR = 64dBc Amplitude = 0dBFS SINGLE-TONE OUTPUT SPECTRUM Frequency (MHz) Magnitude (dBm) –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 5 1 01 52 02 53 03 54 04 55 0 fCLOCK = 100MSPS fOUT = 2.1MHz SFDR = 74dBc Amplitude = 0dBFS

TYPICAL PERFORMANCE CURVES, V D = VA = +3V At TA = +25°C, differential transformer coupled output, 50Ω doubly terminated, and SFDR up to Nyquist, unless otherwise noted. DIFFERENTIAL vs SINGLE-ENDED SFDR vs fOUT AT 100MSPS (3V) Frequency (MHz) SFDR (dBc) Diff (0dBFS) IOUT (–6dBFS) IOUT (0dBFS) Diff (–6dBFS) SFDR vs fOUT AT 165MSPS (3V) Frequency (MHz) SFDR (dBc) –6dBFS 0dBFS SFDR vs fOUT AT 125MSPS (3V) Frequency (MHz) SFDR (dBc) 0dBFS –6dBFS SFDR vs fOUT AT 100MSPS (3V) Frequency (MHz) SFDR (dBc) –6dBFS 0dBFS SFDR vs fOUT AT 50MSPS (3V) Frequency (MHz) SFDR (dBc) –6dBFS 0dBFS SFDR vs fOUT AT 25MSPS (3V) Frequency (MHz) SFDR (dBc) 0dBFS –6dBFS

TYPICAL PERFORMANCE CURVES, V D = VA = +3V (Cont.) At TA = +25°C, differential transformer coupled output, 50Ω doubly terminated, and SFDR up to Nyquist, unless otherwise noted. FOUR-TONE OUTPUT SPECTRUM (3V) Frequency (MHz) Magnitude (dBm) –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 51 0 1 5 2 0 2 5 fCLOCK = 50MSPS fOUT1 = 6.25MHz fOUT2 = 6.75MHz fOUT3 = 7.25MHz fOUT4 = 7.75MHz SFDR = 66dBc Amplitude = 0dBFS DUAL-TONE OUTPUT SPECTRUM (3V) Frequency (MHz) Magnitude (dBm) –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 5 1 01 52 02 53 03 54 04 55 0 fCLOCK = 100MSPS fOUT1 = 13.5MHz fOUT2 = 14.5MHz SFDR = 68dBc Amplitude = 0dBFS SINGLE-TONE OUTPUT SPECTRUM (3V) Frequency (MHz) Magnitude (dBm) –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 5 1 01 52 02 53 03 54 04 55 0 fCLOCK = 100MSPS fOUT = 2.1MHz SFDR = 76dBc Amplitude = 0dBFS SFDR vs TEMPERATURE AT 100MSPS, 0dBFS (3V) Temperature (°C) SFDR (dBc) –20 0 25 70 50 85–40 2.1MHz 10.1MHz 40.4MHz X X XXXXX THD vs fCLOCK AT fOUT = 2.1MHz (3V) fCLOCK (MSPS) THD (dBc) –70 –75 –80 –85 –90 –95 –100 25 50 100 125 1500 2HD 4HD 3HD IOUTFS (mA) SFDR (dBc) 51 02 02 X X X X SFDR vs IOUTFS and fOUT AT 100MSPS, 0dBFS (3V) 2.1MHz 20.2MHz 10.1MHz 40.4MHz

ability of dynamic gain control. within their specified limits. operate over a supply range of 2.7V to 5.5V. FIGURE 8. External Reference Configuration. normal operation of the converter. signal layers by ground layers, etc.

Further supply decoupling with surface mount tantalum capacitors (1uF to 4.7uF) may be added as needed in proximity of the converter. Low noise is required for all supply and ground connections to the DAC902. It is recommended to use a multilayer pc- board utilizing separate power and ground planes. Mixed signal designs require particular attention to the routing of the different supply currents and signal traces. Generally, analog supply and ground planes should only extend into analog signal areas, such as the DAC output signal and the reference signal. Digital supply and ground planes must be confined to areas covering digital circuitry, including the digital input lines connecting to the converter, as well as the clock signal. The analog and digital ground planes should be joined together at one point underneath the D/A converter. This can be realized with a short track of approximately 1/8inch (3mm). The power to the DAC902 should be provided through the use of wide pcb runs or planes. Wide runs will present a lower trace impedance, further optimizing the supply decou- pling. The analog and digital supplies for the converter should only be connected together at the supply connector of the pc board. In the case of only one supply voltage being available to power the DAC, ferrite beads along with bypass capacitors may be used to create an LC filter. This will generate a low noise analog supply voltage, which can then be connected to the +V A supply pin of the DAC902. While designing the layout, it is important to keep the analog signal traces separated from any digital line, in order to prevent noise coupling onto the analog signal path.