DACx0502, Dual, 16-Bit, 14-Bit, and 12-Bit, 1-LSB INL, Voltage-Output DACs With Precision Internal Reference datasheet (Rev. A)
Document overview
- Manufacturer or author: Texas Instruments, Incorporated [SBAS793,A]
- PDF pages: 47
Technical content
Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DAC80502, DAC70502, DAC60502 SBAS793A –NOVEMBER 2019–REVISED APRIL 2020 DACx0502,Dual,16-Bit,14-Bit,and12-Bit,1-LSBINL,Voltage-OutputDACs WithPrecisionInternalReference
1 Features
1• 16-bit performance: 1-LSB INL and DNL (max)
- Low glitch energy: 4 nV-s
- Wide power supply: 2.7 V to 5.5 V
- Buffered output range: 5 V, 2.5 V, or 1.25 V
- Low power: 1 mA per channel at 5.5 V
- Integrated 5-ppm/˚C (max), 2.5-V precision reference
- Pin-selectable serial interface – 3-wire, SPI compatible up to 50-MHz – 2-wire, I2C compatible
- Power-on-reset: zero scale or midscale
- 1.62-V VIH with VDD = 5.5 V
- Temperature range: –40˚C to +125˚C
- Package: Tiny 10-pin WSON
2 Applications
- Oscilloscope (DSO)
- Battery test
- Semiconductor test
- Data acquisition (DAQ)
- LCD test
- Small cell base station
- Analog output module
- Process analytics (pH, gas, concentration, force and humidity)
- DC power supply, ac source, electronic load
3 Description
The 16-bit DAC80502, 14-bit DAC70502, and 12-bit DAC60502 (DACx0502) digital-to-analog converters (DACs) are highly accurate, low-power devices with voltage output. The DACx0502 offer linearity of < 1 LSB. The high accuracy combined with tiny package make the DACx0502 an excellent choice for applications such as gain and offset calibration, current or voltage set point generation, and power-supply control. These devices include a 2.5-V, 5-ppm/°C internal reference, giving full-scale output voltage ranges of 1.25 V, 2.5 V, or 5 V. The DACx0502 incorporate a power- on-reset circuit that makes sure the DAC output powers up at zero scale or midscale based on the status of RSTSEL pin, and remains at that scale until a valid code is written to the device. The digital interface of the DACx0502 can be configured to SPI or I2C mode using the SPI2C pin. In SPI mode, the DACx0502 use a versatile 3-wire serial interface that operates at clock rates up to 50 MHz. In I2C mode, the DACx0502 operate in standard (100 kbps), fast (400 kbps), and fast+ (1.0 Mbps) modes. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) DAC80502 WSON (10) 2.50 mm × 2.50 mmDAC70502 DAC60502 (1) For all available packages, see the package option addendum at the end of the data sheet. Functional Block Diagram
DAC80502, DAC70502, DAC60502 SBAS793A –NOVEMBER 2019–REVISED APRIL 2020 www.ti.com Product Folder Links: DAC80502 DAC70502 DAC60502 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Table of Contents
12.3 Receiving Notification of Documentation Updates 39
13 Mechanical, Packaging, and Orderable
4 Revision History
Changes from Original (November 2019) to Revision A Page
DAC80502, DAC70502, DAC60502 www.ti.com SBAS793A –NOVEMBER 2019–REVISED APRIL 2020 Product Folder Links: DAC80502 DAC70502 DAC60502 Submit Documentation FeedbackCopyright © 2019–2020, Texas Instruments Incorporated
5 Device Comparison Table
DEVICE RESOLUTION REFERENCE DAC80502 16-bit Internal (default) or external DAC70502 14-bit Internal (default) or external DAC60502 12-bit Internal (default) or external
6 Pin Configuration and Functions
NAME NO. AGND 4 Ground Ground reference point for all circuitry on the device RSTSEL 3 Input Reset select pin. DACs power up to zero scale if RSTSEL = AGND. DACs power up to midscale if RSTSEL = VDD SCLK/SCL 6 Input Serial interface clock. SPI or I2C mode. SDIN/SDA 8 Input/Output SPI mode: Serial interface data input. Data are clocked into the input shift register on each falling edge of the SCLK pin. I2C mode: Data are clocked into or out of the input register. This pin is a bidirectional, SDA drain data line that must be connected to the supply voltage with an external pull-up resistor. SPI2C 5 Input Interface select pin. The SPI2C pin must be kept static after device powers up. If SPI2C = 0, the digital interface is in SPI mode If SPI2C = 1, the digital interface is in I2C mode SYNC/A0 7 Input SPI mode: Active low serial data enable. This input is the frame-synchronization signal for the serial data. When the signal goes low, the serial interface input shift register is enabled. I2C mode: Four-state address input. VDD 1 Power Analog supply voltage (2.7 V to 5.5 V) VOUTA 2 Output Analog output voltage from DAC A VOUTB 9 Output Analog output voltage from DAC B VREFIO 10 Input/Output When using the internal reference, this pin is the reference output voltage pin (default). When operating with an external reference, this pin is the reference input to the device.
DAC80502, DAC70502, DAC60502 SBAS793A –NOVEMBER 2019–REVISED APRIL 2020 www.ti.com Product Folder Links: DAC80502 DAC70502 DAC60502 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Input voltage VDD to AGND –0.3 6 VVREFIO to AGND –0.3 VDD + 0.3 Digital input(s) to AGND –0.3 VDD + 0.3 Output voltage VOUTx to AGND –0.3 VDD + 0.3 V Input current Current into any pin –10 10 mA Temperature Junction temperature (TJ) –40 150 Storage temperature (Tstg) –65 150 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.2 ESD Ratings
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS- 001, all pins(1) ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1000
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT POWER SUPPLY VDD to AGND Positive supply voltage to ground 2.7 5.5 V DIGITAL INPUTS VIH Input high voltage 1.62 V VIL Input low voltage 0.45 V REFERENCE INPUT VREFIO to AGND 2.7 V ≤ VDD < 3.3 V, reference divider disabled (REF-DIV bit = 0) 1.2 0.5 × (VDD – 0.2) V VREFIO to AGND 2.7 V ≤ VDD < 3.3 V, reference divider enabled (REF-DIV bit = 1) 2.4 (VDD – 0.2) V VREFIO to AGND 3.3 V ≤ VDD ≤ 5.5 V, reference divider disabled (REF-DIV bit = 0) 1.2 0.5 × VDD V VREFIO to AGND 3.3 V ≤ VDD ≤ 5.5 V, reference divider enabled (REF-DIV bit = 1) 2.4 VDD V TEMPERATURE TA Operating temperature –40 125 °C
DAC80502, DAC70502, DAC60502 www.ti.com SBAS793A –NOVEMBER 2019–REVISED APRIL 2020 Product Folder Links: DAC80502 DAC70502 DAC60502 Submit Documentation FeedbackCopyright © 2019–2020, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
7.4 Thermal Information
THERMAL METRIC(1) DACx0502 UNITDRX (WSON)
10 PINS
RθJA Junction-to-ambient thermal resistance 99.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 49.9 °C/W RθJB Junction-to-board thermal resistance 35.9 °C/W ΨJT Junction-to-top characterization parameter 1.7 °C/W ΨJB Junction-to-board characterization parameter 35.7 °C/W (1) End point fit between code 256 to code 64,511 for 16-bit, code 64 to code 16,127 for 14-bit, code 16 to code 4031 for 12-bit, DAC output unloaded, performance under resistive and capacitive load conditions are specified by design and characterization, DAC output range ≥ 2.5 V.
7.5 Electrical Characteristics
all minimum and maximum values at TA = –40°C to +125°C and all typcal values at TA = 25°C, 2.7 V ≤ VDD ≤ 5.5 V, external or internal VREFIO = 1.25 V to 5.5 V , RLOAD = 2 kΩ to AGND, CLOAD = 200 pF to AGND, and digital inputs at VDD or AGND (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STATIC PERFORMANCE Resolution DAC80502 16 BitsDAC70502 14 DAC60502 12 INL Integral nonlinearity(1) –1 1 LSB DNL Differential nonlinearity(1) –1 1 LSB TUE Total unadjusted error(1) –0.1 0.04 0.1 %FSR Zero code error(1) DAC loaded with zero scale code –1.5 0.5 1.5 mV Zero code error temperature coefficient(1) ±2 µV/°C Offset error(1) –1.5 0.5 1.5 mV Offset error temperature coefficient (1) ±2 µV/°C Gain error(1) –0.1 0.04 0.1 %FSR Gain error temperature coefficient(1) ±1 ppm FSR/°C Full-scale error(1) –0.1 0.04 0.1 %FSR Full-scale error temperature coefficient(1) ±2 ppm FSR/°C
DAC80502, DAC70502, DAC60502 SBAS793A –NOVEMBER 2019–REVISED APRIL 2020 www.ti.com Product Folder Links: DAC80502 DAC70502 DAC60502 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Electrical Characteristics (continued) all minimum and maximum values at TA = –40°C to +125°C and all typcal values at TA = 25°C, 2.7 V ≤ VDD ≤ 5.5 V, external or internal VREFIO = 1.25 V to 5.5 V , RLOAD = 2 kΩ to AGND, CLOAD = 200 pF to AGND, and digital inputs at VDD or AGND (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (2) Not production tested. OUTPUT CHARACTERISTICS VO Output voltage BUFF-GAIN bit set to 1, REF-DIV bit set to 0 0 2 × VREFIO VBUFF-GAIN bit set to 1, REF-DIV bit set to 1 0 VREFIO BUFF-GAIN bit set to 0, REF-DIV bit set to 1 0 0.5 × VREFIO RLOAD Resistive load(2) VDD = 2.7 V 0.25 kΩ VDD = 5.5 V 0.5 CLOAD Capacitive load(2) RLOAD = infinite 2 nF RLOAD = 2 kΩ 10 Load regulation DAC at midscale, –10 mA ≤ IOUT ≤ 10 mA 80 µV/mA Short circuit current Full scale output shorted to AGND (per channel) 30 mA Zero output shorted to VDD (per channel) 30 Output voltage headroom to VDD, DAC at full code, IOUT = 10 mA (sourcing) 0.3 0.1 V Output voltage footroom to AGND, DAC at zero code, IOUT = 10 mA (sinking) 0.3 V ZO DC small signal output impedance DAC at midscale 0.1 ΩDAC at code 256 10 DAC at code 65279 10 Power supply rejection ratio (DC) DAC at midscale; VDD = 5 V ± 10% 0.15 mV/V Output voltage drift vs time TA = 35°C, VOUT = midscale, 1900 hr 20 ppm of FSR VOLTAGE REFERENCE INPUT ZVREFIO Reference input impedance (VREFIO) 100 kΩ CVREFIO Reference input capacitance (VREFIO) 5 pF VOLTAGE REFERENCE OUTPUT Output (initial accuracy) TA = 25°C 2.4975 2.5025 V Output drift DAC80502 5 ppm/℃ DAC70502, DAC60502 10 Output impedance 0.1 Ω Output noise 0.1 Hz to 10 Hz 14 µVPP Output noise density Measured at 10 kHz, reference load = 10 nF 140 nV/√Hz Load current ±5 mA Load regulation Sourcing and sinking 90 µV/mA Line regulation 20 µV/V Output voltage drift vs time TA = 35°C, 1900 hr 20 µV Thermal hysteresis 1st cycle 480 ppm Additional cycle 25 ppm
DAC80502, DAC70502, DAC60502 www.ti.com SBAS793A –NOVEMBER 2019–REVISED APRIL 2020 Product Folder Links: DAC80502 DAC70502 DAC60502 Submit Documentation FeedbackCopyright © 2019–2020, Texas Instruments Incorporated Electrical Characteristics (continued) all minimum and maximum values at TA = –40°C to +125°C and all typcal values at TA = 25°C, 2.7 V ≤ VDD ≤ 5.5 V, external or internal VREFIO = 1.25 V to 5.5 V , RLOAD = 2 kΩ to AGND, CLOAD = 200 pF to AGND, and digital inputs at VDD or AGND (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (3) Output buffer in gain = 2X setting (BUFF-GAIN bit = 1). DYNAMIC PERFORMANCE ts Output voltage settling time(3) ¼ to ¾ scale and ¾ to ¼ scale settling to ±2 LSB, VDD = 5.5 V, VREFIO = 2.5 V 5 µs 10-mV settling to ±2 LSB, VDD = 5.5 V, VREFIO = 2.5 V 3 Slew rate(3) VDD = 5.5 V, VREFIO = 2.5 V 2 V/µs Power on glitch magnitude CLOAD = 50 pF 200 mV Vn Output noise(3)
0.1 Hz to 10 Hz, DAC at midscale,
VDD = 5.5 V, external VREFIO = 2.5 V 14 µVPP 100-kHz Bandwidth, DAC at midscale, VDD = 5.5 V, external VREFIO = 2.5 V 23 µVrms Vn Output noise density Measured at 1 kHz, DAC at midscale, VDD = 5.5 V, external VREFIO = 2.5 V, gain = 2X (BUFF-GAIN bit = 1) nV/√Hz Measured at 10 kHz, DAC at midscale, VDD = 5.5 V, external VREFIO = 2.5 V, gain = 2X (BUFF-GAIN bit = 1) Measured at 1 kHz, DAC at full scale, VDD = 2.7 V, external VREFIO = 2.5 V, gain = 1X (BUFF-GAIN bit = 0) Measured at 10 kHz, DAC at full scale, VDD = 2.7 V, external VREFIO = 2.5 V, gain = 1X (BUFF-GAIN bit = 0) SFDR Spurious free dynamic range 1-kHz sinusiod at DAC output, DAC updated at 500 kHz, include up to 7th harmonics, no filter on DAC output 70 dB THD Total harmonic distortion 1-kHz sinusiod at DAC output, DAC updated at 500 kHz, include up to 7th harmonics, no filter on DAC output 70 dB Power supply rejection ratio (ac) 200-mV, 50-Hz to 60-Hz sine wave on VDD, DAC at midscale. 85 dB Code change glitch impulse Midcode ±1 LSB (including feedthrough) 4 nV-s Code change glitch magnitude Midcode ±1 LSB (including feedthrough) gain = 1X (BUFF-GAIN bit = 0) 7.5 mV Channel to channel ac crosstalk Full scale swing on adjacent channel, measured channel at midscale 4 nV-s Channel to channel dc crosstalk Full scale swing on adjacent channel, measured channel at midscale 1 LSB Digital feedthrough At SCLK = 1 MHz, DAC output at midscale 4 nV-s DIGITAL INPUTS Hysteresis voltage 0.4 V Input current –5 5 µA Pin capacitance Per pin 10 pF
DAC80502, DAC70502, DAC60502 SBAS793A –NOVEMBER 2019–REVISED APRIL 2020 www.ti.com Product Folder Links: DAC80502 DAC70502 DAC60502 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Electrical Characteristics (continued) all minimum and maximum values at TA = –40°C to +125°C and all typcal values at TA = 25°C, 2.7 V ≤ VDD ≤ 5.5 V, external or internal VREFIO = 1.25 V to 5.5 V , RLOAD = 2 kΩ to AGND, CLOAD = 200 pF to AGND, and digital inputs at VDD or AGND (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER IVDD Current flowing into VDD Normal mode, internal reference enabled, all DACs at full scale, SPI static 1.9 2.6 mA Normal mode, external reference = 2.5 V, all DACs at full scale, SPI static 1.5 1.9 All DACs and Internal reference power-down 15 µA IVREFIO Current flowing into VREFIO 0-V to 5-V range, midscale code 25 µA
DAC80502, DAC70502, DAC60502 www.ti.com SBAS793A –NOVEMBER 2019–REVISED APRIL 2020 Product Folder Links: DAC80502 DAC70502 DAC60502 Submit Documentation FeedbackCopyright © 2019–2020, Texas Instruments Incorporated
7.6 Timing Requirements : SPI Mode
all input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VIL + VIH) / 2. 2.7 V ≤ VDD ≤ 5.5 V, VIH = 1.62 V, VIL = 0.15 V, VREFIO = 1.25 V to 5.5 V, and TA = –40°C to +125°C (unless otherwise noted) MIN NOM MAX UNIT fSCLK SCLK frequency 50 MHz tSCLKHIGH SCLK high time 9 ns tSCLKLOW SCLK low time 9 ns tSDIS SDIN setup 5 ns tSDIH SDIN hold 10 ns tSYNCS SYNC falling edge to SCLK falling edge setup 13 ns tSYNCH SCLK falling edge to SYNC rising edge 10 ns tSYNCHIGH SYNC high time 160 ns tSYNCIGNORE SCLK falling edge to SYNC ignore 15 ns tDACWAIT Sequential DAC update wait time 1 µs
7.7 Timing Requirements : I2C Standard Mode
all input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VIL + VIH) / 2. 2.7 V ≤ VDD ≤ 5.5 V, VIH = 1.62 V, VIL = 0.45 V, VREFIO = 1.25 V to 5.5 V, and TA = – 40°C to +125°C (unless otherwise noted) MIN NOM MAX UNIT fSCLK SCL frequency 0.1 MHz tBUF Bus free time between stop and start conditions 4.7 µs tHDSTA Hold time after repeated start 4 µs tSUSTA Repeated start setup time 4.7 µs tSUSTO Stop condition setup time 4 µs tHDDAT Data hold time 0 ns tSUDAT Data setup time 250 ns tLOW SCL clock low period 4700 ns tHIGH SCL clock high period 4000 ns tR Clock and data fall time 300 ns tF Clock and data rise time 1000 ns tUPDATE Sequential DAC update wait time 1 µs
7.8 Timing Requirements : I2C Fast Mode
all input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VIL + VIH) / 2. 2.7 V ≤ VDD ≤ 5.5 V, VIH = 1.62 V, VIL = 0.45 V, VREFIO = 1.25 V to 5.5 V, and TA = – 40°C to +125°C (unless otherwise noted) MIN NOM MAX UNIT fSCLK SCL frequency 0.4 MHz tBUF Bus free time between stop and start conditions 1.3 µs tHDSTA Hold time after repeated start 0.6 µs tSUSTA Repeated start setup time 0.6 µs tSUSTO Stop condition setup time 0.6 µs tHDDAT Data hold time 0 ns tSUDAT Data setup time 100 ns tLOW SCL clock low period 1300 ns tHIGH SCL clock high period 600 ns tR Clock and data fall time 300 ns tF Clock and data rise time 300 ns tUPDATE Sequential DAC update wait time 1 µs
7.9 Timing Requirements : I2C Fast-Mode Plus
Figure 1. SPI Mode Timing Figure 2. I2C Mode Timing
7.10 Typical Characteristics
Figure 3. Integral Linearity Error vs Digital Input Code Figure 4. Differential Linearity Error vs Digital Input Code Figure 5. Total Unadjusted Error vs Digital Input Code Figure 6. Integral Linearity Error vs Temperature Figure 7. Differential Linearity Error vs Temperature Figure 8. Total Unadjusted Error vs Temperature
8 Detailed Description
8.1 Overview
DACx0502 devices operate in standard (100 kbps), fast (400 kbps), and fast+ (1.0 Mbps) modes.
8.2 Functional Block Diagram
8.3 Feature Description
8.3.1 Digital-to-Analog Converter (DAC) Architecture
Figure 56. DACx0502 DAC Block Diagram
DAC_DATA VREFIOV GAIN DIV2 DAC80502, DAC70502, DAC60502 www.ti.com SBAS793A –NOVEMBER 2019–REVISED APRIL 2020 Product Folder Links: DAC80502 DAC70502 DAC60502 Submit Documentation FeedbackCopyright © 2019–2020, Texas Instruments Incorporated Feature Description (continued)
8.3.1.1 DAC Transfer Function
The input data writes to the individual DAC data registers in straight binary format. After a power-on or a reset event, all DAC registers are set to zero code (RSTSEL = 0) or midscale code (RSTSEL = 1). The DAC transfer function is shown by Equation 1. where:
- N = resolution in bits = either 12 (DAC60502), 14 (DAC70502) or 16 (DAC80502).
- DAC_DATA = decimal equivalent of the binary code that is loaded to the DAC register (address 8h), DAC_DATA ranges from 0 to 2N – 1.
- VREFIO = DAC reference voltage. Either VREFIO from the internal 2.5-V reference or VREFIO from an external reference.
- DIV = 1 (default) or 2 as set by the REF-DIV bit in the GAIN register (address 4h).
- GAIN = 1 or 2 (default) as set by the BUFF-GAIN bit for that DAC channel in the GAIN register (address 4h). (1)
8.3.1.2 DAC Register Structure
Data written to the DAC data registers are initially stored in the DAC buffer registers. The update mode of the DAC output is determined by the status of the DAC_SYNC_EN bit (address 2h). In asynchronous mode (default, DAC_SYNC_EN = 0), a write to the DAC buffer register results in an immediate update of the DAC active register. In SPI mode, the DAC output (VOUTx pin) updates on the rising edge of SYNC. In I2C mode, the DAC output (VOUT pin) updates on the falling edge of SCL on the last acknowledge bit. In synchronous mode (DAC_SYNC_EN = 1), writing to the DAC buffer register does not automatically update the DAC active register. Instead, the update occurs only after a software LDAC trigger event. A software LDAC trigger generates through the LDAC bit in the TRIGGER register (address 5h). When the host reads from a DAC buffer register, the value held in the DAC buffer register is returned (not the value held in the DAC active register).
8.3.1.3 Output Amplifier
The output buffer amplifier generates rail-to-rail voltages on the output, giving a maximum output range of 0 V to VDD. Equation 1 shows that the full-scale output range of the DAC output is determined by the voltage on the VREFIO pin, the reference divider setting (DIV) as set by the REF-DIV bit (address 4h), and the gain configuration for that channel set by the corresponding BUFF-GAIN bit (address 4h).
8.3.2 Internal Reference
The DAx0502 family of devices includes a 2.5-V precision band-gap reference enabled by default. Operation from an external reference is supported by disabling the internal reference in the REF_PWDWN bit (address 3h). The internal reference is externally available at the VREFIO pin and sources up to 5 mA. For noise filtering, use a minimum 150-nF capacitor between the reference output and AGND. The reference voltage to the device, either from the internal reference or an external one, can be divided by a factor of two by setting the REF-DIV bit (address 4h) to 1. The REF-DIV bit provides additional flexibility in setting the full-scale output range of the DAC output. Make sure to configure REF-DIV so that there is sufficient headroom from VDD to the DAC operating reference voltage, VREFIO (see Equation 1). See the Recommended Operating Conditions for more information. Improper configuration of the reference divider triggers a reference alarm condition. In this case, the reference buffer is shut down, and all the DAC outputs go to 0 V. The DAC data registers are unaffected by the alarm condition, and thus enable the DAC output to return to normal operation after the reference divider is configured correctly.
8.3.2.1 Solder Heat Reflow
A known behavior of IC reference voltage circuits is the shift induced by the soldering process. Figure 54 and Figure 55 show the effect of solder heat reflow for the DACx0502 internal reference.
8.3.3 Power-On Reset (POR)
The DACx0502 family of devices includes a power-on reset function that controls the output voltage at power up. the power-up voltage until a valid command is written to a channel. device on power up. In order to make sure that a POR occurs, VDD must be less than 0.7 V for at least 1 ms. may or may not reset under all specified temperature and power-supply conditions. In this case, initiate a POR. When VDD remains greater than 2.2 V, a POR does not occur. Figure 57. Threshold Levels for the VDD POR Circuit
8.3.4 Software Reset
TRIGGER register (address 5h). A software reset initiates a POR event.
8.4 Device Functional Modes
The DACx0502 have two modes of operation: normal and power-down.
8.4.1 Power-Down Mode
down mode, the DACs output (VOUTx pin) is internally connected to AGND through a 1-kΩ resistor.
8.5 Programming
8.5.1 Serial Interface
The DACx0502 family of devices is controlled through either a 3-wire SPI or a 2-wire I2C interface. SPI2C pin must be kept static after the device powers up.
8.5.1.1 SPI Mode
shift register is 24-bits wide. Table 1. SPI Mode Frame Format Serial clock SCLK is a continuous or a gated clock. The first falling edge of SYNC starts the operation cycle. shift register on the rising edge of SYNC.
8.5.1.1.1 SYNC Interrupt
operating mode does not change, as shown in Figure 58. Figure 58. SYNC Interrupt
8.5.1.2 I2C Mode
slave device acknowledges master commands, and upon master control, receives or transmits data. Typically, the DACx0502 operate as a slave receiver. A master device writes to the DACx0502, a slave receiver. write refer to the master device.
- Fast-mode plus (1.0 Mbps)
not output current. The low-level output current would be 3 mA, similar to the case of standard and fast modes. the ninth clock cycle as shown in Figure 59. Figure 59. Acknowledge and Not Acknowledge on the I2C Bus
8.5.1.2.1 F/S Mode Protocol
- The master initiates data transfer by generating a start condition. The start condition is when a high to-low
recognize a start condition. Figure 60. Start and Stop Conditions Figure 61. Bit Transfer on the I2C Bus
- The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit
Figure 61. All devices recognize the address sent by the master and compare it to their internal fixed acknowledge, the master knows the communication link with a slave has been established.
- The master generates further SCL cycles to transmit (R/W bit 0) or receive (R/W bit 1) data to the slave. In
sequences consists of eight data bits and one acknowledge-bit, and can continue for as long as necessary.
- To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from
8.5.1.2.2 DACx0502 I2C Update Sequence
data bytes (the most significant data byte, MSDB, and least significant data byte, LSDB), as listed in Table 2. Table 2. Update Sequence clock cycles required for a single update to occur. A valid I2C™ address byte selects the DACx0502 devices. Figure 62. I2C Bus Protocol the falling edge of the acknowledge signal that follows the LSDB. is received, the DACx0502 family releases the I2C bus and awaits a new start condition.
address pin and consequently responds to that particular address according to Table 4. Table 3. DACx0502 Address Byte Table 4. Address Format being accessed when writing to or reading from the DACx0502 series. Table 5. DACx0502 Command Byte
Table 6. DACx0502 Data Byte
8.5.1.2.3 DACx0502 I2C Read Sequence
- Send a start or repeated start command with a slave address and the R/W bit set to 0 for writing. The device
- Send a command byte for the register to be read. The device acknowledges this event again.
- Send a repeated start with the slave address and the R/W bit set to 1 for reading. The device acknowledges
- The device writes the MSDB byte of the addressed register. The master must acknowledge this byte.
- Finally, the device writes out the LSDB of the register
read out. All the registers in DACx0502 family can be read out with the exception of SOFT-RESET register. Table 6 shows the read command set. Table 7. Read Sequence
8.6 Register Maps
8.6.1 Registers
Table 8. DACx0502 Register Map
8.6.1.1 NOOP Register (offset = 0h) [reset = 0000h]
Figure 63. NOOP Register Table 9. NOOP Register Field Descriptions
8.6.1.2 DEVID Register (offset = 1h) [reset = 0214h for DAC80502, 1214h for DAC70502, 2214h for
Figure 64. DEVID Register
0 RESOLUTION 0 0 1 0 0 0 0 1 0 1 0 1
Table 10. DEVID Register Field Descriptions
15 RESERVED R 0h RESERVED
8.6.1.3 SYNC Register (offset = 2h) [reset = 0300h]
Figure 65. SYNC Register Table 11. SYNC Register Field Descriptions
9 DAC-B-BRDCAST-EN RW 1h When set to 1 the corresponding DAC is set to update its output
after a serial interface write to the BRDCAST register.
8 DAC-A-BRDCAST-EN RW 1h When set to 1 the corresponding DAC is set to update its output
after a serial interface write to the BRDCAST register.
1 DAC-B-SYNC-EN RW 0h When set to 1, the DAC output is set to update in response to
an LDAC trigger (synchronous mode). (asynchronous mode), default.
0 DAC-A-SYNC-EN RW 0h When set to 1, the DAC output is set to update in response to
an LDAC trigger (synchronous mode). (asynchronous mode), default.
8.6.1.4 CONFIG Register (offset = 3h) [reset = 0000h]
Figure 66. CONFIG Register Table 12. CONFIG Register Field Descriptions
8 REF-PWDWN RW 0h When set to 1 disables the device internal reference
1 DAC-B-PWDWN RW 0h When set to 1, the corresponding DAC in power-down mode and
output is connected to GND through a 1-kΩ internal resistor.
0 DAC-A-PWDWN RW 0h When set to 1, the corresponding DAC in power-down mode and
output is connected to GND through a 1-kΩ internal resistor.
8.6.1.5 GAIN Register (offset = 4h) [reset = 0003h]
Figure 67. GAIN Register Table 13. GAIN Register Field Descriptions
8 REF-DIV RW 0h The reference voltage to the device (either from the internal or
When cleared to 0 the reference voltage is unaffected.
1 BUFF-B-GAIN RW 1h When set to 1 the buffer amplifier for corresponding DAC has a
0 BUFF-A-GAIN RW 1h When set to 1 the buffer amplifier for corresponding DAC has a
8.6.1.6 TRIGGER Register (offset = 5h) [reset = 0000h]
Figure 68. TRIGGER Register Table 14. TRIGGER Register Field Descriptions
4 LDAC W 0h Set this bit to 1 to synchronously load those DACs who have
default state. This is a self resetting bit.
8.6.1.7 BRDCAST Register (offset = 6h) [reset = 0000h for RSTSEL = 0, or reset = 8000h for RSTSEL = 1]
Figure 69. BRDCAST Register Table 15. BRDCAST Register Field Descriptions its active register data to the BRDCAST-DATA one.
8.6.1.8 STATUS Register (offset = 7h) [reset = 0000h]
Figure 70. STATUS Register Table 16. STATUS Register Field Descriptions reference and supply pins is below a minimum analog threshold. difference is above the analog threshold.
8.6.1.9 DAC-n Register (offset = 8h–9h) [reset = 0000h for RSTSEL = 0, or reset = 8000h for RSTSEL = 1]
Figure 71. DAC-n Register Table 17. DAC-A Data Register Field Descriptions (8h) Table 18. DAC-B Data Register Field Descriptions (9h)
9 Application and Implementation
validate and test their design implementation to confirm system functionality.
9.1 Application Information
Generating accurate, stable programmable dc voltages is a key requirement in most precision end equipment. automation and control, test and measurement, and more.
9.2 Typical Application
calibration simple. The integrated reference and the small package make the design very compact. Figure 72. Battery Test Equipment
9.2.1 Design Requirements
- DAC output range: 0 V to 2.5 V
- DAC output accuracy after calibration: 0.05%FSR
- Operating temperature: 0°C to 100°C
9.2.2 Detailed Design Procedure
of 1 for an output range of 2.5 V. The reference divider is 1. Select the 16-bit DAC80502 for the best accuracy.
- TCOE is the temperature drift of the offset error.
- TCGE is the temperature drift of the gain error.
- EREF is the initial accuracy of the reference.
- TCREF is the temperature drift of the reference.
- GAIN is the gain setting of the DAC in combination with the reference divider. (2) Convert the INL value in LSB to %FSR using Equation 3. (3) Convert the temperature drift values in ppm/°C to %FSR using Equation 4. where
- ∆T is the temperature range. (4) Calculate the total error after the offset and gain of DAC are calibrated using Equation 5 (5) The total error at the DAC output calculated using the previous equations is 0.112%FSR before calibration, and 0.05%FSR after calibration. For better accuracy, perform a temperature calibration. Figure 73 and Figure 74 show the drift in the internal reference voltage and TUE, respectively over 0°C to 100°C.
9.2.3 Application Curves
Figure 73. Internal Reference vs Temperature Figure 74. TUE vs Temperature
9.3 System Examples
series resistor on the digital lines so that the current flow on the digital lines is limited to ±10 mA on any pin.
9.3.1 SPI Connection to a Processor
of the digital signals, and in turn, help in minimizing the digital feedthrough of the DAC. Figure 75. SPI Connection to a Processor
9.3.2 I2C Interface Connection to a Processor
increased power consumption. Figure 76. I2C Interface Connection to a Processor
DAC80502, DAC70502, DAC60502 www.ti.com SBAS793A –NOVEMBER 2019–REVISED APRIL 2020 Product Folder Links: DAC80502 DAC70502 DAC60502 Submit Documentation FeedbackCopyright © 2019–2020, Texas Instruments Incorporated
9.4 What To Do and What Not To Do
9.4.1 What To Do
- When using an external reference, disable the internal reference. This step must be the first step after power on, especially when the external reference is greater than the 2.5-V internal reference.
- Maintain the required headroom between the reference voltage and VDD.
- Use the reference divider when the headroom exceeds the limit.
9.4.2 What Not To Do
- Do not use an external reference when the internal reference is on. There is no current limit on the internal reference.
9.5 Initialization Setup
The DACx0502 requires a simple software initialization process based on the interface, power supply, and reference selection. The initialization steps are as follows: 1. When using an external reference, disable the internal reference. 2. Divide the reference by two when the reference voltage exceeds the headroom required from VDD. For example, when using 3.3-V VDD and the internal reference of 2.5 V, the DAC outputs are disabled unless the reference is divided by two. 3. Set the output gain. 4. Write to the DAC register. The following text shows the pseudocode to get started with the DACx0502: //SPI Settings //Mode: Mode-1 (CPOL: 0, CPHA: 1) //CS Type: Active Low, Per Packet //Frame length: 24 //SYNTAX: <WRITE REGISTER (HEX ADDRESS)>, <HEX DATA> //Disable internal reference (only in case of external reference) WRITE CONFIG (0x03), 0x0100 //Select REFDIV=1 (reference divided by 2) and GAIN=1 (gain at both the DAC outputs is 2) WRITE GAIN (0x04), 0x0103 //Write mid-code to DACA WRITE DAC-A (0x08), 0x7FFF //Write Full-code to DACB WRITE DAC-B (0x09), 0xFFFF
10 Power Supply Recommendations
Characteristics section. The power supply must meet the aforementioned current requirements.
11 Layout
11.1 Layout Guidelines
- Bypass the VDD to ground with a low ESR ceramic bypass capacitor. The typical recommended bypass capacitance is 0.1-µF to 0.22-µF ceramic capacitor, with a X7R or NP0 dielectric.
- Place power supplies and REF bypass capacitors close to the pins to minimize inductance and optimize performance.
- Use a high-quality, ceramic-type NP0 or X7R for optimal performance across temperature, and a very low dissipation factor.
- The digital and analog sections must have proper placement with respect to the digital pins and analog pins of the DACx0502 devices. The separation of analog and digital blocks minimizes coupling into neighboring blocks, as well as interaction between analog and digital return currents.
11.2 Layout Example
Figure 77. Layout Example
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
12.2 Related Links
tools and software, and quick access to sample or buy. Table 19. Related Links
12.3 Receiving Notification of Documentation Updates
changed. For change details, review the revision history included in any revised document.
12.4 Support Resources
from the experts. Search existing answers or ask your own question to get the quick design help you need. not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com 9-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DAC60502DRXR Active Production WSON (DRX) | 10 3000 | LARGE T&R Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 125 D652 DAC60502DRXR.A Active Production WSON (DRX) | 10 3000 | LARGE T&R Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 125 D652 DAC60502DRXR.B Active Production WSON (DRX) | 10 3000 | LARGE T&R Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 125 D652 DAC60502DRXT Active Production WSON (DRX) | 10 250 | SMALL T&R Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 125 D652 DAC60502DRXT.A Active Production WSON (DRX) | 10 250 | SMALL T&R Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 125 D652 DAC60502DRXT.B Active Production WSON (DRX) | 10 250 | SMALL T&R Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 125 D652 DAC70502DRXR Active Production WSON (DRX) | 10 3000 | LARGE T&R Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 125 D752 DAC70502DRXR.A Active Production WSON (DRX) | 10 3000 | LARGE T&R Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 125 D752 DAC70502DRXR.B Active Production WSON (DRX) | 10 3000 | LARGE T&R Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 125 D752 DAC70502DRXT Active Production WSON (DRX) | 10 250 | SMALL T&R Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 125 D752 DAC70502DRXT.A Active Production WSON (DRX) | 10 250 | SMALL T&R Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 125 D752 DAC70502DRXT.B Active Production WSON (DRX) | 10 250 | SMALL T&R Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 125 D752 DAC80502DRXR Active Production WSON (DRX) | 10 3000 | LARGE T&R Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 125 D852 DAC80502DRXR.B Active Production WSON (DRX) | 10 3000 | LARGE T&R Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 125 D852 DAC80502DRXT Active Production WSON (DRX) | 10 250 | SMALL T&R Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 125 D852 DAC80502DRXT.B Active Production WSON (DRX) | 10 250 | SMALL T&R Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 125 D852 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. Addendum-Page 1
www.ti.com 9-Nov-2025 (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 17-Apr-2023 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 17-Apr-2023 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC60502DRXR WSON DRX 10 3000 205.0 200.0 33.0 DAC60502DRXT WSON DRX 10 250 205.0 200.0 33.0 DAC70502DRXR WSON DRX 10 3000 205.0 200.0 33.0 DAC70502DRXT WSON DRX 10 250 205.0 200.0 33.0 DAC80502DRXR WSON DRX 10 3000 205.0 200.0 33.0 DAC80502DRXT WSON DRX 10 250 205.0 200.0 33.0 Pack Materials-Page 2
www.ti.com PACKAGE OUTLINE C 10X 0.30 0.18 10X 1.1 0.9
0.8 MAX
0.5 0.05 0.00 A 2.6 2.4 B 2.6 2.4 (0.2) TYP 4223856/B 01/2020 WSON - 0.8 mm max heightDRX0010A PLASTIC SMALL OUTLINE - NO LEAD PIN 1 INDEX AREA SEATING PLANE 0.08 C 5 6 PIN 1 ID (45 X0.15) 0.1 C A B 0.05 C SYMM SYMM NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. SCALE 5.000
www.ti.com EXAMPLE BOARD LAYOUT
0.07 MIN
0.07 MAX
10X (1.2) 10X (0.24) (1.7) 8X (0.5) 4223856/B 01/2020 WSON - 0.8 mm max heightDRX0010A PLASTIC SMALL OUTLINE - NO LEAD SYMM 5 6 SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:30X NOTES: (continued) 3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). SOLDER MASK OPENING SOLDER MASK METAL UNDER SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING SOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED) EXPOSED METAL
www.ti.com EXAMPLE STENCIL DESIGN 10X (1.2) 10X (0.24) 8X (0.5) (1.7) 4223856/B 01/2020 WSON - 0.8 mm max heightDRX0010A PLASTIC SMALL OUTLINE - NO LEAD NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:30X SYMM 5 6 SYMM
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