DAC8043 TI | Alldatasheet
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Technical content
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 DAC8043
FEATURES
l 12-BIT ACCURACY IN 8-PIN SOIC l FAST 3-WIRE SERIAL INTERFACE l LOW INL AND DNL: ±1/2 LSB max l GAIN ACCURACY TO ±1LSB max l LOW GAIN TEMPCO: 5ppm/ °C max l OPERATES WITH +5V SUPPLY l TTL/CMOS COMPATIBLE l ESD PROTECTED CMOS 12-Bit Serial Input Multiplying DIGITAL-TO-ANALOG CONVERTER
APPLICATIONS
l MICROPROCESSOR CONTROL SYSTEMS l PROGRAMMABLE AMPLIFIER/ ATTENUATORS l DIGITALLY CONTROLLED FILTERS
DESCRIPTION
The DAC8043 is a 12-bit current output multiplying digital-to-analog converter (DAC) that is packaged in a space-saving, surface-mount 8-pin SOIC. Its 3-wire se- rial interface saves additional circuit board space which results in low power dissipation. When used with micro- processors having a serial port, the DAC8043 minimizes the digital noise feedthrough from its input to output. The serial port can be used as a dedicated analog bus and kept inactive while the DAC8043 is in use. Serial inter- facing reduces the complexity of opto or transformer isolation applications. The DAC8043 contains a 12-bit serial-in, parallel-out shift register, a 12-bit DAC register, a 12-bit CMOS DAC, and control logic. Serial input (SRI) data is clocked into the input register on the rising edge of the clock (CLK) pulse. When the new data word had been clocked in, it is loaded into the DAC register by taking the LD input low. Data in the DAC register is converted to an output current by the D/A converter. The DAC8043 operates from a single +5V power supply which makes the DAC8043 an ideal low power, small size, high performance solution for several applications. 12-Bit D/A Converter 12-Bit DAC Register 12-Bit Input Shift Register VREF LD CLK SRI R FB IOUT VDD GND R FB © 1993 Burr-Brown Corporation PDS-1197B Printed in U.S.A. March, 1998 SBAS028
ELECTRICAL CHARACTERISTICS
At VDD = +5V; VREF = +10V; IOUT = GND = 0V; TA = Full Temperature Range specified under Absolute Maximum Ratings, unless otherwise noted. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. PARAMETER SYMBOL CONDITIONS MIN TYP MAX MIN TYP MAX UNITS STATIC PERFORMANCE Resolution N 12 12 Bits Nonlinearity(1) INL ±1 ±1/2 LSB Differential Nonlinearity(2) DNL ±1 ±1/2 LSB Gain Error(3) FSE T A = +25°C ±2 ±1 LSB TA = Full Temp Range ±2 ±2 LSB Gain Tempco(5) TC FSE ±5 ±5 ppm/ °C Power Supply Rejection Ratio PSRR ΔVDD = ±5% ±0.0006 ±0.002 ±0.0006 ±0.002 %/% Output Leakage Current(4) ILKG TA = +25°C ±5 ±5n A TA = Full Temp Range ±100 ±25 nA Zero Scale Error(7, 12) IZSE TA = +25°C 0.03 0.03 LSB TA = Full Temp Range 0.60 0.15 LSB Input Resistance(8) R IN 7 11 15 7 11 15 k Ω AC PERFORMANCE Output Current Settling Time(5, 6) tS TA = +25°C 0.25 1 0.25 1 µs Digital-to-Analog Glitch V REF = 0V 2 20 2 20 nVs Energy(5, 10) QI OUT = Load = 100Ω C EXT = 13pF DAC Register Loaded Alternately with all 0s and all 1s Feedthrough Error(5, 11) FT V REF = 20Vp-p at f = 10kHz 0.7 1 0.7 1 mVp-p (VREF to IOUT ) Digital Input = 0000 0000 0000 TA = +25°C Total Harmonic Distortion(5) THD V REF = 6VRMS at 1kHz –85 –85 dB DAC Register Loaded with all 1s Output Noise Voltage Density(5, 13) eN 10Hz to 100kHz 17 17 nV/ √Hz Between RFB and IOUT DIGITAL INPUTS Digital Input High V IH 2.4 2.4 V Digital Input Low V IL 0.8 0.8 V Input Leakage Current(9) IIL VIN = 0V to +5V ±1 ±1 µA Input Capacitance(5, 11) C IN VIN = 0V 8 8 pF ANALOG OUTPUTS Output Capacitance(5) C OUT Digital Inputs = VIH 110 110 pF Digital Inputs = VIL 80 80 pF TIMING CHARACTERISTICS (5, 14) Data Setup Time t DS TA = Full Temperature Range 40 40 ns Data Hold Time t DH TA = Full Temperature Range 80 80 ns Clock Pulse Width High t CH TA = Full Temperature Range 90 90 ns Clock Pulse Width Low t CL TA = Full Temperature Range 120 120 ns Load Pulse Width t LD TA = Full Temperature Range 120 120 ns LSB Clock into Input Register to Load DAC Register Time t ASB TA = Full Temperature Range 0 0 ns POWER SUPPLY Supply Voltage V DD 4.75 5 5.25 4.75 5 5.25 V Supply Current I DD Digital Inputs = VIH or VIL 500 500 µA Digital Inputs = 0V or VDD 100 100 µA NOTES: (1) ±1/2 LSB = ±0.012% of Full Scale. (2) All grades are monotonic to 12-bits over temperature. (3) Using internal feedback resistor. (4) Applies to IOUT ; All digital inputs = 0V. (5) Guaranteed by design and not tested. (6) IOUT Load = 100Ω , CEXT = 13pF, digital input = 0V to VDD or VDD to 0V. Extrapolated to 1/2 LSB: tS = propagation delay (tPD ) + 9τ where τ = measured time constant of the final RC decay. (7) VREF = +10V, all digital inputs = 0V. (8) Absolute temperature coefficient is less than ±50ppm/°C. (9) Digital inputs are CMOS gates: IIN is typically 1nA at +25°C. (10) VREF = 0V, all digital inputs = 0V to VDD or VDD to 0V. (11) All digital inputs = 0V. (12) Calculated from worst case RREF : IZSE (in LSBs) = (RREF X ILKG X 4096)/VREF . (13) Calculations from en = √4K TRB where: K = Boltzmann constant, J/°K, R = resistance, Ω . T = Resistor temperature, °K, B = bandwidth, Hz. (14) Tested at VIN = 0V or VDD .
PARAMETER SYMBOL CONDITIONS LIMIT UNITS STATIC ACCURACY Resolution N 12 Bits min Integral Nonlinearity INL ±1 LSB max Differential Nonlinearity DNL ±1 LSB max Gain Error G FSE Using Internal Feedback Resistor ±2 LSB max Power Supply Rejection Ratio PSRR ΔVDD = ±5% ±0.002 %/% max Output Leakage Current (IOUT )I LKG Digital Inputs = VIL ±5 nA max REFERENCE INPUT Input Resistance R IN 7/15 k Ω min/max DIGITAL INPUTS Digital Input HIGH V IH 2.4 V min Digital Input LOW V IL 0.8 V max Input Leakage Current I IL VIN = 0V to VDD ±1 µA max POWER SUPPLY Supply Current I DD Digital Inputs = VIH or VIL 500 µA max Digital Inputs = 0V to VDD 100 µA max NOTE: Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. WAFER TEST LIMITS At VDD = +5V; VREF = +10V; IOUT = GND = 0V; TA = +25°C. ELECTROSTATIC DISCHARGE SENSITIVITY Any integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degrada- tion to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. Digital Inputs: All digital inputs of the DAC8043 incorpo- rate on-chip ESD protection circuitry. This protection is designed and has been tested to withstand five 2500V positive and negative discharges (100pF in series with 1500Ω ) applied to each digital input. Analog Pins: Each analog pin has been tested to Burr- Brown’s analog ESD test consisting of five 1000V positive and negative discharges (100pF in series with 1500Ω ) ap- plied to each pin. VREF and RFB show some sensitivity. ABSOLUTE MAXIMUM RATINGS Operating Temperature Range CAUTION: 1. Do not apply voltages higher than VDD or less than GND potential on any terminal except VREF (Pin 1) and RFB (Pin 2). 2. The digital control inputs are ESD protected: however, permanent damage may occur on unprotected units from high-energy electrostatic fields. Keep units in conduc- tive foam at all times until ready to use. 3. Use proper anti-static handling procedures. 4. Absolute Maximum Ratings apply to both packaged devices. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Top View 8-Pin SOIC PIN CONFIGURATION CLK SRI LD VDD1 R FB IOUT GND VREF PACKAGE/ORDERING INFORMATION PACKAGE TEMPERATURE DRAWING PRODUCT INL RANGE PACKAGE NUMBER (1) DAC8043U 1LSB –40 °C to +85°C 8-pin SOIC 182 DAC8043UC 1/2LSB –40 °C to +85°C 8-pin SOIC 182 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book.
WRITE CYCLE TIMING DIAGRAM SRI Bit 1 MSB (1) Bit 2 Bit 11 Bit 12 LSB tDH tCH tCL 1CLK INPUT LD Load Serial Data Into Input Register Load Input Register's Data Into DAC Register tDS 2 11 NOTE: (1) Data loaded MSB first. tASB tLD
LINEARITY ERROR vs DIGITAL CODE Digital Input Code (Decimal) 0 1024 2048 3072 4096 0.75 0.5 0.25 –0.25 –0.5 –0.75 Linearity Error (LSB) TA = +25°C VREF = +10V DNL ERROR vs REFERENCE VOLTAGE 0.5 0.25 –0.25 –0.5 DNL (LSB) VREF (V) 24 68 1 0 TOTAL HARMONIC DISTORTION vs FREQUENCY (Multiplying Mode) Frequency (Hz) 100 1000 10000 THD (dB) –20 –40 –60 –80 –100 –120 VDD = +5V VIN = 6Vrms TA = +25°C SUPPLY CURRENT vs LOGIC INPUT VOLTAGE 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 IDD (mA) VIN (V) 01234 VDD = +5V GAIN vs FREQUENCY Gain (dB) –20 –40 –60 –80 –100 –120 Frequency (Hz) 1k 10k 100k 1M 10M Digital Input = 1111 1111 1111 Digital Input = 0000 0000 0000 VDD = +5V VREF = 100mV TA = +25°C LINEARITY ERROR vs REFERENCE VOLTAGE 0.5 0.25 –0.25 –0.5 INL (LSB) VREF (V) 2468 1 0 TYPICAL PERFORMANCE CURVES At VDD = +5V; VREF = +10V; IOUT = GND = 0V; TA = Full Temperature Range specified under Absolute Maximum Ratings, unless otherwise noted.
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) DAC8043U ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DAC8043U/2K5 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DAC8043U/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DAC8043UC ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DAC8043UC/2K5 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DAC8043UC/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DAC8043UCG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DAC8043UG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 16-Feb-2009 Addendum-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC8043U/2K5 SOIC D 8 2500 346.0 346.0 29.0 DAC8043UC/2K5 SOIC D 8 2500 346.0 346.0 29.0 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 Pack Materials-Page 2
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