DAC8043A AD | Alldatasheet

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REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a DAC8043A Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 12-Bit Serial Input Multiplying D/A Converter FUNCTIONAL BLOCK DIAGRAM 12-BIT SHIFT REGISTER DAC REG DAC DAC8043A VDD VREF LD CLK SRI GND IOUT R FB

FEATURES

Compact SO-8 and TSSOP Packages True 12-Bit Accuracy +5 V Operation @ <10 mA Fast 3-Wire Serial Input Fast 1 ms Settling Time

2.4 MHz 4-Quadrant Multiply BW

Pin-for-Pin Upgrade for DAC8043 Standard and Rotated Pinout

APPLICATIONS

Ideal for PLC Applications in Industrial Control Programmable Amplifiers and Attenuators Digitally Controlled Calibration and Filters Motion Control Systems GENERAL DESCRIPTION The DAC8043A is an improved high accuracy 12-bit multiply- ing digital-to-analog converter in space-saving 8-lead packages. Featuring serial input, double buffering and excellent analog performance, the DAC8043A is ideal for applications where PC board space is at a premium. Improved linearity and gain error performance permit reduced parts count through the elimina- tion of trimming components. Separate input clock and load DAC control lines allow full user control of data loading and analog output. The circuit consists of a 12-bit serial-in/parallel-out shift regis- ter, a 12-bit DAC register, a 12-bit CMOS DAC and control logic. Serial data is clocked into the input register on the rising edge of the CLOCK pulse. When the new data word has been clocked in, it is loaded into the DAC register with the LD input pin. Data in the DAC register is converted to an output current by the D/A converter. Consuming only 10 mA from a single +5 V power supply, the DAC8043A is the ideal low power, small size, high performance solution to many application problems. The DAC8043A is specified over the extended industrial (–40°C to +85°C) temperature range. DAC8043A is available in plastic DIP, and the low profile 1.75 mm height SO-8 surface mount packages. The DAC8043AFRU is available for ultra- compact applications in a thin 1.1 mm TSSOP-8 package. CODE INL – LSB 0.1 –0.1 0 1024 2048 3072 4096 –0.5 0.5 0.4 0.3 0.2 –0.2 –0.3 –0.4 512 1536 2560 3584 TA = +258C, +858C, –408C VDD = +5V VREF = –10V Figure 1. Integral Nonlinearity Error vs. Code

REV. 0–2– DAC8043A–SPECIFICATIONS Parameter Symbol Condition E Grade F Grade Units STATIC PERFORMANCE Resolution N 12 12 Bits Relative Accuracy INL – 0.5 – 1.0 LSB max Differential Nonlinearity DNL All Grades Monotonic to 12 Bits – 0.5 – 1.0 LSB max Gain Error1 GFSE TA = +25°C, Data = FFFH – 1.0 – 2.0 LSB max TA = –40°C, +85°C, Data = FFFH – 2.0 – 2.0 LSB max Gain Tempco2 TCGFS IOUT Pin Measured – 5 – 5 ppm/ °C max Output Leakage Current I LKG Data = 000H, IOUT Pin Measured – 5 – 5 nA max TA = –40°C, +85°C, Data = 000H, IOUT Pin Measured – 25 – 25 nA max Zero-Scale Error 3 IZSE Data = 000H 0.03 0.03 LSB max TA = –40°C, +85°C, Data = 000H 0.15 0.15 LSB max REFERENCE INPUT Input Resistance R REF Absolute Tempco < 50 ppm/ °C 7/15 7/15 k W min/max Input Capacitance 2 CREF 5 5 pF typ ANALOG OUTPUT Output Capacitance 2 COUT Data = 000H 25 25 pF typ Data = FFFH 30 30 pF typ DIGITAL INPUTS Digital Input Low V IL 0.8 0.8 V max Digital Input High V IH 2.4 2.4 V min Input Leakage Current I IL VLOGIC = 0 V to +5 V 0.001/ – 1 0.001/ – 1 mA typ/max Input Capacitance 2 CIL VLOGIC = 0 V 10 10 pF max INTERFACE TIMING 2, 4 Data Setup t DS 10 10 ns min Data Hold t DH 5 5 ns min Clock Width High t CH 25 25 ns min Clock Width Low t CL 25 25 ns min Load Pulsewidth t LD 25 25 ns min LSB CLK to LD DAC t ASB 0 0 ns min AC CHARACTERISTICS 1, 2 Output Current Settling Time t S To – 0.01% of Full Scale, Ext Op Amp OP42 1 1 ms max DAC Glitch Q Data = 000 H to FFFH to 000H, VREF = 0 V 20 20 nVs max Feedthrough (VOUT/VREF)F T V REF = 20 V p-p, Data = 000 H, f = 10 kHz 1 1 mV p-p Total Harmonic Distortion THD V REF = 6 V rms, Data = FFF H, f = 1 kHz –85 –85 dB typ Output Noise Density 5 en 10 Hz to 100 kHz Between R FB and IOUT 17 17 nV/ ÖHz max Multiplying Bandwidth BW –3 dB, V OUT/VREF, VREF = 100 mV rms, Data = FFF H 2.4 2.4 MHz typ SUPPLY CHARACTERISTICS Power Supply Range V DD RANGE 4.5/5.5 4.5/5.5 V min/max Positive Supply Current I DD VLOGIC = 0 V or VDD 10 10 mA max Power Dissipation P DISS VLOGIC = 0 V or VDD 50 50 mW max Power Supply Sensitivity PSS DVDD = – 5% 0.002 0.002 %/% max NOTES 1Using internal feedback resistor R FB, see Figure 19 test circuit with V REF = +10 V. 2These parameters are guaranteed by design and not subject to production testing. 3Calculated from worst case R REF: IZSE(LSB) = (R REF · ILKG · 4096)/VREF. 4All input control signals are specified with t R = tF = 2 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. 5Calculation from e n = Ö4KTRB where: K = Boltzmann Constant (J/ °K), R = Resistance ( W ), T = Resistor Temperature ( °K), B = 1 Hz Bandwidth. Specifications subject to change without notice. ELECTRICAL CHARACTERISTICS (@ VDD = +5 V, VREF = +10 V, –40 8C < TA < +858C, unless otherwise noted.)

REV. 0 DAC8043A –3– ABSOLUTE MAXIMUM RATINGS* Thermal Resistance qJA *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PIN FUNCTION DESCRIPTIONS #(*) Name Function 1(7) V REF DAC Reference Input Pin. Establishes DAC full- scale voltage. Constant input resistance versus code. 2 (8) R FB Internal Matching Feedback Resistor. Connect to external op amp output. 3 (1) I OUT DAC Current Output, full-scale output 1 LSB less than reference input voltage –V REF. 4 (2) GND Analog and Digital Ground. 5 (3) LD Load Strobe, Level-Sensitive Digital Input. Transfers shift-register data to DAC register while active low. See truth table for operation. 6 (4) SRI 12-Bit Serial Register Input, data loads directly into the shift register MSB first. Extra leading bits are ignored. 7 (5) CLK Clock Input, positive-edge clocks data into shift register. 8 (6) V DD Positive Power Supply Input. Specified range of operation +5 V – 10%. *Note Pin numbers in parenthesis represent the rotated pinout of the DAC8043A1ES and DAC8043A1FS models. DAC8043AE/F PIN CONFIGURATIONS 4 5 SO-8 DAC8043A ES/FS 4 5 TSSOP-8 DAC8043A FRU TOP VIEW (Not to Scale) IOUT GND LD R FB VREF VDD CLK SRI PDIP-8 DAC8043A EP/FP DAC8043A1E AND DAC8043A1F PIN CONFIGURATION (Rotated Pinout) TOP VIEW (Not to Scale) IOUT GND LD R FB VREF VDD CLKSRI SO-8 DAC8043A1ES DAC8043A1FS ORDERING GUIDE Model (LSB) Temp Description Option DAC8043AEP – 0.5 –40/+85 °C 8-Lead P-DIP N-8 DAC8043AES – 0.5 –40/+85 °C 8-Lead SOIC SO-8 DAC8043A1ES – 0.5 –40/+85 °C 8-Lead SOIC SO-8 DAC8043AFP – 1.0 –40/+85 °C 8-Lead P-DIP N-8 DAC8043AFS – 1.0 –40/+85 °C 8-Lead SOIC SO-8 DAC8043A1FS – 1.0 –40/+85 °C 8-Lead SOIC* SO-8 DAC8043AFRU – 1.0 –40/+85 °C TSSOP-8 RU-8 NOTES The DAC8043A contains 346 transistors. The die size measures 70.3 mil · 57.1 mil, 4014 sq mil. *The DAC8043A1ES and DAC8043A1FS have a rotated pinout. Line 1: yww (data code: year, work week). Line 2: 8043A. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the DAC8043A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE

61 LSB

Figure 2. Timing Diagram u positive logic transition. switches in the R-2R DAC ladder. Figure 3. Total Unadjusted Error Histogram Figure 4. Full-Scale Output Tempco Histogram