DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 16
Technical content
12-Bit Serial Input Multiplying CMOS Digital-to-Analog Converter DAC8043 Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2011 Analog Devices, Inc. All rights reserved.
FEATURES
12-bit accuracy in an 8-lead PDIP and SOIC package Fast serial data input Double data buffers Low ±½ LSB maximum INL and ±1 LSB maximum DNL Maximum gain error: 2 LSB Low ±5 ppm/°C maximum tempco ESD resistant Low cost Available in die form
APPLICATIONS
Process control and industrial automation Programmable amplifiers and attenuators Digitally controlled filters FUNCTIONAL BLOCK DIAGRAM 12-BIT DAC 12-BIT DAC REGISTER 12-BIT SHIFT REGISTER DAC8043 RFB VREF LD CLK SRI GND VDD IOUT RFB 00271-001 Figure 1. GENERAL DESCRIPTION The DAC8043 is a high accuracy 12-bit CMOS multiplying DAC in a space-saving 8-lead PDIP package. Featuring serial data input, double buffering, and excellent analog performance, the DAC8043 is ideal for applications where PC board space is at a premium. In addition, improved linearity and gain error performance permit reduced parts count through the elimination of trimming components. Separate input clock and load DAC control lines allow full user control of data loading and analog output. The circuit consists of a 12-bit serial-in, parallel-out shift register, a 12-bit DAC register, a 12-bit CMOS DAC, and control logic. Serial data is clocked into the input register on the rising edge of the CLK pulse. When the new data word has been clocked in, it is loaded into the DAC register with the LD input pin. Data in the DAC register is converted to an output current by the digital-to-analog converter (DAC). The fast interface timing of the DAC8043 may reduce timing design considerations while minimizing microprocessor wait states. For applications requiring an asynchronous clear function or more versatile microprocessor interface logic, refer to the AD5443. Operating from a single 5 V power supply, the DAC8043 is the ideal low power, small size, high performance solution to many application problems. It is available in a PDIP package that is compatible with auto-insertion equipment. There is also a 16-lead SOIC pa ckag e available.
Rev. E | Page 2 of 16 TABLE OF CONTENTS
REVISION HISTORY
1/11—Rev. D to Rev. E 3/03—Data Sheet Changed from Rev. C to Rev. D.
Rev. E | Page 3 of 16 SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VDD = 5 V; VREF = 10 V; IOUT = GND = 0 V; TA = full temperature range specified under the Absolute Maximum Ratings, unless otherwise noted. Table 1. Parameter Symbol Conditions Min Typ Max Unit STATIC ACCURACY Resolution N 12 Bits Nonlinearity1 INL DAC8043G ±½ LSB DAC8043F 1 LSB Differential Nonlinearity2 DNL ±1 LSB Gain Error3 GFSE TA = 25°C 2 LSB TA = full temperature range, all grades 2 LSB Gain Tempco (ΔGain/∆Temp)4 TCGFS ±5 ppm/°C Power Supply Rejection Ratio (ΔGain/ΔVDD) Output Leakage Current5 ILKG TA = 25°C ±5 nA TA = full temperature range ±25 nA Zero Scale Error6, 7 IZSE TA = 25°C 0.03 LSB TA = full temperature range 0.15 LSB Input Resistance8 RIN 7 11 15 kΩ AC PERFORMANCE Output Current Settling Time4, 9 tS TA = 25°C, VREF = 0 V 0.25 1 μs Digital-to-Analog Glitch Energy4, 10 Q IOUT load = 100 Ω, CEXT = 13 pF, DAC register loaded alternately with all 0s and all 1s 2 20 nVs Feedthrough Error (VREF to IOUT)4, 11 FT VREF = 20 V p-p @ f = 10 kHz, digital input = 0000 0000 0000 0.7 1 mV p-p TA = 25°C Total Harmonic Distortion4 THD VREF = 6 V rms @ 1 kHz, DAC register loaded with all 1s –85 dB Output Noise Voltage Density4, 12 en 10 Hz to 100 kHz between RFB and IOUT 17 nV/√Hz DIGITAL INPUTS Digital Input High VIN 2.4 V Low VIL 0.8 V Input Leakage Current13 IIL VIN = 0 V to +5 V ±1 μA Input Capacitance4, 11 CIN VIN = 0 V 8 pF ANALOG OUTPUTS Output Capacitance4 COUT Digital inputs = VIH 110 pF Digital inputs = VIL 80 pF TIMING CHARACTERISTICS4, 14 Data Setup Time tDS TA = full temperature range 40 ns Data Hold Time tDH TA = full temperature range 80 ns Clock Pulsewidth High tCH TA = full temperature range 90 ns Clock Pulsewidth Low tCL TA = full temperature range 120 ns Load Pulsewidth tLD TA = full temperature range 120 ns LSB Clock Into Input Register to Load DAC Register Time tASB TA = full temperature range 0 ns
Rev. E | Page 4 of 16 Parameter Symbol Conditions Min Typ Max Unit POWER SUPPLY Supply Voltage VDD 4.75 5 5.25 V Supply Current IDD Digital inputs = V IH or VIL 500 μA Digital inputs = 0 V or V DD 100 μA 1 ±1/2 LSB = ±0.012% of full scale. 2 All grades are monotonic to 12 bits over temperature. 3 Using internal feedback resistor. 4 Guaranteed by design and not tested. 5 Applies to IOUT; all digital inputs = 0 V. 6 VREF = 10 V; all digital inputs = 0 V. 7 Calculated from worst-case RREF: IZSE (in LSBs) = (RREF × ILKG × 4096)/VREF. 8 Absolute temperature coefficient is less than 300 ppm/°C. 9 IOUT load = 100 Ω , CEXT = 13 pF, digital input = 0 V to VDD or VDD to 0 V. Extrapolated to ½ LSB; tS = propagation delay (tPD) + 9τ where τ = measured time constant of the final RC decay. 10 VREF = 0 V, all digital inputs = 0 V to VDD or VDD to 0 V. 11 All digit inputs = 0 V.
12 Calculations from en = √4K TRB
where: K = Boltzmann constant, J/°K, R = resistance, Ω, T = resistor temperature, °K, B = bandwidth, Hz. 13 Digital inputs are CMOS gates; IIN is typically 1 nA at 25°C. 14 Tested at VIN = 0 V or VDD. WAFER TEST LIMITS VDD = 5 V , VREF = 10 V; IOUT = GND = 0 V , TA = 25°C. Table 2. DAC8043GBC Limit Parameter1 Symbol Conditions Min Typ Max Unit STATIC ACCURACY Resolution N 12 Bits Integral Nonlinearity INL ±1 LSB Differential Nonlinearity DNL ±1 LSB Gain Error GFSE Using internal feedback resistor ±2 LSB Power Supply Rejection Ratio PSRR ΔV DD = ±5% ±0.002 %/% Output Leakage Current (IOUT) I LKG Digital inputs = V IL ±5 nA REFERENCE INPUT Input Resistance RIN 7 15 kΩ DIGITAL INPUTS Digital Input High VIH 2.4 V Digital Input Low VIL 0.8 V Input Leakage Current IIL V IN = 0 V to VDD ±1 μA POWER SUPPLY Supply Current IDD Digital inputs = V IN or VIL 500 μA Digital inputs = 0 V or VDD 100 μA 1 Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult a factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
TA = 25°C, unless otherwise noted.
- Do not apply voltages higher than VDD or less than GND
potential on any terminal except VREF and RFB.
- The digital control inputs are Zener-protected; however,
foam at all times until ready to use.
- Use proper antistatic handling procedures.
- Absolute Maximum Ratings apply to both packaged devices
soldered in a circuit board for surface-mount packages. Table 4. Thermal Resistance
Rev. E | Page 9 of 16 TERMINOLOGY Integral Nonlinearity (INL) This is the single most important DAC specification. Analog Devices, Inc., measures INL as the maximum deviation of the analog output (from the ideal) from a straight line drawn between the end points. It is expressed as a percent of full-scale range or in terms of LSBs. Refer to the Analog Devices Glossary of EE Terms for additional digital-to-analog converter definitions. Interface Logic Information The DAC8043 has been designed for ease of operation. The timing diagram (see Figure 12) illustrates the input register loading sequence. Note that the most significant bit (MSB) is loaded first. Once the input register is full, the data is transferred to the DAC register by taking LD momentarily low.
have a low noise level with no transients greater than 17 V . voltage range of the op amp or ±25 V , whichever is lowest. Figure 16. Unipolar Operation with High Accuracy Op Amp (2-Quadrant) Figure 17. Unipolar Operation with Fast Op Amp and Gain Error Trimming Gain error may be trimmed by adjusting R1, as shown in Figure 17. to yield the desired full-scale output. Table 6. Unipolar Code Table1, 2
2048 REF
1 Nominal full scale for Figure 16 and Figure 17 circuits is given by
2 Nominal LSB magnitude for Figure 16 and Figure 17 circuits is given by
Table 7. Bipolar (Offset Binary) Code Table
1 Nominal full scale for Figure 19 circuits is given by
2 Nominal LSB magnitude for Figure 19 circuits is given by
and R3 mismatch results in full-scale error. value of R5 until the desired VOUT is achieved. where AX assumes a value of 1 for an on bit and 0 for an off bit.
6 VOUT
Figure 18. Analog/Digital Divider Figure 19. Bipolar Operation (4-Quadrant, Offset Binary)
Rev. E | Page 16 of 16 ORDERING GUIDE Model1, 2 Relative Accuracy Temperature Range Package Description Package Option DAC8043FP ±1 LSB −40°C to +85°C 8-Lead PDIP N-8 DAC8043FPZ ±1 LSB −40°C to +85°C 8-Lead PDIP N-8 DAC8043FSZ ±1 LSB −40°C to +85°C 16-Lead SOIC_W RW-16 DAC8043GP ±½ LSB 0°C to 70°C 8-Lead PDIP N-8 DAC8043GPZ ±½ LSB 0°C to 70°C 8-Lead PDIP N-8 1 Z = RoHS Compliant Part. 2 All commercial and industrial temperature range parts are available with burn-in. ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00271-0-1/11(E)