DAC80004IPW

DAC80004 TI | Alldatasheet

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Technical content

Copyright © 2016, Texas Instruments Incorporated Digital Input Code INL Error (LSB) 0 8192 16384 24576 32768 40960 49152 57344 65536 -1.00 -0.75 -0.50 -0.25 0.00 0.25 0.50 0.75 1.00 D001 Channel A Channel B Channel C Channel D Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DAC80004,DAC70004,DAC60004 SLASED6D –APRIL 2016–REVISED DECEMBER 2017 DACx0004,Quad16-,14-,12-Bit,1LSBINL,Buffered,Voltage-OutputDigital-to-Analog Converters

1 Features

1• True 16-Bit Performance: 1 LSB INL/DNL (Max)

• Ultra Low Glitch Energy: 1 nV-s
• Wide Power-Supply Range: 2.7 V to 5.5 V
• Output Buffer with Rail-to-Rail Operation
• Current Consumption: 1 mA/Channel
• 50-MHz, 4- or 3-Wire SPI Compatible Interface
• SDO Pin for Readback and Daisy Chain
• Power-On Reset to Zero or Mid Scale
• Temperature Range: –40°C to +125°C
• Multiple Packages: – Tiny 14-Pin VSON – 14-Pin TSSOP

2 Applications

• Portable Instrumentation
• PLC Analog Output Module (4-20 mA)
• Closed-Loop Servo Control
• Data Acquisition Systems

3 Description

The DAC80004/70004/60004 (DACx0004) are highly accurate, low-power, voltage-output, quad-channel, 16-, 14-, 12-bit digital-to-analog converters (DACs) respectively. The DACx0004 devices are ensured monotonic by design and offer excellent linearity of less than 1 LSB (Max). The reference input of the DAC is buffered internally using a dedicated reference buffer. The DACx0004 devices incorporate a power-on-reset circuit that ensures the DAC output powers up at zero scale or mid scale depending on status of the POR pin and remains in this state until a valid code is written to the device. These devices consume very low current of 1 mA/channel making them ideal for portable, battery-operated equipment. These devices also contain a power-down feature that reduces current consumption to typically 3 µA at 5 V. The DACx0004 devices use a versatile 4- or 3-wire serial interface that operates at clock rates up to 50 MHz. The DACx0004 devices also include a SDO pin to daisy chain multiple devices. The interface is compatible with standard SPI™ , QSPI™ , Microwire, and digital signal processor (DSP) interfaces. The DACx0004 devices are offered in easy-to-assemble 14-pin TSSOP packages or an ultra small 14-pin VSON package and are fully specified over the extended industrial temperature range of –40°C to 125°C. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) DACx0004 VSON (14) 3.00 mm x 4.00 mm DACx0004 TSSOP (14) 5.00 mm x 4.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. DACx0004 Block Diagram Linearity Error vs Digital Input Code

DAC80004,DAC70004,DAC60004 SLASED6D –APRIL 2016–REVISED DECEMBER 2017 www.ti.com Product Folder Links: DAC80004 DAC70004 DAC60004 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated Table of Contents

9.2 Typical Application - Digitally Controlled Asymmetric

12.1 Receiving Notification of Documentation Updates 30

13 Mechanical, Packaging, and Orderable

4 Revision History

Changes from Revision C (August 2016) to Revision D Page Changes from Revision B (June 2016) to Revision C Page Changes from Revision A (June 2016) to Revision B Page Changes from Original (April 2016) to Revision A Page

DAC80004,DAC70004,DAC60004 www.ti.com SLASED6D –APRIL 2016–REVISED DECEMBER 2017 Product Folder Links: DAC80004 DAC70004 DAC60004 Submit Documentation FeedbackCopyright © 2016–2017, Texas Instruments Incorporated

5 Device Comparison Table

6 Pin Configuration and Functions

CLR 9 Digital Input Clear DAC pin, falling edge sensitive GND 12 Power Ground LDAC 1 Digital Input Load DAC pin, active low POR 6 Digital Input Power-on-reset configuration, Connecting the POR pin to GND powers up all four DACs to zero scale. Connecting this pin to VDD powers up all four DACs to midscale. REFIN 7 Analog Input Voltage reference input for all channels SCLK 14 Digital Input Serial interface shift clock SDIN 13 Digital Input Serial interface digital input SDO 8 Digital Output Serial interface digital output for readback and daisy chaining SYNC 2 Digital Input Serial interface synchronization, active low VDD 3 Power Positive power supply (2.7 V to 5.5 V) VOUTA 4 Analog Output DAC A output VOUTB 11 Analog Output DAC B output VOUTC 5 Analog Output DAC C output VOUTD 10 Analog Output DAC D output

DAC80004,DAC70004,DAC60004 SLASED6D –APRIL 2016–REVISED DECEMBER 2017 www.ti.com Product Folder Links: DAC80004 DAC70004 DAC60004 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Voltage, VDD to GND –0.3 7 V Voltage, digital input or output to GND –0.3 VDD + 0.3 V Voltage, analog input (REFIN) or output (VOUTx) to GND –0.3 VDD + 0.3 V Input current to any pin except supply pins –10 10 mA Maximum junction temperature 150 °C Storage temperature range, Tstg -60 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 VCharged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1000

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Voltage, VDD to GND 2.7 5.5 V Voltage, analog input (REFIN) or output (VOUTx) to GND 2.7 V ≤ VDD ≤ 4.5 V 2.2 VDD – 0.2 V 4.5 V ≤ VDD ≤ 5.5 V 2.2 VDD V Ambient Operating Temperature, TA -40 125 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.4 Thermal Information

THERMAL METRIC(1) DACx0004 UNITDMD (VSON) PW (TSSOP)

14 PINS 14 PINS

RθJA Junction-to-ambient thermal resistance 39.6 99.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 27.3 23.4 °C/W RθJB Junction-to-board thermal resistance 9.0 42.8 °C/W ψJT Junction-to-top characterization parameter 0.3 0.9 °C/W ψJB Junction-to-board characterization parameter 8.9 42.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 6.5 N/A °C/W

DAC80004,DAC70004,DAC60004 www.ti.com SLASED6D –APRIL 2016–REVISED DECEMBER 2017 Product Folder Links: DAC80004 DAC70004 DAC60004 Submit Documentation FeedbackCopyright © 2016–2017, Texas Instruments Incorporated (1) 200 mV headroom is required between REFIN and VDD when 2.7 V ≤ VDD ≤ 4.5 V. (2) Output unloaded (3) End point fit between codes Code 512 to Code 65,024 - DAC80004, Code 128 to Code 16,256 - DAC70004, Code 32 to Code 4064 - DAC60004, Output unloaded. (4) With 100 mV headroom between DAC output and VDD.

7.5 Electrical Characteristics

All minimum/maximum specifications at TA = -40°C to +125°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.5 V ≤ REFIN(1) ≤ VDD, Rload = 5 kΩ to GND, Cload = 200 pF to GND (unless otherwise noted), Digital inputs held at 0 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STATIC PERFORMANCE(2) Resolution DAC80004 16 BitsDAC70004 14 DAC60004 12 INL Relative accuracy(3) ±1 LSB DNL Differential nonlinearity(3) Ensured monotonic ±1 LSB TUE Total unadjusted error(3) TA = +20°C to +40°C 1.5 mV TA = –40°C to +125°C 2 ZCE Zero code error TA = –40°C to +125°C, Code 0d into DAC ±0.2 ±2 mV TA = +25°C, Code 0d into DAC ±0.1 ZCE-TC Zero code error TC TA = –40°C to +125°C ±5 µV/°C OE Offset error(3) TA = +20°C to +40°C ±1.2 mVTA = –40°C to +125°C ±0.2 ±1.8 TA = +25°C ±0.2 OE-TC Offset error drift TA = –40°C to +125°C ±4 µV/°C FSE Full-scale error(4) TA = +20°C to +40°C, Code 65535d into DAC ±0.05 %FSR TA = –40°C to +125°C, Code 65535d into DAC ±0.01 ±0.07 %FSR TA = +25°C ±0.01 FSE-TC Full-scale error drift(4) TA = –40°C to +125°C ±2 ppm FSR/°C GE Gain error(3) TA = –40°C to +125°C ±0.005 ±0.05 %FSR TA = +25°C ±0.005 GE-TC Gain drift TA = –40°C to +125°C ±2 ppm FSR/°C Output voltage drift vs.Time TA = +25°C, Vout = ¾ of full scale, 1900 hr 20 ppm FSR Load Regulation TA = +25°C, Vout =Mid Scale 0.003% PSRR DC Power supply rejection ratio(4) TA = +25°C, Vout = full scale –92 dB

DAC80004,DAC70004,DAC60004 SLASED6D –APRIL 2016–REVISED DECEMBER 2017 www.ti.com Product Folder Links: DAC80004 DAC70004 DAC60004 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated Electrical Characteristics (continued) All minimum/maximum specifications at TA = -40°C to +125°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.5 V ≤ REFIN(1) ≤ VDD, Rload = 5 kΩ to GND, Cload = 200 pF to GND (unless otherwise noted), Digital inputs held at 0 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (5) Time to exit power-down mode into normal mode. Measured from 32nd falling edge SCLK to 90% of DAC final value, Characterized at mid scale. DYNAMIC PERFORMANCE Output voltage settling time ¼ to ¾ scale and ¾ to ¼ scale settling to ±1 LSB, RL = 5 kΩ, Cload = 200 pF to GND 5.8 8 µs Slew rate 1.5 V/µs Power-up time(5) 100 µs Power-on glitch energy Supply slew rate <5 V/msec 8 mV Power-off glitch energy DAC in power down mode (1 kΩ- GND), Supply slew rate <5 V/msec 7 mV Output noise

0.1 Hz to 10 Hz 5 µVpp

100 kHz BW 100 µVRMS Output noise density Measured at 1 kHz 60 nV/√Hz Measured at 10 kHz 55 THD Total harmonic distortion REFIN = 3 V ± 0.2 Vpp, Frequency = 10 kHz, DAC at mid scale, specified by design –80 dB PSRR AC power supply rejection ratio 200 mV 50 Hz and 60 Hz sine wave superimposed on power supply voltage (AC analysis) -90 dB Code change glitch impulse 1 LSB change around major carry, Software LDAC mode 1 nV-s Channel-to-channel AC (analog) crosstalk Full-scale swing on adjacent channel, Hardware LDAC mode 1 nV-s Channel-to-channel DC crosstalk Full-scale swing on adjacent channels, Measured channel at zero scale LSB Full-scale swing on all channel, Measured channel at zero scale 1 Digital crosstalk DAC code mid scale, Adjacent input buffer change from 0000h to FFFFh or vice versa 0.2 nV-S Reference feedthrough REFIN = 3 V ± 0.86 Vpp, Frequency = 100 Hz to 100 kHz, DAC at zero scale –85 dB Digital feedthrough At SCLK = 1 MHz, DAC output static at mid scale 0.2 nV-s OUTPUT CHARACTERISTICS Voltage range 0 VDD V Headroom Output loaded 5 kΩ, DAC code FFFFh 0.1 V Output loaded 0.5 kΩ, DAC code FFFFh 10 %FSR RL Resistive load 0.5 kΩ CL Capacitive load RL = ∞ 1 nF RL = 5 kΩ 2 RO DC output impedance Normal mode 0.5 Ω Power down with 100 kΩ network 100 kΩ Power down with 1 kΩ network 1 kΩ Short circuit current 36 mA

DAC80004,DAC70004,DAC60004 www.ti.com SLASED6D –APRIL 2016–REVISED DECEMBER 2017 Product Folder Links: DAC80004 DAC70004 DAC60004 Submit Documentation FeedbackCopyright © 2016–2017, Texas Instruments Incorporated Electrical Characteristics (continued) All minimum/maximum specifications at TA = -40°C to +125°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.5 V ≤ REFIN(1) ≤ VDD, Rload = 5 kΩ to GND, Cload = 200 pF to GND (unless otherwise noted), Digital inputs held at 0 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOLTAGE REFERENCE INPUT Reference input range 2.7 V ≤ VDD ≤ 4.5 V 2.2 VDD – 0.2 V 4.5 V ≤ VDD ≤ 5.5 V 2.2 VDD Reference input current 450 µA Reference input impedance 15 kΩ Reference input capacitance 10 pF MBW Multiplying bandwidth 340 kHz DIGITAL INPUTS VIH High-level input voltage 2.3 V VIL Low-level input voltage 0.7 V Input leakage 0 < VDIGITAL INPUT < VDD ±1 µA Pin capacitance 4 pF DIGITAL OUTPUTS VOH High-level output voltage IOH = 2 mA VDD – 1 V VOL Low-level output voltage IOL = 2 mA 0.7 V Pin capacitance 7 pF POWER SUPPLY REQUIREMENTS VDD Supply voltage 2.7 5.5 V IVDD Supply current TA = –40°C to +125°C, Normal mode 4 5.5 mA TA = –40°C to +125°C, Power-down mode 3 7 µA Power dissipation TA = –40°C to +125°C, Normal mode 20 mW TEMPERATURE RANGE TA Specified performance –40 125 °C

7.6 DACx0004 Timing Requirements

Figure 1. Stand-Alone Timing

Figure 2. Daisy-Chain Timing

7.7 Typical Characteristics

At TA = 25°C, VDD = 5.5 V, REFIN = 5.45 V, DAC outputs unloaded, unless otherwise noted. Figure 3. Linearity Error vs Digital Input Code Figure 4. Differential Linearity Error vs Digital Input Code Figure 5. Linearity Error vs Digital Input Code Figure 6. Differential Linearity Error vs Digital Input Code Figure 7. Total Unadjusted Error vs Digital Input Code Figure 8. Total Unadjusted Error vs Digital Input Code

8 Detailed Description

8.1 Overview

impedance (30 kΩ typical), buffered reference input. The output of the reference buffers drives the R-2R ladders. With the production trim process these devices have excellent dc accuracy and ac performance. Figure 51. DACx0004 Architecture

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Output Amplifier

channel) via SPI command 1010 (see Table 2).

8.3.2 Reference Buffer

these buffers. The integrated reference buffers offers constant impedance of 30 kΩ (typical) at the REFIN pin. This simplifies the external reference drive circuit for the device.

8.3.3 Power-On Reset

is in the process of powering up. At power up all DAC registers are filled with power-on reset code (see Table 1).

8.3.3.1 POR Pin Feature

Configuration and Functions). power up as shown in Table 1. Table 1. DACx0004 Power-On Reset Values

8.3.3.2 Internal Power-On Reset (IPOR) Levels

reset the device on power up. In order to ensure a power-on reset, VDD must be below 0.7 V for at least 1 ms. reset is recommended. When VDD remains above 2.4 V, a power-on reset does not occur.

Figure 52. Relevant Voltage Levels for IPOR Circuit

8.4 Device Functional Modes

8.4.1 Serial Interface

sequences. The input shift register is 32 bits wide.

8.4.1.1 Stand-Alone Mode

8.4.1.1.1 SYNC Interrupt – Stand-Alone Mode

edge, it acts as an interrupt to the write sequence; the shift register resets and the write sequence is discarded. Figure 53. SYNC Interrupt – Stand Alone Operation

8.4.1.1.2 Read-Back Mode

registers can be read if multiple READ commands are issued (see Figure 54). Figure 54. Read-Back Operation

8.4.1.2 Daisy-Chain Mode

Table 3); the SDO pin is set to HIZ when the DSDO bit is set to 0. Figure 55. DACx0004 in Daisy Chain Mode

8.4.1.2.1 SYNC Interrupt – Daisy-Chain Mode

contents, DAC register contents, nor a change in the operating mode occurs (see Figure 56).

Invalid/Interrupted Write Sequence Output/Mode Does Not Update on the Rising SYNC Valid Write Sequence Output/Mode Does Update on the Rising SYNC DAC80004,DAC70004,DAC60004 SLASED6D –APRIL 2016–REVISED DECEMBER 2017 www.ti.com Product Folder Links: DAC80004 DAC70004 DAC60004 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated Device Functional Modes (continued) Figure 56. SYNC Interrupt – Daisy-Chain Operation

8.4.2 SPI Shift Register

Table 3. The DACx0004 accepts DAC code in straight binary format. Note that, the DAC data is left alligned from Table 2. DACx0004 SPI Shift Register Format Table 3. DAC Commands

0 X Disable SDO register

Table 4. Channel Address Bits

DESCRIPTION

1 1 1 1 Select all channel

R2R Ladder Amplifier VOUT X DAC80004,DAC70004,DAC60004 www.ti.com SLASED6D –APRIL 2016–REVISED DECEMBER 2017 Product Folder Links: DAC80004 DAC70004 DAC60004 Submit Documentation FeedbackCopyright © 2016–2017, Texas Instruments Incorporated

8.4.3 DAC Power-Down Modes

The DACx0004 use four modes of operation. These modes are accessed by setting command bits D28 – D24 and power-down register bits D09 and D08. The command bits must be set to 0100 (see Table 3). Once the command bits are set correctly, the four different power-down modes are software programmable by setting bits D09 and D08 in the shift register. Table 5 shows how to control the operating mode with data bits PD1 (D09), PD0 (D08). Table 5. Power-Down Bits 0 0 Normal operation/power up selected channel(s) (Default) 0 1 Power down selected channel(s) 1 kΩ-GND 1 0 Power down selected channel(s) 100 kΩ-GND 1 1 Power down selected channel(s) Hi-Z It is possible to write to the DAC register/buffer of the DAC channel that is powered down. When the DAC channel is then powered up, it powers up to this new value. The advantage of the available power-down modes is that the output impedance of the device is known while it is in power-down mode. As described in Table 5, there are three different power-down options. VOUTX can be connected internally to GND through a 1 kΩ resistor, a 100 kΩ resistor, or open-circuited (Hi-Z). The DAC power- down circuitry is shown in Figure 57. Figure 57. DACx0004 Power Down

8.4.4 CLR Pin Functionality and Software CLEAR Mode

mode bits determine the clear code for all the DACs upon clear operation.

8.4.4.1 DAC Clear Mode Registers

D28 – D24 and clear mode register bits D01 and D00. The command bits must be set to 0101 (see Table 3). or full-scale code, when the CLR pin sees a falling edge or after a software clear command is issued. The user defined clear scale can be set by writing 16-/14-/12- data to 1001 to bits D28 – D24.

DAC80004,DAC70004,DAC60004 SLASED6D –APRIL 2016–REVISED DECEMBER 2017 www.ti.com Product Folder Links: DAC80004 DAC70004 DAC60004 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated Table 6. Clear Mode Bits 0 0 All DACs clear to zero scale (default) 0 1 All DACs clear to mid scale 1 0 All DACs clear to full scale

8.4.5 LDAC Pin Functionality

The DACx0004 devices offer both a software and hardware simultaneous update and control function. The DAC double-buffered architecture has been designed so that new data can be entered for each DAC without disturbing the analog outputs. Data updates can be performed either in synchronous or in asynchronous mode. In asynchronous mode, the LDAC pin is used as an active low signal for simultaneous DAC updates. Multiple single-channel writes can be done in order to set different channel buffers to desired values and then pulse the LDAC pin low to simultaneously update the DAC output registers. Data buffers of all channels must be loaded with desired data before an LDAC low pulse. After a LDAC low pulse, all DACs are simultaneously updated with the last contents of the corresponding data buffers. If the content of a data buffer is not changed, the corresponding DAC output remains unchanged after the LDAC pin is pulsed low. In synchronous mode, data are updated with the falling edge of the 32nd SCLK cycle, which follows a falling edge of SYNC. For such synchronous updates, the LDAC pin is not required, and it must be connected to GND permanently or asserted and held low before sending commands to the device.

8.4.5.1 Software LDAC Mode Registers

Alternatively, all DAC outputs can be updated simultaneously using the built-in software function of LDAC. The LDAC register offers additional flexibility and control by allowing the selection of which DAC channel(s) should be updated simultaneously when the LDAC pin is being brought low. The LDAC register is loaded with a 4-bit word (D03 and D00) using command bits D28 – D24 (see Table 3). The default value for each bit, and therefore for each DAC channel, is zero. If the LDAC register bit is set to 1, it overrides the LDAC pin (the LDAC pin is internally tied low for that particular DAC channel), and this DAC channel updates synchronously after the falling edge of the 32nd SCLK cycle. However, if the LDAC register bit is set to 0, the DAC channel is controlled by the LDAC pin. See Table 7 for more information. Table 7. LDAC Register

0 Determined by LDAC pin (Default)

1 DAC channel ignores LDAC pin, DAC updates on 32nd falling edge of SCLK, DAC channels

8.4.6 Software Reset Mode

(see Table 3). Table 1 shows the reset values for different registers.

8.4.7 Output Short Circuit Limit Register

Table 8. Short Circuit Limit Register

0 DAC output short circuit limit = 40 mA (Default)

1 DAC output short circuit limit = 30 mA

8.4.8 Status Register

command 1101 on bits D28 – D24, followed by a NOP command. ready to accept commands after power up.

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.2 Typical Application - Digitally Controlled Asymmetric Bipolar Output

Figure 58. Asymmetric Bipolar Output Block Diagram

9.2.1 Design Requirements

provides a positive offset and DACNEG has a negative offset.

9.2.2 Detailed Design Procedure

an effective output range of ±15 V, with discrete 16-bit steps.

9.2.3 Application Curve

two examples of the types of outputs that can be achieved using this configuration. Figure 59. Output Voltage vs Fine DAC Input Code

DAC80004,DAC70004,DAC60004 SLASED6D –APRIL 2016–REVISED DECEMBER 2017 www.ti.com Product Folder Links: DAC80004 DAC70004 DAC60004 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated

10 Power Supply Recommendations

The DACx0004 can operate within the specified supply voltage range of 2.7 V to 5.5 V. The power applied to VDD should be well-regulated and have low-noise. Switching power supplies and DC-DC converters often have high frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high frequency spikes. This noise can easily couple into the DAC output voltage through various paths between the power connections and analog output. A 1 µF to 10 µF capacitor and 0.1 µF bypass capacitor is recommended in order to further minimize noise from the power supply. The current consumption on the VDD pin, the short-circuit current limit, and the load current for the device are listed in the Electrical Characteristics. The power supply must meet the aforementioned current requirements.

11 Layout

11.1 Layout Guidelines

supplies. As a general rule it is important to keep digital traces as far away from analog traces when possible. difficult it is to keep digital noise from appearing at the output. the DAC, must flow through a single point. Ideally, GND must be connected directly to an analog ground plane. the power-entry point of the system. good idea to maintain the digital signals away from analog signals.

11.2 Layout Example

Figure 60. Layout Diagram

12 Device and Documentation Support

12.1 Receiving Notification of Documentation Updates

changed. For change details, review the revision history included in any revised document.

12.2 Related Links

resources, tools and software, and quick access to sample or buy. Table 9. Related Links

12.3 Community Resources

solve problems with fellow engineers. contact information for technical support.

12.4 Trademarks

E2E is a trademark of Texas Instruments. SPI, QSPI are trademarks of Motorola. All other trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

during storage or handling to prevent electrostatic damage to the MOS gates.

12.6 Glossary

This glossary lists and explains terms, acronyms, and definitions.

DAC80004,DAC70004,DAC60004 www.ti.com SLASED6D –APRIL 2016–REVISED DECEMBER 2017 Product Folder Links: DAC80004 DAC70004 DAC60004 Submit Documentation FeedbackCopyright © 2016–2017, Texas Instruments Incorporated

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. DAC80004IPW Device Marking Addendum: Note that both DA80004 and XDC84 are valid Device Markings for the DAC80004IPW Orderable Device

www.ti.com 7-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DAC60004IDMDR Active Production VSON (DMD) | 14 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 DA60004 DAC60004IDMDR.B Active Production VSON (DMD) | 14 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 DA60004 DAC60004IDMDT Active Production VSON (DMD) | 14 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 DA60004 DAC60004IDMDT.B Active Production VSON (DMD) | 14 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 DA60004 DAC60004IPW Active Production TSSOP (PW) | 14 90 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 DA60004 DAC60004IPW.B Active Production TSSOP (PW) | 14 90 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 DA60004 DAC60004IPWR Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 DA60004 DAC60004IPWR.B Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 DA60004 DAC70004IDMDR Active Production VSON (DMD) | 14 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 DA70004 DAC70004IDMDR.B Active Production VSON (DMD) | 14 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 DA70004 DAC70004IDMDT Active Production VSON (DMD) | 14 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 DA70004 DAC70004IDMDT.B Active Production VSON (DMD) | 14 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 DA70004 DAC70004IPW Active Production TSSOP (PW) | 14 90 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 DA70004 DAC70004IPW.B Active Production TSSOP (PW) | 14 90 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 DA70004 DAC70004IPWR Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 DA70004 DAC70004IPWR.B Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 DA70004 DAC80004IDMDR Active Production VSON (DMD) | 14 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 DA80004 DAC80004IDMDR.B Active Production VSON (DMD) | 14 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 DA80004 DAC80004IDMDT Active Production VSON (DMD) | 14 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 DA80004 DAC80004IDMDT.B Active Production VSON (DMD) | 14 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 DA80004 DAC80004IDMDTG4 Active Production VSON (DMD) | 14 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 DA80004 DAC80004IDMDTG4.B Active Production VSON (DMD) | 14 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 DA80004 DAC80004IPW Active Production TSSOP (PW) | 14 90 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 DA80004 DAC80004IPW.B Active Production TSSOP (PW) | 14 90 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 DA80004 DAC80004IPWR Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 DA80004 DAC80004IPWR.B Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 DA80004 DAC80004IPWRG4 Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 DA80004 DAC80004IPWRG4.B Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 DA80004 Addendum-Page 1

www.ti.com 7-Oct-2025 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC60004IDMDR VSON DMD 14 3000 367.0 367.0 38.0 DAC60004IDMDT VSON DMD 14 250 213.0 191.0 35.0 DAC60004IPWR TSSOP PW 14 2000 353.0 353.0 32.0 DAC70004IDMDR VSON DMD 14 3000 367.0 367.0 38.0 DAC70004IDMDT VSON DMD 14 250 213.0 191.0 35.0 DAC70004IPWR TSSOP PW 14 2000 353.0 353.0 32.0 DAC80004IDMDR VSON DMD 14 3000 367.0 367.0 38.0 DAC80004IDMDT VSON DMD 14 250 213.0 191.0 35.0 DAC80004IDMDTG4 VSON DMD 14 250 213.0 191.0 35.0 DAC80004IPWR TSSOP PW 14 2000 353.0 353.0 32.0 DAC80004IPWRG4 TSSOP PW 14 2000 353.0 353.0 32.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) DAC60004IPW PW TSSOP 14 90 530 10.2 3600 3.5 DAC60004IPW.B PW TSSOP 14 90 530 10.2 3600 3.5 DAC70004IPW PW TSSOP 14 90 530 10.2 3600 3.5 DAC70004IPW.B PW TSSOP 14 90 530 10.2 3600 3.5 DAC80004IPW PW TSSOP 14 90 530 10.2 3600 3.5 DAC80004IPW.B PW TSSOP 14 90 530 10.2 3600 3.5 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C 14X 0.3 0.2 1.6 1.4 14X 0.55 0.35

1 MAX

3.5 3.312X 0.5 0.05 0.00 A 4.1 3.9 B 3.1 2.9 0.3 0.2 0.55 0.35 (0.2) TYP VSON - 1 mm max heightDMD0014A PLASTIC SMALL OUTLINE - NO LEAD 4221688/A 09/2014 PIN 1 INDEX AREA SEATING PLANE 0.08 C 7 8 (OPTIONAL) PIN 1 ID 0.1 C A B 0.05 C EXPOSED THERMAL PAD NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. DETAIL SEE TERMINAL SCALE 3.500 DETAIL OPTIONAL TERMINAL TYPICAL

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

0.07 MAX

14X (0.65) 14X (0.25) (1.5) (2.75) 12X (0.5) (3.4) ( ) VIA TYP 0.2 (1) TYP (1.2) TYP VSON - 1 mm max heightDMD0014A PLASTIC SMALL OUTLINE - NO LEAD 4221688/A 09/2014 SYMM 7 8 SYMM LAND PATTERN EXAMPLE SCALE:20X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SOLDER MASK OPENING SOLDER MASK METAL UNDER SOLDER MASK DEFINED METALSOLDER MASK OPENING SOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED)

www.ti.com EXAMPLE STENCIL DESIGN 14X (0.65) 14X (0.25) 12X (0.5) (2.75) 2X (1.47) 2X (1.38) (0.835) VSON - 1 mm max heightDMD0014A PLASTIC SMALL OUTLINE - NO LEAD 4221688/A 09/2014 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 80% PRINTED SOLDER COVERAGE BY AREA SCALE:20X SYMM 7 8 SYMM METAL TYP

www.ti.com PACKAGE OUTLINE C 12X 0.65 3.9 14X 0.30 0.17 6.6

6.2 TYP

1.2 MAX

0.15 0.05 0.25 GAGE PLANE 0 -8 4X (0 -12 ) B 4.5 4.3 NOTE 4 A 5.1 4.9 NOTE 3 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023

0.1 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.500

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

14X (1.5) 14X (0.45) 12X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 7 8 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 14X (1.5) 14X (0.45) 12X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 7 8

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