DAC712PBG4

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V +10V REF□OUT Reference Circuit 16-Bit□D/A□Converter D/A□Latch Gain□Adjust Input□Latch WR CLR DB0 DB15 Bipolar□Offset□Adjust DAC712 www.ti.com SBAS023A SEPTEMBER 2000 REVISED JULY 2009 16-BIT DIGITAL-TO-ANALOG CONVERTER with 16-Bit Bus Interface HIGH-SPEED, 16-BIT PARALLEL The DAC712 is a complete 16-bit resolution DOUBLE-BUFFERED INTERFACE digital-to-analog (D/A) converter with bits of monotonicity over temperature. VOLTAGE OUTPUT: 10V 13-, 14-, AND 15-BIT LINEARITY GRADES The DAC712 has a precision +10V temperature-compensated voltage reference, 10V 16-BIT MONOTONIC OVER TEMPERATURE output amplifier, and 16-bit port bus interface. GRADE) The digital interface is fast, 60ns minimum write pulse POWER DISSIPATION: 600mW max width, double-buffered, and has a CLEAR function GAIN AND OFFSET ADJUST: that resets the analog output to bipolar zero. Convenient for Auto-Cal D/A Converters GAIN and OFFSET adjustment inputs are arranged 28-LEAD DIP AND SOIC PACKAGES so that they can be easily trimmed by external D/A converters as well as by potentiometers. The DAC712 is available in two linearity error performance grades: 4LSB and 2LSB, and three differential linearity grades: 4LSB, 2LSB, and 1LSB. The DAC712 is specified at power-supply voltages of 12V and 15V. The DAC712 is packaged in a 28-pin, 0.3" wide plastic DIP and in a 28-lead, wide-body plastic SOIC. The DAC712P, PB, and UB are specified over the C to +85 C temperature range and the DAC712PK, UK, PL, and UL are specified over the C to +70 C range. Please be aware that an important notice concerning availability, standard warranty, and use in critical

applications

sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright 2000 2009, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

(1) DAC712 SBAS023A SEPTEMBER 2000 REVISED JULY 2009 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION (1) DIFFERENTIAL LINEARITY ERROR MAX LINEARITY ERROR MAX PACKAGE- PACKAGE SPECIFIED PRODUCT AT +25 C AT +25 C LEAD DESIGNATOR TEMPERATURE RANGE DAC712P 4LSB 4LSB PDIP-28 NT C to +85 C DAC712U 4LSB 4LSB SOIC-28 DW C to +85 C DAC712PB 2LSB 2LSB PDIP-28 NT C to +85 C DAC712UB 2LSB 2LSB SOIC-28 DW C to +85 C DAC712PK 2LSB 2LSB PDIP-28 NT C to +70 C DAC712UK 2LSB 2LSB SOIC-28 DW C to +70 C DAC712PL 2LSB 1LSB PDIP-28 NT C to +70 C DAC712UL 2LSB 1LSB SOIC-28 DW C to +70 C (1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com DAC712 UNIT CC to COMMON +17 V V CC to COMMON V CC to V CC V Digital Inputs to COMMON to CC 0.7 V External Voltage Applied to BPO and Range Resistors V CC V V REF OUT Indefinite Short to COMMON V OUT Indefinite Short to COMMON Power Dissipation 750 mW Storage Temperature Range to +150 C (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. TRUTH TABLE WR CLR X X No Change X X X Reset D/A Latch Submit Documentation Feedback Copyright 2000 2009, Texas Instruments Incorporated Product Folder Link(s): DAC712

CHARACTERISTICS: DAC712P, PB, UB DAC712 www.ti.com SBAS023A SEPTEMBER 2000 REVISED JULY 2009 At T A +25 CC +12V and +15V, and V CC 12V and 15V, unless otherwise noted. DAC712P, U DAC712PB, UB (1) TEST PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNIT INPUT RESOLUTION Resolution Bits DIGITAL INPUTS Input Code Binary Twos Complement Logic Levels (2) V IH +2.0 CC 1.4 V V IL +0.8 V I IH I +2.7V) µ A I IL I +0.4V) µ A TRANSFER CHARACTERISTICS ACCURACY Linearity Error LSB T MIN to T MAX LSB Differential Linearity Error LSB T MIN to T MAX LSB Monotonicity Over Temperature Bits Gain Error (3) 0.1 T MIN to T MAX 0.2 0.15 Bipolar Zero Error (3) 0.1 FSR (4) mV T MIN to T MAX 0.2 0.15 FSR mV 0.003 FSR/% V CC Power-Supply Sensitivity of Full-Scale ppm FSR/% V CC DYNAMIC PERFORMANCE Settling Time (to 0.003%FSR, Ω 500pF Load) (5) 20V Output Step µ s 1LSB Output Step (6) µ s Output Slew Rate µ s Total Harmonic Distortion Noise 0dB, 1001Hz, f S 100kHz 0.005 20dB, 1001Hz, f S 100kHz 0.03 60dB, 1001Hz, f S 100kHz 3.0 SINAD 1001Hz, f S 100kHz dB Digital Feedthrough (6) nV-s Digital-to-Analog Glitch Impulse (6) nV-s Output Noise Voltage (Includes Reference) 120 nV/ Hz (1) Shaded cells indicate same specification as the DAC712P, U grade. (2) Digital inputs are TTL- and +5V CMOS-compatible over the specified temperature range. (3) Errors externally adjustable to zero. (4) FSR means Full-Scale Range. For example, for a 10V output, FSR 20V. (5) Maximum represents the σ limit. Not 100% tested for this parameter. (6) For the worst-case code changes: FFFFh to 0000h and 0000h to FFFFh. These are binary twos complement (BTC) codes. Copyright 2000 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): DAC712

www.ti.com ELECTRICAL CHARACTERISTICS: DAC712P, PB, UB (continued) At T A +25 CC +12V and +15V, and V CC 12V and 15V, unless otherwise noted. DAC712P, U DAC712PB, UB (1) TEST PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNIT ANALOG OUTPUT Output Voltage Range CC V CC 11.4V V Output Current mA Output Impedance 0.1 Ω Short-Circuit to ACOM, Duration Indefinite REFERENCE VOLTAGE Voltage +9.975 +10.000 +10.025 V T MIN to T MAX +9.960 +10.040 V Output Resistance Ω Source Current mA Short-Circuit to ACOM, Duration Indefinite POWER-SUPPLY REQUIREMENTS Voltage CC +11.4 +15 +16.5 V V CC 11.4 16.5 V Current (No Load, 15V Supplies) CC mA V CC mA Power Dissipation (7) 525 600 mW TEMPERATURE RANGES Specified Temperature Range (All Grades) +85 C Storage Temperature Range +150 C Thermal Coefficient, θ JA DIP Package C/W SOIC Package C/W (7) Typical supply voltages times maximum currents. Submit Documentation Feedback Copyright 2000 2009, Texas Instruments Incorporated Product Folder Link(s): DAC712

CHARACTERISTICS: DAC712PK, UK, PL, UL DAC712 www.ti.com SBAS023A SEPTEMBER 2000 REVISED JULY 2009 At T A +25 CC +12V and +15V, and V CC 12V and 15V, unless otherwise noted. DAC712PK, UK DAC712PL, UL (1) TEST PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNIT INPUT RESOLUTION Resolution Bits DIGITAL INPUTS Input Code Binary Twos Complement Logic Levels (2) V IH +2.0 CC 1.4 V V IL +0.8 V I IH I +2.7V) µ A I IL I +0.4V) µ A TRANSFER CHARACTERISTICS ACCURACY Linearity Error LSB T MIN to T MAX LSB Differential Linearity Error LSB T MIN to T MAX LSB Monotonicity Over Temperature Bits Gain Error (3) 0.1 T MIN to T MAX 0.15 0.2 Bipolar Zero Error (3) 0.1 FSR (4) mV T MIN to T MAX 0.15 FSR mV 0.003 FSR/% V CC Power-Supply Sensitivity of Full-Scale ppm FSR/% V CC DYNAMIC PERFORMANCE Settling Time (to 0.003%FSR, Ω 500pF Load) (5) 20V Output Step µ s 1LSB Output Step (6) µ s Output Slew Rate µ s Total Harmonic Distortion Noise 0dB, 1001Hz, f S 100kHz 0.005 20dB, 1001Hz, f S 100kHz 0.03 60dB, 1001Hz, f S 100kHz 3.0 SINAD 1001Hz, f S 100kHz dB Digital Feedthrough (6) nV-s Digital-to-Analog Glitch Impulse (6) nV-s Output Noise Voltage (Includes Reference) 120 nV/ Hz (1) Shaded cells indicate same specification as the DAC712PK, UK grade. (2) Digital inputs are TTL- and +5V CMOS-compatible over the specified temperature range. (3) Errors externally adjustable to zero. (4) FSR means Full-Scale Range. For example, for a 10V output, FSR 20V. (5) Maximum represents the σ limit. Not 100% tested for this parameter. (6) For the worst-case code changes: FFFFh to 0000h and 0000h to FFFFh. These are binary twos complement (BTC) codes. Copyright 2000 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): DAC712

www.ti.com ELECTRICAL CHARACTERISTICS: DAC712PK, UK, PL, UL (continued) At T A +25 CC +12V and +15V, and V CC 12V and 15V, unless otherwise noted. DAC712PK, UK DAC712PL, UL (1) TEST PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNIT ANALOG OUTPUT Output Voltage Range CC V CC 11.4V V Output Current mA Output Impedance 0.1 Ω Short-Circuit to ACOM, Duration Indefinite REFERENCE VOLTAGE Voltage +9.975 +10.000 +10.025 V T MIN to T MAX +9.960 +10.040 V Output Resistance Ω Source Current mA Short-Circuit to ACOM, Duration Indefinite POWER-SUPPLY REQUIREMENTS Voltage CC +11.4 +15 +16.5 V V CC 11.4 16.5 V Current (No Load, 15V Supplies) CC mA V CC mA Power Dissipation (7) 525 600 mW TEMPERATURE RANGES Specified Temperature Range (All Grades) +70 C Storage Temperature Range +150 C Thermal Coefficient, θ JA DIP Package C/W SOIC Package C/W (7) Typical supply voltages times maximum currents. Submit Documentation Feedback Copyright 2000 2009, Texas Instruments Incorporated Product Folder Link(s): DAC712

Offset□Adjust VREF□OUT Gain□Adjust +VCC /c45VCC CLR WR D15□MSB D14 LSB□D0 D10 D11 D12 D13 DAC712 DAC712 www.ti.com SBAS023A SEPTEMBER 2000 REVISED JULY 2009 DW AND NT PACKAGES SOIC-28 AND PDIP-28 (TOP VIEW) Copyright 2000 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): DAC712

www.ti.com PIN DESCRIPTIONS PIN NAME V OUT 10V D/A Output Offset Adjust Offset Adjust (Bipolar) V REF OUT Voltage Reference Output Gain Adjust Gain Adjust CC +12V to +15V Supply V CC 12V to 15V Supply CLR CLEAR; Sets D/A output to Bipolar Zero (Active Low) WR Write (Active Low) Enable for D/A latch (Active Low) Enable for Input latch (Active Low) D15 Data Bit (Most Significant Bit) D14 Data Bit D13 Data Bit D12 Data Bit D11 Data Bit D10 Data Bit Data Bit Data Bit Data Bit Data Bit Data Bit Data Bit Data Bit Data Bit Data Bit Data Bit (Least Significant Bit) Submit Documentation Feedback Copyright 2000 2009, Texas Instruments Incorporated Product Folder Link(s): DAC712

A ,□A0 1 D0-D15 tDH tAW tWP tDW tAH TIMING REQUIREMENTS Valid to End of WR Hold after End of WR DAC712 www.ti.com SBAS023A SEPTEMBER 2000 REVISED JULY 2009 Figure Timing Diagram At T A C to +85 CC +12V or +15V, and V CC 12V or 15V, unless otherwise noted. DAC712 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t DW Data Valid to End of WR ns t AW ns t AH ns t DH Data Hold after End of WR ns t WP (1) Write Pulse Width ns t CP CLEAR Pulse Width 200 ns (1) For single-buffered operation, t WP is 80ns minimum; see the Single-Buffered Operation section. Copyright 2000 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): DAC712

2.0 1.0 /c45 1.0 /c45 2.0 0.85 1.7 3.4 5.1 DATA WR,□A ,□A0 1 CLR V□Digital□Input I□Digital□Input□( A) /c109 Frequency□(Hz) [Change□in□FSR]/[Change□in□Supply□Voltage] (ppm□of□FSR/□%) 10 100 1k 10k 100k 1M 100 0.1 +VCC /c45VCC Time□(10 s/div)/c109 V (V) OUT WR (V) Time□(1 s/div)/c109 2500 2000 1500 1000 500 /c45 500 /c45 1000 /c45 1500 /c45 2000 /c45 2500 /c68 /c45 /c109 10V□( Around +5V WR Time□(1 s/div)/c109 2500 2000 1500 1000 500 /c45 500 /c45 1000 /c45 1500 /c45 2000 /c45 2500 /c68 /c109 Around□+10V□( +5V 1000 100 1 10 100 1k 10k 100k 1M 10M Frequency□(Hz) nV/ /c214Hz DAC712 SBAS023A SEPTEMBER 2000 REVISED JULY 2009 www.ti.com At T A +25 C and V CC 15V, unless otherwise noted. POWER-SUPPLY REJECTION vs POWER-SUPPLY RIPPLE FREQUENCY LOGIC vs V LEVEL Figure Figure FULL-SCALE OUTPUT SWING SETTLING TIME, +10V TO 10V Figure Figure SETTLING TIME, +10V TO 10V SPECTRAL NOISE DENSITY Figure Figure Submit Documentation Feedback Copyright 2000 2009, Texas Instruments Incorporated Product Folder Link(s): DAC712

www.ti.com SBAS023A SEPTEMBER 2000 REVISED JULY 2009 Linearity error is defined as the deviation of the Total harmonic distortion noise is defined as the analog output from a straight line drawn between the ratio of the square root of the sum of the squares of end points of the transfer characteristic. the values of the harmonics and noise to the value of the fundamental frequency. It is expressed in of the fundamental frequency amplitude at sampling rate f S Differential linearity error (DLE) is the deviation from 1LSB of an output change from one adjacent state to the next. A DLE specification of 1/2LSB means that (SINAD) the output step size can range from 1/2LSB to 3/2LSB when the digital input code changes from one SINAD includes all the harmonic and outstanding code word to the adjacent code word. If the DLE is spurious components in the definition of output noise more positive than 1LSB, the D/A converter is said power in addition to quantizing and internal random to be monotonic. noise power. SINAD is expressed in dB at a specified input frequency and sampling rate, f S A D/A converter is monotonic if the output either increases or remains the same for increasing digital The amount of charge injected into the analog output input values. Monotonicity of the DAC712 is ensured from the digital inputs when the inputs change state. over the specified temperature range to 13, 14, 15, It is measured at half-scale at the input codes where and bits for performance grades DAC712P/U, as many switches as possible change state from DAC712PB/UB, DAC712PK/UK, and DAC712PL/UL, 7FFFh to 8000h. respectively. When the analog-to-digital (A/D) converter is not Settling time is the total time (including slew time) for selected, high-frequency logic activity on the digital the D/A output to settle to within an error band inputs is coupled through the device and shows up as around its final value after a change in input. Settling output noise. This noise is digital feedthrough. times are specified to within 0.003% of Full-Scale Range (FSR) for an output step change of 20V and 1LSB. The 1LSB change is measured at the Major Carry (FFFFh to 0000h, and 0000h to FFFFh: BTC codes), the input transition at which worst-case settling time occurs. Copyright 2000 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): DAC712

16-Bit□Input□Latch 16-Bit□D/A□Latch 28 27 26 25 24 23 22 21 20 19 18 17 DB0 LSB 6 5 +10V Reference 2 1 DCOM +VCC ACOM VREF□OUTGain□Adjust 10WR 12A0 11A1 9CLR /c45 VCC 16 15 14 13 Bipolar Offset Adjust VOUT D/A□Switches /c45 VCC+2.5V 15k/c87 170/c87 9750/c87 250/c87 10k/c87 DAC712 SBAS023A SEPTEMBER 2000 REVISED JULY 2009 www.ti.com The DAC712 is a monolithic integrated-circuit, 16-bit All latches are level-triggered. Data present when the D/A converter complete with 16-bit D/A converter enable inputs are logic '0' enter the latch. When the switches and ladder network, voltage reference, enable inputs return to logic '1', the data are latched. output amplifier, and microprocessor bus interface. The CLR input resets both the input latch and the D/A latch to give a bipolar zero output. The DAC712 has double-buffered data latches. The input data latch holds a 16-bit data word before loading it into the second latch, the D/A latch. This double-buffered organization permits simultaneous update of several D/A converters. All digital control inputs are active low. Refer to the block diagram of Figure Figure DAC712 Block Diagram Submit Documentation Feedback Copyright 2000 2009, Texas Instruments Incorporated Product Folder Link(s): DAC712

+□Full-Scale All□Bits Logic□0 1LSB Range□of Offset□Adjust Offset□Adjust Translates the□Line Digital□Input All□Bits Logic□1 Analog□Output Full-Scale Range Gain□Adjust Rotates□the□Line /c45 Full-Scale MSB□on□All Others□Off Bipolar Offset Range□of Gain□Adjust /c187 /c177 0.3% /c187 /c177 0.3% R 3k:□D ...D0 15 ESD□Protection□Circuit 6.8V 5pF Digital Input /c45VCC +VCC INPUT CODING INTERNAL REFERENCE OUTPUT VOLTAGE SWING Offset Adjustment DAC712 www.ti.com SBAS023A SEPTEMBER 2000 REVISED JULY 2009 The DAC712 digital inputs are TTL-compatible (1.4V Figure illustrates the relationship of offset and gain switching level) with low-leakage, high-impedance adjustments for a bipolar connected D/A converter. inputs. Thus, the inputs are suitable for being driven Offset should be adjusted first to avoid interaction of by any type of logic such as CMOS logic. An adjustments. Table shows calibration values and equivalent circuit of a digital input is shown in codes. These adjustments have a minimum range of Figure 0.3%. Data inputs float to logic '0' and control inputs float to logic '0' if left unconnected. It is recommended that any unused inputs be connected to DCOM to improve noise immunity. Digital inputs remain high-impedance when power is off. Figure 10. Relationship of Offset and Gain Figure Equivalent Circuit of Digital Inputs Adjustments Table Digital Input and Analog Output Voltage Calibration Values The DAC712 is designed to accept positive-true binary twos complement (BTC) input codes that are DAC712 CALIBRATION VALUES LEAST SIGNIFICANT BIT 305 µ V compatible with bipolar analog output operation. For bipolar analog output configuration, a digital input of DIGITAL INPUT CODE BINARY 7FFFh gives a positive full-scale output, 8000h gives TWOS a negative full-scale output, and 0000h gives bipolar COMPLEMENT, ANALOG OUTPUT zero output. BTC (V) +9.999695 1LSB 4000h +5.000000 Scale The DAC712 contains a +10V reference. 0001h +0.000305 BPZ 1LSB The reference output may be used to drive external 0000h 0.000000 Bipolar Zero (BPZ) loads, sourcing up to 2mA. The load current should FFFFh 0.000305 BPZ 1LSB be constant, otherwise the gain and bipolar offset of the converter will vary. C000h 5.000000 Scale 8000h 10.00000 Negative Full-Scale The output amplifier of the DAC712 is committed to a 10V output range. The DAC712 provides a 10V Apply the digital input code that produces the output swing while operating on 11.4V or higher maximum negative output voltage and adjust the voltage supplies. offset potentiometer or the offset adjust D/A converter for 10V. Copyright 2000 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): DAC712

0.01 F/c109

V OUT VREF□OUT +VCC /c45 VCC

0.01 F/c109 +

+12V□to□+15V /c45 12V□to /c45 15V POWER-SUPPLY AND REFERENCE DAC712 SBAS023A SEPTEMBER 2000 REVISED JULY 2009 www.ti.com Apply the digital input that gives the maximum positive voltage output. Adjust the gain potentiometer or the gain adjust D/A converter for this positive full-scale voltage. Because of the high accuracy of these D/A converters, system design problems such as grounding and contact resistance become very important. A 16-bit converter with a 20V full-scale range has a 1LSB value of 305mV. With a load current of µ series wiring and connector resistance of only 60m Ω causes a voltage drop of 300 µ To understand what this means in terms of a system layout, the resistivity of a typical 1-ounce copper-clad printed circuit board (PCB) is 1/2m Ω per square. For a 5mA load, a mil (0.010 inch) wide printed circuit conductor milli-inches long results in a voltage drop of 150 µ Figure 11. Power-Supply Connections The analog output of the DAC712 has an LSB size of 305 µ V 96dB). The noise floor of the D/A converter The DAC712 has separate ANALOG COMMON and must remain below this level in the frequency range DIGITAL COMMON pins. The current through DCOM of interest. The DAC712 noise spectral density (which is mostly switching transients and are up to 1mA includes the noise contributed by the internal peak in amplitude. The current through ACOM is reference) is shown in the Typical Characteristics typically µ A for all codes. section. Use separate analog and digital ground planes with a Wiring to high-resolution D/A converters should be single interconnection point to minimize ground loops. routed to provide optimum isolation from sources of The analog pins are located adjacent to each other to radio frequency interference (RFI) and help isolate analog from digital signals. Analog electromagnetic interference (EMI). The key to signals should be routed as far as possible from elimination of RF radiation or pickup is a small loop digital signals and should cross them at right angles. area. Signal leads and the return conductors should A solid analog ground plane around the D/A be kept close together such that they present a small converter package, as well as under it in the vicinity capture cross-section for any external field. of the analog and power-supply pins, isolates the D/A Wire-wrap construction is not recommended. converter from switching currents. It is recommended that DCOM and ACOM be connected directly to the ground planes under the package. CONNECTIONS If several DAC712s are used, or if the DAC712 Power-supply decoupling capacitors should be added shares supplies with other components, connecting as shown in Figure Best performance occurs the ACOM and DCOM lines together once at the using a µ F to µ F tantalum capacitor at V CC power supplies rather than at each chip may give results. able to use 0.01 µ F at V CC as well as at CC The capacitors should be located close to the package. Submit Documentation Feedback Copyright 2000 2009, Texas Instruments Incorporated Product Folder Link(s): DAC712

Alternate□Ground Sense□Connection System□Ground ACOMDCOM Bus Interface DAC712 Analog Power Supply (1) T o□+VCC T o V/c45 CC VOUT 10k/c8710k/c87 VREF DAC712 www.ti.com SBAS023A SEPTEMBER 2000 REVISED JULY 2009 In some converter. Sensing the Because the reference point for V OUT and V REF OUT is output voltage at the SYSTEM GROUND point is the ACOM pin, it is important to connect the D/A reasonable, because there is no change in the converter load directly to the ACOM pin; see DAC712 ACOM current, provided that R is a Figure low-resistance ground plane or conductor. In this case, DCOM may be connected to SYSTEM Lead and contact resistances are represented by R GROUND as well. through R As long as the load resistance R L is constant, R simply introduces a gain error and can be removed by gain adjustment of the D/A converter or system-wide gain calibration. R is part of R L if the output voltage is sensed at ACOM. (1) Locate close to the DAC712 package. Figure 12. System Ground Considerations for High-Resolution D/A Converters Copyright 2000 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): DAC712

/c17710V□VOUT 9.75k/c87 IDAC 0mA-2mA /c187+2.5V 15k/c87 R 27k/c87 3 R 10k/c87 120/c87 180/c87 R 500/c87 1 R 500/c87 170/c87 250/c87 Internal +10V□Reference VREF□OUT Gain□Adjust Bipolar□Offset□Adjust

2 ACOM

www.ti.com Nominal values of GAIN and OFFSET occur when the D/A converter outputs are at approximately half scale, +5V. GAIN and OFFSET adjust pins provide for trim using external potentiometers. 15-turn potentiometers provide sufficient resolution. Range of adjustment of The DAC712 output amplifier is connected internally these trims is at least 0.3% of Full-Scale Range; see for the 10V bipolar (20V) output range. That is, the Figure bipolar offset resistor is connected to an internal reference voltage and the 20V range resistor is connected internally to V OUT The DAC712 cannot be connected for unipolar operation. The GAIN ADJUST and OFFSET ADJUST circuits of the DAC712 have been arranged so that these points may be easily driven by external D/A converters; see Figure 12-bit D/A converters provide an OFFSET adjust resolution and a GAIN adjust resolution of µ V to µ V per LSB step. (1) For no external adjustments, pins and are not connected. External Resistors R to R are standard values. Range of adjustment is at least 0.3% FSR. Figure 13. Manual Offset and Gain Adjust Circuits Submit Documentation Feedback Copyright 2000 2009, Texas Instruments Incorporated Product Folder Link(s): DAC712

/c177 10V□VOUT DAC712 9.75k/c87 IDAC 0mA-2mA 15k/c87 R 20k/c87 0V□to□+10V R 10k/c87 170/c87 250/c87 Internal +10V□Reference VREF□OUT Gain□Adjust(1) Bipolar□Offset□Adjust(1) R 340/c87 1 R 500/c87 RFB VREF□A RFB VREF□B 0V□to□10V 5k/c87 10k/c87 +10V 10k/c87 /c45 10V(2) (3) (4) DIGITAL INTERFACE BUS INTERFACE SINGLE-BUFFERED OPERATION enabled by connecting to DCOM. If is not used is the enable control for the DATA INPUT LATCH. is the enable for the D/A LATCH. WR is used to strobe data into latches enabled by and Refer TRANSPARENT INTERFACE transparent by asserting and WR LOW, and DAC712 www.ti.com SBAS023A SEPTEMBER 2000 REVISED JULY 2009 (1) For no external adjustments, pins and are not connected. External Resistors R to R tolerance is values. Range of adjustment is at least 0.3% FSR. (2) Suggested op amps: OPA177GP, GS or OPA604AP, AU (3) Suggested op amps: single OPA177GP, GS or dual OPA2604AP, AU (4) Suggested D/A converters: dual DAC7800 (serial input, 12-bit resolution); dual DAC7801 (8-bit port input, 12-bit resolution); dual DAC7802 (12-bit port input, 12-bit resolution); dual DAC7545 (12-bit port input, 12-bit resolution); or single DAC8043 (serial input, 12-bit resolution). BIPOLAR (complete): DAC813 (use 11-bit resolution for to +10V output; no op-amps required). Figure 14. Gain and Offset Adjustment Using D/A Converters The DAC712 has 16-bit, double-buffered data bus To operate the DAC712 interface as a single-buffered interface with control lines for easy interface to latch, the DATA INPUT LATCH is permanently interface to a 16-bit bus. The double-buffered feature permits update of several D/A converters to enable the D/A converter, it should be connected simultaneously. to DCOM as well. For this mode of operation, the width of WR must be at least 80ns minimum to pass data through the DATA INPUT LATCH and into the D/A LATCH. to the block diagram of Figure and to Figure CLR sets the INPUT DATA LATCH to all zeros and The digital interface of the DAC712 can be made the D/A LATCH to a code that gives bipolar at the D/A converter output. asserting CLR HIGH. Copyright 2000 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): DAC712

www.ti.com Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (September 200) to Revision A Page Updated document format to current standards Changed max specification for Accuracy, Gain Error, T MIN to T MAX parameter in Electrical Characteristics: DAC712PK, UK, PL, UL table Submit Documentation Feedback Copyright 2000 2009, Texas Instruments Incorporated Product Folder Link(s): DAC712

www.ti.com 28-Oct-2011 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) DAC712P NRND PDIP NT 28 13 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type DAC712PB NRND PDIP NT 28 13 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type DAC712PBG4 NRND PDIP NT 28 13 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type DAC712PG4 NRND PDIP NT 28 13 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type DAC712PK NRND PDIP NT 28 13 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type DAC712PKG4 NRND PDIP NT 28 13 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type DAC712PL NRND PDIP NT 28 13 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type DAC712PLG4 NRND PDIP NT 28 13 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type DAC712U ACTIVE SOIC DW 28 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DAC712UB ACTIVE SOIC DW 28 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DAC712UB/1K OBSOLETE SOIC DW 28 TBD Call TI Call TI DAC712UB/1KG4 OBSOLETE SOIC DW 28 TBD Call TI Call TI DAC712UBG4 ACTIVE SOIC DW 28 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DAC712UG4 ACTIVE SOIC DW 28 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DAC712UK ACTIVE SOIC DW 28 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DAC712UK/1K OBSOLETE SOIC DW 28 TBD Call TI Call TI DAC712UK/1KG4 OBSOLETE SOIC DW 28 TBD Call TI Call TI DAC712UKG4 ACTIVE SOIC DW 28 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR

www.ti.com 28-Oct-2011 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) DAC712UL ACTIVE SOIC DW 28 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DAC712UL/1K OBSOLETE SOIC DW 28 TBD Call TI Call TI DAC712UL/1KG4 OBSOLETE SOIC DW 28 TBD Call TI Call TI DAC712ULG4 ACTIVE SOIC DW 28 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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