DAC712

DAC712 BURR-BROWN | Alldatasheet

Document overview

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Technical content

+10V Reference Circuit 16-Bit D/A Converter D/A Latch Gain Adjust Input Latch WR CLR DB 0 DB 15 Bipolar Offset Adjust

FEATURES

l HIGH-SPEED 16-BIT PARALLEL DOUBLE- BUFFERED INTERFACE l VOLTAGE OUTPUT: ±10V l 13-, 14-, AND 15-BIT LINEARITY GRADES l 16-BIT MONOTONIC OVER TEMPERATURE (L GRADE) l POWER DISSIPATION: 600mW max l GAIN AND OFFSET ADJUST: Convenient for Auto-Cal D/A Converters l 28-LEAD DIP AND SOIC PACKAGES

DESCRIPTION

DAC712 is a complete 16-bit resolution D/A converter with 16 bits of monotonicity over temperature. DAC712 has a precision +10V temperature compen- sated voltage reference, ±10V output amplifier and 16-bit port bus interface. The digital interface is fast, 60ns minimum write pulse width, is double-buffered and has a CLEAR function that resets the analog output to bipolar zero. GAIN and OFFSET adjustment inputs are arranged so that they can be easily trimmed by external D/A converters as well as by potentiometers. DAC712 is available in two linearity error perfor- mance grades: ±4LSB and ±2LSB and three differen- tial linearity grades: ±4LSB, ±2LSB, and ±1LSB. The DAC712 is specified at power supply voltages of ±12V and ±15V. DAC712 is packaged in a 28-pin 0.3" wide plastic DIP and in a 28-lead wide-body plastic SOIC. The DAC712P, U, PB, UB, are specified over the –40°C to +85°C temperature range and the DAC712PK, UK, PL, UL are specified over the 0°C to +70°C range. 16-BIT DIGITAL-TO-ANALOG CONVERTER With 16-Bit Bus Interface International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 DAC712 DAC712 © 1994 Burr-Brown Corporation PDS-1164G Printed in U.S.A. May, 1998

At TA = 25°C, +VCC = +12V and +15V, –VCC = –12V and –15V, unless otherwise noted. DAC712P, U DAC712PB, UB PARAMETER MIN TYP MAX MIN TYP MAX UNITS INPUT RESOLUTION 16 [ Bits DIGITAL INPUTS Input Code Binary Two’s Complement [ Logic Levels (1) VIH +2.0 +V CC – 1.4 [[ V VIL 0 +0.8 [[ V IIH (VI = +2.7V) ±10 [ µA IIL (VI = +0.4V) ±10 [ µA TRANSFER CHARACTERISTICS ACCURACY Linearity Error ±4 ±2 LSB TMIN to TMAX ±8 ±4 LSB Differential Linearity Error ±4 ±2 LSB TMIN to TMAX ±8 ±4 LSB Monotonicity Over Temp 13 14 Bits Gain Error(3) ±0.1 ±0.1 % TMIN to TMAX ±0.2 ±0.15 % Bipolar Zero Error(3) ±0.1 [ % FSR (2) ±20 [ mV TMIN to TMAX ±0.2 ±0.15 % FSR ±40 ±30 mV Power Supply Sensitivity Of Full Scale: ±0.003 [ % FSR/% V CC ±30 [ ppm FSR/% V CC DYNAMIC PERFORMANCE Settling Time (to ±0.003%FSR, 5kΩ || 500pF Load)(4) 20V Output Step 6 [ 10 µs

1 LSB Output Step(5) 4 [ µs

Output Slew Rate 10 [ V/µs Total Harmonic Distortion + Noise 0dB, 1001Hz, fS = 100kHz 0.005 [ % –20dB, 1001Hz, fS = 100kHz 0.03 [ % –60dB, 1001Hz, fS = 100kHz 3.0 [ % SINAD 1001Hz, fS = 100kHz 87 [ dB Digital Feedthrough(5) 2 [ nV-s Digital-to-Analog Glitch Impulse(5) 15 [ nV-s Output Noise Voltage (Includes Reference) 120 [ nV/√Hz ANALOG OUTPUT Output Voltage Range +V CC , –VCC = ±11.4V ±10 [ V Output Current ±5 [ mA Output Impedance 0.1 [ Ω Short Circuit to ACOM, Duration Indefinite [ REFERENCE VOLTAGE Voltage +9.975 +10.000 +10.025 [[ [ V TMIN to TMAX +9.960 +10.040 [[ V Output Resistance 1 [ Ω Source Current 2 [ mA Short Circuit to ACOM, Duration Indefinite [ POWER SUPPLY REQUIREMENTS Voltage: +VCC +11.4 +15 +16.5 [[ [ V Current (No Load, ±15V Supplies) +VCC 13 15 [[ mA –VCC 22 25 [[ mA Power Dissipation(6) 525 600 [[ mW TEMPERATURE RANGES Specification All Grades –40 +85 [[ °C Storage –60 +150 [[ °C Thermal Coefficient θJA [ Specifications are the same as grade to the left. NOTES: (1) Digital inputs are TTL and +5V CMOS compatible over the specification temperature range. (2) FSR means Full Scale Range. For example, for a ±10V output, FSR = 20V. (3) Errors externally adjustable to zero. (4) Maximum represents the 3σ limit. Not 100% tested for this parameter. (5) For the worst case code changes: FFFF HEX to 0000HEX and 0000HEX to FFFFHEX . These are Binary Two’s Complement (BTC) codes. (6) Typical supply voltages times maximum currents.

At TA = +25°C, +VCC = +12V and +15V, –VCC = –12V and –15V, unless otherwise noted. DAC712PK, UK DAC712PL, UL PARAMETER MIN TYP MAX MIN TYP MAX UNITS INPUT RESOLUTION 16 [ Bits DIGITAL INPUTS Input Code Binary Two’s Complement [ Logic Levels(1) VIH +2.0 +V CC – 1.4 [[ V VIL 0 +0.8 [[ V IIH (VI = +2.7V) ±10 [ µA IIL (VI = +0.4V) ±10 [ µA TRANSFER CHARACTERISTICS ACCURACY Linearity Error ±2 ±2 LSB TMIN to TMAX ±2 ±2 LSB Differential Linearity Error ±2 ±1 LSB TMIN to TMAX ±2 ±1 LSB Monotonicity Over Temp 15 16 Bits Gain Error(3) ±0.1 [ % TMIN to TMAX ±0.15 ±0.02 % Bipolar Zero Error(3) ±0.1 [ % FSR (2) ±20 [ mV TMIN to TMAX ±0.15 ±0.15 % FSR ±30 [ mV Power Supply Sensitivity of Full Scale ±0.003 [ %FSR/% V CC ±30 [ ppm FSR/% V CC DYNAMIC PERFORMANCE Settling Time (to ±0.003%FSR, 5kΩ || 500pF Load)(4) 20V Output Step 6 10 [ 10 µs 1LSB Output Step(5) 4 [ µs Output Slew Rate 10 [ V/µs Total Harmonic Distortion + Noise 0dB, 1001Hz, fS = 100kHz 0.005 [ % –20dB, 1001Hz, fS = 100kHz 0.03 [ % –60dB, 1001Hz, fS = 100kHz 3.0 [ % SINAD 1001Hz, fS = 100kHz 87 [ dB Digital Feedthrough(5) 2 [ nV–s Digital-to-Analog Glitch Impulse(5) 15 [ nV–s Output Noise Voltage (includes reference) 120 [ nV/√Hz ANALOG OUTPUT Output Voltage Range +VCC , –VCC = ±11.4V ±10 [ V Output Current ±5 [ mA Output Impedance 0.1 [ Ω Short Circuit to ACOM, Duration Indefinite [ REFERENCE VOLTAGE Voltage +9.975 +10.000 +10.025 [[[ V TMIN to TMAX +9.960 +10.040 [[ V Output Resistance 1 [ Ω Source Current 2 [ mA Short Circuit to ACOM, Duration Indefinite [ POWER SUPPLY REQUIREMENTS Voltage: +VCC +11.4 +15 +16.5 [[[ V Current (No Load, ±15V Supplies) +VCC 13 15 [[ mA –VCC 22 25 [[ mA Power Dissipation(6) 525 600 [ mW TEMPERATURE RANGES Specification All Grades 0 +70 [[ °C Storage –60 +150 [[ °C Thermal Coefficient, θJA [ Same specification as grade to the left. NOTES: (1) Digital inputs are TTL and +5V CMOS compatible over the specification temperature range. (2) FSR means Full Scale Range. For example, for a ±10V output, FSR = 20V. (3) Errors externally adjustable to zero. (4) Maximum represents the 3σ limit. Not 100% tested for this parameter. (5) For the worst case code changes: FFFF HEX to 0000HEX and 0000HEX to FFFFHEX . These are Binary Two’s Complement (BTC) codes. (6) Typical supply voltages times maximum currents.

NOTE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. PACKAGE DRAWING PRODUCT PACKAGE NUMBER (1) DAC712P Plastic DIP 246 DAC712U Plastic SOIC 217 DAC712PB Plastic DIP 246 DAC712UB Plastic SOIC 217 DAC712PK Plastic DIP 246 DAC712UK Plastic SOIC 217 DAC712PL Plastic DIP 246 DAC712UL Plastic SOIC 217 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book.

PACKAGE INFORMATION

TA = –40°C to +85°C, +VCC = +12V or +15V, –VCC = –12V or –15V. SYMBOL PARAMETER MIN MAX UNITS tDW Data Valid to End of WR 50 ns tAW A0, A1 Valid to End of WR 50 ns tAH A0, A1 Hold after End of WR 10 ns tDH Data Hold after end of WR 10 ns tWP (1) Write Pulse Width 50 ns tCP CLEAR Pulse Width 200 ns NOTES: (1) For single-buffered operation, tWP is 80ns min. Refer to page 10. WR A0, A1 D0-D15 tDH tAW tWP tDW tAH A 0 A 1 WR CLR DESCRIPTION 01 1 → 0 → 1 1 Load Input Latch 10 1 → 0 → 1 1 Load D/A Latch 11 1 → 0 → 1 1 No Change 0 0 0 1 Latches Transparent X X 1 1 No Change X X X 0 Reset D/A Latch TRUTH TABLE ELECTROSTATIC DISCHARGE SENSITIVITY Electrostatic discharge can cause damage ranging from per- formance degradation to complete device failure. Burr-Brown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published speci- fications.

ORDERING INFORMATION

TEMPERATURE ERROR MAX LINEARITY ERROR PRODUCT RANGE at +25 °C MAX at +25 °C DAC712P –40 °C to +85°C ±4LSB ±4LSB DAC712U –40 °C to +85°C ±4LSB ±4LSB DAC712PB –40 °C to +85°C ±2LSB ±2LSB DAC712UB –40 °C to +85°C ±2LSB ±2LSB DAC712PK 0 °C to +70°C ±2LSB ±2LSB DAC712UK 0 °C to +70°C ±2LSB ±2LSB DAC712PL 0 °C to +70°C ±2LSB ±1LSB DAC712UL 0 °C to +70°C ±2LSB ±1LSB

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. PIN CONFIGURATION PIN LABEL DESCRIPTION 1 DCOM Power Supply return for digital currents. 2 ACOM Analog Supply Return. 3V OUT ±10V D/A Output. 4 Off Adj Offset Adjust (Bipolar). 5V REF OUT Voltage Reference Output. 6 Gain Adj Gain Adjust. 7+ V CC +12V to +15V Supply. 8– V CC –12V to –15V Supply. 9 CLR CLEAR. Sets D/A output to BIPOLAR ZERO (Active Low). 10 WR Write (Active Low). 11 A 1 Enable for D/A latch (Active Low). 12 A 0 Enable for Input latch (Active Low). 13 D15 Data Bit 15 (Most Significant Bit). 14 D14 Data Bit 14. 15 D13 Data Bit 13. 16 D12 Data Bit 12. 17 D11 Data Bit 11. 18 D10 Data Bit 10. 19 D9 Data Bit 9. 20 D8 Data Bit 8. 21 D7 Data Bit 7. 22 D6 Data Bit 6. 23 D5 Data Bit 5. 24 D4 Data Bit 4. 25 D3 Data Bit 3. 26 D2 Data Bit 2. 27 D1 Data Bit 1. 28 D0 Data Bit 0 (Least Significant Bit). PIN DESCRIPTIONS DCOM ACOM VOUT Offset Adjust VREF OUT Gain Adjust +VCC –VCC CLR WR D15 MSB D14 LSB D0 D10 D11 D12 D13 DAC712

Time (10µs/div) ± FULL SCALE OUTPUT SWING V (V)OUT TYPICAL PERFORMANCE CURVES At TA = +25°C, VCC = ±15V, unless otherwise noted. –10 Frequency (Hz) [Change in FSR]/[Change in Supply Voltage] 10 100 1k 10k 100k 1M POWER SUPPLY REJECTION vs POWER SUPPLY RIPPLE FREQUENCY (ppm of FSR/ %) 100 0.1 +VCC –VCC 2.0 LOGIC vs V LEVEL 1.0 –1.0 –2.0 0.85 1.7 3.4 5.1 DATA WR, A0, A1 CLR V Digital Input I Digital Input (µA) WR (V) SETTLING TIME, +10V TO –10V Time (1µs/div) 2500 2000 1500 1000 500 –500 –1000 –1500 –2000 –2500 Δ Around –10V (µV) +5V WR SETTLING TIME, –10V TO +10V Time (1µs/div) 2500 2000 1500 1000 500 –500 –1000 –1500 –2000 –2500 Δ Around +10V (µV) +5V –0V 1000 100 1 10 100 1k 10k 100k 1M 10M Frequency (Hz) nV/√Hz Spectral Noise Density

Linearity error is defined as the deviation of the analog output from a straight line drawn between the end points of the transfer characteristic. DIFFERENTIAL LINEARITY ERROR Differential linearity error (DLE) is the deviation from 1LSB of an output change from one adjacent state to the next. A DLE specification of ±1/2LSB means that the output step size can range from 1/2LSB to 3/2LSB when the digital input code changes from one code word to the adjacent code word. If the DLE is more positive than –1LSB, the D/A is said to be monotonic. MONOTONICITY A D/A converter is monotonic if the output either increases or remains the same for increasing digital input values. Monotonicity of DAC712 is guaranteed over the specifica- tion temperature range to 13, 14, 15, and 16 bits for perfor- mance grades DAC712P/U, DAC712PB/UB, DAC712PK/ UK, and DAC712PL/UL respectively. SETTLING TIME Settling time is the total time (including slew time) for the D/A output to settle to within an error band around its final value after a change in input. Settling times are specified to within ±0.003% of Full Scale Range (FSR) for an output step change of 20V and 1LSB. The 1LSB change is mea- sured at the Major Carry (FFFF HEX to 0000HEX , and 0000HEX to FFFFHEX : BTC codes), the input transition at which worst-case settling time occurs. TOTAL HARMONIC DISTORTION + NOISE Total harmonic distortion + noise is defined as the ratio of the square root of the sum of the squares of the values of the harmonics and noise to the value of the fundamental fre- quency. It is expressed in % of the fundamental frequency amplitude at sampling rate f SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) SINAD includes all the harmonic and outstanding spurious components in the definition of output noise power in addition to quantizing and internal random noise power. SINAD is expressed in dB at a specified input frequency and sampling rate, f DIGITAL-TO-ANALOG GLITCH IMPULSE The amount of charge injected into the analog output from the digital inputs when the inputs change state. It is mea- sured at half scale at the input codes where as many as possible switches change state—from 7FFF HEX to 8000HEX . DIGITAL FEEDTHROUGH When the A/D is not selected, high frequency logic activity on the digital inputs is coupled through the device and shows up as output noise. This noise is digital feedthrough. OPERATION DAC712 is a monolithic integrated-circuit 16-bit D/A con- verter complete with 16-bit D/A switches and ladder net- work, voltage reference, output amplifier and microproces- sor bus interface. INTERFACE LOGIC DAC712 has double-buffered data latches. The input data latch holds a 16-bit data word before loading it into the second latch, the D/A latch. This double-buffered organiza- tion permits simultaneous update of several D/A converters. All digital control inputs are active low. Refer to block diagram of Figure 1. All latches are level-triggered. Data present when the enable inputs are logic “0” will enter the latch. When the enable inputs return to logic “1”, the data is latched. The CLR input resets both the input latch and the D/A latch to give a bipolar zero output. LOGIC INPUT COMPATIBILITY DAC712 digital inputs are TTL compatible (1.4V switching level) with low leakage, high impedance inputs. Thus the inputs are suitable for being driven by any type of 5V logic such as 5V CMOS logic. An equivalent circuit of a digital input is shown in Figure 2. Data inputs will float to logic “0” and control inputs will float to logic “0” if left unconnected. It is recommended that any unused inputs be connected to DCOM to improve noise immunity. Digital inputs remain high impedance when power is off. INPUT CODING DAC712 is designed to accept positive-true binary two’s complement (BTC) input codes which are compatible with bipolar analog output operation. For bipolar analog output configuration, a digital input of 7FFF HEX gives a plus full scale output, 8000HEX gives a minus full scale output, and 0000HEX gives bipolar zero output. INTERNAL REFERENCE DAC712 contains a +10V reference. The reference output may be used to drive external loads, sourcing up to 2mA. The load current should be constant, otherwise the gain and bipolar offset of the converter will vary.

FIGURE 1. DAC712 Block Diagram. FIGURE 2. Equivalent Circuit of Digital Inputs. while operating on ±11.4V or higher voltage supplies. have a minimum range of ±0.3%. FIGURE 3. Relationship of Offset and Gain Adjustments.

3 VOUT

or the offset adjust D/A converter for –10V.

1 LEAST SIGNIFICANT BIT = 305µV

adjust D/A converter for this positive full scale voltage. to provide optimum isolation from sources of RFI and EMI. FIGURE 4. Power Supply Connections. switching transients and are up to 1mA peak in amplitude. The current through ACOM is typically 5µA for all codes. connected directly to the ground planes under the package. each chip may give better results. directly to the ACOM pin. Refer to Figure 5. of RL if the output voltage is sensed at ACOM.

least ±0.3% of Full Scale Range. Refer to Figure 6. easily driven by external D/A converters. Refer to Figure 7. converters outputs are at approximately half scale, +5V. cannot be connected by the user for unipolar operation. control lines for easy interface to interface to a 16-bit bus. FIGURE 5. System Ground Considerations for High-Resolution D/A Converters. NOTE: (1) Locate close to DAC712 package.

diagram of Figure 1 and to Timing Diagram on page 3. For no external adjustments, pins 4 and 6 are not connected. adjustment at least ±0.3% FSR.

2 ACOM

FIGURE 6. Manual Offset and Gain Adjust Circuits.

DAC813 (Use 11-bit resolution for 0V to +10V output. No op amps required). For no external adjustments, pins 4 and 6 are not connected. FIGURE 7. Gain and Offset Adjustment Using D/A Converters.